XS ON 10 PUSB3F96 ESD protection for ultra high-speed interfaces Rev. 3 — 29 September 2014 Product data sheet 1. Product profile 1.1 General description The device is designed to protect high-speed interfaces such as SuperSpeed USB, High-Definition Multimedia Interface (HDMI), DisplayPort, external Serial Advanced Technology Attachment (eSATA) and Low Voltage Differential Signaling (LVDS) interfaces against ElectroStatic Discharge (ESD). The device includes four high-level ESD protection diode structures for ultra high-speed signal lines and is encapsulated in a leadless small DFN2510A-10 (SOT1176-1) plastic package. All signal lines are protected by a special diode configuration offering ultra low line capacitance of only 0.5 pF. These diodes utilize a unique snap-back structure in order to provide protection to downstream components from ESD voltages up to 10 kV contact exceeding IEC 61000-4-2, level 4. 1.2 Features and benefits System ESD protection for USB 2.0 and SuperSpeed USB 3.0, HDMI 2.0, DisplayPort, eSATA and LVDS All signal lines with integrated rail-to-rail clamping diodes for downstream ESD protection of 10 kV exceeding IEC 61000-4-2, level 4 Matched 0.5 mm trace spacing Signal lines with 0.05 pF matching capacitance between signal pairs Line capacitance of only 0.5 pF for each channel Design-friendly ‘pass-through’ signal routing 1.3 Applications The device is designed for high-speed receiver and transmitter port protection: TVs and monitors DVD recorders and players Notebooks, main board graphic cards and ports Set-top boxes and game consoles PUSB3F96 NXP Semiconductors ESD protection for ultra high-speed interfaces 2. Pinning information Table 1. Pinning Pin Symbol Description Simplified outline 1 CH1 channel 1 ESD protection 2 CH2 channel 2 ESD protection 3 GND ground 4 CH3 channel 3 ESD protection 5 CH4 channel 4 ESD protection 6 n.c. not connected 7 n.c. not connected 8 GND ground 9 n.c. not connected 10 n.c. not connected 10 9 8 7 6 Graphic symbol 1 2 4 5 1 2 3 4 5 Transparent top view 3, 8 018aaa001 3. Ordering information Table 2. Ordering information Type number PUSB3F96 Package Name Description Version DFN2510A-10 plastic extremely thin small outline package; SOT1176-1 no leads; 10 terminals; body 1 2.5 0.5 mm 4. Marking Table 3. Marking codes Type number Marking code PUSB3F96 96 5. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VI input voltage VESD electrostatic discharge voltage Product data sheet Min Max Unit 0.5 +5.5 V contact discharge 10 +10 kV air discharge 15 +15 kV IEC 61000-4-2, level 4 [1] Tamb ambient temperature 40 +85 C Tstg storage temperature 55 +125 C [1] PUSB3F96 Conditions All pins to ground. All information provided in this document is subject to legal disclaimers. Rev. 3 — 29 September 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 2 of 15 PUSB3F96 NXP Semiconductors ESD protection for ultra high-speed interfaces 6. Characteristics Table 5. Characteristics Tamb = 25 C unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit VBR breakdown voltage II = 1 mA 6 - - V ILR reverse leakage current per channel; VI = 3 V - - 1 A VF forward voltage II = 1 mA - 0.7 - V Cline line capacitance f = 1 MHz; VI = 3.3 V [1] - 0.5 0.6 pF - 0.05 - pF - 0.41 - - 0.26 - - 0.43 - - 0.28 - - 4.6 - V - 2.2 - V Cline line capacitance difference f = 1 MHz; VI = 3.3 V [1] rdyn dynamic resistance surge [2] positive transient negative transient TLP [3] positive transient negative transient VCL clamping voltage IPP = 5.2 A [2] positive transient IPP = 4.4 A negative transient PUSB3F96 Product data sheet [1] This parameter is guaranteed by design. [2] According to IEC 61000-4-5 (8/20 s current waveform). [3] 100 ns Transmission Line Pulse (TLP); 50 ; pulser at 80 ns. All information provided in this document is subject to legal disclaimers. Rev. 3 — 29 September 2014 [2] © NXP Semiconductors N.V. 2014. All rights reserved. 3 of 15 PUSB3F96 NXP Semiconductors ESD protection for ultra high-speed interfaces aaa-009367 2 Sdd21 (dB) aaa-009368 1.2 a -2 0.8 -6 0.4 -10 -14 106 107 108 109 0 1010 0 1 2 3 4 5 VI (V) f (MHz) differential mode C line a = --------------------------------C line V = 0 V I Fig 1. Insertion loss; typical values Fig 2. aaa-009369 0 Relative capacitance as a function of input voltage; typical values aaa-009370 120 Zdif (Ω) Sdd21 (dB) 110 -20 (2) 100 -40 90 (1) -60 106 107 108 109 80 40.0 1010 40.5 41.0 Sdd21 normalized to 100 ; differential pairs CH1/CH2 versus CH3/CH4 41.5 42.0 t (ns) f (MHz) tr = 200 ps; differential pair CH1 + CH2 (1) PUSB3F96 on reference board (2) Reference board without device under test (DUT) Fig 3. Crosstalk; typical values PUSB3F96 Product data sheet Fig 4. Differential Time Domain Reflectometer (TDR) plot; typical values All information provided in this document is subject to legal disclaimers. Rev. 3 — 29 September 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 4 of 15 PUSB3F96 NXP Semiconductors ESD protection for ultra high-speed interfaces aaa-014157 Data rate: 5 Gbit/s Vertical scale: 166.3 mV/div Horizontal scale: 20 ps/div Fig 5. USB 3.0 eye diagram, Printed-Circuit Board (PCB) with PUSB3F96 aaa-014158 Data rate: 5 Gbit/s Vertical scale: 166.3 mV/div Horizontal scale: 20 ps/div Fig 6. PUSB3F96 Product data sheet USB 3.0 eye diagram, PCB without PUSB3F96 (reference) All information provided in this document is subject to legal disclaimers. Rev. 3 — 29 September 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 5 of 15 PUSB3F96 NXP Semiconductors ESD protection for ultra high-speed interfaces aaa-014159 Test frequency: 148.5 MHz Differential swing voltage: 810 mV Horizontal scale: 34 ps/div Fig 7. HDMI 2.0 TP1 eye diagram, PCB with PUSB3F96 (2160p, 60 Hz) aaa-014160 Test frequency: 148.5 MHz Differential swing voltage: 800 mV Horizontal scale: 34 ps/div Fig 8. PUSB3F96 Product data sheet HDMI 2.0 TP1 eye diagram, PCB without PUSB3F96 (2160p, 60 Hz, reference) All information provided in this document is subject to legal disclaimers. Rev. 3 — 29 September 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 6 of 15 PUSB3F96 NXP Semiconductors ESD protection for ultra high-speed interfaces aaa-014161 Test frequency: 148.5 MHz Differential swing voltage: 809 mV Horizontal scale: 34 ps/div Remark: Measured at Test Point 2 (TP2) worst cable emulator, reference cable equalizer and worst case positive skew. Fig 9. HDMI 2.0 TP2 eye diagram, PCB with PUSB3F96 (2160p, 60 Hz) aaa-014162 Test frequency: 148.5 MHz Differential swing voltage: 820 mV Horizontal scale: 34 ps/div Remark: Measured at Test Point 2 (TP2) worst cable emulator, reference cable equalizer and worst case positive skew. Fig 10. HDMI 2.0 TP2 eye diagram, PCB without PUSB3F96 (2160p, 60 Hz, reference) PUSB3F96 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 29 September 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 7 of 15 PUSB3F96 NXP Semiconductors ESD protection for ultra high-speed interfaces aaa-009371 6 IPP (A) aaa-009372 0 IPP (A) 4 -2 2 -4 0 0 2 4 -6 -2.5 6 -2.0 -1.5 -1.0 -0.5 0 VCL (V) VCL (V) IEC 61000-4-5; tp = 8/20 s; positive pulse IEC 61000-4-5; tp = 8/20 s; negative pulse Fig 11. Dynamic resistance with positive clamping; typical values Fig 12. Dynamic resistance with negative clamping; typical values aaa-009373 14 I (A) 12 aaa-009374 0 I (A) -2 10 -4 8 -6 6 -8 4 -10 2 -12 0 -14 0 4 8 12 -6 VCL (V) -4 -2 0 VCL (V) tp = 100 ns; Transmission Line Pulse (TLP) tp = 100 ns; Transmission Line Pulse (TLP) Fig 13. Dynamic resistance with positive clamping; typical values Fig 14. Dynamic resistance with negative clamping; typical values The device uses an advanced clamping structure showing a negative dynamic resistance. This snap-back behavior strongly reduces the clamping voltage to the system behind the ESD protection during an ESD event. Do not connect unlimited DC current sources to the data lines to avoid keeping the ESD protection device in snap-back state after exceeding breakdown voltage (due to an ESD pulse for instance). PUSB3F96 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 29 September 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 8 of 15 PUSB3F96 NXP Semiconductors ESD protection for ultra high-speed interfaces 7. Application information The device is designed to provide high-level ESD protection for high-speed serial data buses such as HDMI, DisplayPort, eSATA and LVDS data lines. When designing the Printed-Circuit Board (PCB), give careful consideration to impedance matching and signal coupling. Do not connect the signal lines to unlimited current sources like, for example, a battery. A basic application diagram for the ESD protection of an HDMI interface is shown in Figure 15. PUSB3F96 TMDS_D2+ 5 4 8 3 2 1 TMDS_CH2+ TMDS_GND TMDS_CH2– TMDS_D2– GND TMDS_D1+ TMDS_CH1+ TMDS_GND TMDS_CH1– TMDS_D1– PUSB3F96 TMDS_D0+ 5 TMDS_CH2+ TMDS_GND 4 8 3 2 1 TMDS_CH2– TMDS_D0– GND TMDS_CLK+ TMDS_CH1+ HDMI CONNECTOR TMDS_GND TMDS_CH1– TMDS_CLKCEC n.c. DDC_CLK DDC_DAT GND +5 V HOT PLUG DETECTION 6 5 4 IP4221CZ6 1 2 100 nF 3 aaa-006751 Fig 15. Application diagram of HDMI ESD protection using PUSB3F96 PUSB3F96 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 29 September 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 9 of 15 PUSB3F96 NXP Semiconductors ESD protection for ultra high-speed interfaces 8. Package outline 1.1 0.9 0.2 min 5 0.127 6 2.6 2 2.4 0.25 0.15 0.5 1 0.45 0.35 Dimensions in mm 10 0.4 0.3 0.05 max 0.5 max 12-05-23 Fig 16. Package outline DFN2510A-10 (SOT1176-1) PUSB3F96 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 29 September 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 10 of 15 PUSB3F96 NXP Semiconductors ESD protection for ultra high-speed interfaces 9. Soldering Footprint information for reflow soldering of DFN2510A-10 package SOT1176-1 Hx C Hy Ay By 0.05 D P 0.05 Generic footprint pattern Refer to the package outline drawing for actual layout solder land solder paste deposit solder land plus solder paste occupied area solder resist Dimensions in mm P Ay By C D Hx Hy 0.5 1.25 0.3 0.475 0.2 2.45 1.5 Remark: Stencil of 75 μm is recommended. A stencil of 75 μm gives an aspect ratio of 0.77 With a stencil of 100 μm one will obtain an aspect ratio of 0.58 sot1176-1_fr Fig 17. Reflow soldering footprint DFN2510A-10 (SOT1176-1) PUSB3F96 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 29 September 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 11 of 15 PUSB3F96 NXP Semiconductors ESD protection for ultra high-speed interfaces 10. Revision history Table 6. Revision history Document ID Release date Data sheet status Change notice Supersedes PUSB3F96 v.3 20140929 Product data sheet - PUSB3F96 v.2 Modifications: • • Section 1 “Product profile”: updated Figure 5 to 10: added PUSB3F96 v.2 20131101 Product data sheet - PUSB3F96 v.2 PUSB3F96 v.1 20130226 Product data sheet - - PUSB3F96 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 29 September 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 12 of 15 PUSB3F96 NXP Semiconductors ESD protection for ultra high-speed interfaces 11. Legal information 11.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 11.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 11.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. PUSB3F96 Product data sheet Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. All information provided in this document is subject to legal disclaimers. Rev. 3 — 29 September 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 13 of 15 PUSB3F96 NXP Semiconductors ESD protection for ultra high-speed interfaces Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 11.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 12. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] PUSB3F96 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 29 September 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 14 of 15 PUSB3F96 NXP Semiconductors ESD protection for ultra high-speed interfaces 13. Contents 1 1.1 1.2 1.3 2 3 4 5 6 7 8 9 10 11 11.1 11.2 11.3 11.4 12 13 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1 General description . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Application information. . . . . . . . . . . . . . . . . . . 9 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 12 Legal information. . . . . . . . . . . . . . . . . . . . . . . 13 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 13 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Contact information. . . . . . . . . . . . . . . . . . . . . 14 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP Semiconductors N.V. 2014. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 29 September 2014 Document identifier: PUSB3F96