For Communications Equipment MN195902 Digital Signal Processor for Image CODEC Overview The MN195902 is a high-speed, programmable digital signal processor based on a vector pipeline architecture for image processing applications. It incorporates many features that make it ideal for highly efficient coding and decoding of still and moving pictures in applications involving the transmission, storage, and retrieval of images. Features Flexible support for complex processing by simply rewriting the contents of its internal program memory Built-in dedicated hardware effective for image CODEC, including • Discrete cosine transform (DCT) converter • Two-dimensional address generator Architecture that links internal memory, a generalpurpose arithmetic unit, dedicated arithmetic unit, and other components with a pipeline to better support vector calculations, multiply-and-accumulate, and other key image processing operations ITU-T H.261 coding for the QCIF size (176 × 144) with a decoding rate of 15 frames per second or higher Applications Image-based communications: Moving picture videophones, video conferencing systems, cable television systems, image LANs, remote monitoring systems, etc. Image storage and retrieval: Electronic still cameras, optical disc files, image databases, etc. Multimedia computers MN195902 For Communications Equipment 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 SPCLK TEST0 TEST1 DRMODE0 DRMODE1 VSS6 VDD6 XWCS XSRE ST1 ST2 XHLD/RUN XRST XCS XSWE DRMODE2 VSS7 SCLK VDD7 X801 X802 XRESEN1 XRESEN2 XOE1 XOE2 XWE1 XWE2 TEST2 TEST3 VDDH XCAS1 XCAS2 Pin Assignment 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 D2[9] D2[8] VDD3 VSS3 D2[7] D2[6] D2[5] D2[4] D2[3] D2[2] D2[1] D2[0] VDD2 VSS2 D1[15] D1[14] D1[13] D1[12] D1[11] D1[10] D1[9] D1[8] D1[7] D1[6] VDD1 VSS1 D1[5] D1[4] D1[3] D1[2] D1[1] D1[0] XSIEMP SIRCLK S1 XSOBSY SOWCLK S0 VDD5 VSS5 P0[7] P0[6] P0[5] P0[4] P0[3] P0[2] P0[1] P0[0] P0[7] P0[6] P0[5] P0[4] P0[3] P0[2] P0[1] P0[0] VDD4 VSS4 D2[15] D2[14] D2[13] D2[12] D2[11] D2[10] LQFP128-P-1818 XRAS1 XRAS2 VSS8 VDD8 A1[0] A1[1] A1[2] A1[3] A1[4] A1[5] A1[6] A1[7] A1[8] A1[9] VSS9 VDD9 A1[10] A1[11] A2[0] A2[1] A2[2] A2[3] A2[4] A2[5] A2[6] A2[7] A2[8] A2[9] VSS10 VDD10 A2[10] A2[11] For Communications Equipment MN195902 Vector Pipeline Processing Examples QP instruction Internal memory SAG Internal memory SAG Internal memory SAG SAG P instruction Internal memory SFT SFT SFT SFT REG REG REG REG Pipeline arithmetic unit Pipeline arithmetic unit REG REG SFT SAG ADD Internal memory REG SAG SFT Internal memory SAG SAG Q instruction Internal memory SFT SFT REG REG Pipeline arithmetic unit REG ADD REG Internal memory MN195902 For Communications Equipment SAG SAG SAG SAG BM1 1Kwd BM2 1Kwd CTL IRAM 2Kwd DRAM IF SAG DM 1Kwd MPY EALU Program CTL A2 D2 A1 D1 Block Diagram SIO REG FREG 16wd SIO DCT FLT PIO PIO ACC REG SAG BM1 BM2 DM IRAM, IROM FREG0 to 15 EALU Two-dimensional address generator Internal memory (1024 × 16 bits) Instruction memory (2048 × 16 bits) Instruction memory (2048 × 16 bits) Instruction memory (2048 × 32 bits) General-purpose registers Arithmetic unit MPY ACC DCT FLT SIO PIO Multiplier Accumulator Discrete cosine transform converter Filter Serial interface Parallel interface For Communications Equipment MN195902 Pin Descriptions Pin No. 15 to 24, Symbol D1 (15:0) I/O I/O/Z Function Description Data bus for data transfers to and from external memory (EM1) A1 (11:0) I/O/Z Address bus for data transfers to and from external memory (EM1) 71 XWE1 O/Z External memory write control output (negative logic) 73 XOE1 O/Z External memory read control output (negative logic) 77 XBO1 O 64 XRAS1 O/Z External memory row address strobe output (negative logic) 66 XCAS1 O/Z External memory row address strobe output (negative logic) 75 XRFSEN1 I 123 to 128, D2 (15:0) I/O/Z Data bus for data transfers to and from external memory (EM2) A2 (11:0) O/Z Address bus for data transfers to and from external memory (EM2) 70 XWE2 O/Z External memory write control output (negative logic) 72 XOE2 O/Z External memory read control output (negative logic) 76 XBO2 O 63 XRAS2 O/Z External memory row address strobe output (negative logic) 65 XCAS2 O/Z External memory row address strobe output (negative logic) 74 XRFSEN2 I External memory refresh enable signal (negative logic) 79 SCLK I System clock input 27 to 32 47 to 48, 51 to 60 External memory cycle bus occupation control output (negative logic) External memory refresh enable signal (negative logic) 1, 2, 5 to 12 33, 34, 37 to 46 External memory cycle bus occupation control output (negative logic) 96 SPCLK I Serial port clock input 85 XHLD/RUN I Operational mode transition control input 83 XCS I Chip select input (negative logic) 82 XSWE I Internal memory write enable input for Hold/Slave mode (negative input) 88 XSRE I Internal memory read enable input for Hold/Slave mode (negative input) 84 XRST I Reset input (negative input) 87 ST1 O Operating status output 86 ST2 O Operating status output 102 SO O/Z Serial out port data 101 SOWCLK O/Z Serial out port external write enable output 100 XSOBSY I Serial out port external busy input (negative logic) 99 SI I Serial in port data 98 SIRCLK O/Z 97 XSIEMP I Serial in port external external empty input (negative logic) 105 to 112 PO (7:0) O Parallel out port data bus (PO7 is MSB) 113 to 120 PI (7:0) I Parallel in port data bus (PI7 is MSB) 81, 92, 93 DRMODE(2:0) I External DRAM mode control inputs Vdd I Power supply pin 3.3[V] Vddh I Power supply pin 5.0 to Vdd[V] Vss I Power supply pin 0 [V] Serial in port external read enable output MN195902 For Communications Equipment Application Circuit Example Double buffer (for input data) MN195902 Memory (DRAM) Port-1 Image input Memory (DRAM) Serial port (for local retrieval) Memory (DRAM) Port-2 Program load Execution control FIFO Code For Communications Equipment MN195902 Package Dimensions (Unit: mm) LQFP128-P-1818 20.0±0.2 18.0±0.1 96 65 64 128 33 32 0.1 SEATING PLANE 0.17±0.1 0.1 M 1.7max. (1.0) 1.4±0.1 0.5 +0.10 0.2 –0.05 0.1±0.1 1 (1.25) 20.0±0.2 18.0±0.1 (1.25) 97 0 to 10° 0.5±0.2