HI5865 Semiconductor PRELIMINARY 12-Bit, 65 MSPS A/D Converter June 1998 Features Description • Sampling Rate . . . . . . . . . . . . . . . . . . . . . . . . . 65 MSPS The HI5865 is a monolithic, 12-bit, 65 MSPS Analog-toDigital Converter fabricated in an advanced CMOS process. It is designed for high speed, high resolution applications where wide bandwidth, low power consumption and excellent SINAD performance are essential. With a 250MHz full power input bandwidth and high frequency accuracy, the converter is ideal for many types of communication systems employing digital IF architectures. • Low Power at 65 MSPS . . . . . . . . . . . . . . . . . . . .450mW • Internal Sample and Hold • Fully Differential Architecture • Full Power Input Bandwidth . . . . . . . . . . . . . . . 250MHz • Low Data Latency • TTL Compatible Clock Input The HI5865 is designed with a fully differential pipelined architecture using a front end differential-in-differential-out Sample-and-Hold amplifier (S/H). The HI5865 has excellent dynamic performance while consuming 450mW of power at 65 MSPS. • CMOS Compatible Digital Data Outputs Applications • Multichannel Digital Communication Receivers • Cellular/PCS Basestation Receivers Data output latches are provided which present valid data to the output bus with a low data latency of 9 clock cycles. • Undersampling Digital IF • Digital Subscriber Line (VDSL) Ordering Information • Medical Ultrasound • Reference Literature - AN9214, Using Harris High Speed A/D Converters PART NUMBER HI5865IN TEMP. RANGE (oC) -40 to 85 HI5865EVAL1 25 PACKAGE PKG. NO. 44 Ld MQFP Q44.10x10 Evaluation Platform Pinout NC D11 DVCC3 DGND DGND3 DVCC DGND DGND DGND CLK DGND HI5865 (MQFP) TOP VIEW DGND 44 43 42 41 40 39 38 37 36 35 34 33 2 32 AGND 3 31 D8 AVCC 4 30 D7 AGND 5 29 DGND AVCC 6 28 DVCC AVCC1 7 27 D6 AGND1 8 26 D5 VIN- 9 25 D4 VIN+ 10 24 D3 VDC 11 23 12 13 14 15 16 17 18 19 20 21 22 D2 D10 D9 NC D1 D0 NC NC DVCC2 DGND2 DVCC1 DGND1 VREF- 1 VREF+ DVCC CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © Harris Corporation 1998 1 File Number 4538 HI5865 Metric Plastic Quad Flatpack Packages (MQFP/PQFP) Q44.10x10 (JEDEC MO-108AA-2 ISSUE A) D 44 LEAD METRIC PLASTIC QUAD FLATPACK PACKAGE D1 -D- -A- -B- E E1 e PIN 1 INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A - 0.093 - 2.35 - A1 0.004 0.010 0.10 0.25 - A2 0.077 0.083 1.95 2.10 - B 0.012 0.018 0.30 0.45 6 B1 0.012 0.016 0.30 0.40 - D 0.510 0.530 12.95 13.45 3 D1 0.390 0.398 9.90 10.10 4, 5 E 0.510 0.530 12.95 13.45 3 E1 0.390 0.398 9.90 10.10 4, 5 L 0.026 0.037 0.65 0.95 N 44 44 e 0.032 BSC 0.80 BSC SEATING A PLANE -H- 7 Rev. 1 1/94 NOTES: 0.10 0.004 -C- 5o-16o 0.40 0.016 MIN 0.20 M C A-B S 0.008 0o MIN 2. All dimensions and tolerances per ANSI Y14.5M-1982. D S 3. Dimensions D and E to be determined at seating plane -C- . 4. Dimensions D1 and E1 to be determined at datum plane -H- . B A2 A1 0o-7o L 5o-16o B1 5. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm (0.010 inch) per side. 0.13/0.17 0.005/0.007 BASE METAL WITH PLATING 1. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 6. Dimension B does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total. 7. “N” is the number of terminal positions. 0.13/0.23 0.005/0.009 2