INTERSIL ISL88731

ISL88731
®
Data Sheet
November 20, 2006
FN9258.0
SMBus Level 2 Battery Charger
Features
The ISL88731 is a highly integrated Lithium-ion battery
charger controller, programmable over the SMBus system
management bus (SMBus). The ISL88731 is intended to be
used in a smart battery charger (SBC) within a smart battery
system (SBS) that throttles the charge power such that the
current from the AC adapter is automatically limited. High
efficiency is achieved with a DC/DC synchronous-rectifier
buck converter, equipped with diode emulation for enhanced
light load efficiency and system bus boosting prevention. The
ISL88731 charges one to four Lithium-ion series cells, and
delivers up to 8A charge current. Integrated MOSFET
drivers and bootstrap diode result in fewer components and
smaller implementation area. Low offset current-sense
amplifiers provide high accuracy with 10mΩ sense resistors.
The ISL88731 provides 0.5% end-of-charge battery voltage
accuracy.
• 0.5% Battery Voltage Accuracy
The ISL88731 provides a digital output that indicates the
presence of the AC adapter as well as an analog output
which indicates the adapter current within 4% accuracy.
• 8A Maximum Battery Charger Current
• 3% Adapter Current Limit Accuracy
• 3% Charge Current Accuracy
• SMBus 2 Wire Serial Interface
• Battery Short Circuit Protection
• Fast Response for Pulse-Charging
• Fast System-Load Transient Response
• Monitor Outputs
- Adapter Current (3% Accuracy)
- AC Adapter Detection
• 11 Bit Battery Voltage Setting
• 6 Bit Charge Current/Adapter Current Setting
• 11A Maximum Adapter Current
• +8V to +28V Adapter Voltage Range
The ISL88731 is available in a small 5mm x 5mm 28 Ld thin
(0.8mm) QFN package. An evaluation kit is available to
reduce design time. The ISL88731 is available in Pb-free
packages.
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Notebook Computers
Pinout
• Tablet PCs
ISL88731
(28 LD TQFN)
TOP VIEW
CSSP
CSSN
VCC
BOOT
UGATE
PHASE
DCIN
• Portable Equipment with Rechargeable Batteries
28
27
26
25
24
23
22
Ordering Information
PART
NUMBER
LGATE
VREF
3
19
PGND
ICOMP
4
18
CSOP
NC
5
17
CSON
VCOMP
6
16
NC
NC
7
15
VFB
8
9
10
11
12
13
14
NC
20
ACOK
2
GND
ACIN
VDDSMB
VDDP
SCL
21
SDA
1
ICM
NC
1
PART
MARKING
TEMP (°C)
PACKAGE
PKG.
DWG. #
ISL88731HRZ
(Note)
ISL887
31HRZ
-10 to +100 28 Ld 5x5 TQFN L28.5x5B
(Pb-free)
ISL88731HRZ-T
(Note)
ISL887
31HRZ
-10 to +100 28 Ld 5x5 TQFN L28.5x5B
(Tape and Reel)
(Pb-free)
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb
and Pb-free soldering operations. Intersil Pb-free products are MSL classified
at Pb-free peak reflow temperatures that meet or exceed the Pb-free
requirements of IPC/JEDEC J STD-020.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL88731
VCC
DCIN
VDDSMB
11
DACV
DACV
6
DACS
DACS
DACI
DACI
SMBus
SDA
6
SCL
Linear
Regulator
Reference
VDDP
REF
VREF
ACOK
+
-
EN
ACIN
ICM
Buff
CSSP
Level
Shifter
20x
CSSN
DACS
EN
GMS
+
BOOT
ICOMP
CSO
UGATE
CSOP
Level
Shifter
20x
CSON
GMI
DACI
PHASE
DC-DC
Converter
+
LVB
VDDP
LVB
+
DACV
GMV
LGATE
-
PGND
VFB
500K 100K
EN
CSSP
GND
VCOMP
FIGURE 1. FUNCTIONAL BLOCK DIAGRAM
AC ADAPTER
TO SYSTEM
RS1
CSSP
CSSN
UGATE
PHASE
ACIN
DCIN
RS2
TO BATTERY
ISL88731
BOOT
LGATE
CSOP
CSON
VFB
AGND
ICOMP
VCOMP
VDDP
PGND
VCC
GND
ACOK
ICM
SDA
SCL
VDDSMB
PGND
HOST
VREF
AGND
FIGURE 2. TYPICAL APPLICATION CIRCUIT
2
FN9258.0
November 20, 2006
ISL88731
Absolute Maximum Ratings
Thermal Information
DCIN, CSSP, CSSN, CSOP, CSON, VFB . . . . . . . . . . -0.3V to +28V
CSSP-CSSN, CSOP-CSON, PGND-GND. . . . . . . . . -0.3V to +0.3V
PHASE to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -6V to +30V
BOOT to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +33V
BOOT to PHASE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6V
UGATE . . . . . . . . . . . . . . . . . . . . . . . . PHASE-0.3V to BOOT+0.3V
LGATE . . . . . . . . . . . . . . . . . . . . . . . . . PGND-0.3V to VDDP+0.3V
ICOMP, VCOMP, VREF, to GND . . . . . . . . . . . . -0.3V to VCC+0.3V
VDDSMB, SCL, SDA, ACIN, ACOK . . . . . . . . . . . . . . . -0.3V to +6V
VDDP, ICM, VCC to GND, VDDP to PGND. . . . . . . . . . -0.3V to +6V
Thermal Resistance (Typical, Notes 1, 2) θJA (°C/W)
θJC (°C/W)
QFN Package. . . . . . . . . . . . . . . . . . . .
39
9.5
Junction Temperature Range. . . . . . . . . . . . . . . . . .-55°C to +150°C
Operating Temperature Range . . . . . . . . . . . . . . . .-10°C to +100°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Lead Temperature (Soldering, 10s) . . . . . . . . . . . . . . . . . . . . +300°C
CAUTION: Stress above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational section of this specification is not implied.
+150°C max junction temperature is intended for short periods of time to prevent shortening the lifetime. Operation close to +150°C junction may trigger the shutdown of
the device even before +150°C, since this number is specified as typical.
1. θJA is measured with the component mounted on a highly effective thermal conductivity test board on free air. See Tech Brief TB379 for details.
2. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
DCIN = CSSP = CSSN = 18V, CSOP = CSON = 12V, VDDP = 5V, BOOT-PHASE = 5.0V, GND = PGND = 0V,
CVDDP = 1µF, IVDDP = 0mA, TA = -10°C to +100°C
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
16.716
16.8
16.884
V
0.5
%
12.592
12.655
V
0.5
%
8.4
8.450
V
0.6
%
4.221
V
0.7
%
CHARGE VOLTAGE REGULATION
Battery Full Charge Voltage and Accuracy ChargeVoltage = 0x41A0
-0.5
ChargeVoltage = 0x3130
12.529
ChargeVoltage = 0x20D0
8.350
-0.5
-0.6
ChargeVoltage = 0x1060
4.163
4.192
-0.7
Battery Undervoltage Lockout Trip Point
for Trickle Charge
VFB rising
2.55
2.7
2.85
V
100
250
400
mV
78.22
80.64
83.06
mV
RS2 = 10mΩ (see Figure 2)
ChargingCurrent = 0x1f80
7.822
8.064
8.306
A
3
%
RS2 = 10mΩ (see Figure 2)
ChargingCurrent = 0x0f80
3.809
4.126
A
4
%
RS2 = 10mΩ (see Figure 2)
ChargingCurrent = 0x0080
64
220
mA
-1.6
1.4
%
0
19
V
Battery Undervoltage Lockout Trip Point
Hysteresis
CHARGE CURRENT REGULATION
CSOP to CSON Full-Scale Current-Sense
Voltage
Charge Current and Accuracy
Charge Current Gain Error
Based on charge current = 128mA and 8.064A
CSOP/CSON Input Voltage Range
3
-3
3.968
-4
128
FN9258.0
November 20, 2006
ISL88731
Electrical Specifications
DCIN = CSSP = CSSN = 18V, CSOP = CSON = 12V, VDDP = 5V, BOOT-PHASE = 5.0V, GND = PGND = 0V,
CVDDP = 1µF, IVDDP = 0mA, TA = -10°C to +100°C (Continued)
PARAMETER
CONDITIONS
Battery Quiescent Current
MIN
Adapter present, not charging,
ICSOP + ICSON + IPHASE + ICSSP + ICSSN + IFB
VPHASE = VCSON = VCSOP = VDCIN = 19V, VACIN = 5V
Adapter Absent
ICSOP + ICSON + IPHASE + ICSSP + ICSSN + IFB
VPHASE = VCSON = VCSOP = 19V, VDCIN = 0V
Adapter Quiescent Current
-1
IDCIN+ICSSP+ICSSN
Vadapter = 8V to 26V, Vbattery 4V to 16.8V
TYP
MAX
UNITS
135
200
µA
0.2
2
µA
3
5
mA
110
113.3
mV
INPUT CURRENT REGULATION
CSSP to CSSN Full-Scale Current-Sense CSSP = 19V
Voltage
Input Current Accuracy
106.7
RS1 = 10mΩ (see Figure 2)
Adapter Current = 11004mA or 3584mA
-3
3
%
RS1 = 10mΩ (see Figure 2)
Adapter Current = 2048mA
-5
5
%
-1.5
1.5
%
Input Current Limit Offset
-1
1
mV
CSSP/CSSN Input Voltage Range
8
26
V
20.2
V/V
Input Current Limit Gain Error
Based on InputCurrent = 1024mA and 11004mA
ICM Gain
VCSSP-CSSN = 110mV
19.8
ICM Offset
Based on VCSSP-CSSN = 110mV and 20mV
-1.5
1.5
mV
ICM Accuracy
VCSSP-CSSN = 110mV
ICM Max Output Current
20
-2.5
2.5
%
VCSSP-CSSN = 55mV or 35mV
-4
4
%
VCSSP-CSSN = 20mV
-8
8
%
500
µA
26
V
5.1
5.23
V
35
100
mV
5.5
V
VCSSP-CSSN = 0.1V
SUPPLY AND LINEAR REGULATOR
DCIN, Input Voltage Range
8
VDDP Output Voltage
8.0V < VDCIN < 28V, no load
VDDP Load Regulation
0 < IVDDP < 30mA
5.0
VDDSMB Range
2.7
VDDSMB UVLO Rising
2.4
2.5
2.6
V
VDDSMB UVLO Hysteresis
100
150
200
mV
20
27
µA
3.168
3.2
3.232
V
2
8
VDDSMB Quiescent Current
VDDP = SCL = SDA = 5.5V
V REFERENCE
VREF Output Voltage
0 < IVREF < 300µA
ACOK
ACOK Sink Current
VACOK = 0.4V, ACIN = 1.5V
ACOK Leakage Current
VACOK = 5.5V, ACIN = 2.5V
mA
1
µA
ACIN
ACIN rising Threshold
3.15
3.2
3.25
V
ACIN Threshold Hysteresis
40
60
90
mV
ACIN Input Bias Current
-1
1
µA
440
kHz
SWITCHING REGULATOR
Frequency
330
4
400
FN9258.0
November 20, 2006
ISL88731
Electrical Specifications
DCIN = CSSP = CSSN = 18V, CSOP = CSON = 12V, VDDP = 5V, BOOT-PHASE = 5.0V, GND = PGND = 0V,
CVDDP = 1µF, IVDDP = 0mA, TA = -10°C to +100°C (Continued)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
170
290
400
µA
0
2
µA
BOOT Supply Current
UGATE High
PHASE Input Bias Current
VDCON = 28V, VCSON = VPHASE = 20V
UGATE On-Resistance Low
IUGATE = -100mA (see note 4)
0.9
1.6
Ω
UGATE On-Resistance High
IUGATE = 10mA (see note 4)
1.4
2.5
Ω
LGATE On-Resistance High
ILGATE = +10mA (see note 4)
1.4
2.5
Ω
LGATE On-Resistance Low
ILGATE = -100mA (see note 4)
0.9
1.6
Ω
Dead Time
Falling UGATE to rising LGATE or
falling LGATE to rising UGATE
35
50
80
ns
GMV Amplifier Transconductance
200
250
300
μA/V
GMI Amplifier Transconductance
40
50
60
μA/V
GMS Amplifier Transconductance
40
50
60
μA/V
GMI/GMS Saturation Current
15
21
25
μA
GMV Saturation Current
10
17
30
μA
200
300
400
mV
0.8
V
ERROR AMPLIFIERS
ICOMP, VCOMP Clamp Voltage
0.25V < VICOMP, VCOMP < 3.5V
LOGIC LEVELS
SDA/SCL Input Low Voltage
VDDSMB = 2.7V to 5.5V
SDA/SCL Input High Voltage
VDDSMB = 2.7V to 5.5V
2
SDA/SCL Input Bias Current
VDDSMB = 2.7V to 5.5V
-1
SDA, Output Sink Current
VSDA = 0.4V
7
15
MIN
TYP
V
1
µA
mA
SMBus
SMB Timing Specification VDDSMB = 2.7V TO 5.5V
PARAMETERS
SYMBOL
CONDITIONS
MAX
UNITS
100
kHz
SMBus Frequency
FSMB
10
Bus Free Time
TBUF
4.7
µs
Start Condition Hold Time from SCL
THD:STA
4
µs
Start Condition Setup Time from SCL
TSU:STA
4.7
µs
Stop Condition Setup Time from SCL
TSU:STO
4
µs
SDA Hold Time from SCL
THD:DAT
300
ns
SDA Setup Time from SCL
TSU:DAT
250
ns
SCL Low Timeout (Note 3)
TTIMEOUT
22
SCL Low Period
TLOW
4.7
µs
SCL High Period
THIGH
4
µs
Maximum Charging Period Without a SMBus Write to
ChargeVoltage or ChargeCurrent Register
140
25
180
30
220
ms
s
NOTE:
3. If SCL is low for longer than the specified time, the charger is disabled.
4. Guaranteed by characterization.
5
FN9258.0
November 20, 2006
ISL88731
Typical Operating Performance
DCIN = 20V, 3S2P Li-Battery, TA = +25°C, unless otherwise noted.
5.15
3.23
5.10
3.22
5.05
3.21
1.0%
5.00
VREF (V)
VDDP (V)
0.5%
4.95
0.0%
3.20
3.19
-0.5%
3.18
4.90
4.85
-1.0%
200
3.17
0
20
40
60
80
0
100
50
100
150
I VREF (µA)
VDDP LOAD CURRENT (mA)
FIGURE 4. VREF LOAD REGULATION
FIGURE 3. VDD LOAD REGULATION
15%
13.0
10%
12.5
3.5
3.0
BATTERY VOLTAGE
0%
-5%
-10%
12.0
VCHG (V)
2.0
11.5
1.5
11.0
1.0
10.5
0.5
ICHG (A)
-15%
1
2
3
4
5
6
7
8
10.0
0
20
40
ADAPTER CURRENT (A)
FIGURE 5. ICM ACCURACY vs AC ADAPTER CURRENT
VCOMP
ICOMP
BATTERY CURRENT
ICM ACCURACY
2.5
5%
60
80
100
TIME (MINUTES)
120
140
0.0
160
FIGURE 6. TYPICAL CHARGING VOLTAGE AND CURRENT
ICOMP
VCOMP
CHARGE
CURRENT
CHARGE
CURRENT
INDUCTOR
CURRENT
FIGURE 7. CHARGE ENABLE
6
INDUCTOR
CURRENT
FIGURE 8. CHARGE DISABLE
FN9258.0
November 20, 2006
ISL88731
Typical Operating Performance
DCIN = 20V, 3S2P Li-Battery, TA = +25°C, unless otherwise noted. (Continued)
UGATE
UGATE
LGATE
INDUCTOR
CURRENT
PHASE
LGATE
INDUCTOR
CURRENT
PHASE
FIGURE 10. SWITCHING WAVEFORMS IN CC MODE
FIGURE 9. SWITCHING WAVEFORMS AT DIODE EMULATION
CSON/
V BATTERY
CSON/
V BATTERY
BATTERY
CURRENT
BATTERY
CURRENT
FIGURE 12. BATTERY INSERTION
FIGURE 11. BATTERY REMOVAL
100
SYSTEM
LOAD
CHARGE
CURRENT
90
16.8V BATTERY
( )
BATTERY
VOLTAGE
95
85
12.6V BATTERY
80
ADAPTER
CURRENT
8.4V BATTERY
75
4.2V BATTERY
70
0
FIGURE 13. LOAD TRANSIENT RESPONSE
7
2
4
CHARGE CURRENT (A)
6
8
FIGURE 14. EFFICIENCY vs CHARGE CURRENT AND
BATTERY VOLTAGE (EFFICIENCY DCIN = 20V)
FN9258.0
November 20, 2006
ISL88731
Functional Pin Descriptions
PGND
BOOT
Power Ground. Connect PGND to the source of the low side
MOSFET.
High-Side Power MOSFET Driver Power-Supply
Connection. Connect a 0.1µF capacitor from BOOT to
PHASE.
UGATE
High-Side Power MOSFET Driver Output. Connect to the
high-side N-channel MOSFET gate.
LGATE
Low-Side Power MOSFET Driver Output. Connect to
low-side N channel MOSFET. LGATE drives between VDDP
and PGND.
VCC
Power input for internal analog circuits. Connect a 4.7Ω
resistor from VCC to VDDP and a 1µF ceramic capacitor
from VCC to ground.
VDDP
Linear Regulator Output. VDDP is the output of the 5.2V
linear regulator supplied from DCIN. VDDP also directly
supplies the LGATE driver and the BOOT strap diode.
Bypass with a 1µF ceramic capacitor from VDDP to PGND.
ICOMP
PHASE
CSOP
Compensation Point for the charging current and adapter
current regulation Loop. Connect 0.01µF to GND. See the
VCharge Current Control Loop section for details of
selecting the ICOMP capacitor.
Charge Current-Sense Positive Input.
VCOMP
CSON
Compensation Point for the voltage regulation loop. Connect
4.7kΩ in series with 0.01µF to GND. See “VOLTAGE
CONTROL LOOP” on page 19 for details on selecting
VCOMP components.
High-Side Power MOSFET Driver Source Connection.
Connect to the source of the high-side n channel MOSFET.
Charge Current-Sense Negative Input.
CSSP
Input Current-Sense Positive Input.
VFB
CSSN
Feed Back for the Battery Voltage.
Input Current-Sense Negative Input.
VDDSMB
DCIN
SMBus interface Supply Voltage Input. Bypass with a 0.1µF
capacitor to GND.
Charger Bias Supply Input. Bypass DCIN with a 0.1µF
capacitor to GND.
ACIN
AC Adapter Detection Input. Connect to a resistor divider
from the AC adapter output.
ACOK
AC Detect Output. This open drain output is high impedance
when ACIN is greater than 3.2V. The ACOK output remains
low when the ISL88731 is powered down. Connect a 10k
pull-up resistor from ACOK to VDDSMB.
ICM
Input Current Monitor Output. ICM voltage equals
20 x (VCSSP - VCSSN).
SDA
SMBus Data I/O. Open-drain Output. Connect an external
pull-up resistor according to SMBus specifications.
SCL
SMBus Clock Input. Connect an external pull-up resistor
according to SMBus specifications.
GND
Analog Ground. Connect directly to the backside paddle.
Connect to PGND close to the output capacitor.
Back Side Paddle
Connect the backside paddle to GND.
NC
No Connect. Pins 1, 5, 7 and 14 are not connected.
8
FN9258.0
November 20, 2006
ISL88731
Theory of Operation
Introduction
The ISL88731 includes all of the functions necessary to
charge 1 to 4 cell Li-Ion and Li-polymer batteries. A high
efficiency synchronous buck converter is used to control the
charging voltage up to 19.2V and charging current up to 8A.
The ISL88731 also has input current limiting up to 11A. The
Input current limit, charge current limit and charge voltage
limit are set by internal registers written with SMBus. The
ISL88731 “Typical Application Circuit” is shown on Figure 2.
The ISL88731 charges the battery with constant charge
current, set by the ChargeCurrent register, until the battery
voltage rises to a voltage set by the ChargeVoltage register.
The charger will then operate at a constant voltage. The
adapter current is monitored and if the adapter current rises to
the limit set by the InputCurrent register, battery charge
current is reduced so the charger does not reduce the adapter
current available to the system.
The ISL88731 features a voltage regulation loop (VCOMP)
and 2 current regulation loops (ICOMP). The VCOMP
voltage regulation loop monitors VFB to limit the battery
charge voltage. The ICOMP current regulation loop limits the
battery charging current delivered to the battery to ensure
that it never exceeds the current set by the ChargeCurrent
register. The ICOMP current regulation loop also limits the
input current drawn from the AC adapter to ensure that it
never exceeds the limit set by the InputCurrent register, and
to prevent a system crash and AC adapter overload.
PWM Control
The ISL88731 employs a fixed frequency PWM control
architecture with a feed-forward function. The feed-forward
function maintains a constant modulator gain of 11 to achieve
fast line regulation as the input voltage changes.
The duty cycle of the buck regulator is controlled by the lower
of the voltages on ICOMP and VCOMP. The voltage on
ICOMP and VCOMP are inputs to a Lower Voltage Buffer
(LVB) who’s output is the lower of the 2 inputs. The output of
the LVB is compared to an internal 400kHz ramp to produce
the Pulse Width Modulated signal that controls the UGATE
and LGATE drivers. An internal clamp holds the higher of the
2 voltages (0.3V) above the lower voltage. This speeds the
transition from voltage loop control to current loop control or
vice versa.
The ISL88731 can operate up to 99.6% duty cycle if the input
voltage drops close to or below the battery charge voltage
(drop out mode). The DC/DC converter has a timer to prevent
the frequency from dropping into the audible frequency range.
To prevent boosting of the system bus voltage, the battery
charger drives the lower FET in a way that prevents negative
inductor current.
9
An adaptive gate drive scheme is used to control the dead
time between two switches. The dead time control circuit
monitors the LGATE output and prevents the upper side
MOSFET from turning on until 20ns after LGATE falls below
1V VGS, preventing cross-conduction and shoot-through.
The same occurs for LGATE turn on. In order for the dead
time circuit to work properly, there must be a low resistance,
low inductance path from the LGATE driver to MOSFET
gate, and from the source of MOSFET to PGND. An internal
Schottky diode between the VDDP pin and BOOT pin keeps
the bootstrap capacitor charged.
AC Adapter Detection
Connect the AC adapter voltage through a resistor divider to
ACIN to detect when AC power is available, as shown in
Figure 2. ACOK is an open-drain output and is active low
when ACIN is less than Vth,fall, and high when ACIN is
above Vth,rise. The ACIN rising threshold is 3.2V (typ) with
57mV hysteresis.
Current Measurement
Use ICM to monitor the adapter current being sensed across
CSSP and CSSN. The output voltage range is 0 to 2.5V. The
voltage of ICM is proportional to the voltage drop across
CSSP and CSSN, and is given by Equation 1:
ICM = 20 ⋅ I INPUT ⋅ R S1
(EQ. 1)
where Iadapter is the DC current drawn from the AC adapter.
It is recommended to have an RC filter at the ICM output for
minimizing the switching noise.
VDDP Regulator
VDDP provides a 5.2V supply voltage from the internal LDO
regulator from DCIN and can deliver up to 30mA of
continuous current. The MOSFET drivers are powered by
VDDP. VDDP also supplies power to VCC through a low
pass filter as shown in the “TYPICAL APPLICATION
CIRCUIT” on page 2. Bypass VDDP and VCC with a 1µF
capacitor.
VDDSMB Supply
The VDDSMB input provides power to the SMBus interface.
Connect VDDSMB to VCC, or apply an external supply to
VDDSMB to keep the SMBus interface active while the
supply to DCIN is removed. When VDDSMB is biased the
internal registers are maintained. Bypass VDDSMB to GND
with a 0.1µF or greater ceramic capacitor.
Short Circuit Protection and 0V Battery Charging
Since the battery charger will regulate the charge current to
the limit set by the ChargeCurrent register, it automatically
has short circuit protection and is able to provide the charge
current to wake up an extremely discharged battery.
Undervoltage trickle charge folds back current if there is a
short circuit on the output.
FN9258.0
November 20, 2006
ISL88731
Undervoltage Detect and Battery Trickle Charging
If the voltage at CSON falls below 2.5V ISL88731 reduces
the charge current limit to 128mA to trickle charge the
battery. When the voltage rises above 2.7V the charge
current reverts to the programmed value in the
ChargeCurrent register.
The STOP condition is a LOW to HIGH transition on the SDA
line while SCL is HIGH. A STOP condition must be sent before
each START condition.
SDA
Over Temperature Protection
If the die temp exceeds +150°C, it stops charging. Once the
die temp drops below +125°C, charging will start up again.
SCL
The System Management Bus
The System Management Bus (SMBus) is a 2 wire bus that
supports bidirectional communications. The protocol is
described briefly here. More detail is available from
www.smbus.org.
General SMBus Architecture
VDDSMB
SMBus Slave
input
output
SMBus master
SCL
control
CPU
SDA
control
input
input
output
output
SCL
control
SDA
control
state
machine,
registers,
memory,
etc.
S
P
START
CONDITION
STOP
CONDITION
FIGURE 16. START AND STOP WAVEFORMS
Acknowledge
Each address and data transmission uses 9 clock pulses. The
ninth pulse is the acknowledge bit (ACK). After the start
condition, the master sends 7 slave address bits and a R/W bit
during the next 8 clock pulses. During the ninth clock pulse, the
device that recognizes its own address holds the data line low
to acknowledge. The acknowledge bit is also used by both the
master and the slave to acknowledge receipt of register
addresses and data as described below.
SCL
input
output
1
SMBus Slave
input
input
SDA
S CL
output
output
SCL
control
SDA
control
state
machine,
registers,
memory,
etc.
to other
slave devices
2
8
9
SDA
MSB
START
ACKNOWLEDGE
FROM SLAVE
FIGURE 17. ACKNOWLEDGE ON THE I2C BUS
SMBus Transactions
Data Validity
The data on the SDA line must be stable during the HIGH
period of the SCL, unless generating a START or STOP
condition. The HIGH or LOW state of the data line can only
change when the clock signal on the SCL line is LOW. Refer
to Figure 15.
SDA
SCL
DATA LINE CHANGE
STABLE
OF DATA
DATA VALID ALLOWED
FIGURE 15. DATA VALIDITY
All transactions start with a control byte sent from the SMBus
master device. The control byte begins with a Start condition,
followed by 7-bits of slave address (0001001 for the ISL88731)
followed by the R/W bit. The R/W bit is 0 for a write or 1 for a
read. If any slave devices on the SMBus bus recognize their
address, they will Acknowledge by pulling the serial data (SDA)
line low for the last clock cycle in the control byte. If no slaves
exist at that address or are not ready to communicate, the data
line will be 1, indicating a Not Acknowledge condition.
Once the control byte is sent, and the ISL88731
acknowledges it, the 2nd byte sent by the master must be a
register address byte such as 0x14 for the ChargeCurrent
register. The register address byte tells the ISL88731 which
register the master will write or read. See Table 1 for details
of the registers. Once the ISL88731 receives a register
address byte it responds with an acknowledge.
START and STOP Conditions
As shown in Figure 16, START condition is a HIGH to LOW
transition of the SDA line while SCL is HIGH.
10
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November 20, 2006
ISL88731
Write to a Register
S
SLAVE
ADDR + W
A
REGISTER
ADDR
LO BYTE
DATA
A
A
HI BYTE
DATA
A
A
LO BYTE
DATA
P
Read from a Register
S
SLAVE
ADDR + W
A
REGISTER
ADDR
A
P
S
SLAVE
ADDR + R
A
HI BYTE
DATA
N
P
S
Start
A
Acknowledge
Driven by the master
P
Stop
N
No Acknowledge
Driven by ISL88731
FIGURE 18. SMBus/ISL88731 READ AND WRITE PROTOCOL
Byte Format
Every byte put on the SDA line must be eight bits long and
must be followed by an acknowledge bit. Data is transferred
with the most significant bit first (MSB) and the least
significant bit last (LSB).
The data (SDA) and clock (SCL) pins have Schmitt-trigger
inputs that can accommodate slow edges. Choose pull-up
resistors for SDA and SCL to achieve rise times according to
the SMBus specifications. The ISL88731 is controlled by the
data written to the registers described in Table 1.
Battery Charger Registers
ISL88731 and SMBus
The ISL88731 receives control inputs from the SMBus
interface. The serial interface complies with the SMBus
protocols as documented in the System Management Bus
Specification V1.1, which can be downloaded from
www.smbus.org. The ISL88731 uses the SMBus Read-Word
and Write-Word protocols (Figure 18) to communicate with
the smart battery. The ISL88731 is an SMBus slave device
and does not initiate communication on the bus. It responds
to the 7-bit address 0b0001001_ (0x12).
Read address = 0b00010011 and
Write address = 0b00010010.
In addition, the ISL88731 has two identification (ID)
registers: a 16-bit device ID register and a 16-bit
manufacturer ID register.
The ISL88731 supports five battery-charger registers that
use either Write-Word or Read-Word protocols, as
summarized in Table 1. ManufacturerID and DeviceID are
“read only” registers and can be used to identify the
ISL88731. On the ISL88731, ManufacturerID always returns
0x0049 (ASCII code for “I” for Intersil) and DeviceID always
returns 0x0001.
Enabling and Disabling Charging
After applying power to ISL88731, the internal registers
contain their POR values (see Table 1). The POR values for
charge current and charge voltage are 0x0000. These
values disable charging. To enable charging, the
ChargeCurrent register must be written with a number
>0x007F and the ChargeVoltage register must be written
with a number >0x000F. Charging can be disabled by writing
0x0000 to either of these registers.
TABLE 1. BATTERY CHARGER REGISTOR SUMMARY
REGISTER
ADDRESS
REGISTER NAME
READ/WRITE
DESCRIPTION
POR STATE
0x14
ChargeCurrent
Read or Write
6-Bit Charge Current Setting
0x0000
0x15
ChargeVoltage
Read or Write
11-Bit Charge Voltage Setting
0x0000
0x3F
InputCurrent
Read or Write
6-Bit Charge Current Setting
0x0080
0xFE
ManufacturerID
Read Only
Manufacturer ID
0x0049
0xFF
DeviceID
Read Only
Device ID
0x0001
11
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ISL88731
Setting Charge Voltage
Charge voltage is set by writing a valid 16-bit number to the
ChargeVoltage register. This 16-bit number translates to a
65.535V full-scale voltage. The ISL88731 ignores the first 4
LSBs and uses the next 11 bits to set the voltage DAC. The
charge voltage range of the ISL88731 is 1.024V to 19.200V.
Numbers requesting charge voltage greater than 19.200V
result in a ChargeVoltage of 19.200V. All numbers
requesting charge voltage below 1.024V result in a voltage
set point of zero, which terminates charging. Upon initial
power up or reset, the ChargeVoltage and ChargeCurrent
registers are reset to 0 and the charger remains shut down
until valid numbers are sent to the ChargeVoltage and
ChargeCurrent registers. Use the Write-Word protocol
(Figure 18) to write to the ChargeVoltage register. The
register address for ChargeVoltage is 0x15. The 16-bit
binary number formed by D15–D0 represents the charge
voltage set point in mV. However, the resolution of the
ISL88731 is 16mV because the D0–D3 bits are ignored as
shown in Table 2. The D15 bit is also ignored because it is
not needed to span the 1.024V to 19.2V range. Table 2
shows the mapping between the charge-voltage set point
and the 16-bit number written to the ChargeVoltage register.
The ChargeVoltage register can be read back to verify its
contents.
TABLE 2. CHARGEVOLTAGE (REGISTER 0x15)
BIT
BIT NAME
DESCRIPTION
0
Not used.
1
Not used.
2
Not used.
3
Not used.
4
Charge Voltage, DACV 0
0 = Adds 0mV of charger voltage, 1024mV min.
1 = Adds 16mV of charger voltage.
5
Charge Voltage, DACV 1
0 = Adds 0mV of charger voltage, 1024mV min.
1 = Adds 32mV of charger voltage.
6
Charge Voltage, DACV 2
0 = Adds 0mV of charger voltage, 1024mV min.
1 = Adds 64mV of charger voltage.
7
Charge Voltage, DACV 3
0 = Adds 0mV of charger voltage, 1024mV min.
1 = Adds 128mV of charger voltage.
8
Charge Voltage, DACV 4
0 = Adds 0mV of charger voltage, 1024mV min.
1 = Adds 256mV of charger voltage.
9
Charge Voltage, DACV 5
0 = Adds 0mV of charger voltage, 1024mV min.
1 = Adds 512mV of charger voltage.
10
Charge Voltage, DACV 6
0 = Adds 0mA of charger voltage.
1 = Adds 1024mV of charger voltage.
11
Charge Voltage, DACV 7
0 = Adds 0mV of charger voltage.
1 = Adds 2048mV of charger voltage.
12
Charge Voltage, DACV 8
0 = Adds 0mV of charger voltage.
1 = Adds 4096mV of charger voltage.
13
Charge Voltage, DACV 9
0 = Adds 0mV of charger voltage.
1 = Adds 8192mV of charger voltage.
14
Charge Voltage, DACV 10
0 = Adds 0mV of charger voltage.
1 = Adds 16384mV of charger voltage, 19200mV max.
15
Not used. Normally a 32768mV weight.
12
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ISL88731
Setting Charge Current
ISL88731 has a 16-bit ChargeCurrent register that sets the
battery charging current. ISL88731 controls the charge
current by controlling the CSOP-CSON voltage. The
register’s LSB translates to 10µV at CSON-CSOP. With a
10mΩ charge current Rsense resistor (RS2 in “TYPICAL
APPLICATION CIRCUIT” on page 2), the LSB translates to
1mA charge current. The ISL88731 ignores the first 7 LSBs
and uses the next 6 bits to control the current DAC. The
charge-current range of the ISL88731 is 0 to 8.064A (using a
10mΩ current-sense resistor). All numbers requesting
charge current above 8.064A result in a current setting of
8.064A. All numbers requesting charge current between
0mA to 128mA result in a current setting of 0mA. The default
charge current setting at Power-On Reset (POR) is 0mA. To
stop charging, set ChargeCurrent to 0. Upon initial power up,
the ChargeVoltage and ChargeCurrent registers are reset to
0 and the charger is disabled. To start the charger, write valid
numbers to the ChargeVoltage and ChargeCurrent registers.
The ChargeCurrent register uses the Write-Word protocol
(Figure 18). The register code for ChargeCurrent is 0x14
(0b00010100). Table 3 shows the mapping between the
charge current set point and the ChargeCurrent number. The
ChargeCurrent register can be read back to verify its
contents.
The ISL88731 includes a fault limiter for low battery
conditions. If the battery voltage is less than 2.5V, the charge
current is temporarily set to 128mA. The ChargeCurrent
register is preserved and becomes active again when the
battery voltage is higher than 2.7V. This function effectively
provides a foldback current limit, which protects the charger
during short circuit and overload.
TABLE 3. CHARGE CURRENT (REGISTER 0x14) (10mΩ SENSE RESISTOR, RS2)
BIT
BIT NAME
DESCRIPTION
0
Not used.
1
Not used.
2
Not used.
3
Not used.
4
Not used.
5
Not used.
6
Not used.
7
Charge Current, DACI 0
0 = Adds 0mA of charger current.
1 = Adds 128mA of charger current.
8
Charge Current, DACI 1
0 = Adds 0mA of charger current.
1 = Adds 256mA of charger current.
9
Charge Current, DACI 2
0 = Adds 0mA of charger current.
1 = Adds 512mA of charger current.
10
Charge Current, DACI 3
0 = Adds 0mA of charger current.
1 = Adds 1024mA of charger current.
11
Charge Current, DACI 4
0 = Adds 0mA of charger current.
1 = Adds 2048mA of charger current.
12
Charge Current, DACI 5
0 = Adds 0mA of charger current.
1 = Adds 4096mA of charger current, 8064mA max.
13
Not used.
14
Not used.
15
Not used.
13
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ISL88731
Setting Input-Current Limit
The total power from an AC adapter is the sum of the power
supplied to the system and the power into the charger and
battery. When the input current exceeds the set input current
limit, the ISL88731 decreases the charge current to provide
priority to system load current. As the system load rises, the
available charge current drops linearly to zero. Thereafter, the
total input current can increase to the limit of the AC adapter.
The internal amplifier compares the differential voltage
between CSSP and CSSN to a scaled voltage set by the
InputCurrent register. The total input current is the sum of
the device supply current, the charger input current, and the
system load current. The total input current can be estimated
as follows:
I INPUT = I SYSTEM + [ ( I CHARGE × V BATTERY ) ⁄ ( V IN × η ) ]
(EQ. 2)
Where η is the efficiency of the DC/DC converter (typically
85% to 95%).
The ISL88731 has a 16-bit InputCurrent register that
translates to a 2mA LSB and a 131.071A full scale current
using a 10mΩ current-sense resistor (RS1 in Figure 2).
Equivalently, the 16-bit InputCurrent number sets the voltage
across CSSP and CSSN inputs in 20µV per LSB increments.
To set the input current limit use the SMBus to write a 16-bit
InputCurrent register using the data format listed in Table 4.
The InputCurrent register uses the Write-Word protocol (see
Figure 18). The register code for InputCurrent is 0x3F
(0b00111111). The InputCurrent register can be read back to
verify its contents.
The ISL88731 ignores the first 7 LSBs and uses the next
6 bits to control the input-current DAC. The input-current
range of the ISL88731 is from 256mA to 11.004A. All 16-bit
numbers requesting input current above 11.004A result in an
input-current setting of 11.004A. All 16-bit numbers
requesting input current between 0mA to 256mA result in an
input-current setting of 0mA. The default input-current-limit
setting at POR is 256mA. When choosing the current-sense
resistor RS1, carefully calculate its power rating. Take into
account variations in the system’s load current and the
overall accuracy of the sense amplifier. Note that the voltage
drop across RS1 contributes additional power loss, which
reduces efficiency. System currents normally fluctuate as
portions of the system are powered up or put to sleep.
Without input current regulation, the input source must be
able to deliver the maximum system current and the
maximum charger-input current. By using the input-currentlimit circuit, the output-current capability of the AC wall
adapter can be lowered, reducing system cost.
TABLE 4. INPUT CURRENT (REGISTER 0x3F) (10mΩ SENSE RESISTOR, RS1)
BIT
BIT NAME
DESCRIPTION
0
Not used.
1
Not used.
2
Not used.
3
Not used.
4
Not used.
5
Not used.
6
Not used.
7
Input Current, DACS 0
0 = Adds 0mA of input current.
1 = Adds 256mA of input current.
8
Input Current, DACS 1
0 = Adds 0mA of input current.
1 = Adds 512mA of input current.
9
Input Current, DACS 2
0 = Adds 0mA of input current.
1 = Adds 1024mA of input current.
10
Input Current, DACS 3
0 = Adds 0mA of input current.
1 = Adds 2048mA of input current.
11
Input Current, DACS 4
0 = Adds 0mA of input current.
1 = Adds 4096mA of input current.
12
Input Current, DACS 5
0 = Adds 0mA of input current.
1 = Adds 8192mA of input current, 11004mA max.
13
Not used.
14
Not used.
15
Not used.
14
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November 20, 2006
ISL88731
Charger Timeout
The ISL88731 includes 2 timers to insure the SMBus master
is active and to prevent over charging the battery. ISL88731
will terminate charging if the charger has not received a write
to the ChargeVoltage or ChargeCurrent register within 175s
or if the SCL line is low for more than 25ms. If a time-out
occurs, either ChargeVoltage or ChargeCurrent registers
must be written to re-enable charging.
ISL88731 Data Byte Order
Each register in ISL88731 contains 16-bits or 2, 8 bit bytes.
All data sent on the SMBus is in 8 bit bytes and 2 bytes must
be written or read from each register in ISL88731. The order
in which these bytes are transmitted appears reversed from
the way they are normally written. The LOW byte is sent first
and the HI byte is sent second. For example, When writing
0x41A0, 0xA0 is written first and 0x41 is sent second.
Writing to the Internal Registers
In order to set the charge current, charge voltage or input
current, valid 16-bit numbers must be written to ISL88731’s
internal registers via the SMBus.
To write to a register in the ISL88731, the master sends a
control byte with the R/W bit set to 0, indicating a write. If it
receives an Acknowledge from the ISL88731 it sends a
register address byte setting the register to be written (i.e.
0x14 for the ChargeCurrent register). The ISL88731 will
respond with an Acknowledge. The master then sends the
lower data byte to be written into the desired register. The
ISL88731 will respond with an Acknowledge. The master
then sends the higher data byte to be written into the desired
register. The ISL88731 will respond with an Acknowledge.
The master then issues a Stop condition, indicating to the
ISL88731 that the current transaction is complete. Once this
transaction completes the ISL88731 will begin operating at
the new current or voltage.
ISL88731 does not support writing more than one register
per transaction
Reading from the Internal Registers
The ISL88731 has the ability to read from 5 internal registers.
Prior to reading from an internal register, the master must first
select the desired register by writing to it and sending the
registers address byte. This process begins by the master
sending a control byte with the R/W bit set to 0, indicating a
write. Once it receives an Acknowledge from the ISL88731 it
sends a register address byte representing the internal
register it wants to read. The ISL88731 will respond with an
Acknowledge. The master must then respond with a Stop
condition. After the Stop condition the master follows with a
new Start condition, then sends a new control byte with the
ISL88731 slave address and the R/W bit set to 1, indicating a
read. The ISL88731 will Acknowledge then send the lower
byte stored in that register. After receiving the byte, the master
15
Acknowledges by holding SDA low during the 9th clock pulse.
ISL88731 then sends the higher byte stored in the register.
After the second byte neither device holds SDA low (No
Acknowledge). The master will then produce a Stop condition
to end the read transaction.
ISL88731 does not support reading more than 1 register per
transaction.
Application Information
The following battery charger design refers to the “TYPICAL
APPLICATION CIRCUIT” on page 2, where typical battery
configuration of 3S2P is used. This section describes how to
select the external components including the inductor, input
and output capacitors, switching MOSFETs and current
sensing resistors.
Inductor Selection
The inductor selection has trade-offs between cost, size,
cross over frequency and efficiency. For example, the lower
the inductance, the smaller the size, but ripple current is
higher. This also results in higher AC losses in the magnetic
core and the windings, which decreases the system
efficiency. On the other hand, the higher inductance results
in lower ripple current and smaller output filter capacitors,
but it has higher DCR (DC resistance of the inductor) loss,
lower saturation current and has slower transient response.
So, the practical inductor design is based on the inductor
ripple current being ±15% to ±20% of the maximum
operating DC current at maximum input voltage. Maximum
ripple is at 50% duty cycle or VBAT = VIN,MAX/2. The
required inductance for ±15% ripple current can be
calculated from Equation 3:
V IN, MAX
L = --------------------------------------------------------4 ⋅ F SW ⋅ 0.3 ⋅ I L, MAX
(EQ. 3)
Where VIN,MAX is the maximum input voltage, FSW is the
switching frequency and IL,MAX is the max DC current in the
inductor.
For VIN,MAX = 20V, VBAT = 12.6V, IBAT,MAX = 4.5A, and
fs = 400kHz, the calculated inductance is 9.3µH. Choosing
the closest standard value gives L = 10µH. Ferrite cores are
often the best choice since they are optimized at 400kHz to
600kHz operation with low core loss. The core must be large
enough not to saturate at the peak inductor current IPeak in
Equation 4:
1
I PEAK = I L, MAX + --- ⋅ I RIPPLE
2
(EQ. 4)
Inductor saturation can lead to cascade failures due to very
high currents. Conservative design limits the peak and RMS
current in the inductor to less than 90% of the rated
saturation current.
Cross over frequency is heavily dependent on the inductor
value. FCO should be less than 20% of the switching
frequency and a conservative design has FCO less than
FN9258.0
November 20, 2006
ISL88731
10% of the switching frequency. The highest FCO is in
voltage control mode with the battery removed and may be
calculated (approximately) from Equation 5:
5 ⋅ 11 ⋅ R SENSE
F CO = ------------------------------------------2π ⋅ L
(EQ. 5)
Output Capacitor Selection
The output capacitor in parallel with the battery is used to
absorb the high frequency switching ripple current and
smooth the output voltage. The RMS value of the output
ripple current Irms is given by Equation 6:
V IN, MAX
I RMS = ----------------------------------- ⋅ D ⋅ ( 1 – D )
12 ⋅ L ⋅ F SW
(EQ. 6)
Where the duty cycle D is the ratio of the output voltage
(battery voltage) over the input voltage for continuous
conduction mode which is typical operation for the battery
charger. During the battery charge period, the output voltage
varies from its initial battery voltage to the rated battery
voltage. So, the duty cycle varies from 0.53 for the minimum
battery voltage of 7.5V (2.5V/Cell) to 0.88 for the maximum
battery voltage of 12.6V. The maximum RMS value of the
output ripple current occurs at the duty cycle of 0.5 and is
expressed as Equation 7:
V IN, MAX
I RMS = ------------------------------------------4 ⋅ 12 ⋅ L ⋅ F SW
(EQ. 7)
For VIN,MAX = 19V, VBAT = 16.8V, L = 10µH, and
fs = 400kHz, the maximum RMS current is 0.19A. A typical
20μF ceramic capacitor is a good choice to absorb this
current and also has very small size. Organic polymer
capacitors have high capacitance with small size and have a
significant equivalent series resistance (ESR). Although
ESR adds to ripple voltage, it also creates a high frequency
zero that helps the closed loop operation of the buck
regulator.
EMI considerations usually make it desirable to minimize
ripple current in the battery leads. Beads may be added in
series with the battery pack to increase the battery
impedance at 400kHz switching frequency. Switching ripple
current splits between the battery and the output capacitor
depending on the ESR of the output capacitor and battery
impedance. If the ESR of the output capacitor is 10mΩ and
battery impedance is raised to 2Ω with a bead, then only
0.5% of the ripple current will flow in the battery.
MOSFET Selection
The Notebook battery charger synchronous buck converter
has the input voltage from the AC adapter output. The
maximum AC adapter output voltage does not exceed 25V.
Therefore, 30V logic MOSFET should be used.
The high side MOSFET must be able to dissipate the
conduction losses plus the switching losses. For the battery
charger application, the input voltage of the synchronous
16
buck converter is equal to the AC adapter output voltage,
which is relatively constant. The maximum efficiency is
achieved by selecting a high side MOSFET that has the
conduction losses equal to the switching losses. Switching
losses in the low-side FET are very small. The choice of
low-side FET is a trade-off between conduction losses
(rDS(ON)) and cost. A good rule of thumb for the rDS(ON) of
the low-side FET is 2X the rDS(ON) of the high-side FET.
The LGATE gate driver can drive sufficient gate current to
switch most MOSFETs efficiently. However, some FETs may
exhibit cross conduction (or shoot-through) due to current
injected into the drain-to-source parasitic capacitor (Cgd) by
the high dV/dt rising edge at the phase node when the high
side MOSFET turns on. Although LGATE sink current (1.8A
typical) is more than enough to switch the FET off quickly,
voltage drops across parasitic impedances between LGATE
and the MOSFET can allow the gate to rise during the fast
rising edge of voltage on the drain. MOSFETs with low
threshold voltage (<1.5V) and low ratio of Cgs/Cgd (<5) and
high gate resistance (>4Ω) may be turned on for a few ns by
the high dV/dt (rising edge) on their drain. This can be
avoided with higher threshold voltage and Cgs/Cgd ratio.
Another way to avoid cross conduction is slowing the turn-on
speed of the high-side MOSFET by connecting a resistor
between the BOOT pin and the boot strap cap.
For the high-side MOSFET, the worst-case conduction
losses occur at the minimum input voltage, as shown in
Equation 8:
V OUT
2
P Q1, conduction = ---------------- ⋅ I BAT ⋅ r DS ( ON )
V IN
(EQ. 8)
The optimum efficiency occurs when the switching losses
equal the conduction losses. However, it is difficult to
calculate the switching losses in the high-side MOSFET
since it must allow for difficult-to-quantify factors that
influence the turn-on and turn-off times. These factors
include the MOSFET internal gate resistance, gate charge,
threshold voltage, stray inductance and the pull-up and pulldown resistance of the gate driver.
The following switching loss calculation (Equation 9)
provides a rough estimate.
P Q1, Switching =
⎛ Q gd ⎞ 1
⎛ Q gd ⎞
1
-⎟ + --- V IN I LP f sw ⎜ ----------------⎟ + Q rr V IN f sw
--- V IN I LV f sw ⎜ -----------------------I
2
2
⎝ g, source⎠
⎝ I g, sin k⎠
(EQ. 9)
where the following are the peak gate-drive source/sink
current of Q1, respectively:
• Qgd: drain-to-gate charge,
• Qrr: total reverse recovery charge of the body-diode in
low-side MOSFET,
• ILV: inductor valley current,
• ILP: Inductor peak current,
• Ig,sink
• Ig,source
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November 20, 2006
ISL88731
Low switching loss requires low drain-to-gate charge Qgd.
Generally, the lower the drain-to-gate charge, the higher the
on-resistance. Therefore, there is a trade-off between the
on-resistance and drain-to-gate charge. Good MOSFET
selection is based on the Figure of Merit (FOM), which is a
product of the total gate charge and on-resistance. Usually,
the smaller the value of FOM, the higher the efficiency for
the same application.
For the low-side MOSFET, the worst-case power dissipation
occurs at minimum battery voltage and maximum input
voltage (Equation 10):
V OUT⎞
⎛
2
P Q2 = ⎜ 1 – ----------------⎟ ⋅ I BAT ⋅ r DS ( ON )
V IN ⎠
⎝
(EQ. 10)
Choose a low-side MOSFET that has the lowest possible
on-resistance with a moderate-sized package like the SO-8
and is reasonably priced. The switching losses are not an
issue for the low-side MOSFET because it operates at
zero-voltage-switching.
Ensure that the required total gate drive current for the
selected MOSFETs should be less than 24mA. So, the total
gate charge for the high-side and low-side MOSFETs is
limited by Equation 11:
I GATE
Q GATE ≤ ----------------f sw
(EQ. 11)
Where IGATE is the total gate drive current and should be
less than 24mA. Substituting IGATE = 24mA and fs = 400kHz
into the above equation yields that the total gate charge
should be less than 80nC. Therefore, the ISL88731 easily
drives the battery charge current up to 8A.
Snubber Design
ISL88731's buck regulator operates in discontinuous current
mode (DCM) when the load current is less than half the
peak-to-peak current in the inductor. After the low-side FET
turns off, the phase voltage rings due to the high impedance
with both FETs off. This can be seen in Figure 9. Adding a
snubber (resistor in series with a capacitor) from the phase
node to ground can greatly reduce the ringing. In some
situations a snubber can improve output ripple and
regulation.
The snubber capacitor should be approximately twice the
parasitic capacitance on the phase node. This can be
estimated by operating at very low load current (100mA) and
measuring the ringing frequency.
CSNUB and RSNUB can be calculated from Equations 12
and 13:
2
C SNUB = ------------------------------------2
( 2πF ring ) ⋅ L
R SNUB =
2⋅L
-------------------C SNUB
(EQ. 13)
(EQ. 12)
17
Input Capacitor Selection
The input capacitor absorbs the ripple current from the
synchronous buck converter, which is given by Equation 14:
Irms = IBAT
VOUT (VIN − VOUT )
VIN
(EQ. 14)
This RMS ripple current must be smaller than the rated RMS
current in the capacitor datasheet. Non-tantalum chemistries
(ceramic, aluminum, or OSCON) are preferred due to their
resistance to power-up surge currents when the AC adapter
is plugged into the battery charger. For Notebook battery
charger applications, it is recommended that ceramic
capacitors or polymer capacitors from Sanyo be used due to
their small size and reasonable cost.
Loop Compensation Design
ISL88731 has three closed loop control modes. One controls
the output voltage when the battery is fully charged or
absent. A second controls the current into the battery when
charging and the third limits current drawn from the adapter.
The charge current and input current control loops are
compensated by a single capacitor on the ICOMP pin. The
voltage control loop is compensated by a network on the
VCOMP pin. Descriptions of these control loops and
guidelines for selecting compensation components will be
given in the following sections. Which loop controls the
output is determined by the minimum current buffer and the
minimum voltage buffer shown in the Block Diagram. These
three loops will be described separately.
Transconductance Amplifiers GMV, GMI and GMS
ISL88731 uses several transconductance amplifiers (also
known as gm amps). Most commercially available op amps
are voltage controlled voltage sources with gain expressed
as A = VOUT/VIN. gm amps are voltage controlled current
sources with gain expressed as gm = IOUT/VIN. gm will
appear in some of the equations for poles and zeros in the
compensation.
PWM Gain Fm
The Pulse Width Modulator in the ISL88731 converts voltage
at VCOMP to a duty cycle by comparing VCOMP to a
triangle wave (duty = VCOMP/VPP RAMP). The low-pass
filter formed by L and CO convert the duty cycle to a DC
output voltage (Vo = VDCIN*duty). In ISL88731, the triangle
wave amplitude is proportional to VDCIN. Making the ramp
amplitude proportional to DCIN makes the gain from
VCOMP to the PHASE output a constant 11 and is
independent of DCIN. For small signal AC analysis, the
battery is modeled by its internal resistance. The total output
resistance is the sum of the sense resistor and the internal
resistance of the MOSFETs, inductor and capacitor.
Figure19 shows the small signal model of the pulse width
modulator (PWM), power stage, output filter and battery.
FN9258.0
November 20, 2006
ISL88731
11
RAMP GEN
VRAMP = VDD/11
+
RL_DCR
RFET_RDSON
L
DRIVERS
-
L
PHASE
VDD
Σ
SΣ
CO
PWM
INPUT
+
CA2
+
0.25
-
20X
GMI
GMI
+
+
CF2
F2
-
DACI
DACI
C
CICOMP
ICOMP
PWM
GAIN=11
L
RS2
S2
CSON
-
ICOMP
RF2
CSOP
CO
C
O
RBAT
R
BAT
RESR
R
ESR
FIGURE 20. CHARGE CURRENT LIMIT LOOP
RSENSE
11
RL_DCR
RFET_RDSON
PWM
INPUT
CO
RBAT
RESR
frequency (smaller CICOMP), the DC gain will be higher but
the phase margin will be lower. Us a capacitor on ICOMP
that is equal to or greater than the value calculated in
Equation 18. The factor of 1.5 is to ensure the zero is at a
frequency lower than the pole including tolerance variations.
FIGURE 19. SMALL SIGNAL AC MODEL
In most cases the Battery resistance is very small (<200mΩ)
resulting in a very low Q in the output filter. This results in a
frequency response from the input of the PWM to the
inductor current with a single pole at the frequency
calculated in Equation 15:
( R SENSE + r DS ( ON ) + R DCR + R BAT )
F POLE1 = ------------------------------------------------------------------------------------------------------2π ⋅ L
(EQ. 15)
The output capacitor creates a pole at a very high frequency
due to the small resistance in parallel with it. The frequency
of this pole is calculated in Equation 16:
1
F POLE2 = --------------------------------------2π ⋅ C o ⋅ R BAT
(EQ. 16)
Charge Current Control Loop
1.5 ⋅ 4 ⋅ ( 50μA ⁄ V ) ⋅ L
C ICOMP = ------------------------------------------------------------------------------------------------------( R SENSE + r DS ( ON ) + R DCR + R BAT )
(EQ. 18)
A filter should be added between RS2 and CSOP and CSON
to reduce switching noise. The filter roll-off frequency should
be between the cross over frequency and the switching
frequency (~100kHz). RF2 should be small (<10Ω) to
minimize offsets due to leakage current into CSOP. The filter
cut off frequency is calculated using Equation 19:
1
F FILTER = ------------------------------------------( 2π ⋅ C F2 ⋅ R F2 )
(EQ. 19)
The cross over frequency is determined by the DC gain of
the modulator and output filter and the pole in Equation 16.
The DC gain is calculated in Equation 20 and the cross over
frequency is calculated with Equation 21:
When the battery is less than the fully charged, the voltage
error amplifier goes to it’s maximum output (limited to 0.3V
above ICOMP) and the ICOMP voltage controls the loop
through the minimum voltage buffer. Figure 21 shows the
charge current control loop.
11 ⋅ R SENSE
A DC = ------------------------------------------------------------------------------------------------------( R SENSE + r DS ( ON ) + R DCR + R BAT )
The compensation capacitor (CICOMP) gives the error
amplifier (GMI) a pole at a very low frequency (<<1Hz) and a
a zero at FZ1. FZ1 is created by the 0.25*CA2 output added to
ICOMP. The frequency can be calculated from Equation 17:
The Bode plot of the loop gain, the compensator gain and
the power stage gain is shown in Figure 21.
4 ⋅ gm2
F ZERO = --------------------------------------( 2π ⋅ C ICOMP )
gm2 = 50μA ⁄ V
(EQ. 17)
Placing this zero at a frequency equal to the pole calculated
in Equation 16 will result in maximum gain at low frequencies
and phase margin near 90°. If the zero is at a higher
18
11 ⋅ R SENSE
F CO = A DC ⋅ F POLE = ----------------------------------2π ⋅ L
(EQ. 20)
(EQ. 21)
Adapter Current Limit Control Loop
If the combined battery charge current and system load
current draws current that equals the adapter current limit
set by the InputCurrent register, ISL88731 will reduce the
current to the battery and/or reduce the output voltage to
hold the adapter current at the limit. Above the adapter
current limit the minimum current buffer equals the output of
GMS and ICOMP controls the charger output. Figure 22
shows the adapter current limit control loop.
FN9258.0
November 20, 2006
ISL88731
60
40
Compensator
Modulator
Loop
F
ZERO
GAIN (dB)
20
0
-20
F
F
POLE1
takes control of the output (assuming that the adapter
current is below the limit set by ACLIM). The voltage error
amplifier (GMV) discharges the cap on VCOMP to limit the
output voltage. The current to the battery decreases as the
cells charge to the fixed voltage and the voltage across the
internal battery resistance decreases. As battery current
decreases the 2 current error amplifiers (GMI and GMS)
output their maximum current and charge the capacitor on
ICOMP to its maximum voltage (limited to 0.3V above
VCOMP). With high voltage on ICOMP, the minimum voltage
buffer output equals the voltage on VCOMP.
The voltage control loop is shown in Figure 23.
FILTER
-40
F
L
PHASE
POLE2
11
-60
0.01
0.1
1
10
100
RL_DCR
RFET_RDSON
1000
FREQUENCY (kHz)
FIGURE 21. CHARGE CURRENT LOOP BODE PLOTS
Σ
S
CA2
+
-
DCIN
RF2
CSOP
+
0.25
20X
CF2
-
RS2
CSON
L
PHASE
RS1
VCOMP
11
RFET_RDSON
RF1
R3
-
CO
GMV
RL_DCR
+
R4
CVCOMP
CF1
+
SΣ
CSSN
CSSP
CA2
-
20X
CF2
-
RS2
CSON
- 20
+
RVCOMP
+
0.25
FIGURE 23. VOLTAGE CONTROL LOOP
CO
CA1
RBAT
RESR
-
GMS
ICOMP
+
DACS
CICOMP
FIGURE 22. ADAPTER CURRENT LIMIT LOOP
The loop response equations, bode plots and the selection
of CICOMP are the same as the charge current control loop
with loop gain reduced by the duty cycle and the ratio of
RS1/RS2. In other words, if RS1 = RS2 and the duty cycle
D = 50%, the loop gain will be 6dB lower than the loop gain
in Figure 22. This gives lower crossover frequency and
higher phase margin in this mode. If RS1/RS2 = 2 and the
duty cycle is 50% then the adapter current loop gain will be
identical to the gain in Figure 22.
A filter should be added between RS1 and CSIP and CSIN to
reduce switching noise. The filter roll off frequency should be
between the cross over frequency and the switching
frequency (~100kHz).
Voltage Control Loop
When the battery is charged to the voltage set by
ChargeVoltage register the voltage error amplifier (GMV)
19
RESR
DACV
RF2
CSOP
RBAT
Output LC Filter Transfer Functions
The gain from the phase node to the system output and
battery depend entirely on external components. Typical
output LC filter response is shown in Figure 24. Transfer
function ALC(s) is shown in Equation 22:
s ⎞
⎛ 1 – --------------⎝
ω ESR⎠
A LC = ----------------------------------------------------------⎛ s2
⎞
s
⎜ ------------ + ------------------------- + 1⎟
⎝ ω DP ( ω LC ⋅ Q )
⎠
1
ω ESR = --------------------------------( R ESR ⋅ C o )
1
ω LC = -----------------------( L ⋅ Co )
L
Q = R o ⋅ ------Co
(EQ. 22)
The resistance RO is a combination of MOSFET rDS(ON),
inductor DCR, RSENSE and the internal resistance of the
battery (normally between 50mΩ and 200mΩ) The worst
case for voltage mode control is when the battery is absent.
This results in the highest Q of the LC filter and the lowest
phase margin.
The compensation network consists of the voltage error
amplifier GMV and the compensation network RVCOMP,
CVCOMP which give the loop very high DC gain, a very low
frequency pole and a zero at FZERO1. Inductor current
FN9258.0
November 20, 2006
ISL88731
information is added to the feedback to create a second zero
FZERO2. The low pass filter RF2, CF2 between RS2 and
ISL88731 add a pole at FFILTER. R3 and R4 are internal
divider resistors that set the DC output voltage. For a 3 cell
battery, R3 = 500kΩ and R4 = 100kΩ. The equations
following relate the compensation network’s poles, zeros
and gain to the components in Figure 23. Figure 25 shows
an asymptotic Bode plot of the DC/DC converter’s gain vs.
frequency. It is strongly recommended that FZERO1 is
approximately 30% of FLC and FZERO2 is approximately 70%
of FLC.
GAIN (dB)
NO BATTERY
RBATTERY
= 200mΩ
RBATTERY
= 50mΩ
Compensation Break Frequency Equations
1
F ZERO1 = ----------------------------------------------------------------------( 2π ⋅ C VCOMP ⋅ R 1COMP )
(EQ. 23)
R VCOMP
⎛
⎞ ⎛ R 4 ⎞ gm1
F ZERO2 = ⎜ -----------------------------------------------⎟ ⋅ ⎜ ---------------------⎟ ⋅ ⎛ ------------⎞
⎝ 2π ⋅ R SENSE ⋅ C o⎠ ⎝ R 4 + R 3⎠ ⎝ 5 ⎠
(EQ. 24)
1
F LC = ------------------------------( 2π L ⋅ C o )
(EQ. 25)
1
F FILTER = ------------------------------------------( 2π ⋅ R F2 ⋅ C F2 )
(EQ. 26)
1
F POLE1 = ---------------------------------------------------( 2π ⋅ R SENSE ⋅ C o )
(EQ. 27)
1
F ESR = -------------------------------------------( 2π ⋅ C o ⋅ R ESR )
(EQ. 28)
Choose RVCOMP equal or lower than the value calculated
from Equation 29.
⎛ R 3 + R 4⎞
5
R VCOMP = ( 0.7 ⋅ F LC ) ⋅ ( 2π ⋅ C o ⋅ R SENSE ) ⋅ ⎛ ------------⎞ ⋅ ⎜ ---------------------⎟
⎝ gm1⎠ ⎝ R
4 ⎠
(EQ. 29)
PHASE (°)
Next choose CVCOMP equal or higher than the value
calculated from Equation 30.
1
C VCOMP = --------------------------------------------------------------------------( 0.3 ⋅ F LC ) ⋅ ( 2π ⋅ R VCOMP )
PCB Layout Considerations
FREQUENCY
FIGURE 24. FREQUENCY RESPONSE OF THE LC OUTPUT
FILTER
Power and Signal Layers Placement on the PCB
As a general rule, power layers should be close together,
either on the top or bottom of the board, with signal layers on
the opposite side of the board. As an example, layer
arrangement on a 4-layer board is shown below:
60
Compensator
1. Top Layer: signal lines, or half board for signal lines and
the other half board for power lines
Modulator
Loop
40
FPOLE1
F
2. Signal Ground
LC
20
GAIN (dB)
(EQ. 30)
3. Power Layers: Power Ground
4. Bottom Layer: Power MOSFET, Inductors and other
Power traces
0
Separate the power voltage and current flowing path from
the control and logic level signal path. The controller IC will
stay on the signal layer, which is isolated by the signal
ground to the power signal traces.
FFILTER
-20
F
ZERO1
-40
F
ZERO2
Component Placement
F
ESR
-60
0.1
1
10
100
1000
FREQUENCY (kHz)
FIGURE 25. ASYMPTOTIC BODE PLOT OF THE VOLTAGE
CONTROL LOOP GAIN
20
The power MOSFET should be close to the IC so that the
gate drive signal, the LGATE, UGATE, PHASE, and BOOT,
traces can be short.
Place the components in such a way that the area under the
IC has less noise traces with high dv/dt and di/dt, such as
gate signals and phase node signals.
FN9258.0
November 20, 2006
ISL88731
Signal Ground and Power Ground Connection
CSOP, CSON, CSSP and CSSN Pins
At minimum, a reasonably large area of copper, which will
shield other noise couplings through the IC, should be used
as signal ground beneath the IC. The best tie-point between
the signal ground and the power ground is at the negative
side of the output capacitor on each side, where there is little
noise; a noisy trace beneath the IC is not recommended.
Accurate charge current and adapter current sensing is
critical for good performance. The current sense resistor
connects to the CSON and the CSOP pins through a low
pass filter with the filter cap very near the IC (see Figure 2).
Traces from the sense resister should start at the pads of the
sense resister and should be routed close together, through
the low pass filter and to the CSOP and CSON pins (see
Figure 26). The CSON pin is also used as the battery voltage
feedback. The traces should be routed away from the high
dv/dt and di/dt pins like PHASE, BOOT pins. In general, the
current sense resistor should be close to the IC. These
guidelines should also be followed for the adapter current
sense resister and CSSP and CSSN. Other layout
arrangements should be adjusted accordingly.
GND and VCC Pin
At least one high quality ceramic decoupling cap should be
used to cross these two pins. The decoupling cap can be put
close to the IC.
LGATE Pin
This is the gate drive signal for the bottom MOSFET of the
buck converter. The signal going through this trace has both
high dv/dt and high di/dt, and the peak charging and
discharging current is very high. These two traces should be
short, wide, and away from other traces. There should be no
other traces in parallel with these traces on any layer.
DCIN Pin
This pin connects to AC adapter output voltage, and should
be less noise sensitive.
Copper Size for the Phase Node
PGND Pin
PGND pin should be laid out to the negative side of the
relevant output cap with separate traces.The negative side
of the output capacitor must be close to the source node of
the bottom MOSFET. This trace is the return path of LGATE.
The capacitance of PHASE should be kept very low to
minimize ringing. It would be best to limit the size of the
PHASE node copper in strict accordance with the current
and thermal management of the application.
Identify the Power and Signal Ground
PHASE Pin
This trace should be short, and positioned away from other
weak signal traces. This node has a very high dv/dt with a
voltage swing from the input voltage to ground. No trace
should be in parallel with it. This trace is also the return path
for UGATE. Connect this pin to the high-side MOSFET
source.
UGATE Pin
This pin has a square shape waveform with high dv/dt. It
provides the gate drive current to charge and discharge the
top MOSFET with high di/dt. This trace should be wide,
short, and away from other traces, similar to the LGATE.
The input and output capacitors of the converters, the source
terminal of the bottom switching MOSFET PGND should
connect to the power ground. The other components should
connect to signal ground. Signal and power ground are tied
together at one point.
Clamping Capacitor for Switching MOSFET
It is recommended that ceramic caps be used closely
connected to the drain of the high-side MOSFET, and the
source of the low-side MOSFET. This capacitor reduces the
noise and the power loss of the MOSFET.
BOOT Pin
This pin’s di/dt is as high as the UGATE; therefore, this trace
should be as short as possible.
HIGH
CURRENT
TRACE
SENSE
RESISTER
HIGH
CURRENT
TRACE
KELVIN CONNECTION TRACES
TO THE LOW PASS FILTER AND
CSOP AND CSON
FIGURE 26. CURRENT SENSE RESISTOR LAYOUT
21
FN9258.0
November 20, 2006
ISL88731
Thin Quad Flat No-Lead Plastic Package (TQFN)
Thin Micro Lead Frame Plastic Package (TMLFP)
2X
28 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220WHHD-1 ISSUE I)
0.15 C A
D
A
9
MILLIMETERS
D/2
D1
D1/2
2X
N
6
INDEX
AREA
L28.5x5B
0.15 C B
1
2
3
E1/2
E/2
E1
SYMBOL
MIN
0.70
0.75
0.80
-
-
0.02
0.05
-
A2
-
0.55
0.80
9
b
0.20 REF
0.20
0.15 C B
2X
4X
B
TOP VIEW
0.15 C A
D2
A2
0
A
SEATING PLANE
A1
A3
SIDE VIEW
9
5
NX b
0.10 M C A B
4X P
D2
(DATUM B)
8
7
3.25
4X P
9
3.35
5.00 BSC
-
4.75 BSC
9
3.15
3.25
3.35
-
k
0.20
-
-
-
L
0.50
0.55
0.60
8
N
28
2
Nd
7
3
7
3
P
-
-
0.60
q
-
-
12
(Ne-1)Xe
REF.
E2
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
8
2. N is the number of terminals.
E2/2
N e
8
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
9
CORNER
OPTION 4X
(Nd-1)Xe
REF.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
BOTTOM VIEW
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
A1
NX b
5
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land Pattern
Design efforts, see Intersil Technical Brief TB389.
SECTION "C-C"
C
L
9
NOTES:
7
NX L
9
Rev. 0 7/05
2
3
6
INDEX
AREA
7,8
0.50 BSC
1
(DATUM A)
7,8
E
Ne
NX k
D2
2 N
5,8
4.75 BSC
3.15
e
0.08 C
0.30
E1
E2
/ / 0.10 C
C
0.25
9
5.00 BSC
D1
2X
NOTES
A
D
9
MAX
A1
A3
E
NOMINAL
C
L
L1
10
L
e
L1
10
L
9. Features and dimensions A2, A3, D1, E1, P & q are present when
Anvil singulation method is used and not present for saw
singulation.
e
C C
TERMINAL TIP
FOR ODD TERMINAL/SIDE
FOR EVEN TERMINAL/SIDE
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notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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22
FN9258.0
November 20, 2006