advertisement Programming Pulse Generators for Flash Memories Design Note 17 Jim Williams Recently introduced “flash” memories add electrical chip-erasure and reprogramming to established EPROM technology. These features make them a cost effective and reliable alternative for updatable nonvolatile memory. Utilizing the electrical program-erase capability requires linear circuitry techniques. The Intel 28F256 flash memory, built on the ETOX process, specifies programming operation with 12V or 12.75V (faster erase/program times) amplitude pulses. These “VPP” amplitudes must fall within 1.6%, and excursions beyond 14.0V will damage the device. Providing the VPP pulse requires generating and controlling high voltages within the tightly specified limits. Figure 1’s circuit does this. When the VPP command pulse goes low (trace A, Figure 2) the LT®1072 switching regulator drives L1, producing high voltage. DC feedback occurs via R1 and R2, with AC roll-off controlled by C1 and R3-C2. The result is a smoothly rising VPP pulse (trace B) which settles to the required value. The specified R1 values allow either 12V or 12.75V outputs. The 5.6V zener permits the output to return to 0V when the VPP command goes high. It may be deleted in cases where a 4.5V minimum output is acceptable (see Intel 28F256 data sheet). The 0.1% resistors combine with the LT1072’s tight internal reference to eliminate circuit + 10 5V MUR120 1N5919A 5.6V* VIN LT1072 C1 1μF FB VPP COMMAND 270k 120k Figure 1’s repetition rate is limited because the regulator must fully rise and settle for each VPP command. Figure 3’s circuit serves cases which require higher repetition rate VPP pulses. Here, the switching regulator runs continuously, with the VPP pulses generated by the A1-A2 loop. If desired, the “VPP Lock” line can be driven, shutting down the regulator to preclude any possibility of inadvertent VPP outputs. When VPP Lock goes low (trace A, Figure 4) the LT1072 loop comes on (trace B), stabilizing at about 17V. Pulsing the VPP command line low causes the 74C04 (trace C) to bias the LT1004 reference. The LT1004 clamps at 1.23V with A1 and A2 giving a scaled output (trace D). The 680pF capacitor controls loop slewing, eliminating overshoots. Figure 5 details the VPP output. Trace A is the 74C04 output, with trace B showing clean VPP characteristics. As in Figure 1, spurious VPP outputs are suppressed during power-up or down. The diode path around A2 prevents overshoot during short circuit recovery. L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. L1 150μH VIN GND trimming requirements. Additionally, this circuit will not spuriously overshoot during power-up or down. VC Q1 2N3904 + R3 1k C2 1μF R1 R2 1.24k 0.1% VO = 12.00V 10.7k 0.1% VO = 12.75V 11.5k 0.1% + VPP OUTPUT 200mA MAX 100μF A = 5V/DIV 0.1% RESISTORS = IRC- #CM55-T13 L1 = PULSE ENGINEERING #PE-52645 * = ZENER DIODE OPTIONAL – SEE TEXT B = 5V/DIV DN017 F01 HORIZ = 20ms/DIV Figure 1. Basic Flash Memory VPP Pulse Generator 10/88/17_conv DN017 F02 Figure 2. Waveforms for Basic Flash Memory Pulser A good question might be; “Why not set the switching regulator output voltage at the desired VPP level and use a simple low resistance FET or bipolar switch?” Figure 6 shows that this is a potentially dangerous approach. Figure 6a shows the clean output of a low resistance switch operating directly at the VPP supply. The PC trace run to the memory chip looks like a transmission line with ill-defined termination characteristics. As such, Figure 6a’s clean pulse degrades and rings badly (Figure 6b) at the memory IC’s pins. Overshoot exceeds 20V, well beyond the 14V destruction level. The controlled edge times of the circuits discussed eliminate this problem. Further discussion of these and other circuits appears in LTC Application Note 31, “Linear Circuits for Digital Systems” (Available February, 1989). 10μF 5V A = 5V/DIV B = 5V/DIV HORIZ = 100μs/DIV DN017 F05 Figure 5. Expanded Scale Display of Figure 3’s VPP Pulse. Controlled Risetime Eliminates Overshoots. A = 5V/DIV L1 150μH MUR120 + VIN VIN + 200μF LT1072 0.68 DN017 F06a 16k HORIZ = 100ns/DIV 1.2k Figure 6a. An “Ideal” Flash Memory VPP Pulse FB GND 270k VPP LOCK 120k VC Q1 2N3904 + 1k 1μF ≈17 10k VPP COMMAND LT1004 1.2V 74C04 OR EQUIVALENT IN914 A = 5V/DIV + A1 LT1006 VPP OUTPUT 150mA MAX A2 LT1010 – 680pF DN017 F03 1N914 1.24k 0.1% 10.7k 0.1% – 12.0V 11.5k 0.1% – 12.75V L1 = PULSE ENGINEERING #PE-52645 0.1% RESISTORS = IRC- #CM55-T13 HORIZ = 100ns/DIV DN017 F06b Figure 6B. Rings at Destructive Voltages After a PC Trace Run Figure 3. High Repetition Rate VPP Pulse Generator A = 5V/DIV B = 10V/DIV C = 5V/DIV D = 10V/DIV HORIZ = 20ms/DIV DN017 F04 Figure 4. Operating Details of High Repetition Rate Flash Memory Pulser Data Sheet Download www.linear.com Linear Technology Corporation For applications help, call (408) 432-1900 dn17f_conv IM/GP 1088 165K • PRINTED IN THE USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 1988