PIC16C74A PIC16C74A Rev. A Silicon Errata Sheet The PIC16C74A (Rev. A) parts you have received conform functionally to the Device Data Sheet (DS30390E), except for the anomalies described below. All the problems listed here will be addressed in future revisions of the PIC16C74A silicon. TABLE 1: COMPARE OUTPUT LOW SWITCHING CCP Mode CCPxM<3:0> = I/O pin State 1001 1000 H L L L L L H H — L L — H — L L — L H L L L L L H L L L L L 1. Module: 8-bit A/D Module If the Analog Port is configured so that all analog pins are digital inputs (PCFG2:PCFG0 = 11x), then doing a conversion on any pin of the analog port will give a result of ADRES = 0xFF. 0xxx Work around 1000 Configure the PCFG2:PCFG0 bits to a value that has any pin of the analog port configured as an analog input (such as PCFG2:PCFG0 = 100). Conversion on any pin of the analog port (analog or digital) will now convert as expected. 1001 2. Module: CCP (Compare Mode) The Compare mode may not operate as expected when configuring the compare match to drive the I/O pin low (CCPxM<3:0> = 1001). When the CCP module is changed to compare output low (CCPxM<3:0> = 1001) from any other non-compare CCP mode, the I/O pin will immediately be driven low, regardless of the state of the I/O data latch. The pin will remain low when the compare match occurs (see Table 1). However, when the CCP module is changed to compare output high (CCPxM<3:0> = 1000) from any other CCP mode, the I/O pin will immediately be driven low, regardless of the state of the I/O data latch. The pin will be driven high when the compare match occurs. 2001 Microchip Technology Inc. Change CCP to CCPxM<3:0> = 101x 11xx Work around To have the I/O pin high until the compare match low occurs, force a compare match high to get the I/O pin into the high state, then reconfigure the compare match to force the I/O low when the compare condition occurs. DS80089A-page 1 PIC16C74A 3. Module: CCP (Compare Mode) EXAMPLE 1: The special event trigger of the Compare mode may not occur if both of the following conditions exist: • An instruction, one cycle (TCY) prior to a Timer1/Compare register match has literal data equal to the address of a CCP register being used. Specific cases include: Unit Register Literal Data CCPR1L 15h CCP1 CCPR1H 16h CCP2 • CCP1CON 17h CCPR2L 1Bh CCPR2H 1Ch CCP2C0N 1Dh An instruction in the same cycle as a Timer1/Compare register match has an MSb of ‘0’. The interrupt for the compare event will still be generated, but no special event trigger will occur. Work around Use the Interrupt Service Routine instead of using the special event trigger to reset Timer1 (and start an A/D conversion, if applicable). 4. Module: SSP (SPI Mode) When the SPI is using Timer2/2 as the clock source, a shorter than expected SCK pulse may occur on the first bit of the transmitted/received data (Figure 1). FIGURE 1: SCK PULSE VARIATION USING TIMER2/2 Write SSPBUF AVOIDING THE INITIAL SHORT SCK PULSE BSF STATUS, RP0 LOOP BTFSS SSPSTAT,BF GOTO BCF MOVF MOVWF MOVF BCF CLR MOVWF BSF LOOP STATUS, SSPBUF, RXDATA TXDATA, T2CON, TMR2 SSPBUF T2CON, ;Bank 1 ;Data received? ;(Xmit complete?) ;No RP0 ;Bank 0 W ;W = SSPBUF ;Save in user RAM W ;W = TXDATA TMR2ON ;Timer2 off ;Clear Timer2 ;Xmit New data TMR2ON ;Timer2 on 5. Module: SSP Module (I2C™ mode) If the bus is active when the I2C mode is enabled, and the next 8 bits of data on the bus match the address of the device, then the SSP module will generate an Acknowledge pulse. Work around Before enabling the I2C mode, ensure that the bus is not active. 6. Module: Timer0 The TMR0 register may increment when the WDT postscaler is switched to the Timer0 prescaler. If TMR0 = FFh, this will cause TMR0 to overflow (setting T0IF). Work around Follow the following sequence: a) Read the 8-bit TMR0 register into the W register b) Clear the TMR0 register c) Assign WDT postscaler to Timer0 d) Write W register to TMR0 bit0=1 bit1=0 bit2=1 . . . . SD0 SCK Work around To avoid producing the short pulse, turn off Timer2 and clear the TMR2 register, load the SSPBUF with the data to transmit, and then turn Timer2 back on. Refer to Example 1 for sample code. DS80089A-page 2 2001 Microchip Technology Inc. PIC16C74A 7. Module: Timer1 The Timer1 value may unexpectedly increment if either the TMR1H, or the TMR1L register is written. If Timer1 is ON and then turned OFF, performing any write instruction with TMR1H as the destination, may cause TMR1L to increment. EXAMPLE 2: 8. Module: USART When the USART (SCI) is configured in Asynchronous mode with the BRGH bit set, a high number of receive errors may be experienced. For asynchronous receive operations, it is recommended that the USART be configured with the BRGH bit cleared. TMR1L INCREMENT (CASE 1) BSF T1CON, TMR1ON : BCF T1CON, TMR1ON MOVF TMR1H, 1 TMR1 value before MOVF instruction: TMR1H:TMR1L = 3F:00 TMR1 value after MOVF instruction: TMR1H:TMR1L = 3F:01 EXAMPLE 3: TMR1L INCREMENT (CASE 2) BSF T1CON, TMR1ON : BCF T1CON, TMR1ON MOVF TMR1H, 1 TMR1 value before MOVF instruction: TMR1H:TMR1L = FF:FF TMR1 value after MOVF instruction: TMR1H:TMR1L = FF:00 If Timer1 is ON and then turned OFF when TMR1H:TMR1L = xx:FF, performing any write instruction with TMR1L as the destination may cause TMR1H to increment. EXAMPLE 4: TMR1H INCREMENT BSF T1CON, TMR1ON BCF T1CON, TMR1ON CLRF TMR1L TMR1 value before CLRF instruction: TMR1H:TMR1L = FF:FF TMR1 value after CLRF instruction: TMR1H:TMR1L = 00:00 (TMR1IF is not set.) Work around To preserve Timer1 register values: a) Read Timer1 register values into “shadow” registers. b) Perform any write instruction(s) on the shadow registers. c) Write the shadow register values back into the Timer1 registers. 2001 Microchip Technology Inc. DS80089A-page 3 PIC16C74A Clarifications/Corrections to the Data Sheet: In the Device Data Sheet (DS30390E), the following clarifications and corrections should be noted. 1. Module: I/O Ports The specification for the High Voltage Open Drain I/O (parameter D150, the RA4 pin) cannot be met without possible long term reliability issues on that I/O pin. If a high voltage drive is required, use an external transistor that can support the required voltage. The new value is shown in Table 1. TABLE 1: Param No. D150 DC SPECIFICATION CHANGES FROM DATA SHEET Data Sheet Specification New Specification Sym. VOD Characteristic RA4 Open Drain High Voltage Units Min Typ Max Min Typ Max — — 10 — — 14 V 2. Module: 8-Bit A/D The minimum A/D reference voltage (parameter A20) has been improved. The new value is shown in Table 2. TABLE 2: Param No. A20 DC SPECIFICATION CHANGES FROM DATA SHEET Data Sheet Specification New Specification Sym. VREF Characteristic Reference Voltage Min Typ Max Min Typ Max 2.5* — VDD + 0.3 V 3.0 — VDD + 0.3 V Units V * This parameter is characterized but not tested. DS80089A-page 4 2001 Microchip Technology Inc. PIC16C74A 3. Module: SSP (SPITM Mode Timing Specifications) The SPI interface timings (parameters 71, 71A, 72, 72A, 73, and 73A) have been modified. The new values are shown in Table 3. TABLE 3: Param No. DC SPECIFICATION CHANGES FROM DATA SHEET New Specification Sym. 71 TSCH 71A 72 TSCL Characteristic SCK input high time Continuous (slave mode) Single Byte(1) SCK input low time (slave mode) 72A 73A TB2B Continuous Single Byte(1) Last clock edge of the Byte1 to 1st clock edge of the Byte2(1) Data Sheet Specification Units Min Typ Max Min Typ Max 1.25 TCY + 30 ns — — TCY + 20 ns — — 40 — — 1.25 TCY + 30 ns — — 40 — — N.A. 1.5 TCY + 40 ns — — N.A. N.A. TCY + 20 ns — ns ns — ns ns ns * This parameter is characterized but not tested. Note 1: Specification 73A is only required if specifications 71A and 72A are used. 4. Module: Timer1 The operation of Timer1 needs some clarification when the timer registers are written when the TMR1ON bit is set. When the TMR1H and/or TMR1L registers are written while this clock is low, TMR1 will not increment on the next rising edge of this clock, but must first have a falling clock and the rising clock, for TMR1 to increment. The internal clock signal that is the input to the TMR1 prescaler affects the incrementing of Timer1 (TMR1H:TMR1L registers and the Timer1 prescaler). When the Timer1 registers are NOT written, the Timer1 will increment on the rising edge of the TMR1 increment clock. Figure 1 shows the two cases of writes to the TMR1H and/or TMR1L registers. Due to the VIH and VIL thresholds on the oscillator/clock pins, external Timer1 oscillator components, and external clock frequency, the Timer1 increment clock may not be of a 50% duty cycle. When the TMR1H and/or TMR1L registers are written while this clock is high, TMR1 will increment on the next rising edge of this clock. The TMR1 increment clock is out of phase of the T1OSO/T1CKI pin by a small propagation delay. FIGURE 1: WRITES TO TIMER1 (EXTERNAL CLOCK/OSCILLATOR MODE) TMR1 Increment Clock (Input to Prescaler) Write to TMR1H and/or TMR1L Register(s) TMR1H:TMR1L Increments 2001 Microchip Technology Inc. Write to TMR1H and/or TMR1L Register(s) TMR1H:TMR1L Increments DS80089A-page 5 PIC16C74A 5. Module: RC Oscillator The table for RC Oscillator Frequencies in the Device Characterization section of the Data Sheet is incorrect. The correct characterization information is shown in Table 4. TABLE 4: RC OSCILLATOR FREQUENCIES CHARACTERIZATION CHANGES FROM DATA SHEET Correct Characterization Data Current Data Sheet Values REXT CEXT 22 pF 100 pF 330 pF Average % Variation Average % Variation 5.1 K 3.55 MHz ± 9.63% 4.12 MHz ± 1.4% 10 K 1.99 MHz ± 10.53% 2.35 MHz ± 1.4% 100 K 221.9 kHz ± 12.10% 268 kHz ± 1.1% 3.3 K 1.77 MHz ± 10.67% 1.80 MHz ± 1.0% 5.1 K 1.22 MHz ± 10.41% 1.27 MHz ± 1.0% 10 K 669.4 kHz ± 10.92% 688 kHz ± 1.2% 100 K 71.5 kHz ± 11.21% 77.2 kHz ± 1.0% 3.3 K 625.1 kHz ± 10.68% 707 kHz ± 1.4% 5.1 K 428.5 kHz ± 10.96% 501 kHz ± 1.2% 10 K 231.9 kHz ± 11.32% 269 kHz ± 1.6% 100 K 24.4 kHz ± 12.93% 28.3 kHz ± 1.1% The percentage variation indicated here is part-to-part variation due to normal process distribution. The variation indicated is ±3 standard deviation from the average value for VDD = 5V. 6. Module: Brown-Out Reset (BOR) The levels specified for the BOR module thresholds (parameter D005) have changed. The new values are shown in Table 5. TABLE 5: Param No. D005 . MINIMUM AND MAXIMUM BOR RESET VOLTAGES Data Sheet Specification New Specification Sym. VBOR DS80089A-page 6 Characteristic Brown-out Reset Voltage Min Typ Max Min Typ Max 3.65 — 4.35 3.70 — 4.30 Units V 2001 Microchip Technology Inc. “All rights reserved. Copyright © 2001, Microchip Technology Incorporated, USA. Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights.” Trademarks The Microchip name, logo, PIC, PICmicro, PICMASTER, PICSTART, PRO MATE, KEELOQ, SEEVAL, MPLAB and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. Total Endurance, ICSP, In-Circuit Serial Programming, FilterLab, MXDEV, microID, FlexROM, fuzzyLAB, MPASM, MPLINK, MPLIB, PICDEM, ICEPIC, Migratable Memory, FanSense, ECONOMONITOR, SelectMode and microPort are trademarks of Microchip Technology Incorporated in the U.S.A. Serialized Quick Term Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2001, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999. The Company’s quality system processes and procedures are QS-9000 compliant for its PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs and microperipheral products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001 certified. 2001 Microchip Technology Inc. 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Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, except as maybe explicitly expressed herein, under any intellectual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies. DS80089A-page 8 2001 Microchip Technology Inc.