Freescale Semiconductor Document Number: AN4793 Rev. 0, 09/2013 Application Note Examples of using eTimer on Power Architecture devices by: Tomas Kulig 1 Introduction This application note describes how to use the Enhanced Motor Control Timer (eTimer) module and what is necessary to set in the device for using the eTimer. The base features of the eTimer are shown in four examples which were developed in a GreenHills project for RAM memory; generating periodical signal, generating periodical pulse, generating one-shot signal and measure signal parameters. This application note focuses on the eTimer module on the MPC5744P. Contents 1 Introduction ............................................................................................... 1 2 Implementation of eTimer in the device .................................................... 2 2.1 CGM module - for live – set clock ................................................ 2 2.2 Enable clock in mode entry ........................................................... 2 2.3 SIUL2 module ............................................................................... 4 3 Generating periodical signal ...................................................................... 7 4 Generating periodical pulse (signal which has long period but thin pulse) 10 4.1 Check if it is possible to generate the signal with parameters width and period with motc_clk input frequency..................................................... 12 4.2 Set registers for generating the pulse ........................................... 12 4.3 Set registers for generating short period ................................................................................................... 13 4.4 period 5 Set registers for generating long .................................................................................................... 14 Generating one-shot signal ...................................................................... 15 5.1 Check if it is possible to generate the signal with parameters width and delay with motc_clk input frequency ...................................................... 16 6 Measure signal parameters ......................................................... 17 6.1 Calculate the signal parameters ....................................... 18 6.2 Calculate the signal parameters ....................................... 19 6.3 Start measurement (second part of implementation) ....... 19 7 Description of the Green Hills project........................................ 20 8 Reference ................................................................................... 21 © 2013 Freescale Semiconductor, Inc. _______________________________________________________________________ 2 Implementation of eTimer in the device There are three independent modules and each has six independent channels. All three modules are able to generate external signals and work with input signals. For using eTimer we need to configure following: 2.1 CGM module - for live – set clock There is no special divider and clock selector for the eTimers modules. The eTimers use the Motor Control clock which can be up to 160 MHz if the selector uses the PLL. The selector CGM_AC0_SC can use internal oscillator, external oscillator (crystal) or PLL0. This selector is valid for ADC and SWG clock. Figure 2 shows the field description of CGM_AC0_DC0 register. Figure 1. MC_CGM_AC0_SC field description Where SELSTAT can be 0 - internal oscillator 16 MHz, 1 - external oscillator/crystal 8-40 MHz or 2 – PLL0. The divider CGM_AC0_DC0 can enable/disable the clock and divide by 1 up to 16. Warning: Use only odd DIV values (i.e., division factor of 2, 4, 6, 8, 10, 12, 14 or 16). Even values will cause incorrect device behavior. Figure 2 shows the field description of CGM_AC0_DC0 register. Figure 2. MC_CGM_AC0_DC0 field description Where DE bit is for divider enable - 1/disable - 0. Div can be 0 up to 15. The motor control clock is divided by value “DIV+1”. 2.2 Enable clock in mode entry PCTLs registers select the group for non- low- power mode and for low-power modes, each peripheral can be asserted only to one low-power group and one non-low-power group. Each group can be asserted for one or more modes. There are eight groups for non-low-power modes (RUN_PC0 – RUN_PC7) and eight groups for low-power modes (LP_PC0 – LP_PC7). See Figure 3 and code below which shows an example of enabling the clocks for the eTimers. All eTimer have clocks enabled in modes RUN0, RUN1, RUN2, RUN3 and DRUN. The eTimer0 has enable clock in modes STOP0 and HALT0 but eTimer1 and eTimer2 have enable clock only in STOP0 mode. 2 Examples of using eTimer on Power Architecture devices, Rev. 0, 09/2013 Freescale Semiconductor, Inc. Example code: //enable group RUN_PC0 MC_ME.RUN_PC[0].R = //enable group LP_PC0 MC_ME.LP_PC[0].R = //enable group LP_PC1 MC_ME.LP_PC[1].R = //set peripherals for group MC_ME.PCTL247.B.RUN_CFG = MC_ME.PCTL137.B.RUN_CFG = MC_ME.PCTL245.B.RUN_CFG = //set peripherals for group MC_ME.PCTL247.B.LP_CFG = //set peripherals for group MC_ME.PCTL137.B.LP_CFG = MC_ME.PCTL245.B.LP_CFG = 0xF8; //enable DRUN, RUN3, RUN2, RUN1 and RUN0 0x500 //enable STOP0 and HALT0 0x400 //enable HALT0 RUN_PC0 0x0 //eTimer 0 - set 0x0 //eTimer 1 - set 0x0 //eTimer 2 - set LP_PC0 0x0 //eTimer 0 - set LP_PC1 0x1 //eTimer 1 - set 0x1 //eTimer 2 - set group RUN_PC0 for enable clock group RUN_PC0 for enable clock group RUN_PC0 for enable clock group LP_PC0 for enable clock group LP_PC1 for enable clock group LP_PC1 for enable clock Figure 3. Example of clock enable Examples of using eTimer on Power Architecture devices, Rev. 0, 09/2013 Freescale Semiconductor, Inc. 3 2.3 SIUL2 module SIUL2 module provides communication with external world. Table 1, 2 and 3 show all pins which can be used for eTimers modules. MSCR is used for output direction and IMCR is used for input direction. Table 1. eTimer 0 pins PINS PORT channel direction MSCR/IMCR SSS PIN 144 LQFP 257MAPBGA 1 73 P12 O 0/A0 2 73 P12 0 0/59 A0 I 76 R16 58/59 1 D10 1 74 T14 O 1/A1 2 74 T14 1 1/60 A1 I 1 78 P17 59/60 D11 1 84 L14 O 2/A2 2 84 L14 2 2/61 A2 I 1 133 B6 80/61 F0 1 92 G15 O 3/A3 2 92 G15 3 3/62 A3 I 1 105 E17 62/62 D14 3 108 D16 4/A4 O 1 80 P16 43/C11 3 108 D16 4/63 A4 4 1 30/63 B14 64 P11 I 4 80 P16 43/63 C11 2 104 E16 99/63 G3 1 82 M14 44/C12 O 1 117 A11 77/E13 1 47 P7 24/64 B8 5 3 82 M14 44/64 C12 I 4 117 A11 77/64 E13 2 100 F16 100/64 G4 channel 0 1 4 Table 2. eTimer 1 pins PINS PORT direction MSCR/IMCR SSS PIN 144 LQFP 257MAPBGA 4/1 A4 108 D16 O 47/2 C15 124 A8 4/65 1 A4 108 D16 I 47/65 2 C15 124 FA8 O 45/1 C13 101 E15 Examples of using eTimer on Power Architecture devices, Rev. 0, 09/2013 Freescale Semiconductor, Inc. channel direction MSCR/IMCR SSS I O 2 I O 3 I O 4 I O 5 I channel 0 48/45/66 48/66 16/46/49/16/67 46/67 49/67 17/50/92/17/68 50/68 92/68 14/51/56/93/14/69 51/69 56/69 93/69 5/15/52/78/5/70 15/70 52/70 78/70 2 1 2 2 1 2 1 2 3 2 2 1 1 2 3 2 2 2 1 1 2 3 4 2 2 2 1 1 2 3 4 PINS PORT PIN 144 LQFP 257MAPBGA D0 125 B8 C13 101 E15 D0 125 B8 B0 109 C16 C14 103 F14 D1 3 E3 B0 109 C16 C14 103 F14 D1 3 E3 B1 110 C14 D2 140 B4 F12 106 D17 B1 110 C14 D2 140 B4 F12 106 D17 A14 143 A3 D3 128 A5 D8 32 L4 F13 112 A15 A14 143 A3 D3 128 A5 D8 32 L4 F13 112 A15 A5 14 H4 A15 144 D3 D4 129 B7 E14 119 B10 A5 14 H4 A15 144 D3 D4 129 B7 E14 119 B10 Table 3. eTimer 2 pins PORT direction MSCR/IMCR SSS PIN 116/2 H4 O 128/1 I0 I 116/71 1 H4 PINS 144 LQFP 257MAPBGA F4 C6 F4 Examples of using eTimer on Power Architecture devices, Rev. 0, 09/2013 Freescale Semiconductor, Inc. 5 channel direction MSCR/IMCR O 1 I O 2 I O 3 I O 4 I O 5 I 6 128/71 119/129/119/72 129/72 6/122/130/152/6/73 122/73 130/72 152/73 7/125/131/7/74 125/74 131/74 8/126/137/152/8/75 126/75 137/75 152/75 9/127/138/153/9/76 127/76 138/76 153/76 SSS 2 2 1 1 2 2 2 1 2 1 2 3 4 2 2 1 1 2 3 2 2 1 1 1 2 3 4 2 2 1 1 1 2 3 4 PORT PIN I0 H7 I1 H7 I1 A6 H10 I2 J8 A6 H10 I2 J8 A7 H13 I3 A7 H13 I3 A8 H14 I9 J8 A8 H14 I9 J8 A9 H15 I10 J9 A9 H15 I10 J9 PINS 144 LQFP 257MAPBGA C6 F2 T3 F2 T3 2 D1 C7 D11 95 G16 2 D1 C7 D11 95 G16 10 G4 A14 A10 10 G4 A14 A10 12 H1 P13 L3 95 G16 12 H1 P13 L3 95 G16 134 A4 C17 M3 16 K1 134 A4 C17 M3 16 K1 Examples of using eTimer on Power Architecture devices, Rev. 0, 09/2013 Freescale Semiconductor, Inc. 2.3.1 Set as input Set the IMCR and MSCR register. The IMCR registers select the input functionality of a pin and other parameters are set by the MSCR registers. The MSCR register manages the following main parameters of a pin: input buffer enable (IBE) output buffer enable (OBE) slew rate (SRC) output functionality (SSS). IMCR[number of functionality MSCR[number of MSCR[number of MSCR[number of IMCR register].SSS.B = SSS from table; //select the input MSCR register].IBE.B = MSCR register].OBE.B = MSCR register].SRC = 0x1; 0x0; slew_rate; //enable input buffer //disable output buffer //set slew rate MSCR register].SSS.B = SSS from table; //select the output MSCR register].IBE.B = MSCR register].OBE.B = MSCR register].SRC = 0x0; 0x1; slew_rate; //disable input buffer //enable output buffer //set slew rate 2.3.2 Set as output Set the MSCR register. MSCR[number of functionality MSCR[number of MSCR[number of MSCR[number of 3 Generating periodical signal Description: This function is for generating periodical signal with variable duty cycle. Minimum steps of duty cycle variance given by motor control clock (motc_clk) are given in the Table 4. Table 4: Minimum step of duty cycle Minimal frequency Maximum frequency Minimum variance of duty cycle > 0 <= motc_clk/1000 0.1 % > motc_clk/1000 <= motc_clk/100 1 % > motc_clk/100 <= motc_clk/10 10 % > motc_clk/10 <= motc_clk/2 50 % What is needed: 1 channel, 1 pad Implementation: The COMP1 register is used for driving the duty cycle, the CMPLD1 register is used for driving the frequency of the signal. Figure 4 shows this. The output signal is set on a successful compare of COMP1 and cleared on successful compare of COMP2. Examples of using eTimer on Power Architecture devices, Rev. 0, 09/2013 Freescale Semiconductor, Inc. 7 Figure 4. Generating periodical signal waveforms d- duty cycle f- frequency motc_clk- motor control clock eTimer_div- eTimer internal divider 1. Check if it is possible to generate the signal with parameters d and f with input frequency of module motc_clk: motc_clk[Hz]/(MAX_DIVIDER*MIN_FREQ[Hz]) < f[Hz] <= motc_clk[Hz]/2 where, MAX_DIVIDER is value 128, it is the maximal internal eTimer divider MIN_FREQ is value 65000. The maximum value of counter is 65535. The value 535 is reserve. The left side of equation is low frequency board and the right side is the high frequency board. Example: motc_clk = 160 MHz 160*10^6/(128*65000) < f <= 160*10^6/2 19 Hz < f <= 80 MHz It means device is able to generate signal form 20 Hz up to 80 MHz. 2. Set the internal eTimer divider: eTimer_div >= motc_clk/(f*MIN_FREQ) 8 Examples of using eTimer on Power Architecture devices, Rev. 0, 09/2013 Freescale Semiconductor, Inc. but DIV can be only following: 1, 2, 4, 8, 16, 32, 64 or 128 Example: motc_clk = 160 MHz f = 50 Hz eTimer_div >= 160*10^6/(50*65000) eTimer_div >= 49 The closest possible value is DIV = 64. 3. Set the registers for generating signal with parameter d and f: a) Set up the signal parameters: //See the table 5 CTRL1.B.PRISRC = this is given by eTimer_div; Table 5: eTimer dividers values eTimer_div PRISRC value COMP1.R = 0xFFFF – (range*d)/1000; CMPLD1.R = 0xFFFF – range + 1; 24 2 25 4 26 8 27 16 28 32 29 64 30 128 31 // count rising edges of primary source // count until compare then reinitialize // reinitializing counter by value which is stored in CMPLD1 CTRL1.B.CNTMODE = 0x1; CTRL1.B.LENGTH = 0x1; CCCTRL.B.CLC1 = 0x7; COMP2.R = 0xFFFF; 1 // // // where range = motc_clk/(eTimer_div*frequency) b) Output setting: CTRL2.B.OEN = 0x1; CTRL2.B.OUTMODE = 0x8; //output enable //set on successful compare on COMP1, clear on successful compare on COMP2 Examples of using eTimer on Power Architecture devices, Rev. 0, 09/2013 Freescale Semiconductor, Inc. 9 4 Generating periodical pulse (signal which has long period but thin pulse) Description: This function is for generating periodical signal with variable pulse width. One channel of eTimer is used for generating the pulse. Period is given by 1 or 2 channels. It depends on length of the period. What is needed: a) short period: 2 channel, 1 pad b) long period: 3 channel, 1 pad, two chained channels are used for period Implementation: The Figure 5 shows the connection between the eTimer channels. The colors of blocks correspond with the waveform on figures 6 and 7. Short period Channel C defines the period of the signal that triggers the channel A which generates the pulse. The channel A COMP1 register is used for driving 50 % duty cycle and the CMPLD1 register is used for driving period of signal. The output signal is set on successful compares of COMP1 and cleared on successful compares of COMP2. The output signal of channel C is used as the secondary source for channel A (as a trigger). This signal is only inside the device (inside the module). The channel A COMP1 register is used for driving the width. The output signal is cleared on the secondary source input edge and set on the compare with COMP1. The output signal is inverted and then is routed to the pin (output). The waveforms are shown on the Figure 6. Long Period Channel C is used as a source of channel B which triggers the channel A which then generates the pulse. The channels B and C define the period of signal. The channels B and C COMP1 registers are used for driving 50 % duty cycle and CMPLD1 registers are used for driving period of signal. The output signals of both channels are set on successful compare of COMP1s and cleared on successful compares of COMP2s. The output signal of channel C is used as the source of clock for channel B. This signal is only inside the device (inside the module). The output signal of channel B is used as the secondary source for channel A (as a trigger). This signal is only inside the device (inside the module). The channel A COMP1 register is used for driving the width. The output signal is cleared on the secondary source input edge and set on compare with COMP1. The output signal is inverted and then is routed to the pin (output). The waveforms are shown on the Figure 7. Figure 5. Connection between channels 10 Examples of using eTimer on Power Architecture devices, Rev. 0, 09/2013 Freescale Semiconductor, Inc. Figure 6. Short period waveforms Figure 7. Long period waveforms Examples of using eTimer on Power Architecture devices, Rev. 0, 09/2013 Freescale Semiconductor, Inc. 11 width -width of pulse period - period of signal range_b- range for channel of timer which defines the period – short period range_c-range for channel of timer which defines the period, this is used only for longer period div_pulse-value of channel divider which is used for pulse div_period-divider of channel which is used for period short x long period motc_clk -motor control clock 4.1 Check if it is possible to generate the signal with parameters width and period with motc_clk input frequency a) Check the width 1000000/motc_clk [kHz] < width [ns] < MIN_FREQ*MAX_DIVIDER*1000000/motc_clk [kHz], where MAX_DIVIDER is value 128, it is the maximal internal eTimer divider MIN_FREQ is value 65000, it is maximum value of counter (535 is reserve). The left side of equation is the minimum period and the right side is the maximum period. b) Check the period 2/motc_clk [kHz] < period [ms] < MIN_FREQ*MIN_FREQ*MAX_DIVIDER/motc_clk [kHz], where MAX_DIVIDER is value 128, it is the maximal internal eTimer divider MIN_FREQ is value 65000, it is maximum value of counter (535 is reserve). The left side of equation is the minimum period and the right side is the maximum period. It makes sense to check one more conclusion: 2*period [ms] *1000000 > width [ns] Period must be at least twice bigger than width. Decide if the signal has long or short period short period < MIN_FREQ*MAX_DIV/motc_clk <= long period Example: motc_clk = 160 MHz short period < 65000 * 128 / 160 [MHz] <= long period short period < 52 [ms] <= long period 4.2 Set registers for generating the pulse The width of the pulse does not depend on the number of channels which are used for generating the period but the secondary source depends on this. It means that for short periods the output of channel C is used and for long periods the output of channel B is used as the secondary source. The first channel is used for short period (channel C) and the second channel (channel B) is used for long period. Set the internal eTimer divider: div_pulse >= (width [ns] * motc_clk [GHz])/MIN_FREQ, but div can be only following: 1, 2, 4, 8, 16, 32, 64 or 128. 12 Examples of using eTimer on Power Architecture devices, Rev. 0, 09/2013 Freescale Semiconductor, Inc. Example: a) motc_clk = 160 MHz width = 750 ns div_pulse >= (750 * 0.16)/65000 div_pulse >= 0 The closest possible value is div_pulse = 1. b) Set up the pulse parameters: CTRL1.B.PRISRC = this is given by div_pulse; //See the table 5 - eTimer_div = div_period CTRL1.B.CNTMODE = 0x6; //edge of secondary source triggers primary count till compare CTRL1.B.LENGTH = 0x1; //count until compare then reinitialize COMP2.R = 0xFFFF; // here is not use this comparator set out of working area COMP1.R = (motor_clk [GHz] * width [ns])/div_pulse; The secondary source of channel A (channel which generates the pulse) is given by the length of period generating signal. It is channel C for short period. It is channel B for long period. Short: CTRL1.B.SECSRC = 16 + number of channel C; //for period is use one channel (channel C) Long: CTRL1.B.SECSRC = 16 + number of channel B; //for this period is used two channels, here is used the channel B which trigger channel A which create the pulse. The channel C is source of primary clock for the channel B. Output setting: CTRL2.B.OEN = 0x1; CTRL2.B.OUTMODE = 0x5; source //output enable // set on successful compare on COMP1, clear on secondary Input edge: CTRL2.B.OPS = 0x1; // inverted output 4.3 Set registers for generating short period Only one channel of eTimer is used (channel C on Figure 5). a) Set the internal eTimer divider: div_period >= motc_clk [kHz] * period [ms]/ MIN_FREQ Example: motc_clk = 160 MHz period = 20 ms div_period >= (160000 * 160000)/65000 div_period >= 49 The closest possible value is div_period = 64. b) Set up the period parameters: CTRL1.B.PRISRC = this is given by div_period; //See the table 5 - eTimer_div = div_period CTRL1.B.CNTMODE = 0x1; //count rising edges of primary source CTRL1.B.LENGTH = 0x1; //count until compare then reinitialize CCCTRL.B.CLC1 = 0x7; //reinitializing counter by value which is stored in CMPLD1 COMP2.R = 0xFFFF; COMP1.R = 0xFFFF – range_b/2; // //duty cycle is always 50 % Examples of using eTimer on Power Architecture devices, Rev. 0, 09/2013 Freescale Semiconductor, Inc. 13 CMPLD1.R = 0xFFFF – range_b + 1; // where range_b = motc_clk * period/div_period c) Output setting CTRL2.B.OUTMODE = 0x8; clear on successful compare on COMP2 //set on successful compare on COMP1, This signal is not routed on the output pin. It is used as trigger of channel which creates pulse. 4.4 Set registers for generating long period There are two channels for generating period channel C and channel B (Figure 5). The Setting period has three level of latitude: internal eTimer divider (channel C), two counting values (channel C) and (channels B). a) Determine ranges of both counters and divider for the channels C for given period and motor control: period [ms] = div_period * range_b * range_c/motc_clk [kHz] where range_b and range_c is from 2 up to MIN_FREQ and div_period 1, 2, 4, 8, 16, 32, 64 or 128 Example: motc_clk = 160 MHz period = 250 ms 250 = div_period * range_b * range_c/160000 4 * 107 = div _period * range_b * range_c Check the value of div_period: range_b = range_c = MIN_FREQ 4*107 = div_period * MIN_FREQ2 div_period = 4 * 107/4225 * 106 = 0,01 -> select dic_period = 1 range_b * range_c = 160000 * 250 / 1 = 4 * 107 Chose range_b = 40000 range_c = 4 * 107/range_b range_c = 4 * 107/4 * 104 range_c = 1000 b) Channel C – internal CTRL1.B.PRISRC = this is given by div_period; CTRL1.B.CNTMODE = 0x1; CTRL1.B.LENGTH = 0x1; CCCTRL.B.CLC1 = 0x7; COMP2.R = 0xFFFF; COMP1.R = 0xFFFF – range_b/2; CMPLD1.R = 0xFFFF – range_b + 1; 14 //See the table 5 - eTimer_div = div_period //count rising edges of primary source //count until compare then reinitialize //reinitializing counter by value which is stored in CMPLD1 // //duty cycle is always 50 % // Examples of using eTimer on Power Architecture devices, Rev. 0, 09/2013 Freescale Semiconductor, Inc. Output setting CTRL2.B.OUTMODE = 0x8; //set on successful compare on COMP1, clear on successful compare on COMP2 c) Channel B – trigger for the channel A which creates the pulse CTRL1.B.PRISRC = this is given by div_period; //See the table 5 - eTimer_div = div_period CTRL1.B.CNTMODE = 0x1; CTRL1.B.LENGTH = 0x1; CCCTRL.B.CLC1 = 0x7; //count rising edges of primary source //count until compare then reinitialize //reinitializing counter by value which is stored in CMPLD1 COMP2.R = 0xFFFF; COMP1.R = 0xFFFF – range_c/2; CMPLD1.R = 0xFFFF – range_c + 1; // //duty cycle is always 50 % // d) Output setting CTRL2.B.OUTMODE = 0x8; //set on successful compare on COMP1, clear on successful compare on COMP2 5 Generating one-shot signal Description: This function generates a single short pulse which has two parameters: delay and width. The width expresses the width of the pulse and the delay expresses time between generating pulse start and the function trigger. It is possible to select the active level of pulse – high or low. What is needed: 1 channel, 1 pad Implementation: The COMP1 register is used for the delay and the COMP2 register is used for driving the width of the pulse. Figure 8 shows this. The output signal is set on successful compare of COMP1 and cleared on successful compare of COMP2. The first part is used to set the eTimer channel and the second part is used for generating the signal. Examples of using eTimer on Power Architecture devices, Rev. 0, 09/2013 Freescale Semiconductor, Inc. 15 Figure 8. Generating one-shot signal waveforms 5.1 Check if it is possible to generate the signal with parameters width and delay with motc_clk input frequency a) check delay 2/motor_freq [MHz] < delay [us] < MIN_FREQ* MAX_DIVIDER/ motor_freq [MHz],Where MAX_DIVIDER is 128 and MIN_FREQ = 65000. Example: motc_clk = 160 MHz 2/160 < delay [us] <128*65000/160 25 ns < delay < 52 ms b) Check width width < delay 5.2. Setting of eTimer channel a) Set the internal eTimer divider: div_period >= motc_clk [MHz] * delay [us]/ MIN_FREQ Example: motc_clk = 160 MHz delay = 1 ms div_period >= 160 [MHz] * 1000 [us]/ 65000 div_period >= 2.46 The closest possible value is div_period = 4. b) Set up the period parameters: 16 Examples of using eTimer on Power Architecture devices, Rev. 0, 09/2013 Freescale Semiconductor, Inc. CTRL1.B.PRISRC = this is given by div_period; //See the table 5 - eTimer_div = div_period CNTR.R //clear counter for the new use = 0x0 ; // COMP1.R = range – delay; COMP2.R = range + (width [us] *motc_clk [MHz]/div_period) – delay + width; c) Where range = delay [ s]*motc_clk [MHz]/div_period //count until compare and then stop CTRL1.B.ONCE= 0x1; c) Output setting CTRL2.B.OEN CTRL2.B.OPS CTRL2.B.OUTMODE = 0x1; - enable output = output active level; // 0 – low, 1- high = 0x4; // toggle OFLAG output using alternating compare registers 5.3. Start generating: CNTR.R CTRL1.B.CNTMODE = 0x0; = 0x1; // clear counter for the new use // count rising edges of primary source/start generating signal 6 Measure signal parameters Description: This function is for measuring signal frequency and duty cycle. What is needed: 1 channel, 1 pad Implementation: One channel of the eTimer is used for measuring the frequency and duty cycle. The function uses the capture functionality of the eTimer. The motor control clock is used as the primary source of clock and the input signal as secondary source. Its edges drive the capturing values of internal counter. The counter is counting repeatedly the primary source and captures its values on edges produced by the secondary source or input. The capture 1 register is set for capture the counter value on rising edge of signal and the capture 2 register is set for capture the counter value on falling edge of input signal. The capture registers have two-deep FIFO so they are able to capture two values. The frequency is calculated from the two values related to the rising edges and the duty cycle using the difference between the values related to the first rising edge and the first falling edge. The implementation is divided into two parts. First part is used for setting the eTimer channel and the second part is used for doing the measurement (start capturing and calculate the frequency and duty cycle). The Figure 9 shows the waveforms. Examples of using eTimer on Power Architecture devices, Rev. 0, 09/2013 Freescale Semiconductor, Inc. 17 Figure 9. Measurement signal waveforms The values in the brackets mean the position in the FIFO of the capture registers. 6.1 Calculate the signal parameters a) Frequency: f [kHz] = motc_clk [kHz]/(CAPT1.R[1] - CAPT1.R[0]), where motc_clk is motor control clock. Example: The input signal was generated by function generator. Following setting has been used: 3 kHz, 11.26%, slewrates of falling and rising edge 150 ns. motc_clk CAPT1.R[1] CAPT1.R[0] = 160 MHz = 0xC642 = 50754 = 0xF5F0 = 62960 f [kHz] = 160000/(50754-62960) = 160000/53329 = 3.0002 kHz (3 kHz in device) 50754 – 62960 is equal 53329 because 16 bit unsigned format is used and the counter counts repeatedly. So the counter counts from 62960 to 65535 – overflow to 0 (maximum 16 bit value) and from 0 to 50754 so = 65535 – 62960 + 50754 = 53329. 18 Examples of using eTimer on Power Architecture devices, Rev. 0, 09/2013 Freescale Semiconductor, Inc. b) Duty cycle duty [per thousand] = ((CAPT2.R[0] - CAPT1.R[0])*1000)/(CAPT1.R[1] - CAPT1.R[0]) Example: CAPT1.R[1] CAPT1.R[0] CAPT2.R[0] = 0xC642 = 50754 = 0xF5F0 = 62960 = 0x0D66 = 3430 duty [per thousand] = ((3430- 62960)*1000)/(50754 - 62960) = 6005*1000/53329 = 112.6 (112 in device) 6.2 Calculate the signal parameters CTRL1.B.PRISRC CCCTRL.B.CPT1MODE = 0x2; CCCTRL.B.CPT2MODE = 0x1; CCCTRL.B.CFWM = IP_BUS_DIVIDER[0]; //maximum resolution //capture counter by rising edge of secondary input (measure signal) //capture counter by falling edge of secondary input (measure signal) = 0x2; //capture flag set as soon as more than 3 values will be in FIFOs CTRL1.B.LENGTH CTRL1.B.ONCE CTRL1.B.SECSRC = 0x0; = 0x0; = channel; //continue counting to roll over //count repeatedly //counter "channel" input pin is use for trigger the capturing – measuring signal is connect to this pin CTRL1.B.CNTMODE = 0x1; //count rising edge of primary source 6.3 a) Start measurement (second part of implementation) Measure CCCTRL.B.ARM = 0x1; //enable/start capturing while ((STS.B.ICF1 == 0x0)||( STS.B.ICF2 == 0x0)); //wait for capture 2 cap1 values and 2 capt2 values CCCTRL.B.ARM STS.B.ICF1 STS.B.ICF2 //disable/stop capturing = 0x0; //clear capture 1 flag //clear capture 2 flag = 0x1; = 0x1; Read captures values from FIFOs: measure[0] measure[1] measure[2] measure[3] b) = = = = CAPT1.R; CAPT1.R; CAPT2.R; CAPT2.R; //read //read //read //read first capture1 value second capture 1 value first capture2 value second capture2 value Calculate frequency frequency [kHz] = motor_freq [kHz]/(uint16_t)((measure[1] - measure[0])); It is very important to use uint16_t data type for captured values because the counter rolls over and if the 16 bit unsigned data type is used the counter overflow is not important. It has no effect on value captured for frequency and duty. See “Calculate the signal parameters” for more details about this. Examples of using eTimer on Power Architecture devices, Rev. 0, 09/2013 Freescale Semiconductor, Inc. 19 c) Calculate duty duty measure[0])); = (uint16_t)((measure[2] - measure[0]))*1000/(uint16_t)((measure[1] - Duty cycle is calculated in per thousand. 7 Description of the Green Hills project The example codes use the eTimer 0 module. Before using any of the function it is necessary to set up the device for using the eTimer 0. The function Init_peripheral_eTimer() enables the clock for the eTimer 0 module. The function eTimer_CONFIG_PINS() sets the pin for communication with external world. Table 6 shows details about function which are in the project. Example name Generating periodical signal Generating periodical pulse (signal which has long period but thin pulse) Generating one-shot signal Measure signal 20 Table 6: Summary of functions which are in the project Function name Function parameters unit Description Generate_Signal Generate_Signal2 Generate_OneShot _signal_set timer [-] which timer channel [-] which channel of timer frequency [Hz] frequency of the output signal duty [‰] duty of the output signal motor_freq [kHz] module frequency timer [-] which timer channel4period_b [-] base channel for period channel4period_0 [-] output channel for period channel4pulse [-] channel create the pulses period [ms] period of the output signal width [ns] width of the pulse motor_freq [kHz] module frequency timer [-] which timer channel [-] which channel of timer delay [ s] delay of the pulse width [ s] width of the pulse motor_freq [kHz] module frequency active_level [-] HIGH or LOW Start_Generate _OneShot_signal timer [-] which timer channel [-] which channel of timer Measure_signal timer [-] which timer Examples of using eTimer on Power Architecture devices, Rev. 0, 09/2013 Freescale Semiconductor, Inc. Example name parameters Function name _parameters_set Start_Measure _signal Function parameters unit Description channel [-] which channel of timer timer [-] which timer channel [-] which channel of timer motor_freq [kHz] module frequency *frequency1 [Hz] frequency of the measure signal *duty1 [‰] duty of the measure signal The project can be opened as follows: “Location on computer”\ eTimer\build\ghs\blocks\eTimer\eTimer_sram.gpj 8 Reference MPC5744PRM - Reference manual available at www.freescale.com 1 These variables are returned by the function. Examples of using eTimer on Power Architecture devices, Rev. 0, 09/2013 Freescale Semiconductor, Inc. 21 How to Reach Us: Home Page: freescale.com Web Support: freescale.com/support Information in this document is provided solely to enable system and software implementers to use Freescale products. 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