Freescale Semiconductor Data Sheet: Product Preview Document Number: MPC5744P Rev. 0.3, 06/2012 MPC5744P Data Sheet 32-bit Qorivva MCU suitable for ISO26262 ASIL-D chassis and safety applications The MPC5744P Qorivva microcontroller is based on the Power Architecture® developed by Freescale. It targets chassis and safety applications and other applications requiring a high Automotive Safety Integrity Level (ASIL). The MPC5744P is a SafeAssure solution. This document provides electrical specifications, pin assignments, and package diagram information for the MPC5744P series of microcontroller units (MCUs). All information is preliminary and subject to change without notice. For functional characteristics and the programming model, see the MPC5744P Microcontroller Reference Manual. This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. © Freescale Semiconductor, Inc., 2012. All rights reserved. Preliminary—Subject to Change Without Notice Table of Contents 1 2 3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 1.1 Feature list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 1.2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 2.1 Package pinouts and ballouts . . . . . . . . . . . . . . . . . . . . .7 2.2 Pin/ball descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . .10 2.2.1 Pin/ball startup and reset states . . . . . . . . . . . .10 2.2.2 Power supply and reference voltage pins/balls . 11 2.2.3 System pins/balls. . . . . . . . . . . . . . . . . . . . . . . .14 2.2.4 LVDS pins/balls . . . . . . . . . . . . . . . . . . . . . . . . .16 2.2.5 Generic pins/balls . . . . . . . . . . . . . . . . . . . . . . .17 2.2.6 Peripheral pin muxing . . . . . . . . . . . . . . . . . . . .48 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 3.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . .62 3.3 Recommended operating conditions . . . . . . . . . . . . . .63 3.4 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . .64 3.4.1 General notes for specifications at maximum junction temperature . . . . . . . . . . . . . . . . . . . . .66 3.5 Electromagnetic Interference (EMI) characteristics . . .67 3.6 Electrostatic discharge (ESD) characteristics . . . . . . . .68 3.7 Voltage regulator electrical characteristics . . . . . . . . . .69 3.8 DC electrical characteristics . . . . . . . . . . . . . . . . . . . . .72 3.9 3.10 3.11 3.12 3.13 3.14 4 5 6 Supply current characteristics . . . . . . . . . . . . . . . . . . . 74 Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Main oscillator electrical characteristics . . . . . . . . . . . 76 FMPLL electrical characteristics . . . . . . . . . . . . . . . . . 78 Internal 16 MHz RC oscillator electrical characteristics 79 ADC electrical characteristics . . . . . . . . . . . . . . . . . . . 80 3.14.1 Input Impedance and ADC Accuracy . . . . . . . . 80 3.15 Flash memory electrical characteristics. . . . . . . . . . . . 85 3.16 SWG electrical characteristics. . . . . . . . . . . . . . . . . . . 87 3.17 AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 3.17.1 Reset pad (EXT_POR, RESET) electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 88 3.17.2 WKUP/NMI timing . . . . . . . . . . . . . . . . . . . . . . 90 3.17.3 Debug/JTAG/Nexus/Aurora timing . . . . . . . . . . 90 3.17.4 External interrupt timing (IRQ pin) . . . . . . . . . . 97 3.17.5 DSPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 3.17.6 LVDS Fast Asynchronous Transmission (LFAST) electrical characteristics . . . . . . . . . . . . . . . . . 104 3.17.7 FlexRay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Obtaining package dimensions . . . . . . . . . . . . . . . . . . . . . . .111 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . 113 MPC5744P Data Sheet, Rev. 0.3 2 Preliminary—Subject to Change Without Notice Freescale Semiconductor Introduction 1 Introduction 1.1 Feature list Table 1 summarizes major features of the MPC5744P device. The feature column represents a combination of module names and capabilities of certain modules. Table 1. MPC5744P feature summary Feature Details CPU Power Architecture 2 x e200z4 in delayed lock step Architecture Harvard Execution Speed 0 MHz to TBD (design target: 180 MHz or greater) (+2% FM) Embedded FPU Yes Core MPU 24 regions Instruction Set PPC No Instruction Set VLE Yes Instruction cache 8 KB, EDC Data cache 4 KB, EDC Data local memory 64 KB, ECC System MPU Yes (16 regions) Buses Core bus AHB, 32-bit address, 64-bit data, e2e ECC Internal periphery bus 32-bit address, 32-bit data Crossbar Master x slave ports 4x5 Memory Code/data flash memory 2.5 MB, ECC, RWW Data flash memory Supported with RWW SRAM 384 KB, ECC Modules Interrupt controller 32 interrupt priority levels, 16 software programmable interrupts PIT 1 module with 4 channels System Timer Module (STM) 1 module with 4 channels Software Watchdog Timer (SWT) Yes eDMA 32 channels, in delayed lock step FlexRay 1 module with 64 message buffer, dual channel MPC5744P Data Sheet, Rev. 0.3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 3 Introduction Table 1. MPC5744P feature summary (continued) Feature Details FlexCAN 3 modules with 64 message buffer LINFlexD (UART and LIN with DMA support) 2 modules Clockout Yes Fault Collection and Control Unit (FCCU) Yes Cross Triggering Unit (CTU) 2 modules eTimer 3 modules with 6 channels FlexPWM 2 modules with 4 x (2+1) channels Analog-to-digital converter (ADC) 4 modules with 12 bit ADC, (25 external channels including shared channels plus internal channels) Sine-wave generator (SWG) 32 point DSPI 4 modules As many as 8 chip selects CRC Unit Yes SENT 2 modules with 2 channels Interprocessor serial link interface (SIPI) Yes Junction temperature sensor Yes Replicated module Digital I/Os >= 16 Peripheral register protection Yes Supply Device Power Supply 3.3 V with external ballast transistor or 3.3 V with external 1.25 V low drop-out (LDO) regulator ADC Analog Reference voltage 3.15 V to 3.6 V and 4.5 V to 5.5 V Clocking Phase Lock Loop (PLL) 1 x PLL and 1 coupled FMPLL Internal RC Oscillator 16 MHz External Crystal Oscillator 8 MHz to 40 MHz Low power modes HALT and STOP Yes Debug Nexus Level 3+, MDO and Aurora interface Package LQFP 144 pins LQFP exposed pads (EP) 176 pins MPC5744P Data Sheet, Rev. 0.3 4 Preliminary—Subject to Change Without Notice Freescale Semiconductor Introduction Table 1. MPC5744P feature summary (continued) Feature MAPBGA Details 257 MAPBGA Temperature Temperature range (junction) -40°C to +150°C, option for 165°C Ambient temperature range (LQFP) -40°C to +125°C, TBD option (with 165°C junction option) Ambient temperature range (BGA) -40°C to +125°C, TBD option (with 165°C junction option) 1.2 Block diagram Figure 1 shows the top-level block diagram of the MPC5744P device. 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Figure 2. 144LQFP pinout MPC5744P Data Sheet, Rev. 0.3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 7 Pinouts Figure 3. 176LQFP pinout MPC5744P Data Sheet, Rev. 0.3 8 Preliminary—Subject to Change Without Notice Freescale Semiconductor Pinouts Figure 4. 257MAPBGA ballmap MPC5744P Data Sheet, Rev. 0.3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 9 Pinouts 2.2 Pin/ball descriptions The following sections provide signal descriptions and related information about the functionality and configuration of the MPC5744P devices. Note that this section is under development. 2.2.1 Pin/ball startup and reset states This table provides startup state and reset state information for device pins/balls. Table 2. Pin/ball startup and reset states Pin Startup state1 State during reset State after reset 144 LQFP 176 LQFP 257MAPBGA GPIOs hi-z hi-z hi-z 2 2 2 Analog inputs3 hi-z hi-z hi-z 2 2 2 JCOMP (TRST) hi-z input, weak pull-down input, weak pull-down 4 4 4 TDI hi-z input, weak pull-up input, weak pull-up 4 4 4 TDO hi-z weak pull-up hi-z 4 4 4 TMS hi-z input, weak pull-down input, weak pull-down 4 4 4 TCK hi-z input, weak pull-down input, weak pull-down 4 4 4 XTAL/EXTAL hi-z hi-z hi-z 4 4 4 FCCU_F[0] hi-z input, hi-z output/input, hi-z 38 46 R2 FCCU_F[1] hi-z input, hi-z output/input, hi-z 141 173 C4 4 4 4 4 EXT_POR hi-z input, weak pull-down input, weak pull-down 4 RESET_B hi-z input, weak pull-down input, weak pull-down 4 NOTES: 1 Startup state is exited when the core and high-voltage supplies reach minimum levels as defined in the Power Management chapter. 2 See Section 2.2.5, Generic pins/balls. 3 Not all non-supply or reference pins on the device that are explicitly defined in this table. 4 See Section 2.2.3, System pins/balls. MPC5744P Data Sheet, Rev. 0.3 10 Preliminary—Subject to Change Without Notice Freescale Semiconductor Pinouts 2.2.2 Power supply and reference voltage pins/balls Table 3. Power supply and reference voltage pins/balls Supply Symbol VDD_LV Type Power QFP Description Low voltage power Supply 144LQFP 18 39 70 93 131 135 PBGA 176LQFP 257MAPBGA 23 47 81 117 163 167 F6 F7 F8 F9 F10 F11 F12 G6 G12 H6 H12 J6 J12 K6 K12 L6 L12 M6 M7 M8 M9 M10 M11 M12 MPC5744P Data Sheet, Rev. 0.3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 11 Pinouts Table 3. Power supply and reference voltage pins/balls Supply Symbol Type QFP Description 144LQFP PBGA 176LQFP 257MAPBGA VSS_LV Ground Low voltage ground. PLL Ground is also connected to low voltage ground for core logic on 144 LQFP (pin 35).. 17 35 40 71 94 96 132 137 22 42 48 82 118 120 164 169 G7 G8 G9 G10 G11 H7 H8 H9 H10 H11 J7 J8 J9 J10 J11 K7 K8 K9 K10 K11 L7 L8 L9 L10 L11 VDD_LV_PLL Power PLL low voltage Supply 36 43 P4 VSS_LV_PLL Ground PLL low voltage Ground 35 42 N4 VDD_HV_IO Power High voltage Power Supply for I/O. 6 21 91 126 9 26 36 84 115 158 A9 B2 B16 D8 D14 G2 M2 T2 T16 MPC5744P Data Sheet, Rev. 0.3 12 Preliminary—Subject to Change Without Notice Freescale Semiconductor Pinouts Table 3. Power supply and reference voltage pins/balls Supply Symbol Type QFP Description 144LQFP PBGA 176LQFP 257MAPBGA VSS_HV_IO Ground High voltage Ground Supply for I/O 7 22 90 127 10 27 37 85 114 159 A1 A2 A16 A17 B1 B9 B17 C3 C15 D9 H2 N2 R3 R15 T1 T17 U1 U2 U16 U17 VDD_HV_PMU VDD_HV_PMU_AUX Power PMU high voltage Supply 72 83 U14 VDD_HV_OSC0 Power Power Supply for the oscillator 27 32 M1 VSS_HV_OSC0 Ground Ground Supply for the oscillator 28 33 P1 VDD_HV_FLA0 Power Decoupling supply pin for Flash 97 121 H16 VDD_HV_ADV0/1 Power High voltage Supply for ADC, SWG(3.3V) 58 69 T10 VSS_HV_ADV0/1 Ground High voltage Ground for ADC 59 70 U9 VDD_HV_AD0_VDDE1 Supply High voltage Supply for digital portion of ADC pads Voltage reference of ADC/TSENS High voltage Supply for ADC and ADC pad switches 50 58 R7 Ground High voltage Ground for digital portion of ADC pads Voltage reference Ground of ADC/TSENS High voltage Ground for ADC and ADC pad switches 51 59 T7 VDD_HV_AD1_VDDE2 Supply VDD_HV_ADRE1 VDD_HV_ADSW1 High voltage Supply for digital portion of ADC pads Voltage reference of ADC/TSENS High voltage Supply for ADC and ADC pad switches 56 67 R9 VDD_HV_ADRE0 VDD_HV_ADSW0 VSS_HV_AD0_VSSE VSS_HV_ADRE0 VSS_HV_ADSW0 MPC5744P Data Sheet, Rev. 0.3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 13 Pinouts Table 3. Power supply and reference voltage pins/balls Supply Symbol Type QFP Description VSS_HV_AD1_VSSE VSS_HV_ADRE1 VSS_HV_ADSW1 Ground High voltage Ground for digital portion of ADC pads Voltage reference Ground of ADC/TSENS High voltage Ground for ADC and ADC pad switches VDD_LV_LFAST Supply VSS_LV_LFAST 144LQFP PBGA 176LQFP 257MAPBGA 57 68 T9 LFAST PLL low voltage Supply - 99 N16 Ground LFAST PLL low voltage Ground - 100 N17 VDD_LV_NEXUS Supply Aurora LVDS Supply - - J16 VSS_LV_NEXUS Ground Aurora LVDS Ground - - K16 NOTES: 1 Connected to ADC0/2. Can be 3.3V or 5V. 2 Connected to ADC1/3. Can be 3.3V or 5V. 2.2.3 System pins/balls The following table contains information on system pin functions for the devices. MPC5744P Data Sheet, Rev. 0.3 14 Preliminary—Subject to Change Without Notice Freescale Semiconductor Pinouts Table 4. System Pins/Balls QFP Symbol Type PBGA Description 144LQFP 176LQFP 257MAPBGA NMI_B Input Non maskable Interrupt 1 1 E4 XTAL Input Crystal Oscillator/External Clock Input 29 34 N1 EXTAL Input Input of the oscillator amplifier circuit 30 35 R1 RESET_B Input Functional Reset 31 38 P2 Input External Power On Reset 130 162 D6 VPP_TEST Input SoC Test Mode 107 131 D15 JCOMP Input JTAGC, JTAG Compliance Enable 123 154 A6 TCK Input JTAGC, Test Clock Input 88 112 H17 TMS Input JTAGC, Test Mode Select 87 111 H15 TDO Output JTAGC, Test Data Out 89 113 G14 TDI Input JTAGC, Test Data Input 86 109 J17 MDO[0] Output NEXUS, Message data out pins; reflects the state of the internal power on reset signal until RESET is negated 9 13 G1 MDO[3:1] Output NEXUS, Message data out pins 4,5,8 5,8,11 E1,F1,E2 EVTO Output NEXUS, Event Out Pin 24 29 K2 EVTI Input NEXUS, Event In Pin 25 30 L2 MCKO Output NEXUS, Message clock out pin 19 24 J4 MSEO Output NEXUS, Message Start/End out pin 20 25 J3 RDY_B Output NEXUS, Read/Write Transfer completed - - J2 BCTRL Output Base control signal of external npn ballast 69 80 R13 J[11],J[10] -- - - L17,K17 EXT_POR 1 Freescale Factory Test2 NOTES: 1 VPP_TEST must be connected to ground. 2 Do not connect on the board. MPC5744P Data Sheet, Rev. 0.3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 15 Pinouts 2.2.4 LVDS pins/balls The following table contains information on LVDS pin functions for the devices. Table 5. SIPI LFAST LVDS pin descriptions Functional block SIPI LFAST1 Port pin Signal I[5] SIPI_TXN C[12]2 Signal description Direction 176LQFP 257MAPBGA Interprocessor Bus LFAST, LVDS Transmit Negative Terminal O 102 N15 SIPI_TXP Interprocessor Bus LFAST, LVDS Transmit Positive Terminal O 101 M14 I[6] SIPI_RXN Interprocessor Bus LFAST, LVDS Receive Negative Terminal I 103 M15 G[7]2 SIPI_RXP Interprocessor Bus LFAST, LVDS Receive Positive Terminal I 104 M16 NOTES: 1 DRCLK and TCK/DRCLK usage for SIPI LFAST and Debug LFAST are described in the MPC5744P reference manual’s SIPI LFAST and Debug LFAST chapters.. 2 G[7] and C[12] are available in the 144LQFP, but there is no SIPI LFAST functionality available. SIPI LFAST pins are muxed with GPIOs. Do not use GPIO and SIPI LFAST functionality in parallel. MPC5744P Data Sheet, Rev. 0.3 16 Preliminary—Subject to Change Without Notice Freescale Semiconductor Pinouts Table 6. Aurora LVDS pin descriptions Functional Block Nexus Aurora High Speed Trace MAPBGA PAD Signal Signal Description Direction G[12] TX0P Nexus Aurora High Speed Trace Lane 0, LVDS Positive Terminal O H14 G[13] TX0N Nexus Aurora High Speed Trace Lane 0, LVDS Negative Terminal O J14 G[14] TX1P Nexus Aurora High Speed Trace Lane 1, LVDS Positive Terminal O L15 G[15] TX1N Nexus Aurora High Speed Trace Lane 1, LVDS Negative Terminal O K14 H[0] CLKP Nexus Aurora High Speed Trace Clock, LVDS Positive Terminal I K15 H[1] CLKN Nexus Aurora High Speed Trace Clock, LVDS Negative Terminal I J15 2571 NOTES: 1 Nexus Aurora High Speed Trace is only available on the 257 Pin MAPBGA 2.2.5 Generic pins/balls The I/O signal descriptions for the device are in the following table. It contains the port definition, multiplexing, direction, pad type, and package pin/ball numbers for each I/O pin on the device. See the device Reference Manual for the MSCR register address map. MPC5744P Data Sheet, Rev. 0.3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 17 Pinouts A[0] MSCR[0] MSCR/ IMCR SSS Value 0000 (Default)1 Short Signal Description Dir SIUL2-GPIO[0] General Purpose IO A[0] I/O 0001 ETC0 eTimer_0 eTimer_0 Input/Output Data Channel 0 I/O 0010 SCK DSPI2 DSPI 2 Serial Clock (output) I/O - Reserved - - IMCR[59] 0010 (Default) ETC0 eTimer_0 eTimer_0 Input Data Channel 0 I/O IMCR[173] 0001 REQ0 SIUL2 SIUL2 External Interrupt 0 I GPIO[1] SIUL2-GPIO[1] General Purpose IO A[1] I/O 0001 ETC1 eTimer_0 eTimer_0 Input/Output Data Channel 1 I/O 0010 SOUT DSPI2 DSPI 2 Serial Data Out O - Reserved - - MSCR[1] 0000 (Default) 0011-1111 A[2] Module GPIO[0] 0011-1111 A[1] Signal IMCR[60] 0010 ETC1 eTimer_0 eTimer_0 Input Data Channel 1 I/O IMCR[174] 0001 REQ1 SIUL2 SIUL2 External Interrupt Source 1 I GPIO[2] SIUL2-GPIO[2] General Purpose IO A[2] I/O 0001 ETC2 eTimer_0 eTimer_0 Input/Output Data Channel 2 I/O 0010 - Reserved - - 0011 A3 FlexPWM_0 FlexPWM_0 Channel A Input 3 I/O - Reserved - - ABS1 MC_RGM RGM external boot mode 1 I MSCR[2] 0000 (Default) 0100-1111 IMCR[169] 0000 (Default) IMCR[47] 0010 SIN DSPI2 DSPI 2 Serial Data Input I IMCR[61] 0010 ETC2 eTimer_0 eTimer_0 Input Data Channel 2 I IMCR[175] 0001 REQ2 SIUL2 SIUL2 External Interrupt Source 2 I BGA257 SIUL2 MSCR/ IMCR Number LQFP176 Port Pin LQFP144 Table 7. Pin Muxing 73 86 P12 74 91 T14 84 106 L14 MPC5744P Data Sheet, Rev. 0.3 18 Preliminary—Subject to Change Without Notice Freescale Semiconductor Pinouts MSCR[3] MSCR/ IMCR SSS Value 0000 (Default) Module Short Signal Description Dir GPIO[3] SIUL2-GPIO[3] General Purpose IO A[3] I/O 0001 ETC3 eTimer_0 eTimer_0 Input/Output Data Channel 3 I/O 0010 CS0 DSPI2 DSPI 2 Peripheral Chip Select 0 I/O 0011 B3 FlexPWM_0 FlexPWM_0 Channel B Input/Output 3 I/O - Reserved - - 0100-1111 A[4] Signal IMCR[171] 0000 ABS2 MC_RGM RGM external boot mode 2 I IMCR[62] 0010 ETC3 eTimer_0 eTimer_0 Input Data Channel 3 I/O IMCR[176] 0001 REQ3 SIUL2 SIUL2 External Interrupt Source 3 I GPIO[4] SIUL2-GPIO[4] General Purpose IO A[4] I/O 0001 ETC0 eTimer_1 eTimer_1 Input/Output Data Channel 0 I/O 0010 CS1 DSPI2 DSPI 2 Peripheral Chip Select 1 O 0011 ETC4 eTimer_0 eTimer_0 Input/Output Data Channel 4 I/O 0100 A2 FlexPWM_1 FlexPWM_1 Channel A Input/Output 2 I/O - Reserved - - MSCR[4] 0000 (Default) 0101-1111 IMCR[112] 0001 A2 FlexPWM_1 FlexPWM_1 Channel A Input 2 I/O IMCR[177] 0001 REQ4 SIUL2 SIUL2 External Interrupt Source 4 I IMCR[172] 0000 FAB MC_RGM RGM Force Alternate Boot Mode I IMCR[63] 0011 ETC4 eTimer_0 eTimer_0 Input Data Channel 4 I/O BGA257 A[3] SIUL2 MSCR/ IMCR Number LQFP176 Port Pin LQFP144 Table 7. Pin Muxing (continued) 92 116 G15 108 132 D16 MPC5744P Data Sheet, Rev. 0.3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 19 Pinouts A[5] MSCR[5] MSCR/ IMCR SSS Value 0000 (Default) A[6] MSCR[6] A[7] MSCR[7] A[8] MSCR[8] Dir General Purpose IO A[5] I/O 0001 CS0 DSPI1 DSPI 1 Peripheral Chip Select 0 I/O 0010 ETC5 eTimer_1 eTimer_1 Input/Output Data Channel 5 I/O 0011 CS7 DSPI0 DSPI 0 Peripheral Chip Select 7 O - Reserved - - REQ5 SIUL2 SIUL2 External Interrupt Source 5 I GPIO[6] SIUL2-GPIO[6] General Purpose IO A[6] I/O 0001 SCK DSPI1 DSPI 1 Serial Clock (output) I/O 0010 ETC2 eTimer_2 eTimer_2 Input/Output Data Channel 2 I/O - Reserved - - REQ6 SIUL2 SIUL2 External Interrupt Source 6 I GPIO[7] SIUL2-GPIO[7] General Purpose IO A[7] I/O 0001 SOUT DSPI1 DSPI 1 Serial Data Out O 0010 ETC3 eTimer_2 eTimer_2 Input/Output Data Channel 3 I/O - Reserved - - REQ7 SIUL2 SIUL2 External Interrupt Source 7 I GPIO[8] SIUL2-GPIO[8] General Purpose IO A[8] I/O 0001 - Reserved - - 0010 ETC4 eTimer_2 eTimer_2 Input/Output Data Channel 4 I/O - Reserved - - 0001 0000 (Default) 0001 0000 (Default) 0011-1111 IMCR[180] Short Signal Description SIUL2-GPIO[5] 0011-1111 IMCR[179] Module GPIO[5] 0100-1111 IMCR[178] Signal 0001 0000 (Default) 0011-1111 IMCR[44] 0001 SIN DSPI1 DSPI 1 Serial Data Input I IMCR[181] 0001 REQ8 SIUL2 SIUL2 External Interrupt Source 8 I BGA257 SIUL2 MSCR/ IMCR Number LQFP176 Port Pin LQFP144 Table 7. Pin Muxing (continued) 14 18 H4 2 2 D1 10 14 G4 12 16 H1 MPC5744P Data Sheet, Rev. 0.3 20 Preliminary—Subject to Change Without Notice Freescale Semiconductor Pinouts MSCR[9] MSCR/ IMCR SSS Value 0000 (Default) Dir General Purpose IO A[9] I/O 0001 CS1 DSPI2 DSPI 2 Peripheral Chip Select 1 O 0010 ETC5 eTimer_2 eTimer_2 Input/Output Data Channel 5 I/O 0011 B3 FlexPWM_0 FlexPWM_0 Channel B Input/Output 3 I/O - Reserved - - FAULT0 FlexPWM_0 FlexPWM_0 Fault Input 0 I/O GPIO[10] SIUL2-GPIO[10] General Purpose IO A[10] I/O 0001 CS0 DSPI2 DSPI 2 Peripheral Chip Select 0 I/O 0010 B0 FlexPWM_0 FlexPWM_0 Channel B Input/Output 0 I/O 0011 X2 FlexPWM_0 FlexPWM_0 Auxiliary Input/Output 2 I/O - Reserved - - REQ9 SIUL2 SIUL2 External Interrupt Source 9 I GPIO[11] SIUL2-GPIO[11] General Purpose IO A[11] I/O 0001 SCK DSPI2 DSPI 2 Serial Clock (output) I/O 0010 A0 FlexPWM_0 FlexPWM_0 Channel A Input/Output 0 I/O 0011 A2 FlexPWM_0 FlexPWM_0 Channel A Input/Output 2 I/O - Reserved - - REQ10 SIUL2 SIUL2 External Interrupt Source 10 I IMCR[183] 0001 MSCR[10] 0000 (Default) IMCR[182] 0001 MSCR[11] 0000 (Default) 0100-1111 IMCR[183] Short Signal Description SIUL2-GPIO[9] 0100-1111 A[11] Module GPIO[9] 0100-1111 A[10] Signal 0001 BGA257 A[9] SIUL2 MSCR/ IMCR Number LQFP176 Port Pin LQFP144 Table 7. Pin Muxing (continued) 134 166 A4 118 145 B11 120 149 D10 MPC5744P Data Sheet, Rev. 0.3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 21 Pinouts MSCR/ IMCR SSS Value MSCR[12] 0000 (Default) Short Signal Description Dir SIUL2-GPIO[12] General Purpose IO A[12] I/O 0001 SOUT DSPI2 DSPI 2 Serial Data Out O 0010 A2 FlexPWM_0 FlexPWM_0 Channel A Input/Output 2 I/O 0011 B2 FlexPWM_0 FlexPWM_0 Channel B Input/Output 2 I/O - Reserved - - REQ11 SIUL2 SIUL2 External Interrupt Source 11 I GPIO[13] SIUL2-GPIO[13] General Purpose IO A[13] I/O 0001 - Reserved - - 0010 B2 FlexPWM_0 FlexPWM_0 Channel B Input/Output 2 I/O - Reserved - - IMCR[184] 0001 MSCR[13] 0000 (Default) 0011-1111 A[14] Module GPIO[12] 0100-1111 A[13] Signal IMCR[83] 0010 FAULT0 FlexPWM_0 FlexPWM_0 Fault Input 0 I IMCR[47] 0001 SIN DSPI2 DSPI 2 Serial Data Input I IMCR[185] 0001 REQ12 SIUL2 SIUL2 External Interrupt Source 12 I MSCR[14] 0000 (Default) GPIO[14] SIUL2-GPIO[14] General Purpose IO A[14] I/O 0001 TXD CAN1 CAN 1 Transmit Pin O 0010 ETC4 eTimer_1 eTimer_1 Input/Output Data Channel 4 I/O - Reserved - - REQ13 SIUL2 SIUL2 External Interrupt Source 13 I 0011-1111 IMCR[186] 0001 BGA257 A[12] SIUL2 MSCR/ IMCR Number LQFP176 Port Pin LQFP144 Table 7. Pin Muxing (continued) 122 152 D7 136 168 C5 143 175 A3 MPC5744P Data Sheet, Rev. 0.3 22 Preliminary—Subject to Change Without Notice Freescale Semiconductor Pinouts MSCR/ IMCR SSS Value MSCR[15] 0000 (Default) Short Signal Description Dir SIUL2-GPIO[15] General Purpose IO A[15] I/O 0001 - Reserved - - 0010 ETC5 eTimer_1 eTimer_1 Input/Output Data Channel 5 I/O - Reserved - - IMCR[32] 0001 RXD CAN0 CAN 0 Receive Pin I IMCR[33] 0001 RXD CAN1 CAN 1 Receive Pin I IMCR[187] 0001 REQ14 SIUL2 SIUL2 External Interrupt Source 14 I MSCR[16] 0000 (Default) GPIO[16] SIUL2-GPIO[16] General Purpose IO B[0] I/O 0001 TXD CAN0 CAN 0 Transmit Pin O 0010 ETC2 eTimer_1 eTimer_1 Input/Output Data Channel 2 I/O 0011 DEBUG0 SSCM SSCM Debug Output 0 O - Reserved - - REQ15 SIUL2 SIUL2 External Interrupt Source 15 I GPIO[17] SIUL2-GPIO[17] General Purpose IO B[1] I/O 0001 - Reserved - - 0010 ETC3 eTimer_1 eTimer_1 Input/Output Data Channel 3 I/O 0011 DEBUG1 SSCM SSCM Debug Output 1 O - Reserved - - 0100-1111 B[1] Module GPIO[15] 0011-1111 B[0] Signal IMCR[188] 0001 MSCR[17] 0000 (Default) 0100-1111 IMCR[32] 0010 RXD CAN0 CAN 0 Receive Pin I IMCR[33] 0010 RXD CAN1 CAN 1 Receive Pin I IMCR[189] 0001 REQ16 SIUL2 SIUL2 External Interrupt Source 16 I BGA257 A[15] SIUL2 MSCR/ IMCR Number LQFP176 Port Pin LQFP144 Table 7. Pin Muxing (continued) 144 176 D3 109 134 C16 110 135 C14 MPC5744P Data Sheet, Rev. 0.3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 23 Pinouts MSCR/ IMCR SSS Value MSCR[18] 0000 (Default) I/O 0001 TXD LIN0 LINFlexD 0 Transmit Pin O 0010 - Reserved - - 0011 DEBUG2 SSCM SSCM Debug Output 2 O - Reserved - - REQ17 SIUL2 SIUL2 External Interrupt Source 17 I GPIO[19] SIUL2-GPIO[19] General Purpose IO B[3] I/O 0001 - Reserved - - 0010 - Reserved - - 0011 DEBUG3 SSCM SSCM Debug Output 3 O - Reserved - - IMCR[190] 0001 MSCR[19] 0000 (Default) IMCR[165] 0001 RXD LIN0 LIN 0 Receive Pin I MSCR[20] 0000 GPIO[20] SIUL2-GPIO[20] General Purpose IO B[4] I/O TDO TDO_MUX JTAGC Test Data Out (TDO) O - Reserved - - GPIO[21] SIUL2-GPIO[21] JTAGC Test Data In (TDI)2 General Purpose IO B[5] I/O 0001 - Reserved - - 0010-1111 - Reserved - - 0000 (Default) GPIO[22] SIUL2-GPIO[22] General Purpose IO B[6] I/O 0001 CLK_OUT MC_RGM CGM Clock out for off-chip use and observation O 0010 CS2 DSPI2 DSPI 2 Peripheral Chip Select 2 O - Reserved - - REQ18 SIUL2 SIUL2 External Interrupt Source 18 I 0010-1111 B[6] Dir General Purpose IO B[2] 0001 (Default) B[5] Short Signal Description SIUL2-GPIO[18] 0100-1111 B[4] Module GPIO[18] 0100-1111 B[3] Signal MSCR[21] MSCR[22] 0000 (Default) 0011-1111 IMCR[191] 0001 BGA257 B[2] SIUL2 MSCR/ IMCR Number LQFP176 Port Pin LQFP144 Table 7. Pin Muxing (continued) 114 141 C12 116 143 B12 89 113 G14 86 109 J17 138 170 B5 MPC5744P Data Sheet, Rev. 0.3 24 Preliminary—Subject to Change Without Notice Freescale Semiconductor Pinouts B[7] B[8] B[9] B[10] B[11] B[12] B[13] MSCR/ IMCR SSS Value MSCR[23] 0000 (Default) Signal Module Short Signal Description Dir GPI[23]3 ADC0_AN[0] SIUL2-GPI[23] General Purpose Input B[7] I 0001 - Reserved - - 0010-1111 - Reserved - - IMCR[165] 0010 RXD LIN0 LIN 0 Receive Pin I MSCR[24] 0000 GPI[24]3 ADC0_AN[1] SIUL2-GPI[24] General Purpose Input B[8] I 0001 - Reserved - - 0010-1111 - Reserved - - ETC5 eTimer_0 eTimer_0 Input Data Channel 5 I GPI[25]3 ADC0_AN[2] SIUL2-GPI[25] General Purpose Input B[9] I 0001 - Reserved - - 0010-1111 - Reserved - - GPI[26]3 ADC0_ADC1_A N[12] SIUL2-GPI[26] General Purpose Input B[10] I 0001 - Reserved - - 0010-1111 - Reserved - - GPI[27]3 ADC0_ADC1_A N[13] SIUL2-GPI[27] General Purpose Input B[11] I 0001 - Reserved - - 0010-1111 - Reserved - - GPI[28]3 ADC0_ADC1_A N[14] SIUL2-GPI[28] General Purpose Input B[12] I 0001 - Reserved - - 0010-1111 - Reserved - - GPI[29]3 ADC1_AN[0] SIUL2-GPI[29] General Purpose Input B[13] I 0001 - Reserved - - 0010-1111 - Reserved - - RXD LIN1 LIN 1 Receive Pin I IMCR[64] 0001 MSCR[25] 0000 (Default) MSCR[26] MSCR[27] MSCR[28] MSCR[29] IMCR[166] 0000 (Default) 0000 (Default) 0000 (Default) 0000 (Default) 0001 BGA257 SIUL2 MSCR/ IMCR Number LQFP176 Port Pin LQFP144 Table 7. Pin Muxing (continued) 43 51 R5 47 55 P7 52 60 U7 53 61 R8 54 62 T8 55 63 U8 60 71 R10 MPC5744P Data Sheet, Rev. 0.3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 25 Pinouts B[14] B[15] C[0] C[1] C[2] C[4] MSCR/ IMCR SSS Value MSCR[30] 0000 (Default) Signal Module Short Signal Description Dir GPI[30]3 ADC1_AN[1] SIUL2-GPI[30] General Purpose Input B[14] I 0001 - Reserved - - 0010-1111 - Reserved 0001 ETC4 eTimer_0 eTimer_0 Input Data Channel 4 I IMCR[192] 0001 REQ19 SIUL2 SIUL2 External Interrupt Source 19 I MSCR[31] 0000 (Default) GPI[31]3 ADC1_AN[2] SIUL2-GPI[31] General Purpose Input B[15] I 0001 - Reserved - - 0010-1111 - Reserved - - REQ20 SIUL2 SIUL2 External Interrupt Source 20 I GPI[32]3 ADC1_AN[3] SIUL2-GPI[32] General Purpose Input C[0] I 0001 - Reserved - - 0010-1111 - Reserved - - GPI[33]3 ADC0_AN[2] SIUL2-GPI[33] General Purpose Input C[1] I 0001 - Reserved - - 0010-1111 - Reserved - - GPI[34]3 ADC0_AN[3] SIUL2-GPI[34] General Purpose Input C[2] I 0001 - Reserved - - 0010-1111 - Reserved - - GPIO[36] SIUL2-GPIO[36] General Purpose IO C[4] I/O 0001 CS0 DSPI0 DSPI 0 Peripheral Chip Select 0 I/O 0010 X1 FlexPWM_0 FlexPWM_0 Auxiliary Input/Output 1 I/O 0011 DEBUG4 SSCM SSCM Debug Output 4 O - Reserved - - REQ22 SIUL2 SIUL2 External Interrupt Source 22 I 0001 MSCR[32] 0000 (Default) MSCR[33] MSCR[34] MSCR[36] 0000 (Default) 0000 (Default) 0000 (Default) 0100-1111 IMCR[195] 0001 64 75 P11 62 73 R11 66 77 R12 41 49 T4 45 53 U5 11 15 H3 - IMCR[63] IMCR[193] BGA257 SIUL2 MSCR/ IMCR Number LQFP176 Port Pin LQFP144 Table 7. Pin Muxing (continued) MPC5744P Data Sheet, Rev. 0.3 26 Preliminary—Subject to Change Without Notice Freescale Semiconductor Pinouts C[5] MSCR/ IMCR SSS Value MSCR[37] 0000 (Default) Dir General Purpose IO C[5] I/O 0001 SCK DSPI0 DSPI 0 Serial Clock (output) I/O 0010 - Reserved - - 0011 DEBUG5 SSCM SSCM Debug Output 5 O - Reserved - - IMCR[86] 0001 FAULT3 FlexPWM_0 FlexPWM_0 Fault Input 3 I IMCR[196] 0001 REQ23 SIUL2 SIUL2 External Interrupt Source 23 I MSCR[38] 0000 (Default) GPIO[38] SIUL2-GPIO[38] General Purpose IO C[6] I/O 0001 SOUT DSPI0 DSPI 0 Serial Data Out O 0010 B1 FlexPWM_0 FlexPWM_0 Channel B Input/Output 1 I/O 0011 DEBUG6 SSCM SSCM Debug Output 6 O - Reserved - - REQ24 SIUL2 SIUL2 External Interrupt Source 24 I GPIO[39] SIUL2-GPIO[39] General Purpose IO C[7] I/O 0001 - Reserved - - 0010 A1 FlexPWM_0 FlexPWM_0 Channel A Input/Output 1 I/O 0011 DEBUG7 SSCM SSCM Debug Output 7 O - Reserved - - SIN DSPI0 DSPI 0 Serial Data Input I GPIO[42] SIUL2-GPIO[42] General Purpose IO C[10] I/O 0001 CS2 DSPI2 DSPI 2 Peripheral Chip Select 2 O 0010 - Reserved - - 0011 A3 FlexPWM_0 FlexPWM_0 Channel A Input/Output 3 I/O - Reserved - - FAULT1 FlexPWM_0 FlexPWM_0 Fault Input 1 I IMCR[197] 0001 MSCR[39] 0000 (Default) 0100-1111 C[10] Short Signal Description SIUL2-GPIO[37] 0100-1111 C[7] Module GPIO[37] 0100-1111 C[6] Signal IMCR[41] 0001 MSCR[42] 0000 (Default) 0100-1111 IMCR[84] 0001 BGA257 SIUL2 MSCR/ IMCR Number LQFP176 Port Pin LQFP144 Table 7. Pin Muxing (continued) 13 17 G3 142 174 D4 15 19 J1 111 136 B14 MPC5744P Data Sheet, Rev. 0.3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 27 Pinouts C[11] MSCR/ IMCR SSS Value MSCR[43] 0000 (Default) Module Short Signal Description SIUL2-GPIO[43] General Purpose IO C[11] I/O 0001 ETC4 eTimer_0 eTimer_0 Input/Output Data Channel 4 I/O 0010 CS2 DSPI2 DSPI 2 Peripheral Chip Select 2 O - Reserved - - ETC4 eTimer_0 eTimer_0 Input Data Channel 4 I GPIO[44] SIUL2-GPIO[44] General Purpose IO C[12] I/O ETC5 eTimer_0 eTimer_0 Input/Output Data I/O IMCR[63] 0100 MSCR[44] 0000 (Default) 0001 Channel 5 C[13] Dir GPIO[43] 0011-1111 C[12] Signal CS3 DSPI2 DSPI 2 Peripheral Chip Select 3 O 0011 - Reserved - O 0100-1111 - Reserved - - ETC5 eTimer_0 eTimer_0 Input Data Channel 5 I GPIO[45] SIUL2-GPIO[45] General Purpose IO C[13] I/O ETC1 eTimer_1 eTimer_1 Input/Output Data Channel 1 I/O - Reserved - - A0 FlexPWM_1 FlexPWM_1 Channel A Input 0 I/O - Reserved - - EXT_IN CTU_0 CTU 0 External Trigger Input I 0011 MSCR[45] 0000 (Default) 0001 0010-0011 0100 0101-1111 80 97 P16 82 101 M14 101 125 E15 4 0010 IMCR[64] BGA257 SIUL2 MSCR/ IMCR Number LQFP176 Port Pin LQFP144 Table 7. Pin Muxing (continued) IMCR[38] 0001 (Default) IMCR[87] 0001 EXT_SYNC FlexPWM_0 FlexPWM_0 External Trigger Input I IMCR[105] 0001 A0 FlexPWM_1 FlexPWM_1 Channel A Input 0 I MPC5744P Data Sheet, Rev. 0.3 28 Preliminary—Subject to Change Without Notice Freescale Semiconductor Pinouts MSCR/ IMCR SSS Value MSCR[46] 0000 (Default) Short Signal Description Dir SIUL2-GPIO[46] General Purpose IO C[14] I/O 0001 ETC2 eTimer_1 eTimer_1 Input/Output Data Channel 2 I/O 0010 EXT_TGR CTU_0 CTU0 External Trigger Output O 0011 CS7 DSPI1 DSPI 1 Peripheral Chip Select 7 O 0100 B0 FlexPWM_1 FlexPWM_1 Channel B Input/Output 0 I/O - Reserved - - B0 FlexPWM_1 FlexPWM_1 Channel B Input 0 I GPIO[47] SIUL2-GPIO[47] General Purpose IO C[15] I/O 0001 FR_A_TXEN FLEXRAY FlexRay Transmit Enable Channel A O 0010 ETC0 eTimer_1 eTimer_1 Input/Output Data Channel 0 I/O 0011 A1 FlexPWM_0 FlexPWM_0 Channel A Input/Output 1 I/O - Reserved - - IMCR[106] 0001 MSCR[47] 0000 (Default) 0100-1111 D[0] Module GPIO[46] 0101-1111 C[15] Signal IMCR[38] 0010 EXT_IN CTU_0 CTU 0 External Trigger Input I IMCR[87] 0010 EXT_SYNC FlexPWM_0 FlexPWM_0 External Sync Input I MSCR[48] 0000 (Default) GPIO[48] SIUL2-GPIO[48] General Purpose IO D[0] I/O 0001 FR_A_TX FLEXRAY FlexRay Transmit Data Channel A O 0010 ETC1 eTimer_1 eTimer_1 Input/Output Data Channel 1 I/O 0011 B1 FlexPWM_0 FlexPWM_0 Channel B Input/Output 1 I/O - Reserved - - 0100-1111 BGA257 C[14] SIUL2 MSCR/ IMCR Number LQFP176 Port Pin LQFP144 Table 7. Pin Muxing (continued) 103 127 F14 124 156 A8 125 157 B8 MPC5744P Data Sheet, Rev. 0.3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 29 Pinouts D[1] MSCR/ IMCR SSS Value MSCR[49] 0000 (Default) Dir General Purpose IO D[1] I/O 0001 - Reserved - - 0010 ETC2 eTimer_1 eTimer_1 Input/Output Data Channel 2 I/O 0011 EXT_TGR CTU_0 CTU 0 External Trigger Output O - Reserved - - IMCR[136] 0001 FR_A_RX FLEXRAY FlexRay Channel A Receive Pin I MSCR[50] 0000 (Default) GPIO[50] SIUL2-GPIO[50] General Purpose IO D[2] I/O 0001 - Reserved - - 0010 ETC3 eTimer_1 eTimer_1 Input/Output Data Channel 3 I/O 0011 X3 FlexPWM_0 FlexPWM_0 Auxiliary Input/Output 3 I/O - Reserved - - IMCR[137] 0001 FR_B_RX FLEXRAY FlexRay Channel B Receive Pin I MSCR[51] 0000 (Default) GPIO[51] SIUL2-GPIO[51] General Purpose IO D[3] I/O 0001 FR_B_TX FLEXRAY FlexRay Transmit Data Channel B O 0010 ETC4 eTimer_1 eTimer_1 Input/Output Data Channel 4 I/O 0011 A3 FlexPWM_0 FlexPWM_0 Channel A Input/Output 3 I/O - Reserved - - GPIO[52] SIUL2-GPIO[52] General Purpose IO D[4] I/O 0001 FR_B_TXEN FLEXRAY FlexRay Transmit Enable Channel B O 0010 ETC5 eTimer_1 eTimer_1 Input/Output Data Channel 5 I/O 0011 B3 FlexPWM_0 FlexPWM_0 Channel B Input/Output 3 I/O - Reserved - - 0100-1111 D[4] Short Signal Description SIUL2-GPIO[49] 0100-1111 D[3] Module GPIO[49] 0100-1111 D[2] Signal MSCR[52] 0000 (Default) 0100-1111 BGA257 SIUL2 MSCR/ IMCR Number LQFP176 Port Pin LQFP144 Table 7. Pin Muxing (continued) 3 4 E3 140 172 B4 128 160 A5 129 161 B7 MPC5744P Data Sheet, Rev. 0.3 30 Preliminary—Subject to Change Without Notice Freescale Semiconductor Pinouts D[5] MSCR/ IMCR SSS Value MSCR[53] 0000 (Default) 0001 0010-1111 D[6] Short Signal Description Dir GPIO[53] SIUL2-GPIO[53] General Purpose IO D[5] I/O CS3 DSPI0 DSPI 0 Peripheral Chip Select 3 O - Reserved - - 0001 FAULT2 FlexPWM_0 FlexPWM_0 Fault Input 2 I IMCR[205] 0001 SENT_RX[0] SENT0 SENT 0 Receiver channel 0 I MSCR[54] 0000 (Default) GPIO[54] SIUL2-GPIO[54] General Purpose IO D[6] I/O 0001 CS2 DSPI0 DSPI 0 Peripheral Chip Select 2 O 0010 - Reserved - - 0011 X3 FlexPWM_0 FlexPWM_0 Auxiliary Input/Output 3 I/O - Reserved - - FAULT1 FlexPWM_0 FlexPWM_0 Fault Input 1 I GPIO[55] SIUL2-GPIO[55] General Purpose IO D[7] I/O IMCR[84] 0010 MSCR[55] 0000 (Default) CS3 DSPI1 DSPI 1 Peripheral Chip Select 3 O 0010 - Reserved - - 0011 CS4 DSPI0 DSPI 0 Peripheral Chip Select 4 O - Reserved - - SENT_RX[0] SENT1 SENT 1 Receiver channel 0 I GPIO[56] SIUL2-GPIO[56] General Purpose IO D[8] I/O 0001 CS2 DSPI1 DSPI 1 Peripheral Chip Select 2 O 0010 ETC4 eTimer_1 eTimer_1 Input/Output Data Channel 4 I/O 0011 CS5 DSPI0 DSPI 0 Peripheral Chip Select 5 O - Reserved - - FAULT3 FlexPWM_0 FlexPWM_0 Fault Input 3 I IMCR[213] 0001 MSCR[56] 0000 (Default) 0100-1111 IMCR[86] 0010 33 40 M4 34 41 P3 37 45 R4 32 39 L4 SWG OUT5 0001 0100-1111 D[8] Module IMCR[85] 0100-1111 D[7] Signal BGA257 SIUL2 MSCR/ IMCR Number LQFP176 Port Pin LQFP144 Table 7. Pin Muxing (continued) MPC5744P Data Sheet, Rev. 0.3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 31 Pinouts D[9] MSCR/ IMCR SSS Value MSCR[57] 0000 (Default) MSCR[58] I/O 0001 X0 FlexPWM_0 FlexPWM_0 Auxiliary Input/Output 0 I/O 0010 TXD LIN1 LINFlexD 1 Transmit Pin O - Reserved - - GPIO[58] SIUL2-GPIO[58] General Purpose IO D[10] I/O A0 FlexPWM_0 FlexPWM_0 Channel A Input/Output 0 I/O - Reserved - - ETC0 eTimer_0 eTimer_0 Input Data Channel 0 I GPIO[59] SIUL2-GPIO[59] General Purpose IO D[11] I/O B0 FlexPWM_0 FlexPWM_0 Channel B Input/Output 0 I/O - Reserved - - ETC1 eTimer_0 eTimer_0 Input Data Channel 1 I GPIO[60] SIUL2-GPIO[60] General Purpose IO D[12] I/O 0001 X1 FlexPWM_0 FlexPWM_0 Auxiliary Input/Output 1 I/O 0010 CS6 DSPI1 DSPI 1 Peripheral Chip Select 6 O - Reserved - - RXD LIN1 LIN 1 Receive Pin I GPIO[62] SIUL2-GPIO[62] General Purpose IO D[14] I/O B1 FlexPWM_0 FlexPWM_0 Channel B Input/Output 1 I/O - Reserved ETC3 eTimer_0 0000 (Default) IMCR[59] 0001 MSCR[59] 0000 (Default) 0001 0010-1111 IMCR[60] 0001 MSCR[60] 0000 (Default) 0011-1111 D[14] IMCR[166] 0010 MSCR[62] 0000 (Default) 0001 0010-1111 IMCR[62] Dir General Purpose IO D[9] 0010-1111 D[12] Short Signal Description SIUL2-GPIO[57] 0001 D[11] Module GPIO[57] 0011-1111 D[10] Signal 0001 BGA257 SIUL2 MSCR/ IMCR Number LQFP176 Port Pin LQFP144 Table 7. Pin Muxing (continued) 26 31 N3 76 93 R16 78 95 P17 99 123 F15 105 129 E17 eTimer_0 Input Data Channel 3 I MPC5744P Data Sheet, Rev. 0.3 32 Preliminary—Subject to Change Without Notice Freescale Semiconductor Pinouts E[0] E[2] E[4] E[5] E[6] E[7] E[9] E[10] MSCR/ IMCR SSS Value MSCR[64] 0000 (Default) MSCR[66] MSCR[68] MSCR[69] MSCR[70] MSCR[71] MSCR[73] MSCR[74] Signal Module Short Signal Description Dir GPI[64]3 ADC1_ADC3_A N[5] SIUL2-GPI[64] General Purpose Input E[0] I 0001 - Reserved - - 0010-1111 - Reserved - - GPI[66]3 ADC0_AN[5] SIUL2-GPI[66] General Purpose Input E[2] I 0001 - Reserved - - 0010-1111 - Reserved - - GPI[68]3 ADC0_AN[7] SIUL2-GPI[68] General Purpose Input E[4] I 0001 - Reserved - - 0010-1111 - Reserved - - GPI[69]3 ADC0_AN[8] SIUL2-GPI[69] General Purpose Input E[5] I 0001 - Reserved - - 0010-1111 - Reserved - - GPI[70]3 ADC0_AN[4] SIUL2-GPI[70] General Purpose Input E[6] I 0001 - Reserved - - 0010-1111 - Reserved - - GPI[71]3 ADC0_AN[6] SIUL2-GPI[71] General Purpose Input E[7] I 0001 - Reserved - - 0010-1111 - Reserved - - 0000 GPI[73]3 ADC1_ADC3_A N[7] SIUL2-GPI[73] General Purpose Input E[9] I 0001 - Reserved - - 0010-1111 - Reserved - - GPI[74]3 ADC1_ADC3_A N[8] SIUL2-GPI[74] General Purpose Input E[10] I 0001 - Reserved - - 0010-1111 - Reserved - - 0000 (Default) 0000 (Default) 0000 (Default) 0000 (Default) 0000 (Default) 0000 (Default) BGA257 SIUL2 MSCR/ IMCR Number LQFP176 Port Pin LQFP144 Table 7. Pin Muxing (continued) 68 79 T13 49 57 U6 42 50 U4 44 52 T5 46 54 R6 48 56 T6 61 72 U10 63 74 T11 MPC5744P Data Sheet, Rev. 0.3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 33 Pinouts E[11] E[12] E[13] MSCR/ IMCR SSS Value MSCR[75] 0000 (Default) MSCR[76] MSCR[77] Module Short Signal Description Dir GPI[75]3 ADC1_ADC3_A N[5] SIUL2-GPI[75] General Purpose Input E[11] I 0001 - Reserved - - 0010-1111 - Reserved - - GPI[76]3 ADC1_ADC3_A N6] SIUL2-GPI[76] General Purpose Input E[12] I 0001 - Reserved - - 0010-1111 - Reserved - - GPIO[77] SIUL2-GPIO[77] General Purpose IO E[13] I/O 0001 ETC5 eTimer_0 eTimer_0 Input/Output Data Channel 5 I/O 0010 CS3 DSPI2 DSPI 2 Peripheral Chip Select 3 O 0011 CS4 DSPI1 DSPI 1 Peripheral Chip Select 4 O - Reserved - - 0000 (Default) 0000 (Default) 0100-1111 E[14] Signal IMCR[198] 0001 REQ25 SIUL2 SIUL2 External Interrupt Source 25 I IMCR[64] 0100 ETC5 eTimer_0 eTimer_0 Input Data Channel I MSCR[78] 0000 (Default) GPIO[78] SIUL2-GPIO[78] General Purpose IO E[14] I/O 0001 ETC5 eTimer_1 eTimer_1 Input/Output Data Channel 5 I/O 0010 - Reserved - - 0011 CS5 DSPI1 DSPI 1 Peripheral Chip Select 5 O 0100 B2 FlexPWM_1 FlexPWM_1 Channel B Input/Output 2 I/O - Reserved - - 0101-1111 IMCR[113] 0001 B2 FlexPWM_1 FlexPWM_1 Channel B Input 2 I IMCR[199] 0001 REQ26 SIUL2 SIUL2 External Interrupt Source 26 I BGA257 SIUL2 MSCR/ IMCR Number LQFP176 Port Pin LQFP144 Table 7. Pin Muxing (continued) 65 76 U11 67 78 T12 117 144 A11 119 148 B10 MPC5744P Data Sheet, Rev. 0.3 34 Preliminary—Subject to Change Without Notice Freescale Semiconductor Pinouts MSCR/ IMCR SSS Value MSCR[79] 0000 (Default) 0001 0010-1111 F[0] IMCR[200] 0001 MSCR[80] 0000 (Default) 0001 0010-1111 F[3] Short Signal Description Dir GPIO[79] SIUL2-GPIO[79] General Purpose IO E[15] I/O CS1 DSPI0 DSPI 0 Peripheral Chip Select 1 O - Reserved - - REQ27 SIUL2 SIUL2 External Interrupt Source 27 I GPIO[80] SIUL2-GPIO[80] General Purpose IO F[0] I/O A1 FlexPWM_0 FlexPWM_0 Channel A Input/Output 1 I/O - Reserved - - 0001 ETC2 eTimer_0 eTimer_0 Input Data Channel 2 I IMCR[201] 0001 REQ28 SIUL2 SIUL2 External Interrupt Source 28 I MSCR[83] 0000 (Default) GPIO[83] SIUL2-GPIO[83] General Purpose IO F[3] I/O CS6 DSPI0 DSPI 0 Peripheral Chip Select 6 O - Reserved - - GPIO[84] SIUL2-GPIO[84] General Purpose IO F[4] I/O 0001 - Reserved - I/O 0010 MDO[3] NPC_WRAPPER Nexus - Message Data Out Pin 3 O - Reserved - - GPIO[85] SIUL2-GPIO[85] General Purpose IO F[5] I/O 0001 - Reserved - I/O 0010 MDO[2] NPC_WRAPPER Nexus Message Data Out Pin 2 O - Reserved - - 0010-1111 MSCR[84] 0000 (Default) 0011-1111 F[5] Module IMCR[61] 0001 F[4] Signal MSCR[85] 0000 (Default) 0011-1111 BGA257 E[15] SIUL2 MSCR/ IMCR Number LQFP176 Port Pin LQFP144 Table 7. Pin Muxing (continued) 121 151 C8 133 165 B6 139 171 B3 4 5 E1 5 8 F1 MPC5744P Data Sheet, Rev. 0.3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 35 Pinouts F[6] MSCR/ IMCR SSS Value MSCR[86] 0000 (Default) MSCR[87] MSCR[88] MSCR[89] I/O 0001 - Reserved - I/O 0010 MDO[1] NPC_WRAPPER Nexus Message Data Out Pin 1 O - Reserved - - GPIO[87] SIUL2-GPIO[87] General Purpose IO F[7] I/O 0001 - Reserved - I/O 0010 MCKO NPC_WRAPPER Nexus Message Clock Out for development tools O - Reserved - - GPIO[88] SIUL2-GPIO[88] General Purpose IO F[8] I/O 0001 - Reserved - I/O 0010 MSEO_B[1] NPC_WRAPPER Nexus Message Start/End Out Pin 1 O - Reserved - - GPIO[89] SIUL2-GPIO[89] General Purpose IO F[9] I/O 0001 - Reserved - I/O 0010 MSEO_B[0] NPC_WRAPPER Nexus Message Start/End Out Pin 0 O - Reserved - - GPIO[90] SIUL2-GPIO[90] General Purpose IO F[10] I/O 0001 - Reserved - - 0010 EVTO_B NPC_WRAPPER Nexus Event Out Pin O - Reserved - - GPIO[91] SIUL2-GPIO[91] General Purpose IO F[11] I/O 0001 - Reserved - - 0010 EVTI_IN NPC_WRAPPER Nexus Event In Pin I - Reserved - - 0000 (Default) 0000 (Default) 0000 (Default) 0011-1111 F[10] MSCR[90] 0000 (Default) 0011-1111 F[11] MSCR[91] Dir General Purpose IO F[6] 0011-1111 F[9] Short Signal Description SIUL2-GPIO[86] 0011-1111 F[8] Module GPIO[86] 0011-1111 F[7] Signal 0000 (Default) 0011-1111 BGA257 SIUL2 MSCR/ IMCR Number LQFP176 Port Pin LQFP144 Table 7. Pin Muxing (continued) 8 11 E2 19 24 J4 20 25 J3 23 28 K3 24 29 K2 25 30 L2 MPC5744P Data Sheet, Rev. 0.3 36 Preliminary—Subject to Change Without Notice Freescale Semiconductor Pinouts MSCR/ IMCR SSS Value MSCR[92] 0000 (Default) 0001 0010-0011 0100 0101-1111 F[13] Short Signal Description Dir GPIO[92] SIUL2-GPIO[92] General Purpose IO F[12] I/O ETC3 eTimer_1 eTimer_1 Input/Output Data Channel 3 I/O - Reserved - - A1 FlexPWM_1 FlexPWM_1 Channel A Input 1 I/O - Reserved - - 0001 A1 FlexPWM_1 FlexPWM_1 Channel A Input 1 I IMCR[203] 0001 REQ30 SIUL2 SIUL2 External Interrupt Source 30 I MSCR[93] 0000 (Default) GPIO[93] SIUL2-GPIO[93] General Purpose IO F[13] I/O ETC4 eTimer_1 eTimer_1 Input/Output Data Channel 4 I/O - Reserved - - B1 FlexPWM_1 FlexPWM_1 Channel B Input/Output 1 I/O - Reserved - - 0010-0011 0100 0101-1111 IMCR[110] 0001 B1 FlexPWM_1 FlexPWM_1 Channel B Input 1 I IMCR[204] 0001 REQ31 SIUL2 SIUL2 External Interrupt Source 31 I MSCR[94] 0000 (Default) GPIO[94] SIUL2-GPIO[94] General Purpose IO F[14] I/O 0001 TXD LIN1 LINFlexD 1 Transmit Pin O 0010 TXD CAN2 CAN 2 Transmit Pin O - Reserved - - GPIO[95] SIUL2-GPIO[95] General Purpose IO F[15] I/O 0001 - Reserved - - 0010-1111 - Reserved - - 0011-1111 F[15] Module IMCR[109] 0001 F[14] Signal MSCR[95] 0000 (Default) IMCR[166] 0011 RXD LIN1 LIN1 RXD I IMCR[34] 0001 RXD CAN2 CAN2 RXD I BGA257 F[12] SIUL2 MSCR/ IMCR Number LQFP176 Port Pin LQFP144 Table 7. Pin Muxing (continued) 106 130 D17 112 137 A15 115 142 D12 113 140 A13 MPC5744P Data Sheet, Rev. 0.3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 37 Pinouts MSCR/ IMCR SSS Value MSCR[98] 0000 (Default) MSCR[99] MSCR[100] I/O 0001 X2 FlexPWM_0 FlexPWM_0 Auxiliary Input/Output 1 I/O 0010 CS1 DSPI1 DSPI 1 Peripheral Chip Select 1 O - Reserved - - GPIO[99] SIUL2-GPIO[99] General Purpose IO G[3] I/O A2 FlexPWM_0 FlexPWM_0 Channel A Input/Output 2 I/O - Reserved - - ETC4 eTimer_0 eTimer_0 Input Data Channel 4 I GPIO[100] SIUL2-GPIO[100] General Purpose IO G[4] I/O B2 FlexPWM_0 FlexPWM_0 Channel B Input/Output 2 I/O - Reserved - - ETC5 eTimer_0 eTimer_0 Input Data Channel 5 I GPIO[101] SIUL2-GPIO[101] General Purpose IO G[5] I/O 0001 X3 FlexPWM_0 FlexPWM_0 Auxiliary Input/Output 3 I/O 0010 CS3 DSPI2 DSPI 2 Peripheral Chip Select 3 O - Reserved - - GPIO[102] SIUL2-GPIO[102] General Purpose IO G[6] I/O A3 FlexPWM_0 FlexPWM_0 Channel A Input/Output 3 I/O - Reserved - - 0000 (Default) 0010 0000 (Default) 0001 0010-1111 IMCR[64] G[5] MSCR[101] 0010 0000 (Default) 0011-1111 G[6] MSCR[102] Dir General Purpose IO G[2] 0010-1111 G[4] Short Signal Description SIUL2-GPIO[98] 0001 IMCR[63] Module GPIO[98] 0011-1111 G[3] Signal 0000 (Default) 0001 0010-1111 BGA257 G[2] SIUL2 MSCR/ IMCR Number LQFP176 Port Pin LQFP144 Table 7. Pin Muxing (continued) 102 126 F17 104 128 E16 100 124 F16 85 107 M17 98 122 G17 MPC5744P Data Sheet, Rev. 0.3 38 Preliminary—Subject to Change Without Notice Freescale Semiconductor Pinouts G[8] MSCR/ IMCR SSS Value MSCR[103] 0000 (Default) MSCR[104] Short Signal Description Dir SIUL2-GPIO[103] General Purpose IO G[7]6 I/O 0001 B3 FlexPWM_0 FlexPWM_0 Channel B Input/Output 3 I/O 0010 - Reserved - - 0011 - Reserved - - 0100-1111 - Reserved - - 0000 (Default) GPIO[104] SIUL2-GPIO[104] General Purpose IO G[8] I/O 0001 FR_DBG[0] FLEXRAY FlexRay Debug Strobe Signal 0 O 0010 CS1 DSPI0 DSPI 0 Peripheral Chip Select 1 O - Reserved - - IMCR[194] 0001 REQ21 SIUL2 SIUL2 External Interrupt Source 21 I IMCR[83] 0011 FAULT0 FlexPWM_0 FlexPWM_0 Fault Input 0 I 0000 (Default) GPIO[105] SIUL2-GPIO[105] General Purpose IO G[9] I/O 0001 FR_DBG[1] FLEXRAY FlexRay Debug Strobe Signal 1 O 0010 CS1 DSPI1 DSPI 1 Peripheral Chip Select 1 O - Reserved - - MSCR[105] 0011-1111 G[10] Module GPIO[103] 0011-1111 G[9] Signal IMCR[202] 0001 REQ29 SIUL2 SIUL2 External Interrupt Source 29 I IMCR[84] 0011 FAULT1 FlexPWM_0 FlexPWM_0 Fault Input 1 I 0000 (Default) GPIO[106] SIUL2-GPIO[106] General Purpose IO G[10] I/O 0001 FR_DBG[2] FLEXRAY FlexRay Debug Strobe Signal 2 O 0010 CS3 DSPI2 DSPI 2 Peripheral Chip Select 3 O - Reserved - - FAULT2 FlexPWM_0 FlexPWM_0 Fault Input 2 I MSCR[106] 0011-1111 IMCR[85] 0010 BGA257 G[7] SIUL2 MSCR/ IMCR Number LQFP176 Port Pin LQFP144 Table 7. Pin Muxing (continued) 83 104 M16 81 98 N14 79 96 P14 77 94 R17 MPC5744P Data Sheet, Rev. 0.3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 39 Pinouts G[11] MSCR/ IMCR SSS Value MSCR[107] 0000 (Default) GPIO[107] SIUL2-GPIO[107] General Purpose IO G[11] I/O 0001 FR_DBG[3] FLEXRAY FlexRay Debug Strobe Signal 3 O - Reserved - - FAULT3 FlexPWM_0 FlexPWM_0 Fault Input 3 I GPIO[116] SIUL2-GPIO[116] General Purpose IO H[4] I/O 0001 X0 FlexPWM_1 FlexPWM_1 Auxiliary Input/Output 0 I/O 0010 ETC0 eTimer_2 eTimer_2 Input/Output Data Channel 0 I/O - Reserved - - GPIO[117] SIUL2-GPIO[117] General Purpose IO H[5] I/O 0001 A0 FlexPWM_1 FlexPWM_1 Channel A Input/Output 0 I/O 0010 - Reserved - - 0011 CS4 DSPI0 DSPI 0 Peripheral Chip Select 4 O - Reserved - - A0 FlexPWM_1 FlexPWM_1 Channel A Input 0 I GPIO[118] SIUL2-GPIO[118] General Purpose IO H[6] I/O 0001 B0 FlexPWM_1 FlexPWM_1 Channel B Input/Output 0 I/O 0010 - Reserved - - 0011 CS5 DSPI0 DSPI 0 Peripheral Chip Select 5 O - Reserved - - B0 FlexPWM_1 FlexPWM_1 Channel B Input 0 I 0010-1111 IMCR[86] H[4] MSCR[116] 0011 0000 (Default) 0011-1111 H[5] MSCR[117] 0000 (Default) 0100-1111 H[6] IMCR[105] 0010 MSCR[118] 0000 (Default) 0100-1111 IMCR[106] 0010 Signal Module Short Signal Description Dir 75 BGA257 SIUL2 MSCR/ IMCR Number LQFP176 Port Pin LQFP144 Table 7. Pin Muxing (continued) 92 T15 6 F4 7 F3 138 C13 MPC5744P Data Sheet, Rev. 0.3 40 Preliminary—Subject to Change Without Notice Freescale Semiconductor Pinouts H[7] MSCR/ IMCR SSS Value MSCR[119] 0000 (Default) MSCR[120] Dir General Purpose IO H[7] I/O 0001 X1 FlexPWM_1 FlexPWM_1 Auxiliary Input/Output 1 I/O 0010 ETC1 eTimer_2 eTimer_2 Input/Output Data Channel 1 I/O - Reserved - - GPIO[120] SIUL2-GPIO[120] General Purpose IO H[8] I/O 0001 A1 FlexPWM_1 FlexPWM_1 Channel A Input/Output 1 I/O 0010 - Reserved - - 0011 CS6 DSPI0 DSPI 0 Peripheral Chip Select 6 O - Reserved - - A1 FlexPWM_1 FlexPWM_1 Channel A Input 1 I GPIO[121] SIUL2-GPIO[121] General Purpose IO H[9] I/O 0001 B1 FlexPWM_1 FlexPWM_1 Channel B Input/Output 1 I/O 0010 - Reserved - - 0011 CS7 DSPI0 DSPI 0 Peripheral Chip Select 7 O - Reserved - - B1 FlexPWM_1 FlexPWM_1 Channel B Input 1 I GPIO[122] SIUL2-GPIO[122] General Purpose IO H[10] I/O 0001 X2 FlexPWM_1 FlexPWM_1 Auxiliary Input/Output 2 I/O 0010 ETC2 eTimer_2 eTimer_2 Input/Output Data Channel 2 I/O - Reserved - - 0000 (Default) IMCR[109] 0010 MSCR[121] 0000 (Default) 0100-1111 H[10] Short Signal Description SIUL2-GPIO[119] 0100-1111 H[9] Module GPIO[119] 0011-1111 H[8] Signal IMCR[110] 0010 MSCR[122] 0000 (Default) 0011-1111 BGA257 SIUL2 MSCR/ IMCR Number LQFP176 Port Pin LQFP144 Table 7. Pin Muxing (continued) 12 F2 21 L1 139 B13 C7 MPC5744P Data Sheet, Rev. 0.3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 41 Pinouts MSCR/ IMCR SSS Value MSCR[123] 0000 (Default) I/O A2 FlexPWM_1 FlexPWM_1 Channel A Input/Output 2 I/O - Reserved - - A2 FlexPWM_1 FlexPWM_1 Channel A Input 2 I GPIO[124] SIUL2-GPIO[124] General Purpose IO H[12] I/O B2 FlexPWM_1 FlexPWM_1 Channel B Input/Output 2 I/O - Reserved - - B2 FlexPWM_1 FlexPWM_1 Channel B Input 2 I GPIO[125] SIUL2-GPIO[125] General Purpose IO H[13] I/O 0001 X3 FlexPWM_1 FlexPWM_1 Auxiliary Input/Output 3 I/O 0010 ETC3 eTimer_2 eTimer_2 Input/Output Data Channel 3 I/O - Reserved - - GPIO[126] SIUL2-GPIO[126] General Purpose IO H[14] I/O 0001 A3 FlexPWM_1 FlexPWM_1 Channel A Input/Output 3 I/O 0010 ETC4 eTimer_2 eTimer_2 Input/Output Data Channel 4 I/O - Reserved - - GPIO[127] SIUL2-GPIO[127] General Purpose IO H[15] I/O 0001 B3 FlexPWM_1 FlexPWM_1 Channel B Input/Output 3 I/O 0010 ETC5 eTimer_2 eTimer_2 Input/Output Data Channel 5 I/O - Reserved - - IMCR[112] 0010 MSCR[124] 0000 (Default) 0010-1111 IMCR[113] 0010 MSCR[125] 0000 (Default) 0011-1111 MSCR[126] 0000 (Default) 0011-1111 H[15] MSCR[127] Dir General Purpose IO H[11] 0001 H[14] Short Signal Description SIUL2-GPIO[123] 0010-1111 H[13] Module GPIO[123] 0001 H[12] Signal 0000 (Default) 0011-1111 BGA257 H[11] SIUL2 MSCR/ IMCR Number LQFP176 Port Pin LQFP144 Table 7. Pin Muxing (continued) 150 C9 153 A7 A14 89 P13 133 C17 MPC5744P Data Sheet, Rev. 0.3 42 Preliminary—Subject to Change Without Notice Freescale Semiconductor Pinouts MSCR/ IMCR SSS Value MSCR[128] 0000 (Default) I/O 0001 ETC0 eTimer_2 eTimer_2 Input/Output Data Channel 0 I/O 0010 CS4 DSPI0 DSPI 0 Peripheral Chip Select 4 O - Reserved - - FAULT0 FlexPWM_1 FlexPWM_1 Fault Input 0 I GPIO[129] SIUL2-GPIO[129] General Purpose IO I[1] I/O 0001 ETC1 eTimer_2 eTimer_2 Input/Output Data Channel 1 I/O 0010 CS5 DSPI0 DSPI 0 Peripheral Chip Select 5 O - Reserved - - FAULT1 FlexPWM_1 FlexPWM_1 Fault Input 1 I GPIO[130] SIUL2-GPIO[130] General Purpose IO I[2] I/O 0001 ETC2 eTimer_2 eTimer_2 Input/Output Data Channel 2 I/O 0010 CS6 DSPI0 DSPI 0 Peripheral Chip Select 6 O - Reserved - - FAULT2 FlexPWM_1 FlexPWM_1 Fault Input 2 I GPIO[131] SIUL2-GPIO[131] General Purpose IO I[3] I/O 0001 ETC3 eTimer_2 eTimer_2 Input/Output Data Channel 3 I/O 0010 CS7 DSPI0 DSPI 0 Peripheral Chip Select 7 O 0011 EXT_TGR CTU_0 CTU0 External Trigger Output O - Reserved - - FAULT3 FlexPWM_1 FlexPWM_1 Fault Input 3 I IMCR[100] 0001 MSCR[129] 0000 (Default) IMCR[101] 0001 MSCR[130] 0000 (Default) IMCR[102] 0001 MSCR[131] 0000 (Default) 0100-1111 IMCR[103] Dir General Purpose IO I[0] 0011-1111 I[3] Short Signal Description SIUL2-GPIO[128] 0011-1111 I[2] Module GPIO[128] 0011-1111 I[1] Signal 0001 BGA257 I[0] SIUL2 MSCR/ IMCR Number LQFP176 Port Pin LQFP144 Table 7. Pin Muxing (continued) 155 C6 44 T3 146 D11 147 A10 MPC5744P Data Sheet, Rev. 0.3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 43 Pinouts RDY_B /I[4] MSCR/ IMCR SSS Value MSCR[132] 0000 (Default) I[6] MSCR[133] MSCR[134] IMCR[34] I[7] MSCR[135] I[9] MSCR[136] Dir General Purpose IO I[4] I/O 0001 - Reserved - - 0010 NEX_RDY_B NPC_WRAPPER Nexus data ready for transfer (RDY_B) O - Reserved - - GPIO[133] SIUL2-GPIO[133] General Purpose IO I[5]7 I/O 0001 TXD CAN2 CAN 2 Transmit Pin O 0010 - Reserved - - 0011 - Reserved - O 0100-1111 - Reserved - - GPIO[134] SIUL2-GPIO[134] General Purpose IO I[6]8 I/O 0001 - Reserved - - 0010 - Reserved - - 0011 - Reserved - I 0100-1111 - Reserved - - RXD CAN2 CAN 2 Receive Pin I GPIO[135] SIUL2-GPIO[135] General Purpose IO I[7] I/O LFAST_REF_C LK MC_CGM SIPI LFAST reference clock - - Reserved - - SENT_RX[0] SENT0 SENT 0 Receiver channel 0 I GPIO[136] SIUL2-GPIO[136] General Purpose IO I[8] I/O 0001 - Reserved - - 0010-1111 - Reserved - - SENT_RX[0] SENT1 SENT 1 Receiver channel 0 I GPIO[137] SIUL2-GPIO[137] General Purpose IO I[9] I/O ETC4 eTimer_2 eTimer_2 Input/Output Data Channel 4 I/O - Reserved - - 0000 (Default) 0000 (Default) 0010 0000 (Default) 0010-1111 I[8] Short Signal Description SIUL2-GPIO[132] 0001 IMCR[717 Module GPIO[132] 0011-1111 I[5] Signal 0010 0000 (Default) IMCR[213] 0010 MSCR[137] 0000 (Default) 0001 0010-1111 BGA257 SIUL2 MSCR/ IMCR Number LQFP176 Port Pin LQFP144 Table 7. Pin Muxing (continued) J2 102 N15 103 M15 3 D2 K4 L3 MPC5744P Data Sheet, Rev. 0.3 44 Preliminary—Subject to Change Without Notice Freescale Semiconductor Pinouts I[10] MSCR/ IMCR SSS Value MSCR[138] 0000 (Default) I[12] I[13] I/O ETC5 eTimer_2 eTimer_2 Input/Output Data Channel 5 I/O - Reserved - - GPIO[139] SIUL2-GPIO[139] General Purpose IO I[11] I/O 0001 - Reserved - - 0010-1111 - Reserved - - SENT_RX[1] SENT0 SENT 0 Receiver channel 1 I GPIO[140] SIUL2-GPIO[140] General Purpose IO I[12] I/O 0001 - Reserved - - 0010-1111 - Reserved - - 0000 (Default) IMCR[206] 0001 MSCR[140] 0000 (Default) IMCR[214] 0001 SENT_RX[1] SENT1 SENT 1 Receiver channel 1 I MSCR[141] 0000 GPIO[141] SIUL2-GPIO[141] General Purpose IO I[13] I/O 0001 EXT_TGR CTU_1 CTU1 External Trigger Output I/O - Reserved - - GPIO[142] SIUL2-GPIO[142] General Purpose IO I[14] I/O CS0 DSPI3 DSPI 3 Peripheral Chip Select 0 O - Reserved - - GPIO[143] SIUL2-GPIO[143] General Purpose IO I[15] I/O SCK DSPI3 DSPI 3 Serial Clock (output) I/O - Reserved - - GPIO[144] SIUL2-GPIO[144] General Purpose IO J[0] I/O SOUT DSPI3 DSPI 3 Serial Data Out O - Reserved - - MSCR[142] 0000 (Default) 0001 0010-1111 I[15] MSCR[143] 0000 (Default) 0001 0010-1111 J[0] Dir General Purpose IO I[10] 0010-1111 I[14] Short Signal Description SIUL2-GPIO[138] 0010-1111 MSCR[139] Module GPIO[138] 0001 I[11] Signal MSCR[144] 0000 (Default) 0001 0010-1111 BGA257 SIUL2 MSCR/ IMCR Number LQFP176 Port Pin LQFP144 Table 7. Pin Muxing (continued) M3 U3 P5 P6 C10 C1 C2 MPC5744P Data Sheet, Rev. 0.3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 45 Pinouts J[1] MSCR/ IMCR SSS Value MSCR[145] 0000 (Default) IMCR[50] J[2] MSCR[146] I/O 0001 - Reserved - - 0010-1111 - Reserved - - SIN DSPI3 DSPI 3 Serial Data Input I GPIO[146] SIUL2-GPIO[146] General Purpose IO J[2] I/O CS1 DSPI3 DSPI 3 Peripheral Chip Select 1 O - Reserved - - GPIO[147] SIUL2-GPIO[147] General Purpose IO J[3] I/O CS2 DSPI3 DSPI 3 Peripheral Chip Select 2 O - Reserved - - GPIO[148] SIUL2-GPIO[148] General Purpose IO J[4] I/O CS3 DSPI3 DSPI 3 Peripheral Chip Select 3 O - Reserved - - EXT_IN CTU_1 CTU 1 External Trigger Input I GPI[149]3 ADC2_ADC3_A N[0] SIUL2-GPI[149] General Purpose Input J[5] I 0001 - Reserved - - 0010-1111 - Reserved - - SENT_RX[1] SENT0 SENT 0 Receiver channel 1 I GPI[150]3 ADC2_ADC3_A N[1] SIUL2-GPI[150] General Purpose Input J[6] I 0001 - Reserved - - 0010-1111 - Reserved - - SENT_RX[1] SENT1 SENT 1 Receiver channel 1 I 0001 0000 (Default) 0000 (Default) 0010-1111 MSCR[148] 0000 (Default) 0001 0010-1111 IMCR[39] J[5] J[6] MSCR[149] 0001 0000 (Default) IMCR[206] 0010 MSCR[150] 0000 (Default) IMCR[214] Dir General Purpose IO J[1] 0001 J[4] Short Signal Description SIUL2-GPIO[145] 0010-1111 MSCR[147] Module GPIO[145] 0001 J[3] Signal 0010 BGA257 SIUL2 MSCR/ IMCR Number LQFP176 Port Pin LQFP144 Table 7. Pin Muxing (continued) A12 C11 B15 D13 64 P8 65 P9 MPC5744P Data Sheet, Rev. 0.3 46 Preliminary—Subject to Change Without Notice Freescale Semiconductor Pinouts J[7] J[8] MSCR/ IMCR SSS Value MSCR[151] 0000 (Default) MSCR[152] J[9] MSCR[153] Short Signal Description Dir SIUL2-GPI[151] General Purpose Input J[7] I 0001 - Reserved - - 0010-1111 - Reserved - - GPIO[152] SIUL2-GPIO[152] General Purpose IO J[8] I/O 0001 ETC4 eTimer_2 eTimer_2 Input/Output Data Channel 4 I/O 0010 ETC2 eTimer_2 eTimer_2 Input/Output Data Channel 2 - - Reserved - - RXD CAN2 CAN 2 Receive Pin I GPIO[153] SIUL2-GPIO[153] General Purpose IO J[9] I/O 0001 ETC5 eTimer_2 eTimer_2 Input/Output Data Channel 5 I/O 0010 NEX_RDY_B NPC Nexus data ready for transfer (RDY_B) O - Reserved - - EXT_IN CTU_1 CTU_1 External Trigger Input I 0000 (Default) 0011 0000 (Default) 0011-1111 IMCR[39] Module GPI[151]3 ADC2_ADC3_A N[2] 0011-1111 IMCR[34] Signal 0010 BGA257 SIUL2 MSCR/ IMCR Number LQFP176 Port Pin LQFP144 Table 7. Pin Muxing (continued) 66 P10 95 119 G16 16 20 K1 NOTES: 1 (Default) = ALT mode configuration after reset. 2 Changing B[5] configuration during debug might impact availability of TDI. 3 ADC analog input. Program corresponding MSCR APC bit and enable ADC to switch-on analog input path. See Table 13 for details. 4 Shared with SIPI LFAST transmit pad SIPI_TXP. Alternative modes and GPIO must be disabled (OBE=0, IBE=0) if port is used for SIPI LFAST. 5 Sine Wave Generator (SWG) output if SWG is enabled. See Table 13 for details. 6 Shared with SIPI LFAST receive pad SIPI_RXP. Alternative modes and GPIO must be disabled (OBE=0, IBE=0) if port is used for SIPI LFAST. 7 Shared with SIPI LFAST transmit pad SIPI_TXN. Alternative modes and GPIO must be disabled (OBE=0, IBE=0) if port is used for SIPI LFAST. 8 Shared with SIPI LFAST receive pad SIPI_RXN. Alternative modes and GPIO must be disabled (OBE=0, IBE=0) if port is used for SIPI LFAST. MPC5744P Data Sheet, Rev. 0.3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 47 Pinouts Table 8 list ports that are not implemented. The corresponding control and data registers are not implemented. Table 8. Ports - Not Implemented Port Name Port Index C 3,8,9 D 15,13 E 1,3,8 F 1,2 G 0,1 J [15:12] H 2,3 Any attempt to access unimplemented MSCRs generates a bus error. The read value from unimplemented ports must be masked in case of parallel port accesses. 2.2.6 Peripheral pin muxing The following table describes the peripheral muxing capabilities of the MPC5744P. See the device Reference Manual for MSCR register addresses. Table 9. Peripheral Muxing Destination Peripherals FlexCAN_0 FlexCAN_1 Destination Functions RXD RXD IMCR Register IMCR[32] IMCR[33] IMCR:SSS Field Value Source Peripherials Source Functions 0000_0000 (Default)1 - Disable 0000_0001 I/O-Pad A[15] 0000_0010 I/O-Pad B[1] 0000_0011-1 111_1111 - Reserved 0000_0000 (Default) - Disable 0000_0001 I/O-Pad A[15] 0000_0010 I/O-Pad B[1] - Reserved 0000_0011-1 111_1111 MPC5744P Data Sheet, Rev. 0.3 48 Preliminary—Subject to Change Without Notice Freescale Semiconductor Pinouts Table 9. Peripheral Muxing Destination Peripherals FlexCAN_2 CTU_0 CTU_1 DSPI_0 DSPI_1 Destination Functions RXD EXT_IN EXT_IN SIN SIN IMCR Register IMCR[34] IMCR[38] IMCR[39] IMCR[41] IMCR[44] IMCR:SSS Field Value Source Peripherials Source Functions 0000_0000 (Default) - Disable 0000_0001 I/O-Pad F[15] 0000_0010 I/O-Pad I[6] 0000_0011 I/O-Pad J[8] 0000_0100-1 111_1111 - Reserved 0000_0000 (Default) - Disable 0000_0001 I/O-Pad C[13] 0000_0010 I/O-Pad C[15] 0000_0011-1 111_1111 - Reserved 0000_0000 (Default) - Disable 0000_0001 I/O-Pad J[4] 0000_0010 I/O-Pad J[9] 0000_0011-1 111_1111 - Reserved 0000_0000 (Default) - Disable 0000_0001 I/O-Pad C[7] 0000_0010-1 111_1111 - Reserved 0000_0000 (Default) - Disable 0000_0001 I/O-Pad A[8] - Reserved 0000_0010-1 111_1111 MPC5744P Data Sheet, Rev. 0.3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 49 Pinouts Table 9. Peripheral Muxing Destination Peripherals DSPI_2 DSPI_3 eTimer_0 eTimer_0 eTimer_0 Destination Functions SIN SIN ETC0 ETC1 ETC2 IMCR Register IMCR[47] IMCR[50] IMCR[59] IMCR[60] IMCR[61] IMCR:SSS Field Value Source Peripherials Source Functions 0000_0000 (Default) - Disable 0000_0001 I/O-Pad A[13] 0000_0010 I/O-Pad A[2] 0000_0011-1 111_1111 - Reserved 0000_0000 (Default) - Disable 0000_0001 I/O-Pad J[1] 0000_0010-1 111_1111 - Reserved 0000_0000 (Default) - Disable 0000_0001 I/O-Pad D[10] 0000_0010 I/O-Pad A[0] 0000_0011-1 111_1111 - Reserved 0000_0000 (Default) - Disable 0000_0001 I/O-Pad D[11] 0000_0010 I/O-Pad A[1] 0000_0011-1 111_1111 - Reserved 0000_0000 (Default) - Disable 0000_0001 I/O-Pad F[0] 0000_0010 I/O-Pad A[2] - Reserved 0000_0011-1 111_1111 MPC5744P Data Sheet, Rev. 0.3 50 Preliminary—Subject to Change Without Notice Freescale Semiconductor Pinouts Table 9. Peripheral Muxing Destination Peripherals eTimer_0 eTimer_0 eTimer_0 flexPWM_0 Destination Functions ETC3 ETC4 ETC5 FAULT0 IMCR Register IMCR[62] IMCR[63] IMCR[64] IMCR[83] IMCR:SSS Field Value Source Peripherials Source Functions 0000_0000 (Default) - Disable 0000_0001 I/O-Pad D[14] 0000_0010 I/O-Pad A[3] 0000_0011-1 111_1111 - Reserved 0000_0000 (Default) - Disable 0000_0001 I/O-Pad B[14] 0000_0010 I/O-Pad G[3] 0000_0011 I/O-Pad A[4] 0000_0100 I/O-Pad C[11] 0000_0101-1 111_1111 - Reserved 0000_0000 (Default) - Disable 0000_0001 I/O-Pad B[8] 0000_0010 I/O-Pad G[4] 0000_0011 I/O-Pad C[12] 0000_0100 I/O-Pad E[13] 0000_0101-1 111_1111 - Reserved 0000_0000 (Default) - Disable 0000_0001 I/O-Pad A[9] 0000_0010 I/O-Pad A[13] 0000_0011 I/O-Pad G[8] - Reserved 0000_0100-1 111_1111 MPC5744P Data Sheet, Rev. 0.3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 51 Pinouts Table 9. Peripheral Muxing Destination Peripherals flexPWM_0 flexPWM_0 flexPWM_0 flexPWM_0 flexPWM_1 Destination Functions FAULT1 IMCR[84] FAULT2 IMCR[85] FAULT3 IMCR[86] EXT_SYNC FAULT0 IMCR Register IMCR[87] IMCR[100] IMCR:SSS Field Value Source Peripherials Source Functions 0000_0000 (Default) - Disable 0000_0001 I/O-Pad C[10] 0000_0010 I/O-Pad D[6] 0000_0011 I/O-Pad G[9] 0000_0100-1 111_1111 - Reserved 0000_0000 (Default) - Disable 0000_0001 I/O-Pad D[5] 0000_0010 I/O-Pad G[10] 0000_0011-1 111_1111 - Reserved 0000_0000 (Default) - Disable 0000_0001 I/O-Pad C[5] 0000_0010 I/O-Pad D[8] 0000_0011 I/O-Pad G[11] 0000_0100-1 111_1111 - Reserved 0000_0000 (Default) - Disable 0000_0001 I/O-Pad C[13] 0000_0010 I/O-Pad C[15] 0000_0011-1 111_1111 - Reserved 0000_0000 (Default) - Disable 0000_0001 I/O-Pad I[0] - Reserved 0000_0010-1 111_1111 MPC5744P Data Sheet, Rev. 0.3 52 Preliminary—Subject to Change Without Notice Freescale Semiconductor Pinouts Table 9. Peripheral Muxing Destination Peripherals flexPWM_1 flexPWM_1 flexPWM_1 flexPWM_1 flexPWM_1 flexPWM_1 Destination Functions FAULT1 FAULT2 FAULT3 A0 B0 A1 IMCR Register IMCR[101] IMCR[102] IMCR[103] IMCR[105] IMCR[106] IMCR[109] IMCR:SSS Field Value Source Peripherials Source Functions 0000_0000 (Default) - Disable 0000_0001 I/O-Pad I[1] 0000_0010-1 111_1111 - Reserved 0000_0000 (Default) - Disable 0000_0001 I/O-Pad I[2] 0000_0010-1 111_1111 - Reserved 0000_0000 (Default) - Disable 0000_0001 I/O-Pad I[3] 0000_0010-1 111_1111 - Reserved 0000_0000 (Default) - Disable 0000_0001 I/O-Pad C[13] 0000_0010 I/O-Pad H[5] 0000_0011-1 111_1111 - Reserved 0000_0000 (Default) - Disable 0000_0001 I/O-Pad C[14] 0000_0010 I/O-Pad H[6] 0000_0011-1 111_1111 - Reserved 0000_0000 (Default) - Disable 0000_0001 I/O-Pad F[12] 0000_0010 I/O-Pad H[8] - Reserved 0000_0011-1 111_1111 MPC5744P Data Sheet, Rev. 0.3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 53 Pinouts Table 9. Peripheral Muxing Destination Peripherals flexPWM_1 flexPWM_1 flexPWM_1 flexRay flexRay LIN_0 Destination Functions B1 A2 B2 FR_A_RX FR_B_RX RXD IMCR Register IMCR[110] IMCR[112] IMCR[113] IMCR[136] IMCR[137] IMCR[165] IMCR:SSS Field Value Source Peripherials Source Functions 0000_0000 (Default) - Disable 0000_0001 I/O-Pad F[13] 0000_0010 I/O-Pad H[9] 0000_0011-1 111_1111 - Reserved 0000_0000 (Default) - Disable 0000_0001 I/O-Pad A[4] 0000_0010 I/O-Pad H[11] 0000_0011-1 111_1111 - Reserved 0000_0000 - Disable 0000_0001 I/O-Pad E[14] 0000_0010 I/O-Pad H[12] 0000_0011-1 111_1111 - Reserved 0000_0000 (Default) - Disable 0000_0001 I/O-Pad D[1] 0000_0010-1 111_1111 - Reserved 0000_0000 (Default) - Disable 0000_0001 I/O-Pad D[2] 0000_0010-1 111_1111 - Reserved 0000_0000 (Default) - Disable 0000_0001 I/O-Pad B[3] 0000_0010 I/O-Pad B[7] - Reserved 0000_0011-1 111_1111 MPC5744P Data Sheet, Rev. 0.3 54 Preliminary—Subject to Change Without Notice Freescale Semiconductor Pinouts Table 9. Peripheral Muxing Destination Peripherals LIN_1 Destination Functions RXD IMCR Register IMCR[166] IMCR:SSS Field Value MC_RGM MC_RGM SIUL SIUL ABS1 ABS2 FAB REQ0 REQ1 IMCR[169] IMCR[171] IMCR[172] IMCR[173] IMCR[174] Source Functions 0000_0000 (Default) - Disable 0000_0001 I/O-Pad B[13] 0000_0010 I/O-Pad D[12] 0000_0011 I/O-Pad F[15] - Reserved 0000_0000 (Default) I/O-Pad A[2] 0000_0001 - Disable 0000_0010-1 111_1111 - Reserved 0000_0000 (Default) I/O-Pad A[3] 0000_0001 - Disable 0000_0010-1 111_1111 - Reserved 0000_0000 (Default) I/O-Pad A[4] 0000_0001 - Disable 0000_0010-1 111_1111 - Reserved 0000_0000 (Default) - Disable 0000_0001 I/O-Pad A[0] 0000_0010-1 111_1111 - Reserved 0000_0000 (Default) - Disable 0000_0001 I/O-Pad A[1] - Reserved 0000_0100-1 111_1111 MC_RGM Source Peripherials 0000_0010-1 111_1111 MPC5744P Data Sheet, Rev. 0.3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 55 Pinouts Table 9. Peripheral Muxing Destination Peripherals SIUL SIUL SIUL SIUL SIUL SIUL SIUL Destination Functions REQ2 REQ3 REQ4 REQ5 REQ6 REQ7 REQ8 IMCR Register IMCR[175] IMCR[176] IMCR[177] IMCR[178] IMCR[179] IMCR[180] IMCR[181] IMCR:SSS Field Value Source Peripherials Source Functions 0000_0000 (Default) - Disable 0000_0001 I/O-Pad A[2] 0000_0010-1 111_1111 - Reserved 0000_0000 (Default) - Disable 0000_0001 I/O-Pad A[3] 0000_0010-1 111_1111 - Reserved 0000_0000 (Default) - Disable 0000_0001 I/O-Pad A[4] 0000_0010-1 111_1111 - Reserved 0000_0000 (Default) - Disable 0000_0001 I/O-Pad A[5] 0000_0010-1 111_1111 - Reserved 0000_0000 (Default) - Disable 0000_0001 I/O-Pad A[6] 0000_0010-1 111_1111 - Reserved 0000_0000 (Default) - Disable 0000_0001 I/O-Pad A[7] 0000_0010-1 111_1111 - Reserved 0000_0000 (Default) - Disable 0000_0001 I/O-Pad A[8] - Reserved 0000_0010-1 111_1111 MPC5744P Data Sheet, Rev. 0.3 56 Preliminary—Subject to Change Without Notice Freescale Semiconductor Pinouts Table 9. Peripheral Muxing Destination Peripherals SIUL SIUL SIUL SIUL SIUL SIUL SIUL Destination Functions REQ9 REQ10 REQ11 REQ12 REQ13 REQ14 REQ15 IMCR Register IMCR[182] IMCR[183] IMCR[184] IMCR[185] IMCR[186] IMCR[187] IMCR[188] IMCR:SSS Field Value Source Peripherials Source Functions 0000_0000 (Default) - Disable 0000_0001 I/O-Pad A[10] 0000_0010-1 111_1111 - Reserved 0000_0000 (Default) - Disable 0000_0001 I/O-Pad A[11] 0000_0010-1 111_1111 - Reserved 0000_0000 (Default) - Disable 0000_0001 I/O-Pad A[12] 0000_0010-1 111_1111 - Reserved 0000_0000 (Default) - Disable 0000_0001 I/O-Pad A[13] 0000_0010-1 111_1111 - Reserved 0000_0000 (Default) - Disable 0000_0001 I/O-Pad A[14] 0000_0010-1 111_1111 - Reserved 0000_0000 (Default) - Disable 0000_0001 I/O-Pad A[15] 0000_0010-1 111_1111 - Reserved 0000_0000 (Default) - Disable 0000_0001 I/O-Pad B[0] - Reserved 0000_0010-1 111_1111 MPC5744P Data Sheet, Rev. 0.3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 57 Pinouts Table 9. Peripheral Muxing Destination Peripherals SIUL SIUL SIUL SIUL SIUL SIUL SIUL Destination Functions REQ16 REQ17 REQ18 REQ19 REQ20 REQ21 REQ22 IMCR Register IMCR[189] IMCR[190] IMCR[191] IMCR[192] IMCR[193] IMCR[194] IMCR[195] IMCR:SSS Field Value Source Peripherials Source Functions 0000_0000 (Default) - Disable 0000_0001 I/O-Pad B[1] 0000_0010-1 111_1111 - Reserved 0000_0000 (Default) - Disable 0000_0001 I/O-Pad B[2] 0000_0010-1 111_1111 - Reserved 0000_0000 (Default) - Disable 0000_0001 I/O-Pad B[6] 0000_0010-1 111_1111 - Reserved 0000_0000 (Default) - Disable 0000_0001 I/O-Pad B[14] 0000_0010-1 111_1111 - Reserved 0000_0000 (Default) - Disable 0000_0001 I/O-Pad B[15] 0000_0010-1 111_1111 - Reserved 0000_0000 (Default) - Disable 0000_0001 I/O-Pad G[8] 0000_0010-1 111_1111 - Reserved 0000_0000 (Default) - Disable 0000_0001 I/O-Pad C[4] - Reserved 0000_0010-1 111_1111 MPC5744P Data Sheet, Rev. 0.3 58 Preliminary—Subject to Change Without Notice Freescale Semiconductor Pinouts Table 9. Peripheral Muxing Destination Peripherals SIUL SIUL SIUL SIUL SIUL SIUL SIUL Destination Functions REQ23 REQ24 REQ25 REQ26 REQ27 REQ28 REQ29 IMCR Register IMCR[196] IMCR[197] IMCR[198] IMCR[199] IMCR[200] IMCR[201] IMCR[202] IMCR:SSS Field Value Source Peripherials Source Functions 0000_0000 (Default) - Disable 0000_0001 I/O-Pad C[5] 0000_0010-1 111_1111 - Reserved 0000_0000 (Default) - Disable 0000_0001 I/O-Pad C[6] 0000_0010-1 111_1111 - Reserved 0000_0000 (Default) - Disable 0000_0001 I/O-Pad E[13] 0000_0010-1 111_1111 - Reserved 0000_0000 (Default) - Disable 0000_0001 I/O-Pad E[14] 0000_0010-1 111_1111 - Reserved 0000_0000 (Default) - Disable 0000_0001 I/O-Pad E[15] 0000_0010-1 111_1111 - Reserved 0000_0000 (Default) - Disable 0000_0001 I/O-Pad F[0] 0000_0010-1 111_1111 - Reserved 0000_0000 (Default) - Disable 0000_0001 I/O-Pad G[9] - Reserved 0000_0010-1 111_1111 MPC5744P Data Sheet, Rev. 0.3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 59 Pinouts Table 9. Peripheral Muxing Destination Peripherals SIUL SIUL SENT_0 SENT_0 SENT_1 SENT_1 Destination Functions REQ30 IMCR Register IMCR[203] REQ31 IMCR[204] SENT_RX[0] SENT_RX[1] SENT_RX[0] SENT_RX[1] IMCR[205] IMCR[206] IMCR[213] IMCR[214] IMCR:SSS Field Value Source Peripherials Source Functions 0000_0000 (Default) - Disable 0000_0001 I/O-Pad F[12] 0000_0010-1 111_1111 - Reserved 0000_0000 (Default) - Disable 0000_0001 I/O-Pad F[13] 0000_0010-1 111_1111 - Reserved 0000_0000 (Default) - Disable 0000_0001 I/O-Pad D[5] 0000_0010 I/O-Pad I[7] 0000_0011-1 111_1111 - Reserved 0000_0000 (Default) - Disable 0000_0001 I/O-Pad I[11] 0000_0010 I/O-Pad J[5] 0000_0011-1 111_1111 - Reserved 0000_0000 (Default) - Disable 0000_0001 I/O-Pad D[7] 0000_0010 I/O-Pad I[8] 0000_0011-1 111_1111 - Reserved 0000_0000 (Default) - Disable 0000_0001 I/O-Pad I[12] 0000_0010 I/O-Pad J[6] - Reserved 0000_0011-1 111_1111 MPC5744P Data Sheet, Rev. 0.3 60 Preliminary—Subject to Change Without Notice Freescale Semiconductor Pinouts 1) (Default) = configuration after reset. Peripheral Muxing Example: SSS field in IMCR register 214: 0x1 I/O-Pad I[12] is connected to SENT_1 Receive input SENT_RX[1] SSS field in IMCR register 214: 0x2 I/O-Pad J[6] is connected to SENT_1 Receive input SENT_RX[1] MPC5744P Data Sheet, Rev. 0.3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 61 Electrical characteristics 3 Electrical characteristics 3.1 Introduction This section contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications for this device. This device is designed to operate at TBD (design target: 180 MHz or greater). The electrical specifications are preliminary and are from previous designs, design simulations, or initial evaluation. These specifications may not be fully tested or guaranteed at this early stage of the product life cycle. Finalized specifications will be published after complete characterization and device qualifications have been completed. The “Symbol” column of the electrical parameter and timings tables contains an additional column containing “SR”, “CC”, “P”, “C”, “T”, or “D”. • “SR” identifies system requirements—conditions that must be provided to ensure normal device operation. An example is the input voltage of a voltage regulator. • “CC” identifies controller characteristics—indicating the characteristics and timing of the signals that the chip provides. • “P”, “C”, “T”, or “D” apply only to controller characteristics—specifications that define normal device operation. They specify how each characteristic is guaranteed. — P: parameter is guaranteed by production testing of each individual device. — C: parameter is guaranteed by design characterization. Measurements are taken from a statistically relevant sample size across process variations. — T: parameter is guaranteed by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. All values are shown in the typical (“typ”) column are within this category. — D: parameters are derived mainly from simulations. NOTE The specification classifications in the “Symbol” column of the tables are preliminary and may change in future releases of this document. 3.2 Absolute maximum ratings Table 10. Absolute maximum ratings1 Symbol Parameter Conditions Min Max2 Unit VDD_HV_PMU SR 3.3 V voltage regulator supply voltage — –0.3 4.03, 4 V VDD_HV_IOx SR 3.3 V input/output supply voltage — –0.3 3.633, 4 V VSS_HV_IOx SR Input/output ground voltage — –0.1 0.1 V V VDD_HV_FLA SR 3.3 V flash supply voltage — –0.3 3.633, 4 VSS_HV_FLA SR Flash memory ground — –0.1 0.1 V VDD_HV_OSC SR 3.3 V crystal oscillator amplifier supply voltage — –0.3 4.03, 4 V MPC5744P Data Sheet, Rev. 0.3 62 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical characteristics Table 10. Absolute maximum ratings1 (continued) Conditions Min Max2 Unit 3.3 V crystal oscillator amplifier reference voltage — –0.1 0.1 V VDD_HV_ADRE0 SR VDD_HV_ADRE1 3.3 V / 5.0 V ADC_0 high reference voltage 3.3 V / 5.0 V ADC_1 high reference voltage — –0.3 6.0 V VSS_HV_ADRE0 SR VSS_HV_ADRE1 ADC_0 ground and low reference voltage ADC_1 ground and low reference voltage — –0.1 0.1 V Symbol VSS_HV_OSC Parameter SR 5 VDD_HV_ADV SR 3.3 V ADC supply voltage — –0.3 4.03, 4 V VSS_HV_ADV SR 3.3 V ADC supply ground — –0.1 0.1 V TVDD SR Supply ramp rate — 0.5 3.0 × 106 (3.0 V / s) V/µs VINA SR Voltage on analog pin with respect to ground (VSS_HV_IOx) — –0.3 6.0 V VIN SR Voltage on any digital pin with respect to ground (VSS_HV_IOx) –0.3 VDD_HV_IOx + 0.36 V IINJPAD SR Injected input current on any pin during overload condition — –10 10 mA IINJSUM SR Absolute sum of all injected input currents during overload condition — –50 50 mA TSTG SR Storage temperature — –55 165 °C Relative to VDD_HV_IOx NOTES: 1 Functional operating conditions are given in the DC electrical characteristics. Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the listed maxima may affect device reliability or cause permanent damage to the device. 2 Absolute maximum voltages are currently maximum burn-in voltages. Absolute maximum specifications for device stress have not yet been determined. 3 5.3 V for 10 hours cumulative over lifetime of device, 3.3 V +10% for time remaining. 4 Voltage overshoots during a high-to-low or low-to-high transition must not exceed 10 seconds per instance. 5 V DD_HV_ADRE0 and VDD_HV_ADRE1 cannot be operated at different voltages, and need to be supplied by the same voltage source. 6 Only when VDD_HV_IOx < 3.63 V. 3.3 Recommended operating conditions Table 11. Recommended operating conditions (VDD_HV_xx = 3.3 V) Symbol Parameter Conditions Min Max1 Unit VDD_HV_PMU SR 3.3 V voltage regulator supply voltage — 3.15 3.6 V VDD_HV_IOx SR 3.3 V input/output supply voltage — 3.15 3.6 V VSS_HV_IOx SR Input/output ground voltage — 0 0 V VDD_HV_FLA SR 3.3 V flash supply voltage — 3.15 3.6 V VSS_HV_FLA SR Flash memory ground — 0 0 V VDD_HV_OSC SR 3.3 V crystal oscillator amplifier supply voltage — 3.15 3.6 V VSS_HV_OSC SR 3.3 V crystal oscillator amplifier reference voltage — 0 0 V MPC5744P Data Sheet, Rev. 0.3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 63 Electrical characteristics Table 11. Recommended operating conditions (VDD_HV_xx = 3.3 V) (continued) Symbol Parameter Conditions VDD_HV_ADRE02 SR 3.3 V / 5.0 V ADC_0 high reference voltage VDD_HV_ADRE1 3.3 V / 5.0 V ADC_1 high reference voltage VDD_HV_ADV Min — Max1 Unit 3.0 to 5.5 V SR 3.3 V ADC supply voltage — 3.15 3.6 V SR ADC_0 ground and low reference voltage ADC_1 ground and low reference voltage — 0 0 V VSS_HV_ADV SR 3.3 V ADC supply ground — 0 0 V VDD_LV_COR SR Core supply, 1.25 V +/-5% — 1.19 1.32 V VDD_LV_CORx SR Internal supply voltage — — — V SR Internal reference voltage — 0 0 V VDD_LV_PLL SR Internal PLL supply voltage — 1.19 1.32 V VSS_LV_PLL3 SR Internal PLL reference voltage — 0 0 V VDD_LV_NEXUS SR Aurora LVDS supply voltage — 1.19 1.32 V VSS_LV_NEXUS SR Aurora LVDS supply ground — 0 0 V VDD_LV_LFAST SR LFAST supply voltage — 1.19 1.32 V VSS_LV_LFAST SR LFAST supply ground — 0 0 V VSS_HV_ADRE02 VSS_HV_ADRE1 3 VSS_LV_CORx TA SR Ambient temperature under bias fCPU ≤ TBD3 –40 TBD °C TJ SR Junction temperature under bias — –40 165 °C NOTES: 1 Full functionality cannot be guaranteed when voltage drops below 3.0 V. In particular, ADC electrical characteristics and I/Os DC electrical specification may not be guaranteed. 2 V DD_HV_ADRE0 and VDD_HV_ADRE1 cannot be operated at different voltages, and need to be supplied by the same voltage source. 3 Maximum frequency is TBD (design target: 180 MHz or greater). 3.4 Thermal characteristics Table 12. Thermal characteristics for 144 LQFP package1 Symbol RθJA CC RθJMA CC RθJB RθJC ΨJT CC CC CC C D D D D D Parameter Conditions Thermal resistance, junction-to-ambient natural Single layer board – 1s convection2 Four layer board – 2s2p Value Unit 42 °C/W 34 Thermal resistance, junction-to-ambient forced Single layer board – 1s convection at 200 ft/min Four layer board – 2s2p 28 Thermal resistance junction-to-board3 — 22 °C/W — 8 °C/W — 3 °C/W Thermal resistance junction-to-case Junction-to-package-top natural 4 convection5 34 °C/W NOTES: 1 Thermal characteristics are targets based on simulation that are subject to change per device characterization. 2 Junction-to-Ambient thermal resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board meets JEDEC specification for this package. MPC5744P Data Sheet, Rev. 0.3 64 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical characteristics 3 Junction-to-Board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification for the specified package. 4 Junction-to-Case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is used for the case temperature. Reported value includes the thermal resistance of the interface layer. 5 Thermal characterization parameter indicating the temperature difference between the package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT. Table 13. Thermal characteristics for 176 LQFP-EP package1 Symbol RθJA RθJMA RθJB RθJC ΨJT D D D D D Parameter Conditions Thermal resistance, junction-to-ambient natural Single layer board – 1s convection2 Four layer board – 2s2p Value Unit 43 24 Thermal resistance, junction-to-ambient forced Single layer board – 1s convection at 200 ft/min Four layer board – 2s2p 18 Thermal resistance junction-to-board3 34 °C/W — 12 °C/W top4 — 10 °C/W convection5 — 3 °C/W Thermal resistance junction-to-case Junction-to-package-top natural °C/W NOTES: 1 Thermal characteristics are targets based on simulation that are subject to change per device characterization. 2 Junction-to-Ambient thermal resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board meets JEDEC specification for this package. 3 Junction-to-Board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification for the specified package. 4 Junction-to-Case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is used for the case temperature. Reported value includes the thermal resistance of the interface layer. 5 Thermal characterization parameter indicating the temperature difference between the package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT. Table 14. Thermal characteristics for 257 MAPBGA package1 Symbol RθJA RθJMA D D Parameter Thermal resistance junction-to-ambient natural Single layer board – 1s convection2 Four layer board – 2s2p 46 °C/W 26 22 — 13 °C/W — 8 °C/W — 2 °C/W D Thermal resistance junction-to-board3 RθJC D Thermal resistance junction-to-case4 D Value Unit Thermal resistance, junction-to-ambient forced Single layer board – 1s convection at 200 ft/min Four layer board – 2s2p RθJB ΨJT Conditions Junction-to-package-top natural convection 5 37 °C/W NOTES: 1 Thermal characteristics are targets based on simulation that are subject to change per device characterization. 2 Junction-to-Ambient thermal resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board meets JEDEC specification for this package. 3 Junction-to-Board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification for the specified package. MPC5744P Data Sheet, Rev. 0.3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 65 Electrical characteristics 4 Junction-to-Case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is used for the case temperature. Reported value includes the thermal resistance of the interface layer. 5 Thermal characterization parameter indicating the temperature difference between the package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT. 3.4.1 General notes for specifications at maximum junction temperature An estimation of the chip junction temperature, TJ, can be obtained from Equation 1: TJ = TA + (RθJA × PD) Eqn. 1 where: TA = ambient temperature for the package (oC) RθJA = junction to ambient thermal resistance (oC/W) PD = power dissipation in the package (W) The junction to ambient thermal resistance is an industry standard value that provides a quick and easy estimation of thermal performance. Unfortunately, there are two values in common usage: the value determined on a single layer board and the value obtained on a board with two planes. For packages such as the PBGA, these values can be different by a factor of two. Which value is closer to the application depends on the power dissipated by other components on the board. The value obtained on a single layer board is appropriate for the tightly packed printed circuit board. The value obtained on the board with the internal planes is usually appropriate if the board has low power dissipation and the components are well separated. When a heat sink is used, the thermal resistance is expressed in Equation 2 as the sum of a junction to case thermal resistance and a case to ambient thermal resistance: RθJA = RθJC + RθCA Eqn. 2 where: RθJA = junction to ambient thermal resistance (°C/W) RθJC = junction to case thermal resistance (°C/W) RθCA = case to ambient thermal resistance (°C/W) RθJC is device related and cannot be influenced by the user. The user controls the thermal environment to change the case to ambient thermal resistance, RθCA. For instance, the user can change the size of the heat sink, the air flow around the device, the interface material, the mounting arrangement on printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. To determine the junction temperature of the device in the application when heat sinks are not used, the Thermal Characterization Parameter (ΨJT) can be used to determine the junction temperature with a measurement of the temperature at the top center of the package case using Equation 3: TJ = TT + (ΨJT × PD) Eqn. 3 where: MPC5744P Data Sheet, Rev. 0.3 66 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical characteristics TT ΨJT PD = thermocouple temperature on top of the package (°C) = thermal characterization parameter (°C/W) = power dissipation in the package (W) The thermal characterization parameter is measured per JESD51-2 specification using a 40 gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire extending from the junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire. 3.4.1.1 References Semiconductor Equipment and Materials International 3081 Zanker Road San Jose, CA 95134 USA (408) 943-6900 MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global Engineering Documents at 800-854-7179 or 303-397-7956. JEDEC specifications are available on the WEB at http://www.jedec.org. 1. C.E. Triplett and B. Joiner, “An Experimental Characterization of a 272 PBGA Within an Automotive Engine Controller Module,” Proceedings of SemiTherm, San Diego, 1998, pp. 47–54. 2. G. Kromann, S. Shidore, and S. Addison, “Thermal Modeling of a PBGA for Air-Cooled Applications,” Electronic Packaging and Production, pp. 53–58, March 1998. 3. B. Joiner and V. Adams, “Measurement and Simulation of Junction to Board Thermal Resistance and Its Application in Thermal Modeling,” Proceedings of SemiTherm, San Diego, 1999, pp. 212–220. 3.5 Electromagnetic Interference (EMI) characteristics The Electromagnetic Interference (EMI) target characteristics are shown in Table 16: • Device configuration, test conditions, and EM testing per standard IEC61967-2 • Supply voltage of 3.3 V DC • Ambient temperature of 25 °C The configuration information referenced in Table 16 is explained in Table 15. MPC5744P Data Sheet, Rev. 0.3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 67 Electrical characteristics Table 15. EMI configuration summary Configuration name Description Configuration A • • • • • High emission = all pads have max slew rate, LVDS pads running at 40 MHz Oscillator frequency = 40 MHz System bus frequency = 80 MHz No PLL frequency modulation IEC level I (≤ 36 dBμV) Configuration B • • • • • Reference emission = pads use min, mid and max slew rates, LVDS pads disabled Oscillator frequency = 40 MHz System bus frequency = 80 MHz 2% PLL frequency modulation IEC level K(≤ 30 dBμV) Table 16. EMI emission testing specifications Symbol VEME 3.6 Parameter CC Radiated emissions Conditions Min Typ Max Unit Configuration A; frequency range 150 kHz–50 MHz — 16 — dBμV Configuration A; frequency range 50–150 MHz — 16 — Configuration A; frequency range 150–500 MHz — 32 — Configuration A; frequency range 500–1000 MHz — 25 — Configuration B; frequency range 50–150 MHz — 15 — Configuration B; frequency range 50–150 MHz — 21 — Configuration B; frequency range 150–500 MHz — 30 — Configuration B; frequency range 500–1000 MHz — 24 — Electrostatic discharge (ESD) characteristics Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n + 1) supply pin). This test conforms to the AEC-Q100-002/-003/-011 standard. MPC5744P Data Sheet, Rev. 0.3 68 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical characteristics Table 17. ESD ratings1, 2 No. Symbol Parameter Conditions Class Max value3 Unit 1 VESD(HBM) SR Electrostatic discharge (Human Body Model) TA = 25 °C conforming to AEC-Q100-002 H1C 2000 V 2 VESD(MM) SR Electrostatic discharge (Machine Model) TA = 25 °C conforming to AEC-Q100-003 M2 200 V 3 VESD(CDM) SR Electrostatic discharge TA = 25 °C (Charged Device Model) conforming to AEC-Q100-011 C3A 500 V 750 (corners) NOTES: 1 All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. 2 A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification requirements. Complete DC parametric and functional testing shall be performed per applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification. 3 Data based on characterization results, not tested in production. 3.7 Voltage regulator electrical characteristics The voltage regulator is composed of the following blocks: • High power regulator (external NPN to support core current) • Low voltage detector (LVD_MAIN_1) for 3.3 V supply to IO (VDDIO) • Low voltage detector (LVD_MAIN_2) for 3.3 V supply (VDDREG) • Low voltage detector (LVD_MAIN_3) for 3.3 V flash supply (VDDFLASH) • Low voltage detector (LVD_MAIN_4) for 3.3 V ADC supply (VDDADC) • Low voltage detector (LVD_MAIN_5) for 3.3 V OSC supply (VDDOSC) • Low voltage detector (LVD_CORE) for 1.2 V digital core supply (HPVDD) • Low voltage detector (LVD_CORE_BK) for the self-test of LVD_CORE • High voltage detector (HVD_CORE) for 1.2 V digital core supply (HPVDD) • High voltage detector (HVD_CORE_BK) for the self-test of HVD_CORE. • Power on Reset (POR) The following bipolar transistors are supported: • BCP68 from ON Semiconductor • NJD2873 • NSS20501Uw3 MPC5744P Data Sheet, Rev. 0.3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 69 Electrical characteristics Table 18. Voltage regulator electrical specifications Symbol C Parameter Cld SR — External decoupling/ stability capacitor SR — Combined ESR of external capacitor Conditions Min Typ Max Unit Min, max values shall be granted with respect to tolerance, voltage, temperature, and aging variations. 10 — — 0.03 — 0.15 Ω Cld = 10 µF — — 2.5 ms µF tSU CC Lbw SR — Bonding inductance 13 nH Rbw SR — Bonding wire and pad resistance 0.5 Ω Rsd SR — Series resistance of on-chip power grid 0.1 Ω Csd SR — On-chip power grid to ground capacitance tbd nF Cpd SR — Parallel decoupling capacitor per pin, no more than 300 nF total Rsn SR — Snubber resistor for stability dep. on transistor tbd Ω Csn SR — Snubber capacitor for stability dep. on transistor tbd nF — SR — Power Supply Rejection (Cld=10uF) @DC no load @200 kHz no load @DC 400 mA @200 kHz 400 mA -23 -23 -23 -23 dB dB dB dB — SR — Load current transient Iload from 20% to 80% Cld = 10 µF 1.0 µs — CC D Supply ramp rate VDD12_CORE — 0.01 — 1 V/ms — CC D Supply Ramp Rate VDD33_REG — 25 — 1000 V/ms — CC T POR VDD12_CORE 0.98 1.02 1.08 V CC T POR VDD33_REG 2.4 2.59 2.76 V CC P LVD_CORE, LVD_CORE_BK calibrated (trimmed) 1.12 1.15 1.18 V CC P HVD_CORE, HVD_CORE_BK calibrated (trimmed) 1.32 1.36 1.40 V CC P LVD_REG calibrated (trimmed) 2.93 3.05 3.13 V CC P LVD_IO calibrated (trimmed) 2.93 3.05 3.13 V Start-up time after main supply stabilization 47 nF MPC5744P Data Sheet, Rev. 0.3 70 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical characteristics Table 18. Voltage regulator electrical specifications (continued) Symbol Tj C Parameter Conditions Min Typ Max Unit CC P LVD_FLS calibrated (trimmed) 2.93 3.05 3.13 V CC P LVD_ADC calibrated (trimmed) 2.93 3.05 3.13 V CC P LVD_OSC calibrated (trimmed) 2.93 3.05 3.13 V CC T Hysteresis LVD_CORE 20 mV CC T Hysteresis HVD_CORE 20 mV CC T Hysteresis LVD_xxx 20 mV CC T LVD/HVD trimming 5 mV CC T Junction Temperature 16 steps -40 — 165 °C VDD33_REG BCTRL Rsn Csn Cld 10u Cpd 47n Lbw Package Rbw Cpd 47n Rbw Cpd 47n Lbw Rbw Rsd Lbw Die Csd Rbw Lbw Cpd 47n Figure 19. Core supply decoupling and parasitics MPC5744P Data Sheet, Rev. 0.3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 71 Electrical characteristics 3.8 DC electrical characteristics The following tables provide DC characteristics for bidirectional pads: • Table 20 provides output driver characteristics FlexRay I/Os (SYM). • Table 21 provides output driver characteristics for LFAST I/Os. Table 20. FlexRay (SYM) configuration output buffer electrical characteristics1 Symbol C Value3 Conditions2 Parameter Unit Min Typ Max ROH_Y CC P PMOS output impedance SYM configuration Push Pull, IOH = 2 mA, VOH = VDD_HV_IOx - (0.28...0.52 V) 35 50 65 Ω ROL_Y CC P PMOS output impedance SYM configuration Push Pull, IOL = 2 mA, VOL = 0.28...0.52 V 35 50 65 Ω Fmax_Y CC T Output frequency SYM configuration CL= 20pF(3), VDD_HV_IOx = 3.3 V –5%, +10% — — 50 MHz Ttr_Y CC T Transition time output pin SYM configuration CL = 20 pF(3), VDD_HV_IOx = 3.3 V –5%, +10% 1 — 6 ns — 0 — 1 ns |Tskew_Y| CC T Difference between rise and fall time NOTES: 1 Please refer to FlexRay section for parameter dedicated to this interface. 2 V DD_HV_IOx = 3.3 V (–5%, +10%), TJ = –40 / 165 °C, unless otherwise specified 3 All values need to be confirmed during device validation. Table 21. LFAST output buffer electrical characteristics1 Symbol C Value3 Conditions2 Parameter Unit Min Typ Max |ΔVO_L| CC T Absolute value for differential output voltage swing (terminated) — 100 200 285 mV VICOM_L CC T Common mode voltage — 1.08 1.2 1.32 V — 0.2 — 1.5 ns Ttr_L CC T Transition time output pin LVDS configuration NOTES: 1 Please refer to LFAST section for parameter dedicated to this interface. 2 V DD_HV_IOx = 3.3 V (–5%, +10%), TJ = –40 / 165 °C, unless otherwise specified 3 All values need to be confirmed during device validation. NOTE Fast IOs must be specified only as fast (and not as high current). See Table 22. MPC5744P Data Sheet, Rev. 0.3 72 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical characteristics Table 22. DC Electrical Specifications Value Symbol C Parameter Conditions Unit Min Typ Max Vdd1 CC D LV (core) Supply Voltage — 1.18 — 1.32 V Vdde1 SR — I/O Supply Voltage — 3.15 — 3.6 V Vih CC D CMOS Input Buffer High Voltage (with hysteresis disabled) — Vdde + 0.3 V Vil CC D CMOS Input Buffer Low Voltage (with hysteresis disabled) — 0.40 * Vdde V CC D — 0.1 * Vdde — Pull_Ioh CC D Weak Pullup Current2 — 15 — 50 uA Pull_Iol CC D Weak Pulldown Current3 — 15 — 50 uA 2.5 uA Vhys CMOS Input Buffer Hysteresis 0.55 * Vdde Vss - 0.3 — — CC D Digital Pad Input Leakage Current (weak pull inactive) — Voh CC D Output High Voltage4 — 0.8 * Vdde — - V Vol Voltage5 — - — 0.2 * Vdde V Iinact_d CC D Output Low -2.5 — V Ioh_f CC D Full drive Ioh6 (ipp_sre[1:0] = 11) — 18 — 70 mA Iol_f CC D Full drive Iol6 (ipp_sre[1:0] = 11) — 21 — 120 mA Ioh_h Ioh6 — 9 — 35 mA — 10.5 — 60 mA Iol_h CC D Half drive 6 (ipp_sre[1:0] = 10) CC D Half drive Iol (ipp_sre[1:0] = 10) Note: 1. Max power supply ramp rate is 100 V / ms 2. Measured when pad = 0 V 3. Measured when pad = VDDE 4. Measured when pad is sourcing 2 mA. 5. Measured when pad is sinking 2 mA. 6. Ioh/Iol is derived from spice simulations. These values are NOT guaranteed by test. MPC5744P Data Sheet, Rev. 0.3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 73 Electrical characteristics 3.9 Supply current characteristics Current consumption data is given in Table 23. These specifications are design targets and are subject to change per device characterization. Table 23. Current consumption characteristics Symbol IDD_LV_TYP + IDD_LV_PLL2 IDD_LV_FULL + IDD_LV_PLL3 IDD_LV_BIST + IDD_LV_PLL IDD_LV_STOP IDD_LV_HALT C Conditions1 Parameter Min Typ Max Unit mA CC P Operating current 1.2 V supplies TJ = 150 °C VDD_LV_COR = 1.32 V — 400 mA TBD CC C 1.2 V supplies TJ = 165 °C VDD_LV_COR = 1.32 V — 480 mA — CC C Operating current 1.2 V supplies TJ = 150 °C VDD_LV_COR = 1.32 V — — 570 mA CC 1.2 V supplies TJ = 165 °C VDD_LV_COR = 1.32 V — — 660 mA CC T Operating current 1.2 V supplies during LBIST (full LBIST configuration) TA = 25 °C VDD_LV_COR = 1.32 V — — TBD CC T 1.2 V supplies TJ = 150 °C VDD_LV_COR = 1.32 V — — TBD CC T 1.2 V supplies TJ = 165 °C VDD_LV_COR = 1.32 V — — TBD CC T Operating current in VDD STOP mode TA = 25 °C VDD_LV_COR = 1.32 V — — TBD CC T TJ = 55 °C VDD_LV_COR = 1.32 V — — TBD CC P TJ = 150 °C VDD_LV_COR = 1.32 V — — TBD CC T TJ = 165 °C VDD_LV_COR = 1.32 V — — TBD CC T Operating current in VDD HALT mode TA = 25 °C VDD_LV_COR = 1.32 V — — TBD CC T TJ = 55 °C VDD_LV_COR = 1.32 V — — TBD CC P TJ = 150 °C VDD_LV_COR = 1.32 V — — TBD CC T TJ = 165 °C VDD_LV_COR = 1.32 V — — TBD mA mA mA mA MPC5744P Data Sheet, Rev. 0.3 74 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical characteristics Table 23. Current consumption characteristics (continued) Symbol IDD_HV_ADV4,5 IDD_HV_ADRE5 IDD_HV_OSC IDD_HV_FLASH Conditions1 Min Typ Max Unit CC T Operating current TJ = 150 °C 4 ADCs operating at 80 MHz VDD_HV_ADV = 3.6 V — — TBD mA CC T TJ = 165 °C 4 ADCs operating at 80 MHz VDD_HV_ADV = 3.6 V — — TBD CC T Operating current TJ = 150 °C ADC operating at 80 MHz VDD_HV_ADRE = 3.6 V — — TBD TJ = 150 °C TBD frequency6 ADC operating at 80 MHz VDD_HV_ADRE = 5.5 V — — TBD TJ = 165 °C ADC operating at 80 MHz VDD_HV_ADRE = 3.6 V — — TBD TJ = 165 °C TBD frequency6 ADC operating at 80 MHz VDD_HV_ADRE = 5.5 V — — TBD TJ = 150 °C 3.3 V supplies TBD frequency6 — — TBD TJ = 165 °C 3.3 V supplies TBD frequency6 — — TBD TJ = 150 °C 3.3 V supplies TBD frequency6 — — TBD TJ = 165 °C 3.3 V supplies TBD frequency6 — — TBD C Parameter CC T Operating current CC T Operating current mA μA mA NOTES: 1 The content of the Conditions column identifies the components that draw the specific current. 2 Enabled Modules in 'Typical mode': two FlexCANs, ADC0/1, CTU, FlexPWM, three eTimers, three DSPIs, SWG, DMA, STM, SWT, PIT (list subject to change). At maximum frequency. I/O supply current excluded. 3 Enabled Modules in 'Full mode': TBD. At maximum frequency. I/O supply current excluded. 4 Internal structures hold the input voltage less than VDD_HV_ADV + 1.0 V on all pads powered by VDDA supplies, if the maximum injection current specification is met (3 mA for all pins) and VDDA is within the operating voltage specifications. 5 This value is the total current for four ADCs. 6 Maximum frequency is TBD (design target: 180 MHz or greater). 3.10 Temperature Sensor The following table describes the temperature sensor electrical characteristics. MPC5744P Data Sheet, Rev. 0.3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 75 Electrical characteristics Table 24. Temperature sensor electrical characteristics Value Symbol 3.11 C Parameter Conditions Unit Min Typ Max — CC C Temperature monitoring range — -40 — 165 °C — CC C Sensitivity — — 5.18 — mV/°C — CC T Accuracy TJ = -40 to 165 °C TBD — TBD °C — CC C Operating Current TJ = -40 to 165 °C — — 600 μA Main oscillator electrical characteristics The device provides an oscillator/resonator driver. Figure 5 describes a simple model of the internal oscillator driver and provides an example of a connection for an oscillator or a resonator. EXTAL Crystal CL EXTAL RP XTAL CL DEVICE VDD I EXTAL Resonator R XTAL DEVICE XTAL DEVICE Figure 5. Crystal oscillator and resonator connection scheme NOTE XTAL/EXTAL must not be directly used to drive external circuits. MPC5744P Data Sheet, Rev. 0.3 76 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical characteristics MTRANS 1 0 VXTAL 1/fXOSCHS VXOSCHS 90% VXOSCHSOP 10% TXOSCHSSU valid internal clock Figure 6. Main oscillator electrical characteristics × Table 25. Main oscillator electrical characteristics Symbol C Value Conditions1 Parameter Typ Max 4.0 — 40.0 MHz TBD TBD TBD mA/V fXOSCHS SR — Oscillator frequency gmXOSCHS CC P Oscillator transconductance VDD_HV_OSC = 3.3 V –5%, +10% VXOSCHS CC D Oscillation amplitude fOSC = 4, 8, 10, 12, 16 MHz TBD fOSC = 40 MHz TBD VXOSCHSOP CC — Unit Min V D Oscillation operating point — TBD V CC D Oscillator consumption — TBD mA TXOSCHSSU CC T Oscillator start-up time TBD ms IXOSCHS fOSC = 4, 8, 10, 12 MHz2 fOSC = 16, 40 MHz 2 TBD VIH SR — Input high level CMOS Schmitt Trigger Oscillator bypass mode TBD V VIL SR — Input low level CMOS Schmitt Trigger Oscillator bypass mode TBD V NOTES: 1 V DD_HV_OSC = 3.3 V -5%,+±10%, TJ = –40 to +165 °C, unless otherwise specified. 2 The recommended configuration for maximizing the oscillator margin are: XOSC_MARGIN = 0 for 4 MHz quartz XOSC_MARGIN = 1 for 8/16/40 MHz quartz MPC5744P Data Sheet, Rev. 0.3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 77 Electrical characteristics 3.12 FMPLL electrical characteristics PLL0_PHI0 RCOSC PLL0 PLL0_PHI1 XOSC PLL1_PHI0 PLL1 Figure 7. PLL integration Table 26. PLL0 electrical characteristics Value Symbol Parameter Conditions1 Unit Min Typ Max fPLL0IN SR — PLL0 input clock2 — 14 — 44 MHz ΔPLL0IN SR — PLL0 input clock duty cycle2 — 40 — 60 % fPLL0VCO CC D PLL0 VCO frequency — 600 — 1250 MHz fPLL0PHI0 CC D PLL0 output clock PHI0 — 4.76 — 625 MHz fPLL0PHI1 CC D PLL0 output clock PHI1 — 20 — 156 MHz tPLL0LOCK CC P PLL0 lock time — — — 100 µs |ΔPLL0LTJ| CC T PLL0 long term jitter fPLL0IN = 8 MHz (reso- fPLL0PHI0 = 40 MHz, 1 µs — — 0.1 % nator), fPLL0PHI0 = 40 MHz, 13 µs — — TBD % PLL0 consumption FINE LOCK state — — 5 mA IPLL0 CC C NOTES: 1 V o DD_LV =1.25 V ± 5%, TJ = -40 / 165 C unless otherwise specified. 2 PLL0IN clock retrieved directly from either internal RCOSC or external XOSC clock. Input characteristics are granted when using internal RCOSC or external oscillator is used in functional mode. MPC5744P Data Sheet, Rev. 0.3 78 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical characteristics Table 27. FMPLL1 electrical characteristics Value Symbol C Parameter Conditions1 Unit Min Typ Max fPLL1IN SR — PLL1 input clock2 — 38 — 78 MHz ΔPLL1IN SR — PLL1 input clock duty cycle2 — 35 — 65 % fPLL1VCO CC D PLL1 VCO frequency — 600 — 1250 MHz fPLL1PHI0 CC D PLL1 output clock PHI0 — 4.76 — 625 MHz tPLL1LOCK CC P PLL1 lock time — — — 100 µs fPLL1MOD CC T PLL1 modulation frequency — — — 250 kHz |δPLL1MOD| CC T PLL1 modulation depth (when enabled) Center spread 0.25 — 2 % Down spread 0.5 — 4 % PLL1 consumption FINE LOCK state — — 6 mA IPLL1 CC C NOTES: 1 V o DD_LV =1.25 V ± 5%, TJ = -40 / 165 C unless otherwise specified. 2 PLL1IN clock retrieved directly from either internal PLL0 or external FXOSC clock. Input characteristics are granted when using internal PPL0 or external oscillator is used in functional mode. 3.13 Internal 16 MHz RC oscillator electrical characteristics Table 28. Internal RC Oscillator electrical specifications (VDD_HV_PMU = 3.15 V to 3.6 V, VSS = 0 V, VDD_LV = 1.18 V to 1.32 V, VSS = 0 V, TJ = –40 / 165 oC) Value Symbol C Parameter Conditions Unit Min Typ Max FTarget CC D IRC target frequency — — 16 — MHz FUntrimmed CC D IRC frequency (Untrimmed) — 9.6 — 24 MHz δFvar_noT CC P IRC frequency variation without temperature compensation1 TJ < 150 oC –8 — +8 % TJ < 165 oC –10 — +10 — — 5 µs Tstartup CC T Startup time without temperature compensation1 IVDD3 CC T Current consumption on 3.3V power supply After Tstartup — — 55 µA IVDD12 CC T Current consumption on 1.2V power supply After Tstartup — — 270 µA NOTES: 1 Pending silicon characterization MPC5744P Data Sheet, Rev. 0.3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 79 Electrical characteristics 3.14 ADC electrical characteristics The device provides a 12-bit Successive Approximation Register (SAR) Analog-to-Digital Converter. Offset Error OSE Gain Error GE 4095 4094 4093 4092 4091 4090 ( 2) 1 LSB ideal =(VrefH-VrefL)/ 4096 = 3.3V/ 4096 = 0.806 mV Total Unadjusted Error TUE = +/- 6 LSB = +/- 4.84mV code out 7 ( 1) 6 5 (5) 4 (4) 3 (3) 2 1 (1) Example of an actual transfer curve (2) The ideal transfer curve (3) Differential non-linearity error (DNL) (4) Integral non-linearity error (INL) (5) Center of a step of the actual transfer curve 1 LSB (ideal) 0 1 2 3 4 5 6 7 4089 4090 4091 4092 4093 4094 4095 Vin(A) (LSBideal) Offset Error OSE Figure 8. ADC characteristics and error definitions 3.14.1 Input Impedance and ADC Accuracy To preserve the accuracy of the A/D converter, it is necessary that analog input pins have low AC impedance. Placing a capacitor with good high frequency characteristics at the input pin of the device can be effective: the capacitor should be as large as possible, ideally infinite. This capacitor contributes to attenuating the noise present on the input pin; further, it sources charge during the sampling phase, when the analog signal source is a high-impedance source. A real filter can typically be obtained by using a series resistance with a capacitor on the input pin (simple RC filter). The RC filtering may be limited according to the value of source impedance of the transducer or circuit supplying the analog signal to be measured. The filter at the input pins must be designed taking into account the dynamic characteristics of the input signal (bandwidth) and the equivalent input impedance of the ADC itself. In fact a current sink contributor is represented by the charge sharing effects with the sampling capacitance: CS being substantially a switched capacitance, with a frequency equal to the conversion rate of the ADC, it can be seen as a resistive path to ground. For instance, assuming a conversion rate of 1 MHz, MPC5744P Data Sheet, Rev. 0.3 80 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical characteristics with CS equal to 3 pF, a resistance of 330 kΩ is obtained (REQ = 1 / (fC × CS), where fc represents the conversion rate at the considered channel). To minimize the error induced by the voltage partitioning between this resistance (sampled voltage on CS) and the sum of RS + RF + RL + RSW + RAD, the external circuit must be designed to respect the Equation 9: R S + R F + R L + R SW + R AD 1 V A • --------------------------------------------------------------------------- < --- LSB R EQ 2 Eqn. 9 Equation 9 generates a constraint for external network design, in particular on resistive path. Internal switch resistances (RSW and RAD) can be neglected with respect to external resistances. EXTERNAL CIRCUIT INTERNAL CIRCUIT SCHEME VDD_HV_IOx Source RS VA Filter RF Current Limiter RL CF CP1 Channel Selection Sampling RSW1 RAD CP2 CS RS Source Impedance RF Filter Resistance CF Filter Capacitance RL Current Limiter Resistance RSW1 Channel Selection Switch Impedance RAD Sampling Switch Impedance CP Pin Capacitance (two contributions, CP1 and CP2) CS Sampling Capacitance Figure 29. Input Equivalent Circuit A second aspect involving the capacitance network shall be considered. Assuming the three capacitances CF, CP1 and CP2 are initially charged at the source voltage VA (refer to the equivalent circuit reported in Figure 29): A charge sharing phenomenon is installed when the sampling phase is started (A/D switch close). MPC5744P Data Sheet, Rev. 0.3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 81 Electrical characteristics Voltage Transient on CS VCS VA VA2 ΔV < 0.5 LSB 1 2 τ1 < (RSW + RAD) CS << TS τ2 = RL (CS + CP1 + CP2) VA1 TS t Figure 30. Transient Behavior during Sampling Phase In particular two different transient periods can be distinguished: • A first and quick charge transfer from the internal capacitance CP1 and CP2 to the sampling capacitance CS occurs (CS is supposed initially completely discharged): considering a worst case (since the time constant in reality would be faster) in which CP2 is reported in parallel to CP1 (call CP = CP1 + CP2), the two capacitances CP and CS are in series, and the time constant is CP • CS τ 1 = ( R SW + R AD ) • --------------------CP + CS Eqn. 10 Equation 10 can again be simplified considering only CS as an additional worst condition. In reality, the transient is faster, but the A/D converter circuitry has been designed to be robust also in the very worst case: the sampling time TS is always much longer than the internal time constant: τ 1 < ( R SW + R AD ) • C S « T S Eqn. 11 The charge of CP1 and CP2 is redistributed also on CS, determining a new value of the voltage VA1 on the capacitance according to Equation 12: V A1 • ( C S + C P1 + C P2 ) = V A • ( C P1 + C P2 ) • Eqn. 12 A second charge transfer involves also CF (that is typically bigger than the on-chip capacitance) through the resistance RL: again considering the worst case in which CP2 and CS were in parallel to CP1 (since the time constant in reality would be faster), the time constant is: τ 2 < R L • ( C S + C P1 + C P2 ) Eqn. 13 MPC5744P Data Sheet, Rev. 0.3 82 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical characteristics In this case, the time constant depends on the external circuit: in particular imposing that the transient is completed well before the end of sampling time TS, a constraints on RL sizing is obtained: 10 • τ 2 = 10 • R L • ( C S + C P1 + C P2 ) < TS Eqn. 14 Of course, RL shall be sized also according to the current limitation constraints, in combination with RS (source impedance) and RF (filter resistance). Being CF definitively bigger than CP1, CP2 and CS, then the final voltage VA2 (at the end of the charge transfer transient) will be much higher than VA1. Equation 15 must be respected (charge balance assuming now CS already charged at VA1): VA2 • ( C S + C P1 + C P2 + C F ) = V A • C F + V A1 • ( C P1 + C P2 + C S ) Eqn. 15 The two transients above are not influenced by the voltage source that, due to the presence of the RFCF filter, is not able to provide the extra charge to compensate the voltage drop on CS with respect to the ideal source VA; the time constant RFCF of the filter is very high with respect to the sampling time (TS). The filter is typically designed to act as anti-aliasing. Analog Source Bandwidth (VA) Noise TC ≤ 2 RFCF (Conversion Rate vs. Filter Pole) fF = f0 (Anti-aliasing Filtering Condition) 2 f0 ≤ fC (Nyquist) f0 f Anti-Aliasing Filter (fF = RC Filter pole) fF f Sampled Signal Spectrum (fC = conversion Rate) f0 fC f Figure 31. Spectral representation of input signal Calling f0 the bandwidth of the source signal (and as a consequence the cut-off frequency of the anti-aliasing filter, fF), according to the Nyquist theorem the conversion rate fC must be at least 2f0; it means that the constant time of the filter is greater than or at least equal to twice the conversion period (TC). Again the conversion period TC is longer than the sampling time TS, which is just a portion of it, even when fixed channel continuous conversion mode is selected (fastest conversion rate at a specific channel): in conclusion it is evident that the time constant of the filter RFCF is definitively much higher than the sampling time TS, so the charge level on CS cannot be modified by the analog signal source during the time in which the sampling switch is closed. MPC5744P Data Sheet, Rev. 0.3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 83 Electrical characteristics The considerations above lead to impose new constraints on the external circuit, to reduce the accuracy error due to the voltage drop on CS; from the two charge balance equations above, it is simple to derive Equation 16 between the ideal and real sampled voltage on CS: Eqn. 16 VA C P1 + C P2 + C F ------------ = -------------------------------------------------------V A2 C P1 + C P2 + C F + C S From this formula, in the worst case (when VA is maximum, that is for instance 5 V), assuming to accept a maximum error of half a count, a constraint is evident on CF value: Eqn. 17 C F > 2048 • C S Table 32. ADC conversion characteristics Conditions1 Min SR — ADC Clock frequency (depends on ADC configuration) (The duty cycle depends on AD_CK2 frequency) — 20 — 80 MHz SR — Sampling frequency — — — 1.00 MHz Symbol fCK fs C Parameter Typ Max Unit tsample CC D Sample time3 80 MHz@200 Ohm source impedance 275 — — ns tconv CC D Conversion time4 80 MHz 650 — — ns CS5 CC D ADC input sampling capacitance — 3 5 pF pF — 5 CC D ADC input pin capacitance 1 - TBD not in ADC spec — — — 5(6) CP25 CC D ADC input pin capacitance 2 - TBD not in ADC spec — — — 0.8 pF RSW15 CC D Internal resistance of analog source - TBD not in ADC spec VREF range = 4.5 to 5.5 V — — 0.3 kΩ VREF range = 3.0 to 3.6 V — — 875 Ω CP1 CC RAD5 CC D Internal resistance of analog source - TBD not in ADC spec — — — 825 Ω INL CC D Integral non linearity — –2 — 2 LSB DNL CC D Differential non linearity7 — –1 — 1 LSB OFS CC T Offset error — –4 — 4 LSB GNE CC T Gain error — –4 — 4 LSB Input (single CC ADC CC channel) D Max leakage 150C — — 250 nA D Max positive/negative injection –3 — 3 mA MPC5744P Data Sheet, Rev. 0.3 84 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical characteristics Table 32. ADC conversion characteristics (continued) Symbol C Parameter Input (double CC ADC CC channel) D Max leakage D Max positive/negative injection Conditions1 Min 150C — — 300 nA |Vref_ad0 - Vref_ad1| < 150 mV –3.6 — 3.6 mA Typ Max Unit SNR CC T Signal-to-noise ratio VREF = 3.3 V, Fin < 125 kHz 67 — — dB SNR CC T Signal-to-noise ratio VREF = 5.0 V, Fin < 125 kHz 69 — — dB THD CC T Total harmonic distortion @ 125 kHz TBD — — dB SINAD CC T Signal-to-noise and distortion Fin < 125 kHz 65 — — dB ENOB CC T Effective number of bits Fin < 125 kHz 10.5 — — bits TUEIS1WINJ CC D Total unadjusted error for IS1WINJ Without current injection –6 — 6 LSB TUEIS1WWINJ CC D Total unadjusted error for IS1WWINJ Without current injection –6 — 6 LSB NOTES: 1 V DD_HV_IOx = 3.3 V -5%,+10%, TJ = –40 to +165 °C, unless otherwise specified, and analog input voltage from VAGND to VAREF. 2 AD_CK clock is always half of the ADC module input clock defined via the auxiliary clock divider for the ADC. 3 During the sample time the input capacitance C can be charged/discharged by the external source. The internal resistance S of the analog source must allow the capacitance to reach its final voltage level within tsample. After the end of the sample time tsample, changes of the analog input voltage have no effect on the conversion result. Values for the sample clock tsample depend on programming. 4 This parameter does not include the sample time t sample, but only the time for determining the digital result and the time to load the result register with the conversion result. 5 See Figure 29. 6 For the 144-pin package 7 No missing codes 3.15 Flash memory electrical characteristics Table 33. Flash memory program and erase specifications Symbol Characteristic Typ1,2 Initial Max 25C3 Initial Max All Temps4 Lifetime Max5 Unit tdwprogram Double Word (64 bits) Program Time6 25 100 — 500 μs tpprogram Page (256 bits) Program Time7 53 200 — 500 μs tqprogram Quad-Page (1024 bits) Program Time8 203 800 1,200 2,000 μs t16kpperase 16 KB Block Pre-program and Erase Time 225 1,000 1,500 5,000 ms t32kpperase 32 KB Block Pre-program and Erase Time 250 1,000 1,500 5,000 ms t64kpperase 64 KB Block Pre-program and Erase Time 325 1,000 1,500 5,000 ms t256kpperase 256 KB Block Pre-program and Erase Time 695 2,000 3,000 15,000 ms tfactory256kp 256 KB Block Factory pre-program and Erase Time 510 1,500 2,250 n/a ms perase MPC5744P Data Sheet, Rev. 0.3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 85 Electrical characteristics NOTES: 1 Typical program and erase times represent the median performance and assume nominal supply values and operation at 25C. These values are characterized, but not tested. 2 For memory sizes greater than 1MB, and for blocks with less than or equal to 100 program/erase cycles, the user can apply a 90% typical + 10% Init Max (25C or All Temps depending on temperature) for each unit (page or block) to calculate the total program or erase time. 3 Initial Max 25C program and erase times provide guidance for time-out limits used in the factory and apply for less than or equal to 100 program or erase cycles, 20C < Tj < 30C junction temperature, and nominal (+/- 2%) supply voltages. These values are verified at production test. 4 Initial Max All Temps program and erase times provide guidance for time-out limits used in the factory and apply for less than or equal to 100 program or erase cycles, -40C < Tj < 150C junction temperature, and nominal (+/- 2%) supply voltages. These values are verified at production test. 5 Lifetime Max program and erase times apply across the voltage, temperature and cycling range of product life. This maximum value is characterized but not tested. 6 Program times are actual hardware programming times and do not include software overhead. 7 Program times are actual hardware programming times and do not include software overhead. 8 Program times are actual hardware programming times and do not include software overhead. Table 34. Flash memory environmental ratings Symbol TA TJ TS TMAX TUV Characteristic Operating Ambient Temperature: - Automotive - Automotive with reduced functionality (slower read performance (15% slower), higher currents, slower erase when done at spec value (2x), and no program, erase or margin reads allowed at greater than 150C). - Consumer Operating Junction Temperature: - Automotive - Automotive with reduced functionality (slower read performance (15% slower), higher currents, slower erase when done at spec value (2x), and no program, erase or margin reads allowed at greater than 150C). - Consumer Storage Ambient Temperature - Automotive - Automotive with reduced functionality Min Typical Max — C -40 -40 +125 +140 -20 +70 — C -40 -40 +150 +165 -20 +95 — -40 -40 Units C +150 +165 Absolute maximum ambient temperature exposure, 30 seconds or less. — — +250 C Allowed time of exposure to UV light — — 0 μs MPC5744P Data Sheet, Rev. 0.3 86 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical characteristics Table 35. Flash memory module life general use specifications Symbol Characteristic Conditions Min Typical Units Array P/E Cycles Number of program/erase cycles per block for 16KB, 32KB and 64KB blocks.1 - 100,000 — P/E Cycles Number of program/erase cycles per block for 256KB blocks.2 - 1,000 100,000 P/E Cycles — Years Data Retention Minimum data retention. Blocks with 0-1,000 P/E cycles. 20 Blocks with 1,001 to 10,000 P/E cycles. 10 — Years Blocks with 10,001 to 100,000 P/E cycles. 5 — Years NOTES: 1 Program and Erase supported across standard temperature specs. See table Table 34. 2 Program and Erase supported across standard temperature specs. See table Table 34. 3.16 SWG electrical characteristics Table 36. SWG electrical characteristics Symbol 3.17 C Parameter Min Max Unit SINAD CC C Signal-to-noise ratio plus distortion 50 — dB FREQ CC T Frequency Range of the sine wave 1 50 kHz FRP CC T Frequency precision of the sine wave -5 5 % APP CC T Sine wave amplitude (peak to peak) 0.426 2.063 V Load CC D Load capacitance 25 100 pF Current CC D Output current - 100 µA TJ CC D Junction Temperature -40 165 °C AC specifications AC Parameters are specified over the full operating junction temperature range of -40°C to +165°C and for the full operating range of the VDD_IO supply defined in Section 3.8, “DC electrical characteristics.” MPC5744P Data Sheet, Rev. 0.3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 87 Electrical characteristics Table 37. Functional Pad AC Specifications Prop. Delay (ns)1 Symbol C Rise/Fall Edge (ns) L>H/H>L Drive Load ipp_sre[1:0] (pF) Min Max Min Max 2.5/2.5 7.5/7.5 0.9.0.9 3/3 50 12/12 200 8/8 3.5/3.5 25 11.5/11.5 6.5/6.5 50 30/30 200 45/45 25/25 50 65/65 30/30 200 75/75 40/40 50 110/110 50/50 200 1.5/1.5 0.5/0.5 0.5 MSB,LSB 11 I/O (output) CC I/O (input) SR T — 10 012 002 NA 1.As measured from 50% of core side input to Voh/Vol of the output 2. Slew rate control modes. Note: Data based on characterization results, not tested in production. 3.17.1 Reset pad (EXT_POR, RESET) electrical characteristics The device implements a dedicated bidirectional RESET pin. VDD_HV_IOx VDDMIN EXT_POR VIH VIL device reset forced by EXT_POR device start-up phase Figure 18. Start-up reset requirements MPC5744P Data Sheet, Rev. 0.3 88 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical characteristics VEXT_POR hw_rst VDD_HV_IO ‘1’ VIH VIL ‘0’ filtered by hysteresis filtered by lowpass filter filtered by lowpass filter unknown reset state device under hardware reset WFRST WFRST WNFRST Figure 19. Noise filtering on reset signal Table 38. Reset (EXT_POR, RESET) electrical characteristics Symbol C Value2 Conditions1 Parameter Unit Min Typ Max 2.0 — VDD_HV_IOx + 0.4 V VIH SR — Input high level TTL (Schmitt Trigger) VIL SR — Input low level TTL (Schmitt Trigger) — –0.4 — 0.8 V CC C Input hysteresis TTL (Schmitt Trigger) — 300 — — mV Device under power-on reset VDD_HV_IO = 1.0 V, VOL = 0.35*VDD_HV_IO 0.2 — — mA Device under power-on reset VDD_HV_IO = 3.0 V, VOL = 0.35*VDD_HV_IO 15 — — mA — — — 10 ns — 100 — — ns VHYS3 IOL_R WFRST — CC P Strong pull-down current SR P (EXT_POR, RESET)-input filtered pulse WNFRST SR P (EXT_POR, RESET)-input not filtered pulse |IWPU| CC P Weak pull-up current absolute value RESET_B pin VIN = 0 V 30 — 80 µA |IWPD| CC P Weak pull-down current absolute value 30 — 80 µA EXT_POR pin VIN = VDD_HV_IOx MPC5744P Data Sheet, Rev. 0.3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 89 Electrical characteristics NOTES: 1 VDD_HV_IOx = 3.3 V -5%,+10%, TJ = –40 / 165 °C, unless otherwise specified 2 All values need to be confirmed during device validation. 3 Data based on characterization results, not tested in production 3.17.2 WKUP/NMI timing Table 39. WKUP/NMI glitch filter No. 3.17.3 Symbol Parameter Min Typ Max Unit — — 20 ns 400 — — ns D NMI pulse width that is rejected 1 WFNMI 2 WNFNMI D NMI pulse width that is passed Debug/JTAG/Nexus/Aurora timing 3.17.3.1 JTAG interface timing Table 40. JTAG pin AC electrical characteristics1 # Symbol C Characteristic Min Max Unit 1 tJCYC CC D TCK Cycle Time2 36 — ns 2 tJDC CC T TCK Clock Pulse Width 40 60 % 3 tTCKRISE CC D TCK Rise and Fall Times (40% - 70%) — 3 ns 4 tTMSS, tTDIS CC D TMS, TDI Data Setup Time 5 — ns 5 tTMSH, tTDIH CC D TMS, TDI Data Hold Time 5 — ns 6 tTDOV CC D TCK Low to TDO Data Valid — 153 ns 7 tTDOI CC C TCK Low to TDO Data Invalid 0 — ns 8 tTDOHZ CC D TCK Low to TDO High Impedance — 15 ns 9 tJCMPPW CC D JCOMP Assertion Time 100 — ns 10 tJCMPS CC D JCOMP Setup Time to TCK Low 40 — ns 11 tBSDV CC D TCK Falling Edge to Output Valid — 6004 ns 12 tBSDVZ CC D TCK Falling Edge to Output Valid out of High Impedance — 600 ns 13 tBSDHZ CC D TCK Falling Edge to Output High Impedance — 600 ns 14 tBSDST CC D Boundary Scan Input Valid to TCK Rising Edge 15 — ns 15 tBSDHT CC D TCK Rising Edge to Boundary Scan Input Invalid 15 — ns NOTES: 1 These specifications apply to JTAG boundary scan only. MPC5744P Data Sheet, Rev. 0.3 90 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical characteristics 2 This timing applies to TDI, TDO, TMS pins, however, actual frequency is limited by pad type for EXTEST instructions. Refer to pad specification for allowed transition frequency 3 Timing includes TCK pad delay, clock tree delay, logic delay and TDO output pad delay. 4 Applies to all pins, limited by pad slew rate. Refer to IO delay and transition specification and add 20 ns for JTAG delay. TCK 2 3 2 1 3 Figure 20. JTAG test clock input timing TCK 4 5 TMS, TDI 6 8 7 TDO Figure 21. JTAG test access port timing MPC5744P Data Sheet, Rev. 0.3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 91 Electrical characteristics TCK 10 JCOMP 9 Figure 22. JTAG JCOMP timing MPC5744P Data Sheet, Rev. 0.3 92 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical characteristics TCK 11 13 Output Signals 12 Output Signals 14 15 Input Signals Figure 23. JTAG boundary scan timing 3.17.3.2 Nexus timing Table 41. Nexus debug port timing1 No. Symbol C Parameter 1 tMCYC CC D MCKO Cycle Time 2 tMDC CC D MCKO Duty Cycle Conditions Min Valid2 Max Unit — 15.6 — ns — 40 60 % — –0.1 3 tMDOV CC D MCKO Low to MDO, MSEO, EVTO Data 4 tEVTIPW CC D EVTI Pulse Width — 4.0 5 tEVTOPW CC D EVTO Pulse Width — 1 — 62.5 — ns Time3 0.25 tMCYC — tTCYC tMCYC 6 tTCYC CC D TCK Cycle 7 tTDC CC D TCK Duty Cycle — 40 60 % tNTDIS, tNTMSS CC D TDI, TMS Data Setup Time — 8 — ns 8 MPC5744P Data Sheet, Rev. 0.3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 93 Electrical characteristics Table 41. Nexus debug port timing1 (continued) No. Symbol C 9 tNTDIH, tNTMSH CC D TDI, TMS Data Hold Time D TCK Low to TDO/RDY Data Valid 10 tJOV CC Parameter Conditions Min Max Unit 5 — ns 0 25 ns NOTES: 1 JTAG specifications in this table apply when used for debug functionality. All Nexus timing relative to MCKO is measured from 50% of MCKO and 50% of the respective signal. 2 For all Nexus modes except DDR mode, MDO, MSEO, and EVTO data is held valid until next MCKO low cycle. 3 The system clock frequency needs to be four times faster than the TCK frequency. 1 2 MCKO 3 MDO MSEO EVTO Output Data Valid 5 Figure 24. Nexus output timing EVTI 4 Figure 25. Nexus EVTI Input Pulse Width MPC5744P Data Sheet, Rev. 0.3 94 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical characteristics 6 7 TCK 8 9 TMS, TDI 10 TDO/RDY Figure 26. Nexus TDI, TMS, TDO timing 3.17.3.3 Aurora LVDS driver electrical characteristics Table 42. Aurora LVDS driver specifications Symbol Value2 Parameter1 C Unit Min Typ Max — 1250 Typ+0.1% Mbps — — 5 µs — — 5 µs Data Rate DATARATE SR — Data rate CC T STARTUP TSTRT_BIAS TSTRT_TX CC T Bias startup time3 4 Transmitter startup time MPC5744P Data Sheet, Rev. 0.3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 95 Electrical characteristics Table 42. Aurora LVDS driver specifications (continued) Symbol TSTRT_RX C CC T Parameter Value2 1 Receiver startup time5 Unit Min Typ Max — — 4 µs NOTES: 1 Conditions for these values are VDD_HV_IOx = 3.3 V (–5%, +10%), TJ = –40 / 150 °C 2 All values need to be confirmed during device characterization. 3 Startup time is defined as the time taken by LVDS current reference block for settling bias current after its pwr_down (power down) has been deasserted. LVDS functionality is guaranteed only after the startup time. 4 Startup time is defined as the time taken by LVDS transmitter for settling after its pwr_down (power down) has been deasserted. Here it is assumed that current reference is already stable (see Bias start-up time). LVDS functionality is guaranteed only after the startup time. 5 Startup time is defined as the time taken by LVDS receiver for settling after its pwr_down (power down) has been deasserted. Here it is assumed that current reference is already stable (see Bias start-up time). LVDS functionality is guaranteed only after the startup time. 3.17.3.4 Nexus Aurora debug port timing Table 43. Nexus Aurora debug port timing # Symbol C Characteristic Min Max Unit 625 1250 MHz — 400 ps 1 tREFCLK CC T Reference clock frequency 1a tMCYC CC T Reference Clock rise/fall time 2 tRCDC CC D Reference Clock Duty Cycle 45 55 % 3 JRC CC D Reference Clock jitter — 40 ps 4 tSTABILITY CC D Reference Clock Stability 50 — PPM -12 — 5 BER CC D Bit Error Rate — 10 6 JD CC D Transmit lane Deterministic Jitter — 0.17 OUI 7 JT CC D Transmit lane Total Jitter — 0.35 OUI 8 SO CC T Differential output skew — 20 ps 9 SMO CC T Lane to lane output skew — 1000 ps 400 400 ps 10 OUI CC D Aurora lane Unit Interval1 NOTES: 1 ± 100 PPM MPC5744P Data Sheet, Rev. 0.3 96 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical characteristics 1 2 2 CLOCKREF Zero Crossover CLOCKREF + 1a 1a 1a 8 1a 8 8 Tx Data Ideal Zero Crossover Tx Data + Tx Data [n] Zero Crossover Tx Data [n+1] Zero Crossover Tx Data [m] Zero Crossover 9 9 Figure 27. Nexus Aurora timings 3.17.4 External interrupt timing (IRQ pin) Table 44. External interrupt timing No. Symbol C Parameter Conditions Min Max Unit 1 tIPWL CC D IRQ pulse width low — 3 — tCYC 2 tIPWH CC D IRQ pulse width high — 3 — tCYC — 6 — tCYC 3 tICYC CC D IRQ edge to edge time1 NOTES: 1 Applies when IRQ pins are configured for rising edge or falling edge events, but not both. MPC5744P Data Sheet, Rev. 0.3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 97 Electrical characteristics IRQ 1 2 3 Figure 28. External interrupt timing 3.17.5 DSPI timing Table 45. DSPI timing No. 1 Symbol tSCK C CC D CC D CC D Parameter Conditions DSPI cycle time Master (MTFE = 0) Slave (MTFE = 0) Slave Receive Only Mode1 Min Max Unit 62 — ns 62 — 16 — 2 tCSC CC D PCS to SCK delay — 16 — ns 3 tASC CC D After SCK delay — 16 — ns 4 tSDC CC D SCK duty cycle — 5 tA CC D Slave access time SS active to SOUT valid — 40 ns 6 tDIS CC D Slave SOUT disable time SS inactive to SOUT High-Z or invalid — 10 ns 7 tPCSC CC D PCSx to PCSS time — 13 — ns 8 tPASC CC D PCSS to PCSx time — 13 — ns D Data setup time for inputs Master (MTFE = 0) 20 — ns Slave 2 — Master (MTFE = 1, CPHA = 0) 5 — Master (MTFE = 1, CPHA = 1) 20 — Master (MTFE = 0) –5 — Slave 4 — Master (MTFE = 1, CPHA = 0) 11 — Master (MTFE = 1, CPHA = 1) –5 — Master (MTFE = 0) — 4 Slave — 23 Master (MTFE = 1, CPHA = 0) — 12 Master (MTFE = 1, CPHA = 1) — 4 9 10 11 tSUI tHI tSUO CC CC CC D D Data hold time for inputs Data valid (after SCK edge) tSCK/2 - 10 tSCK/2 + 10 ns ns ns MPC5744P Data Sheet, Rev. 0.3 98 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical characteristics Table 45. DSPI timing (continued) No. Symbol C 12 tHO D CC Parameter Conditions Data hold time for outputs Min Max Unit Master (MTFE = 0) –2 — ns Slave 6 — Master (MTFE = 1, CPHA = 0) 6 — Master (MTFE = 1, CPHA = 1) –2 — NOTES: 1 Slave Receive Only Mode can operate at a maximum frequency of 60 MHz. In this mode, the DSPI can receive data on SIN, but no valid data is transmitted on SOUT. 2 3 PCSx 1 4 SCK Output (CPOL=0) 4 SCK Output (CPOL=1) 10 9 SIN First Data Data 12 SOUT First Data Last Data 11 Data Last Data Note: The numbers shown are referenced in Table 45. Figure 29. DSPI classic SPI timing — master, CPHA = 0 MPC5744P Data Sheet, Rev. 0.3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 99 Electrical characteristics PCSx SCK Output (CPOL=0) 10 SCK Output (CPOL=1) 9 Data First Data SIN Last Data 12 SOUT First Data 11 Data Last Data Note: The numbers shown are referenced in Table 45. Figure 30. DSPI classic SPI timing — master, CPHA = 1 3 2 SS 1 4 SCK Input (CPOL=0) 4 SCK Input (CPOL=1) 5 SOUT First Data 9 SIN 12 11 Data Last Data Data Last Data 6 10 First Data Note: The numbers shown are referenced in Table 45. Figure 31. DSPI classic SPI timing — slave, CPHA = 0 MPC5744P Data Sheet, Rev. 0.3 100 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical characteristics SS SCK Input (CPOL=0) SCK Input (CPOL=1) 11 5 6 12 SOUT First Data 9 SIN Data Last Data Data Last Data 10 First Data Note: The numbers shown are referenced in Table 45. Figure 32. DSPI classic SPI timing — slave, CPHA = 1 3 PCSx 4 1 2 SCK Output (CPOL=0) 4 SCK Output (CPOL=1) 9 SIN First Data 10 12 SOUT First Data Last Data Data 11 Data Last Data Note: The numbers shown are referenced in Table 45. Figure 33. DSPI modified transfer format timing — master, CPHA = 0 MPC5744P Data Sheet, Rev. 0.3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 101 Electrical characteristics PCSx SCK Output (CPOL=0) SCK Output (CPOL=1) 10 9 SIN First Data Last Data Data 12 First Data SOUT 11 Last Data Data Note: The numbers shown are referenced in Table 45. Figure 34. DSPI modified transfer format timing — master, CPHA = 1 3 2 SS 1 SCK Input (CPOL=0) 4 4 SCK Input (CPOL=1) SOUT First Data Data First Data 6 Last Data 10 9 SIN 12 11 5 Data Last Data Note: The numbers shown are referenced in Table 45. Figure 35. DSPI modified transfer format timing – slave, CPHA = 0 MPC5744P Data Sheet, Rev. 0.3 102 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical characteristics SS SCK Input (CPOL=0) SCK Input (CPOL=1) 11 5 6 12 First Data SOUT 9 Last Data Data Last Data 10 First Data SIN Data Note: The numbers shown are referenced in Table 45. Figure 36. DSPI modified transfer format timing — slave, CPHA = 1 8 7 PCSS PCSx Note: The numbers shown are referenced in Table 45. Figure 37. DSPI PCS strobe (PCSS) timing MPC5744P Data Sheet, Rev. 0.3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 103 Electrical characteristics 3.17.6 3.17.6.1 LVDS Fast Asynchronous Transmission (LFAST) electrical characteristics LFAST interface timing diagrams Figure 38. LFAST timing definition MPC5744P Data Sheet, Rev. 0.3 104 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical characteristics H lfast_pwr_down L Tsu Differential TX Data Lines pad_p/pad_n Data Valid Figure 39. Power-down exit time VIH Differential TX Data Lines 90% 10% pad_p/pad_n VIL Tfall Trise Figure 40. Rise/fall time 3.17.6.2 LFAST Interface electrical characteristics ] Table 46. LFAST electrical characteristics Symbol VDD_HV_IJ C Parameter Value2 Conditions1 SR — Operating supply conditions Unit Min Typ Max 3.15 — 3.6 V Data Rate DATARATE SR — Data rate — — 312/320 Typ+0.1% Mbps TSTRT_BIAS CC T Bias startup time3 — — 0.5 3 µs TPD2NM_TX CC T Transmitter startup time (power down to normal mode)4 — — 0.2 2 µs STARTUP MPC5744P Data Sheet, Rev. 0.3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 105 Electrical characteristics Table 46. LFAST electrical characteristics (continued) Symbol C Parameter Conditions Value2 1 Unit Min Typ Max TSM2NM_TX CC T Transmitter startup time (sleep mode to normal mode)5 — — 0.2 0.5 µs TPD2NM_RX CC T Receiver startup time6 (Power down to Normal mode) — — 20 40 ns TPD2SM_RX CC T Receiver startup time6 (Power down to Sleep mode) — — 20 50 ns TRANSMITTER VOS_DRF CC T Common mode voltage — 1.08 — 1.32 V |ΔVOD_DRF| CC D Differential output voltage swing (terminated) — ±100 ±200 ± 285 mV CC T Rise/Fall time (10% - 90% of swing) — 0.26 — 1.5 ns SR — Terminating resistance VDD_HV_IJ = 5 V±10% 65 — 171 Ω SR — VDD_HV_IJ = 3 V±10% 67 — 198 Ω SR — Capacitance7 — — — 5 pF VICOM_DRF SR — Common mode voltage — 0.158 — 1.69 V |ΔVI_DRF| SR — Differential input voltage — 100 — — mV VHYS_DRF CC C Input hysteresis — 25 — — mV CC D Terminating resistance VDD_HV_IJ = 5V±10% 80 100 120 Ω D Terminating resistance VDD_HV_IJ = 3 V±10% 80 115 150 Ω TTR_DRF ROUT_DRF COUT_DRF RECEIVER RIN_DRF CIN_DRF CC D Capacitance10 — — 3.5 6 pF LIN_DRF CC D Parasitic Inductance11 — — 5 10 nH NOTES: 1 V DD_HV_IOx = 3.3 V -5%,+10%, TJ = –40 / 165 °C, unless otherwise specified 2 All values need to be confirmed during device characterization. 3 Startup time is defined as the time taken by LFAST current reference block for settling bias current after its pwr_down (power down) has been deasserted. LFAST functionality is guaranteed only after the startup time. 4 Startup time is defined as the time taken by LFAST transmitter for settling after its pwr_down (power down) has been deasserted. Here it is assumed that current reference is already stable. LFAST functionality is guaranteed only after the startup time. 5 Startup time is defined as the time taken by LFAST transmitter for settling after its pwr_down (power down) has been deasserted. Here it is assumed that current reference is already stable. LFAST functionality is guaranteed only after the startup time. 6 Startup time is defined as the time taken by LFAST receiver for settling after its pwr_down (power down) has been deasserted. Here it is assumed that current reference is already stable. LFAST functionality is guaranteed only after the startup time. MPC5744P Data Sheet, Rev. 0.3 106 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical characteristics 7 Total lumped capacitance including silicon, package pin and bond wire. Application board simulation needed to verify LFAST template compliancy. 8 Absolute min = 0.15 V – (285 mV / 2) = 0 V 9 Absolute max = 1.6 V + (285 mV / 2) = 1.743 V 10 Total capacitance including silicon, package pin and bond wire 11 Total inductance including silicon, package pin and bond wire Table 47. LFAST electrical characteristics1 Value Symbol C Parameter Condition Unit Min Nominal Max FRF_REF SR D SysClk Frequency — 10 — 262 MHz ERRREF CC D SysClk Frequency Error — –1 — 1 % DCREF CC D SysClk Duty Cycle — 45 — 55 % CLOAD CC D Output Buffer Load Capacitance — — — 10 pF RLOAD CC D Output Buffer Load Resistance — 10 — — kΩ PN CC D 20 MHz — — –58 dBc CC D Integrated Phase Noise (single side band) 10 MHz — — –64 dBc FVCO CC D PLL VCO Frequency — — 320 — MHz TLOCK CC D PLL Phase Lock — — — 40 µs ΔPER CC T PLL Long Term Jitter (peak to peak) — — — 600 ps NOTES: 1 The specifications in this table apply to both the interprocessor bus and debug LFAST interfaces. 2 Guarantee of the 26 MHz SysClk frequency specification is pending device characterization. 3.17.7 3.17.7.1 FlexRay FlexRay timing parameters This section provides the FlexRay interface timing characteristics for the input and output signals. These numbers are recommended per the FlexRay Electrical Physical Layer Specification, Version 3.0.1, and subject to change per the final timing analysis of the device. MPC5744P Data Sheet, Rev. 0.3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 107 Electrical characteristics 3.17.7.2 TxEN TxEN 80 % 20 % dCCTxENFALL dCCTxENRISE Figure 41. FlexRay TxEN signal Table 48. TxEN output characteristics1 Name Description Min Max Unit dCCTxENRISE25 Rise time of TxEN signal at CC — 9 ns dCCTxENFALL25 Fall time of TxEN signal at CC — 9 ns dCCTxEN01 Sum of delay between Clk to Q of the last FF and the final output buffer, rising edge — 25 ns dCCTxEN10 Sum of delay between Clk to Q of the last FF and the final output buffer, falling edge — 25 ns NOTES: 1All parameters specified for V o o DD_HV_IOx = 3.3 V -5%, +10%, TJ = –40 C / 165 C, TxEN pin load maximum 25 pF. PE_Clk TxEN dCCTxEN10 dCCTxEN01 Figure 42. FlexRay TxEN signal propagation delays MPC5744P Data Sheet, Rev. 0.3 108 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical characteristics 3.17.7.3 TxD TxD dCCTxD50% 80 % 50 % 20 % dCCTxDRISE dCCTxDFALL Figure 43. FlexRay TxD signal Table 49. TxD output characteristics Name Description1 Min Max Unit dCCTxAsym Asymmetry of sending CC @ 25 pF load (=dCCTxD50% - 100 ns) –2.45 2.45 ns dCCTxDRISE25+dCCTxDFALL25 Sum of Rise and Fall time of TxD signal at the output — 9 ns dCCTxD01 Sum of delay between Clk to Q of the last FF and the final output buffer, rising edge — 25 ns dCCTxD10 Sum of delay between Clk to Q of the last FF and the final output buffer, falling edge — 25 ns NOTES: 1All parameters specified for V o o DD_HV_IOx = 3.3 V -5%, +10%, TJ = –40 C / 165 C, TxD pin load maximum 25 pF. MPC5744P Data Sheet, Rev. 0.3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 109 Electrical characteristics PE_Clk* TxD dCCTxD10 dCCTxD01 *FlexRay Protocol Engine Clock Figure 44. FlexRay TxD signal propagation delays 3.17.7.4 RxD Table 50. RxD input characteristics Name Description1 Min Max Unit C_CCRxD Input capacitance on RxD pin — 7 pF uCCLogic_1 Threshold for detecting logic high 35 70 % uCCLogic_0 Threshold for detecting logic low 30 65 % dCCRxD01 Sum of delay from actual input to the D input of the first FF, rising edge — 10 ns dCCRxD10 Sum of delay from actual input to the D input of the first FF, falling edge — 10 ns NOTES: 1All parameters specified for V o o DD_HV_IOx = 3.3 V -5%, +10%, TJ = –40 C / 165 C. 3.17.7.5 Receiver asymmetry Table 51. Receiver asymmetry Min Max Unit dCCRxAsymAccept15 Acceptance of asymmetry at receiving CC with 15 pF load (*) Name Description -31.5 +44.0 ns dCCRxAsymAccept25 Acceptance of asymmetry at receiving CC with 25 pF load (*) -30.5 +43.0 ns MPC5744P Data Sheet, Rev. 0.3 110 Preliminary—Subject to Change Without Notice Freescale Semiconductor Obtaining package dimensions 4 Obtaining package dimensions Package dimensions are provided in package drawings. To find a package drawing, go to http://www.freescale.com and perform a keyword search for the drawing’s document number: If you want the drawing for this package Then use this document number 144-pin LQFP 98ASS23177W 176-pin LQFP 98ASA00300D 257-ball MAPBGA 98ASA00081D MPC5744P Data Sheet, Rev. 0.3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 111 Ordering information 5 Ordering information M PC 5744P F K0 M LQ 8 R Qualification status Core code (Power Architecture) Device number F = FlexRay (blank) = No FlexRay Fab and mask identifier Temperature range Package identifier Operating frequency Tape and reel status Temperature range Package identifier Operating frequency Qualification status 8 = 180 MHz M = –40°C to +125°C LQ = 144 LQFP K = –40°C to +TBD°C MM = 257 MAPBGA 5 = 150 MHz for extended temp KU = 176 LQFP (+165°C TJ) Tape and reel status R = Tape and reel P = Pre-qualification M = Fully spec. qualified, general market flow (blank) = Trays S = Fully spec. qualified, automotive flow Note: Not all options are available on all devices. See Table 1. Table 1. Orderable part number summary Part number1 Flash/SRAM Package PPC5744PFK0MLQ8 2.5 MB/384 KB 144 LQFP (Pb free) Other features2 –40 to +125 °C 3 LFAST interface –40 to +125 °C PPC5744PFK0MKU8 2.5 MB/384 KB 176 LQFP exposed pad (Pb free) PPC5744PFK0MMM8 2.5 MB/384 KB 257 MAPBGA (Pb free) LFAST interface Nexus Aurora –40 to +125 °C MPC5743PFK0MLQ8 2 MB/256 KB 144 LQFP (Pb free) –40 to +125 °C MPC5743PFK0MMM8 2 MB/256 KB 257 MAPBGA (Pb free) LFAST interface Nexus Aurora –40 to +125 °C MPC5742PFK0MLQ8 1.5 MB/192 KB 144 LQFP (Pb free) –40 to +125 °C MPC5742PFK0MMM8 1.5 MB/192 KB 257 MAPBGA (Pb free) LFAST interface Nexus Aurora –40 to +125 °C NOTES: 1 All packaged devices are PPC, rather than MPC or SPC, until product qualifications are complete. Not all configurations are available in the PPC parts. 2 The N33E maskset version of the device is limited to a maximum frequency of 180 MHz. 3 The 176 LQFP-EP package is not planned to be available with the N33E maskset version of the PPC5744 device. The 176 LQFP-EP package is under consideration, but not committed, for future maskset versions. MPC5744P Data Sheet, Rev. 0.3 112 Preliminary—Subject to Change Without Notice Freescale Semiconductor Document revision history 6 Document revision history Table 52 summarizes revisions to this document. Table 52. Revision history Revision Date Description of changes Rev. 0.3 06/2012 • Updated specifications and conditions throughout the document and added new information • Updated the name of Freescale’s DigRF module to LFAST module • Updated list and format of orderable part numbers as well as information about the 176 LQFP-EP package’s availability MPC5744P Data Sheet, Rev. 0.3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 113 How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. Technical Information Center, EL516 2100 East Elliot Road Tempe, Arizona 85284 1-800-521-6274 or +1-480-768-2130 www.freescale.com/support Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) www.freescale.com/support Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064 Japan 0120 191014 or +81 3 5437 9125 [email protected] Asia/Pacific: Freescale Semiconductor China Ltd. Exchange Building 23F No. 118 Jianguo Road Chaoyang District Beijing 100022 China +86 10 5879 8000 [email protected] Document Number: MPC5744P Rev. 0.3 06/2012 Preliminary—Subject to Change Without Notice Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. 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