RT8015 2A, 2MHz, Synchronous Step-Down Regulator General Description Features The RT8015 is a high efficiency synchronous, step-down DC/DC converter. Its input voltage range is from 2.6V to 5.5V and provides an adjustable regulated output voltage from 0.8V to 5V while delivering up to 2A of output current. l The internal synchronous low on-resistance power switches increase efficiency and eliminate the need for an external Schottky diode. Switching frequency is set by an external resistor or can be synchronized to an external clock. 100% duty cycle provides low dropout operation extending battery life in portable systems. Current mode operation with external compensation allows the transient response to be optimized over a wide range of loads and output capacitors. RT8015 operation in forced continuous PWM Mode which minimizes ripple voltage and reduces the noise and RF interference. 100% duty cycle in Low Dropout Operation further maximize battery life. l l l l l l l High Efficiency : Up to 95% Low RDS(ON) Internal Switches : 110mΩ Programmable Frequency : 300kHz to 2MHz No Schottky Diode Required 0.8V Reference Allows Low Output Voltage Forced Continuous Mode Operation Low Dropout Operation : 100% Duty Cycle RoHS Compliant and 100% Lead (Pb)-Free Applications l l l l l l Portable Instruments Battery-Powered Equipment Notebook Computers Distributed Power Systems IP Phones Digital Cameras Pin Configurations Ordering Information RT8015 Package Type SP : SOP-8 (Exposed Pad-Option 2) Lead Plating System P : Pb Free G : Green (Halogen Free and Pb Free) (TOP VIEW) SHDN/RT GND 2 LX PGND 3 8 COMP 7 FB GND 9 6 4 5 VDD PVDD SOP-8 (Exposed Pad) Note : Richtek products are : } RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020. } Suitable for use in SnPb or Pb-free soldering processes. DS8015-03 March 2011 www.richtek.com 1 RT8015 Typical Application Circuit RT8015 VIN 2.6V to 5.5V CIN 22uF 5 PVDD LX 6 VDD FB 7 4 ROSC 332k 3 COMP 8 PGND 1 SHDN/RT L1 2.2uH VOUT 2.5V/2A R1 510k COUT 22uF RCOMP 13k GND 2, Exposed Pad (9) CCOMP 1nF R2 240k Note : Using all Ceramic Capacitors Recommended Component for Different Output Voltage Applications VOUT L1 (uH) COUT (uF) R1 (kΩ) R2 (kΩ) RCOMP (kΩ) CCOMP (nF) 3.3V 2.2 22 750 240 13 1 2.5V 2.2 22 510 240 13 1 1.8V 1.0 22 300 240 7.5 1.5 1.2V 1.0 22 120 240 7.5 1.5 Functional Pin Description Pin No. Pin Name Pin Function 1 SHDN/RT Oscillator Resistor Input. Connecting a resistor to ground from this pin sets the switching frequency. Forcing this pin to VDD causes the device to be shut down. 2, 9 (Exposed Pad) GND Signal Ground. All small-signal components and compensation components should connect to this ground, which in turn connects to PGND at one point. The exposed pad must be soldered to a large PCB and connected to GND for maximum power dissipation. 3 LX Internal Power MOSFET Switches Output. Connect this pin to the inductor. 4 PGND Power Ground. Connect this pin close to the (−) terminal of CIN and COUT. 5 PVDD Power Input Supply. Decouple this pin to PGND with a capacitor. 6 VDD 7 FB 8 COMP Signal Input Supply. Decouple this pin to GND with a capacitor. Normally V DD is equal to PVDD. Feedback Pin. Receives the feedback voltage from a resistive divider connected across the output. Error Amplifier Compensation Point. The current comparator threshold increases www.richtek.com 2 with this control voltage. Connect external compensation elements to this pin to stabilize the control loop. DS8015-03 March 2011 RT8015 Function Block Diagram SHDN/RT SD PVDD ISEN OSC Slope Com COMP 0.8V EA FB OC Limit Output Clamp Driver Int-SS LX 0.9V Control Logic 0.7V NISEN POR PGND NMOS I Limit 0.4V VREF OTP GND VDD DS8015-03 March 2011 www.richtek.com 3 RT8015 Operation Main Control Loop The RT8015 is a monolithic, constant-frequency, current mode step-down DC/DC converter. During normal operation, the internal top power switch (P-Channel MOSFET) is turned on at the beginning of each clock cycle. Current in the inductor increases until the peak inductor current reach the value defined by the voltage on the COMP pin. The error amplifier adjusts the voltage on the COMP pin by comparing the feedback signal from a resistor divider on the FB pin with an internal 0.8V reference. When the load current increases, it causes a reduction in the feedback voltage relative to the reference. The error amplifier raises the COMP voltage until the average inductor current matches the new load current. When the top power MOSFET shuts off, the synchronous power switch (N-Channel MOSFET) turns on until either the bottom current limit is reached or the beginning of the next clock cycle. The operating frequency is set by an external resistor connected between the RT pin and ground. The practical switching frequency can range from 300kHz to 2MHz. Power Good comparators will pull the PGOOD output low if the output voltage comes out of regulation by 12.5%. In an over-voltage condition, the top power MOSFET is turned off and the bottom power MOSFET is switched on until either the over-voltage condition clears or the bottom MOSFET's current limit is reached. Frequency Synchronization The internal oscillator of the RT8011 can be synchronized to an external clock connected to the SYNC pin. The frequency of the external clock can be in the range of 300kHz to 2MHz. For this application, the oscillator timing resistor should be chosen to correspond to a frequency that is about 20% lower than the synchronization frequency. The output voltage will then be determined by the input voltage minus the voltage drop across the internal P-Channel MOSFET and the inductor. Low Supply Operation The RT8015 is designed to operate down to an input supply voltage of 2.6V. One important consideration at low input supply voltages is that the RDS(ON) of the P-Channel and N-Channel power switches increases. The user should calculate the power dissipation when the RT8015 is used at 100% duty cycle with low input voltages to ensure that thermal limits are not exceeded. Slope Compensation and Inductor Peak Current Slope compensation provides stability in constant frequency architectures by preventing sub-harmonic oscillations at duty cycles greater than 50%. It is accomplished internally by adding a compensating ramp to the inductor current signal. Normally, the maximum inductor peak current is reduced when slope compensation is added. In the RT8015, however, separated inductor current signals are used to monitor over current condition. This keeps the maximum output current relatively constant regardless of duty cycle. Short Circuit Protection When the output is shorted to ground, the inductor current decays very slowly during a single switching cycle. A current runaway detector is used to monitor inductor current. As current increasing beyond the control of current loop, switching cycles will be skipped to prevent current runaway from occurring. Dropout Operation When the input supply voltage decreases toward the output voltage, the duty cycle increases toward the maximum on-time. Further reduction of the supply voltage forces the main switch to remain on for more than one cycle eventually reaching 100% duty cycle. www.richtek.com 4 DS8015-03 March 2011 RT8015 Absolute Maximum Ratings l l l l l l l l l l (Note 1) Supply Input Voltage, VDD, PVDD --------------------------------------------------------------------------- −0.3V to 6V LX Pin Switch Voltage ------------------------------------------------------------------------------------------ −0.3V to (PVDD + 0.3V) Other I/O Pin Voltages ------------------------------------------------------------------------------------------ −0.3V to (VDD + 0.3V) LX Pin Switch Current ------------------------------------------------------------------------------------------- 4A Power Dissipation, PD @ TA = 25°C SOP-8 (Exposed Pad) ----------------------------------------------------------------------------------------- 1.33W Package Thermal Resistance (Note 2) SOP-8 (Exposed Pad), θJA ------------------------------------------------------------------------------------ 75°C/W SOP-8 (Exposed Pad), θJC ------------------------------------------------------------------------------------ 15°C/W Junction Temperature ------------------------------------------------------------------------------------------- 150°C Lead Temperature (Soldering, 10 sec.)---------------------------------------------------------------------- 260°C Storage Temperature Range ----------------------------------------------------------------------------------- −65°C to 150°C ESD Susceptibility (Note 3) HBM (Human Body Mode) ------------------------------------------------------------------------------------- 2kV MM (Machine Mode) -------------------------------------------------------------------------------------------- 200V Recommended Operating Conditions l l l (Note 4) Supply Input Voltage -------------------------------------------------------------------------------------------- 2.6V to 5.5V Junction Temperature Range ---------------------------------------------------------------------------------- −40°C to 125°C Ambient Temperature Range ---------------------------------------------------------------------------------- −40°C to 85°C Electrical Characteristics (VDD = 3.3V, TA = 25°C, unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit Input Voltage Range VDD 2.6 -- 5.5 V Feedback Reference Voltage VREF 0.784 0.8 0.816 V Active , VFB = 0.78V, Not Switching -- 460 -- µA Shutdown -- -- 1 µA Output Voltage Line Regulation VIN = 2.7V to 5.5V -- 0.04 -- %/V Output Voltage Load Regulation 0A < ILOAD < 2A -- 0.25 -- % DC Bias Current Error Amplifier Transconductance gm -- 800 -- us Current Sense Transresistance RT -- 0.4 -- Ω Power Good Range -- ±12.5 ±15 % Power Good Pull-Down Resistance -- -- 120 Ω ROSC = 332k 0.8 1 1.2 MHz Switching Frequency 0.3 -- 2 MHz 0.3 -- 2 MHz Switching Frequency Sync Frequency Range To be continued DS8015-03 March 2011 www.richtek.com 5 RT8015 Parameter Symbol Test Conditions Min Typ Max Unit Switch On Resistance, High RPMOS I SW = 0.5A -- 110 160 mΩ Switch On Resistance, Low RNMOS I SW = 0.5A -- 110 170 mΩ Peak Current Limit ILIM 2.2 3.2 -- A VDD Rising -- 2.4 -- V VDD Falling -- 2.3 -- V Under Voltage Lockout Threshold Shutdown Threshold VSHDN/RT -- VIN − 0.7 VIN − 0.4 V Note 1. Stresses listed as the above “Absolute Maximum Ratings” may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. θJA is measured in the natural convection at T A = 25°C on 4-layers high effective thermal conductivity test board of JEDEC 51-7 thermal measurement standard. The case point of θJC is on the exposed pad of the package. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. www.richtek.com 6 DS8015-03 March 2011 RT8015 Typical Operating Characteristics Efficiency vs. Output Current Output Voltage vs. Output Current 100 1.810 90 1.808 1.806 VIN = 5V, VOUT = 1.8V 70 Efficiency (%) Output Voltage (V) 80 VIN = 3.3V VIN = 3.3V, VOUT = 1.8V 60 50 40 30 1.804 1.802 1.800 1.798 1.796 20 1.794 10 1.792 1.790 0 0 250 500 750 0 1000 1250 1500 1750 2000 250 500 Peak Current Limited vs. Input Voltage Frequency vs. Temperature 4.0 1100 VOUT = 2.5V Peak Current Limited (A) VIN = 3.3V, VOUT = 1.8V IOUT = 0A 1080 1060 1040 1020 3.5 3.0 2.5 2.0 1000 -50 -25 0 25 50 75 100 3 125 3.25 3.5 3.75 4 4.25 4.5 4.75 5 5.25 5.5 Input Voltage (V) Temperature (°C) Quiescent Current vs. Input Voltage Quiescent Current vs. Temperature 550 500 530 480 Quiescent Current (uA) Quiescent Current (uA) 1000 1250 1500 1750 2000 Output Current (mA) Output Current (mA) Frequency (kHz) 750 510 490 470 450 VIN = 3.3V 460 440 420 400 3 3.25 3.5 3.75 4 4.25 4.5 4.75 Input Voltage (V) DS8015-03 March 2011 5 5.25 5.5 -50 -25 0 25 50 75 100 125 Temperature (°C) www.richtek.com 7 RT8015 Output Voltage vs. Temperature 1.820 VREF vs. Input Voltage 0.805 VIN = 3.3V 1.815 1.805 V REF (V) Output Voltage (V) 0.804 1.810 1.800 1.795 0.803 0.802 1.790 0.801 1.785 0.800 1.780 -50 -25 0 25 50 75 100 3 125 Temperature (°C) 4 4.25 4.5 4.75 5.25 5.5 Load Transient Response VIN = 3.3V, VOUT = 2.5V IOUT = 0A to 2A VIN = 3.3V, VOUT = 2.5V IOUT = 1A to 2A VOUT (50mV/Div) VOUT (50mV/Div) ILX (1A/Div) ILX (1A/Div) Time (50μs/Div) Time (50μs/Div) Output Ripple Output Ripple VIN = 3.3V, VOUT = 2.5V IOUT = 2A VIN = 5V, VOUT = 2.5V IOUT = 2A VOUT (10mV/Div) VOUT (10mV/Div) VLX (5V/Div) VLX (5V/Div) ILX (2A/Div) ILX (2A/Div) Time (250ns/Div) 5 Input Voltage (V) Load Transient Response www.richtek.com 8 3.25 3.5 3.75 Time (250ns/Div) DS8015-03 March 2011 RT8015 Power Good Power On & Inductor Current VIN = 3.3V, VOUT = 2.5V IOUT = 2A VIN (2V/Div) PGOOD (2V/Div) VIN = 3.3V, VOUT = 2.5V IOUT = 2A VIN (2V/Div) VOUT (2V/Div) VLX (5V/Div) VOUT (2V/Div) ILX (2A/Div) ILX (2A/Div) Time (1ms/Div) Time (1ms/Div) Power On & Inductor Current Soft Start and Inrush Current VIN = 5V, VOUT = 2.5V IOUT = 2A VIN = 3.3V, VOUT = 2.5V IOUT = 2A VIN (2V/Div) VLX (5V/Div) VIN (2V/Div) VOUT (2V/Div) VLX (5V/Div) VOUT (2V/Div) I IN (2A/Div) ILX (2A/Div) Time (1ms/Div) Time (2.5ms/Div) Soft Start and Inrush Current VIN = 5V, VOUT = 2.5V IOUT = 2A VIN (2V/Div) VLX (5V/Div) VOUT (2V/Div) I IN (2A/Div) Time (2.5ms/Div) DS8015-03 March 2011 www.richtek.com 9 RT8015 Application Information The basic RT8015 application circuit is shown in Typical Application Circuit. External component selection is determined by the maximum load current and begins with the selection of the inductor value and operating frequency followed by CIN and COUT. The transition from low current operation begins when the peak inductor current falls below the minimum peak current. Lower inductor values result in higher ripple current which causes this to occur at lower load currents. This causes a dip in efficiency in the upper range of low current operation. Operating Frequency The operating frequency of the RT8015 is determined by an external resistor that is connected between the RT pin and ground. The value of the resistor sets the ramp current that is used to charge and discharge an internal timing capacitor within the oscillator. The RT resistor value can be determined by examining the frequency vs. RT curve. Although frequencies as high as 4MHz are possible, the minimum on-time of the RT8015 imposes a minimum limit on the operating duty cycle. The minimum on-time is typically 110ns. Therefore, the minimum duty cycle is equal to 100 x 110ns x f(Hz). Inductor Selection For a given input and output voltage, the inductor value and operating frequency determine the ripple current. The ripple current ∆IL increases with higher VIN and decreases with higher inductance. V V ∆IL = OUT 1 − OUT VIN f × L Having a lower ripple current reduces the ESR losses in the output capacitors and the output voltage ripple. Highest efficiency operation is achieved at low frequency with small ripple current. This, however, requires a large inductor. A reasonable starting point for selecting the ripple current is ∆I = 0.4(IMAX). The largest ripple current occurs at the highest VIN. To guarantee that the ripple current stays below a specified maximum, the inductor value should be chosen according to the following equation : VOUT VOUT L= 1− f × ∆IL(MAX) VIN(MAX) www.richtek.com 10 4.5 4 3.5 Frequency (MHz) Selection of the operating frequency is a tradeoff between efficiency and component size. High frequency operation allows the use of smaller inductor and capacitor values. Operation at lower frequency improves efficiency by reducing internal gate charge and switching losses but requires larger inductance and/or capacitance to maintain low output ripple voltage. 3 RT = 154k for 2MHz 2.5 2 1.5 RT = 332k for 1MHz 1 0.5 0 0 100 200 300 400 500 600 700 800 900 100 1000 0 (kΩ)) RRT RT (k Figure 1 Inductor Core Selection Once the value for L is known, the type of inductor must be selected. High efficiency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite or mollypermalloy cores. Actual core loss is independent of core size for a fixed inductor value but it is very dependent on the inductance selected. As the inductance increases, core losses decrease. Unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. Ferrite designs have very low core losses and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite core material saturates “hard”, which means that inductance collapses abruptly when the peak design current is exceeded. This result in an abrupt increase in inductor ripple current and consequent output voltage ripple. Do not allow the core to saturate! DS8015-03 March 2011 RT8015 Different core materials and shapes will change the size/ current and price/current relationship of an inductor. Toroid or shielded pot cores in ferrite or permalloy materials are small and don't radiate energy but generally cost more than powdered iron core inductors with similar characteristics. The choice of which style inductor to use mainly depends on the price vs. size requirements and any radiated field/EMI requirements. use types that have been surge tested for use in switching power supplies. Aluminum electrolytic capacitors have significantly higher ESR but can be used in cost-sensitive applications provided that consideration is given to ripple current ratings and long term reliability. Ceramic capacitors have excellent low ESR characteristics but can have a high voltage coefficient and audible piezoelectric effects. The high Q of ceramic capacitors with trace inductance can also lead to significant ringing. CIN and COUT Selection The input capacitance, CIN, is needed to filter the trapezoidal current at the source of the top MOSFET. To prevent large ripple voltage, a low ESR input capacitor sized for the maximum RMS current should be used. RMS current is given by : V VIN −1 IRMS = IOUT(MAX) OUT VIN VOUT This formula has a maximum at VIN = 2VOUT , where I RMS = I OUT /2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Note that ripple current ratings from capacitor manufacturers are often based on only 2000 hours of life which makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature than required. Several capacitors may also be paralleled to meet size or height requirements in the design. The selection of COUT is determined by the effective series resistance (ESR) that is required to minimize voltage ripple and load step transients, as well as the amount of bulk capacitance that is necessary to ensure that the control loop is stable. Loop stability can be checked by viewing the load transient response as described in a later section. The output ripple, ∆VOUT , is determined by : 1 ∆VOUT ≤ ∆IL ESR + 8fCOUT The output ripple is highest at maximum input voltage since ∆IL increases with input voltage. Multiple capacitors placed in parallel may be needed to meet the ESR and RMS current handling requirements. Dry tantalum, special polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages. Special polymer capacitors offer very low ESR but have lower capacitance density than other types. Tantalum capacitors have the highest capacitance density but it is important to only DS8015-03 March 2011 Using Ceramic Input and Output Capacitors Higher values, lower cost ceramic capacitors are now becoming available in smaller case sizes. Their high ripple current, high voltage rating and low ESR make them ideal for switching regulator applications. However, care must be taken when these capacitors are used at the input and output. When a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the input, VIN. At best, this ringing can couple to the output and be mistaken as loop instability. At worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at VIN large enough to damage the part. Output Voltage Programming The output voltage is set by an external resistive divider according to the following equation : VOUT = VREF × 1 + R1 R2 where VREF equals to 0.8V typical. The resistive divider allows the FB pin to sense a fraction of the output voltage as shown in Figure 2. VOUT R1 FB RT8015 R2 GND Figure 2. Setting the Output Voltage www.richtek.com 11 RT8015 Efficiency Considerations The efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Efficiency can be expressed as : Efficiency = 100% − (L1+ L2+ L3+ ...) where L1, L2, etc. are the individual losses as a percentage of input power. Although all dissipative elements in the circuit produce losses, two main sources usually account for most of the losses: VDD quiescent current and I2R losses. The VDD quiescent current loss dominates the efficiency loss at very low load currents whereas the I 2R loss dominates the efficiency loss at medium to high load currents. In a typical efficiency plot, the efficiency curve at very low load currents can be misleading since the actual power lost is of no consequence. 1. The VDD quiescent current is due to two components : the DC bias current as given in the electrical characteristics and the internal main switch and synchronous switch gate charge currents. The gate charge current results from switching the gate capacitance of the internal power MOSFET switches. Each time the gate is switched from high to low to high again, a packet of charge ∆Q moves from VDD to ground. The resulting ∆Q/∆t is the current out of VDD that is typically larger than the DC bias current. In continuous mode, IGATECHG = f(QT+QB) where QT and QB are the gate charges of the internal top and bottom switches. Both the DC bias and gate charge losses are proportional to VDD and thus their effects will be more pronounced at higher supply voltages. 2. I2R losses are calculated from the resistances of the internal switches, RSW and external inductor RL. In continuous mode the average output current flowing through inductor L is “chopped” between the main switch and the synchronous switch. Thus, the series resistance looking into the LX pin is a function of both top and bottom MOSFET RDS(ON) and the duty cycle (D) as follows : RSW = RDS(ON)TOP x D + RDS(ON)BOT x (1"D) The RDS(ON) for both the top and bottom MOSFETs can be obtained from the Typical Performance Characteristics curves. Thus, to obtain I2R losses, simply add RSW to RL and multiply www.richtek.com 12 the result by the square of the average output current. Other losses including CIN and COUT ESR dissipative losses and inductor core losses generally account for less than 2% of the total loss. Checking Transient Response The regulator loop response can be checked by looking at the load transient response. Switching regulators take several cycles to respond to a step in load current. When a load step occurs, VOUT immediately shifts by an amount equal to ∆ILOAD(ESR), where ESR is the effective series resistance of COUT . ∆I LOAD also begins to charge or discharge COUT generating a feedback error signal used by the regulator to return VOUT to its steady-state value. During this recovery time, VOUT can be monitored for overshoot or ringing that would indicate a stability problem. The COMP pin external components and output capacitor shown in Typical Application Circuit will provide adequate compensation for most applications. Thermal Considerations For continuous operation, do not exceed absolute maximum operation junction temperature 125°C. The maximum power dissipation depends on the thermal resistance of IC package, PCB layout, the rate of surroundings airflow and temperature difference between junctions to ambient. The maximum power dissipation can be calculated by following formula: PD(MAX) = ( TJ(MAX) − TA ) / θJA Where T J(MAX) is the maximum operation junction temperature 125°C, TA is the ambient temperature and the θJA is the junction to ambient thermal resistance. For recommended operating conditions specification of RT8015, where T J(MAX) is the maximum junction temperature of the die (125°C) and TA is the maximum ambient temperature. The junction to ambient thermal resistance for SOP-8 (Exposed Pad) package is 75°C/W on the standard JEDEC 51-7 (4 layers, 2S2P) thermal test board. The copper thickness is 2oz. The maximum power dissipation at TA = 25°C can be calculated by following formula: PD (MAX) = (125°C − 25°C) / (75°C/W) = 1.33W (SOP-8 Exposed Pad on the minimum layout) DS8015-03 March 2011 RT8015 The maximum power dissipation depends on operating ambient temperature for fixed T J(MAX) and thermal resistance θJA. For RT8015 package, the Figure 3 of derating curves allows the designer to see the effect of rising ambient temperature on the maximum power allowed. The thermal resistance θJA of SOP-8 (Exposed Pad) is determined by the package design and the PCB design. However, the package design had been designed. If possible, it’ s useful to increase thermal performance by the PCB design. The thermal resistance θJA can be decreased by adding a copper under the exposed pad of SOP-8 (Exposed Pad) package. As shown in Figure 4, the amount of copper area to which the SOP-8 (Exposed Pad) is mounted affects thermal performance. When mounted to the standard SOP-8 (Exposed Pad) pad (Figure 4.a), θJA is 75°C/W. Adding copper area of pad under the SOP-8 (Exposed Pad) (Figure 4.b) reduces the θJA to 64°C/W. Even further, increasing the copper area of pad to 70mm2 (Figure 4.e) reduces the θJA to 49°C/W. 2.4 Power Dissipation (W) 1.6 (b) Copper Area = 10mm2, θJA = 64°C/W (c) Copper Area = 30mm2, θJA = 54°C/W Copper Area 70mm2 50mm2 30mm2 10mm2 Min. layout 2 (a) Copper Area = (2.3 x 2.3) mm2, θJA = 75°C/W 1.2 0.8 (d) Copper Area = 50mm2, θJA = 51°C/W 0.4 0 0 20 40 60 80 100 120 140 Ambient Temperature (°C) Figure 3. Derating Curve for Package (e) Copper Area = 70mm2, θJA = 49°C/W Figure 4. Thermal Resistance vs. Copper Area Layout Thermal Design DS8015-03 March 2011 www.richtek.com 13 RT8015 Layout Considerations Follow the PCB layout guidelines for optimal performance of RT8015. } A ground plane is recommended. If a ground plane layer is not used, the signal and power grounds should be segregated with all small-signal components returning to the GND pin at one point that is then connected to the PGND pin close to the IC. The exposed pad should be connected to GND. } Connect the terminal of the input capacitor(s), CIN, as close as possible to the PVDD pin. This capacitor provides the AC current into the internal power MOSFETs. } LX node is with high frequency voltage swing and should be kept small area. Keep all sensitive small-signal nodes away from LX node to prevent stray capacitive noise pick-up. } Flood all unused areas on all layers with copper. Flooding with copper will reduce the temperature rise of power components. You can connect the copper areas to any DC net (PVDD, VDD, VOUT, PGND, GND, or any other DC rail in your system). } Connect the FB pin directly to the feedback resistors. The resistor divider must be connected between VOUT and GND. Output capacitor must be CIN must be placed between V DD and near RT8015 GND as closer as possible V IN V GND C IN COUT OUT RT8015 R1 CF V OUT R2 L1 PVDD 5 4 PGND VDD 6 3 LX FB 7 2 GND COMP 8 1 SHDN/RT R COMP LX should be connected to Inductor by wide and short trace, keep sensitive compontents away from this trace R OSC C COMP GND Connect the FB pin directly to feedback resistors. The resistor divider must be connected between V OUT and GND. Figure 5 Table 1. Recommended Inductor Series Inductance (uH) DCR (mΩ) Current Rating (mA) Component Supplier TAIYO YUDEN NR 4018 2.2 60 2700 Sumida CDRH4D28 2.2 31.3 2040 GOTREND GTSD53 2.2 29 2410 TAIYO YUDEN NR 4018 1.0 30 4000 Sumida CDRH4D28C/LD 1.0 17.5 3000 GOTREND GTSD53 1.0 15 4000 Component Supplier TDK TDK Panasonic Panasonic TAIYO YUDEN TAIYO YUDEN www.richtek.com 14 Table 2. Recommended Capacitor Part No. Capacitance (uF) C3225X5R0J226M 22 C3225X5R0J226M 22 ECJ4YB0J226M 22 ECJ4YB1A226M 22 LMK325BJ226ML 22 JMK316BJ226ML 22 Dimensions (mm) 4.00 x 4.00 x 1.80 4.50 x 4.50 x 3.00 5.00x 5.00 x 2.80 4.00 x 4.00 x 1.80 4.50 x 4.50 x 3.00 5.00x 5.00 x 2.80 Case Size 1210 1210 1210 1210 1210 1206 DS8015-03 March 2011 RT8015 Outline Dimension H A M EXPOSED THERMAL PAD (Bottom of Package) Y J X B F C I D Dimensions In Millimeters Dimensions In Inches Symbol Min Max Min Max A 4.801 5.004 0.189 0.197 B 3.810 4.000 0.150 0.157 C 1.346 1.753 0.053 0.069 D 0.330 0.510 0.013 0.020 F 1.194 1.346 0.047 0.053 H 0.170 0.254 0.007 0.010 I 0.000 0.152 0.000 0.006 J 5.791 6.200 0.228 0.244 M 0.406 1.270 0.016 0.050 X 2.000 2.300 0.079 0.091 Y 2.000 2.300 0.079 0.091 X 2.100 2.500 0.083 0.098 Y 3.000 3.500 0.118 0.138 Option 1 Option 2 8-Lead SOP (Exposed Pad) Plastic Package Richtek Technology Corporation Richtek Technology Corporation Headquarter Taipei Office (Marketing) 5F, No. 20, Taiyuen Street, Chupei City 5F, No. 95, Minchiuan Road, Hsintien City Hsinchu, Taiwan, R.O.C. Taipei County, Taiwan, R.O.C. Tel: (8863)5526789 Fax: (8863)5526611 Tel: (8862)86672399 Fax: (8862)86672377 Email: [email protected] Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek. DS8015-03 March 2011 www.richtek.com 15