AN11415 PTN3355 PCB Layout Guideline, Reference Schematics and BOM Rev. 1 — 16 December 2014 Application note Document information Info Content Keywords DisplayPort, PTN3355 Abstract This document provides a practical guideline to PTN3355 application design and layout. AN11415 NXP Semiconductors PTN3355 PCB Layout Guideline, Reference Schematics and BOM Revision history Rev Date Description 1 20141216 Initial version Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] AN11415 Application note All information provided in this document is subject to legal disclaimers. Rev. 1 — 16 December 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 2 of 19 AN11415 NXP Semiconductors PTN3355 PCB Layout Guideline, Reference Schematics and BOM 1. Introduction This document provides a guideline for PTN3355 application and layout guide line in ULT notebook, docking station and dongle designs. PTN3355 is low power DisplayPort to VGA bridge IC with integrated 1-2 VGA switch. PTN3355 is in an HVQFN40 package, 6 mm x 6 mm, with 0.5 mm pitch. PTN3355 consumes approximately 200 mW of power for video streaming in WUXGA resolution and 890 uW of power in low-power mode. The VGA output is powered down when there is no valid DisplayPort source data being transmitted. PTN3355 is suitable for Ultra Low Power Notebook and other low power devices. PTN3355 also offers second VGA port for docking design. PTN3355 is powered from a 3.3 V power supply, and generated 1.5 V through an internal step-down switch regulator and buck converter for internal core usage and DAC usage. 2. Reference designs 2.1 ULT notebook design PTN3355 can be connected directly to the DP lanes on mother board, or on docking station. Connect PTN3355 to one of the DP ports on PCH/GPU with 0.1uF AC caps in series for DP data lanes and AUX lanes. PTN3355 probably will be used as a primary display; make sure the BIOS is set accordingly. Below is a reference design for one VGA application. AN11415 Application note All information provided in this document is subject to legal disclaimers. Rev. 1 — 16 December 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 3 of 19 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx VBUCK_1V5 VDD_3V3 VDD_3V3 +3V3 0.1uF 27MHz L2 1 L1 VDD_3V3 1 0.1uF 3 RED RED DDC_SDA GRN 0.1uF 31 (OPTIONAL) 12 DDC_SCL 29 28 GRN 27 26 BLU 25 HSYNC 24 VSYNC 36 HSYNC_VGA VSYNC_VGA 23 2 2 J5 75 3.3pF C26 DNL C27 1 1 2 1 PESD5V0U2BT 2 1 3 PESD5V0U2BT 3.3pF 3.3pF C28 DNL C29 3.3pF 3.3pF C30 DNL C31 002aah568_an11415 Parts shown with shading are extra components required in DC-to-DC converter mode to achieve low power performance. Fig 1. ULT notebook reference design BLU_VGA AN11415 4 of 19 © NXP Semiconductors N.V. 2014. All rights reserved. OPTION DESIGN: 3.3pF 1 75 2 75 1 1 3 L8 1 2 22 Ohm 300mA RED I2C BIRD PIN OUT VDD_3V3 RED_VGA GRN_VGA MS_I2C HEADER 4 (NO LOAD) D2 L7 1 2 22 Ohm 300mA GRN 1 MS_SDA_CFG2 R38 10K 74LVC2T45GN 1 2 3 4 2 MS_SCL_CFG1 D1 L6 1 2 22 Ohm 300mA BLU HS_5V VS_5V 1 8 7 6 5 1 VCCB 1B 2B DIR 2 VCCA 1A 2A GND 2 1 2 3 4 3 PI FILTER DESIGN IS CUSTOMER SPECIFIC 2 DNL 2 10K DNL 2 1 1 HSYNC_VGA VSYNC_VGA 10K DDC1_PU CFG1, CFG2: 11, default 00, if MS bus is not used 0.1uF U3 2 C62 C63 1 MS_SDA_CFG2 VDD_5V BAT54 D4 CFG5_XTAL 2.2K 1 VDD_3V3 OPTION DESIGN: ESD PROTECTION CIRCUITRY. CFG3 OPEN, NOT USED CFG5 OPEN: 27 MHZ XTAL IS USED MS_SCL_CFG1 2 VDD_5V DDC_SCL 1uF HPD C33 10pF 3 GND 0.1uF 2.2K OPTION DESIGN: Install U3 to support 5V H/V for legacy projector and CRTs. D3 C32 10pF 2 DDC_SDA 2 22 21 1 36 VDD_3V3 CFG3 16 17 VGA_CONN 41 11 1 C6 2 PTN3355 1.2K 1% PESD5V0U2BT VDDE33_IO DDC_SCL1 DDC_SDA1 ML1_N HSYNC2 ML1_P RSET 1 RED2 RED1 32 34 33 OSC_OUT OSC_IN 36 35 VDDD15 VDDA15_DAC DDC_SCL2 20 10 VDDA15_DP VSYNC2 9 ML1_N VSYNC1 CFG2 ML1_P ML0_N 19 0.01uF C64 0.01uF HSYNC1 RST_N 2 1 8 ML0_P 18 7 BLU2 BLU1 17 ML0_N 0.1uF VBUCK_1V5 AUX_N VDDE33_IO 30 RED_RTN NC1 RED GREEN_RTN SDA GREEN BLUE_RTN HS BLUE +5V VS NC2 GND1 SCL GND2 GND3 GND4 PTN3355 PCB Layout Guideline, Reference Schematics and BOM Rev. 1 — 16 December 2014 All information provided in this document is subject to legal disclaimers. ASSUME SM_BUS HAS PULL UP ON SYSTEM SIDE 6 CFG3 5 GRN2 GRN1 CFG5 4 AUX_N ML0_P VSYNC_VGA RSET AUX_P 16 2 VDD_3V3 HSYNC_VGA BLU DOCK_IN 15 3 CFG1 2 14 DOCK_IN AUX_P HPD 1 0.01uF 0.1uF DDC_SDA2 1 100K MS_SDA_CFG2 2 10K 1 (OPTIONAL) MS_SCL_CFG1 VDDA33_DNW 13 2 R36 1 37 39 HPD TESTMODE VDD_3V3 PVDD33 0.1uF SWOUT PGND U1 38 AUX_N 40 AUX_P C11 6 11 1 7 12 2 8 13 3 9 14 4 10 15 5 BAT54 2 C10 0.1uF VDD_CONN_5V D5 1 C61 SWOUT TESTMODE OPEN: I2C ADD = C0H ML1_N TESTMODE ML1_P VDD_5V 2 0.1uF 2 C60 4.7uH 4.7uF C58 1 CPU/GPU + 0.1uF 2 2.2uF 0.1uF Resonator (with built-in capacitors) OSC_IN ML0_N C21 C3 2 C5 1 FB 2 ML0_P 2 2 OSC_OUT 1 0.1uF 1 C59 0.1uF NXP Semiconductors AN11415 Application note VDD_5V AN11415 NXP Semiconductors PTN3355 PCB Layout Guideline, Reference Schematics and BOM 2.2 Dongle design PTN3355 can also be used on DP-VGA dongles. Connect PTN3355 DPVGA to one of the DP ports on the system board. DPVGA dongle gets 3V3 power from DP connector for PTN3355 IC operation, then boost up to 5 V for VGA connector. AN11415 Application note All information provided in this document is subject to legal disclaimers. Rev. 1 — 16 December 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 5 of 19 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx NXP Semiconductors VBUCK_1V5 0.1uF 1 2 27MHz + 0.1uF SWOUT TESTMODE 1 VDD_3V3 TESTMODE OPEN: I2C ADD = C0H AUX_N VDD_5V D5 1 0.1uF 31 DDC_SCL 29 28 GRN 27 26 BLU 25 HSYNC 24 VSYNC 36 HSYNC_VGA VSYNC_VGA 23 0.1uF 1 2 2.2K 2 1 1 2 2 1 3 RED_VGA GRN_VGA L8 1 2 22 Ohm 300mA 1 1 C30 DNL 2 C29 1 C28 DNL 3.3pF 3.3pF 2 C27 3.3pF 3.3pF 2 C26 DNL 3.3pF 1 3.3pF 2 75 2 75 1 75 1 RED R38 10K VDD_3V3 D2 L7 1 2 22 Ohm 300mA GRN 1 74LVC2T45GN D1 L6 1 2 22 Ohm 300mA BLU HS_5V VS_5V 2 VCCB 1B 2B DIR 8 7 6 5 PESD5V0U2BT PI FILTER DESIGN IS CUSTOMER SPECIFIC 3 DNL 2 10K DNL 2 2 VCCA 1A 2A GND 10K CFG1, CFG2: 11, default 00, if MS bus is not used 0.1uF U3 1 2 3 4 1 1 C63 DDC1_PU PESD5V0U2BT MS_SDA_CFG2 2 1 1 VDD_5V C62 3 2.2K 100k OPTIONAL VDD_3V3 BAT54 D4 CFG5_XTAL CFG5 OPEN: 27 MHZ XTAL IS USED 2 2 OPTION DESIGN: ESD PROTECTION CIRCUITRY. CFG3 MS_SCL_CFG1 C33 10pF VDD_5V DDC_SCL 1uF HPD D3 C32 10pF 3 GND VDD_3V3 2 DDC_SDA 21 2 22 1 36 (OPTIONAL) OPTION DESIGN: Install U3 to support 5V H/V for legacy projector and CRTs. 16 17 VGA_CONN PESD5V0U2BT DDC_SCL1 1.2K 1% 41 20 C6 19 PTN3355 HSYNC2 VDDE33_IO VSYNC2 DDC_SDA1 ML1_N RSET 1 RED2 RED1 32 34 33 OSC_IN OSC_OUT VDDA15_DAC 35 36 37 VDDD15 PVDD33 TESTMODE 40 39 38 ML1_P CFG2 10 DDC_SCL2 CFG3 9 ML1_N VDDA15_DP 18 ML1_P VSYNC1 17 2 10uF_6.3V 0.01uF C64 0.01uF ML0_N CFG5 1 8 HSYNC1 ML0_P CFG1 7 BLU1 30 RED_RTN NC1 RED GREEN_RTN SDA GREEN BLUE_RTN HS BLUE +5V VS NC2 GND1 SCL GND2 GND3 GND4 C31 BLU_VGA Fig 2. ULT DPVGA dongle reference design AN11415 6 of 19 © NXP Semiconductors N.V. 2014. All rights reserved. ULT_DPVGAdongleref PTN3355 PCB Layout Guideline, Reference Schematics and BOM Rev. 1 — 16 December 2014 All information provided in this document is subject to legal disclaimers. VBUCK_1V5 BLU2 VDDE33_IO 16 ML0_N 0.1uF AUX_N 15 5 6 GRN2 GRN1 14 4 AUX_N ML0_P VSYNC_VGA RSET AUX_P HPD 2 VDD_3V3 VDD_3V3 HSYNC_VGA BLU DOCK_IN DDC_SDA2 3 12 2 DOCK_IN AUX_P RST_N 1M 1M 1M 1M 1 11 2 10K 0.01uF 0.1uF VDDA33_DNW 1 1 SWOUT PGND U1 VDD_3V3 0.01uF 6 11 1 7 12 2 8 13 3 9 14 4 10 15 5 RED RED DDC_SDA GRN VDD_3V3 HSYNC_VGA VSYNC_VGA 3 BAT54 HPD 47 ohm @ 100MHz 0.1uF VDD_CONN_5V 2 2 L1 0.1uF AUX_P Resonator (with built-in capacitors) 4.7uH 4.7uF OSC_IN C3 OSC_OUT ML1_N 1 Pin 21 is the PAD to ground pigtail GROUND wire ML0_P ML0_N ML1_P DP_PWR 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 LANE0p GND1 LANE0n LANE1p GND2 LANE1n LANE2p GND3 LANE2n LANE3p GND4 LANE3n GND_DOWN1 GND_DOWN2 AUXp GND5 AUXn HPD RTN DP_PWR GND6 13 AN11415 Application note DP CONN AN11415 NXP Semiconductors PTN3355 PCB Layout Guideline, Reference Schematics and BOM 2.3 Minimum BOM design For cost conscious application, PTN3355 needs only a handful of components to function. Below is a minimum BOM design for embedded or dongle design. AN11415 Application note All information provided in this document is subject to legal disclaimers. Rev. 1 — 16 December 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 7 of 19 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx NXP Semiconductors AN11415 Application note VDD_5V VDD_3V3 C59 0.1uF C21 0.1uF C60 0.1uF 27MHz ML0_P ML0_N Resonator (with built-in capacitors) 0.1uF CPU/GPU ML1_P ML1_N C61 0.1uF C10 0.1uF VDD_3V3 TESTMODE AUX_N C11 0.1uF HPD OSC_IN OSC_OUT VDD_5V AUX_P 0.1uF 6 11 1 7 12 2 8 13 3 9 14 4 10 15 5 RED DOCK_IN 2 0.01uF AUX_P 3 AUX_N 4 VDD_3V3 5 ML0_P 6 ML0_N 7 0.1uF 8 ML1_P 9 ML1_N 10 31 RED1 32 RED2 34 33 OSC_IN 35 PI FILTER DESIGN IS CUSTOMER SPECIFIC DDC_SDA GRN HSYNC_VGA BLU VSYNC_VGA DDC_SCL VDDA33_DNW RSET DOCK_IN GRN2 AUX_P GRN1 AUX_N BLU2 VDDE33_IO BLU1 ML0_P HSYNC1 ML0_N VSYNC1 VDDA15_DP DDC_SCL2 ML1_P DDC_SDA1 ML1_N VDDE33_IO 30 RSET 1.2K 1% 16 17 VGA_CONN 29 28 RED_RTN NC1 RED GREEN_RTN SDA GREEN BLUE_RTN HS BLUE +5V VS NC2 GND1 SCL GND2 GND3 GND4 GRN 27 26 BLU 25 HSYNC 24 VSYNC 36 HSYNC_VGA VSYNC_VGA 23 22 36 DDC_SDA 21 GND 0.1uF BLU 41 DDC_SCL1 20 HSYNC2 19 VSYNC2 18 CFG3 CFG2 17 16 CFG1 CFG5 15 14 DDC_SDA2 HPD 13 PTN3355 12 0.01uF 11 RST_N VDD_3V3 GRN CFG5_XTAL RED TESTMODE DDC_SCL DOCK_IN 75 75 75 MS_SCL_CFG1 CFG5_XTAL MS_SDA_CFG2 2.2K CFG3 VDD_5V CFG3 MS_SDA_CFG2 2.2K MS_SCL_CFG1 HPD TESTMODE OPEN: I2C ADD = C0H CFG5 OPEN: 27 MHZ XTAL IS USED CFG3 OPEN, NOT USED CFG1, CFG2: 11, default 00, if MS bus is not used Fig 3. Minimum BOM reference design AN11415 8 of 19 © NXP Semiconductors N.V. 2014. All rights reserved. min_BOM PTN3355 PCB Layout Guideline, Reference Schematics and BOM Rev. 1 — 16 December 2014 All information provided in this document is subject to legal disclaimers. 1 OSC_OUT 37 36 VDDD15 ASSUME SM_BUS HAS PULL UP ON SYSTEM SIDE VDDA15_DAC VDD_3V3 TESTMODE 39 38 PVDD33 PGND U1 MS_SDA_CFG2 SWOUT MS_SCL_CFG1 40 RED AN11415 NXP Semiconductors PTN3355 PCB Layout Guideline, Reference Schematics and BOM 3. Buck converter 3.1 Buck converter layout guideline PTN3355 utilizes a switch mode power supply to deliver the power needed with high efficiency. Switch mode power supplies require careful attention to the PC board layout. There are two switching high-current loops formed by the switching action of the buck converter. One loop is formed by the current that flows from the input capacitor through the PVDD pin of the part, through the internal PMOS High-side switch, out the SW pin, through the inductor and the load capacitor to the analog ground, and through the ground plane back to the ground connection of the input capacitor. A second switching high current loop is formed when the low-side NMOS switch is on. The current flows from the PGND pin of the part through the internal NMOS switch, out the SW pin, through the inductor and the load capacitor, to the analog ground, and through the ground plane back to the PGND pin of the part. Fig 4. Switching High-current Loop1: PVDD - LC - PMOS -- GND To minimize electromagnetic interference (EMI), it is essential to minimize the length and area of the switching high current loops. It is also critical that the two switching current paths are matched as closely as possible. AN11415 Application note All information provided in this document is subject to legal disclaimers. Rev. 1 — 16 December 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 9 of 19 AN11415 NXP Semiconductors PTN3355 PCB Layout Guideline, Reference Schematics and BOM Fig 5. Switching high-current loop2 : PGND - NMOS - SW - LC - GND Here are some guidelines for PC board design: • • • • Connect the exposed paddle of the IC to the PC board ground plane. Place the input capacitor as close to the PVDD pin as possible. Place the inductor and the load capacitor as close to the SW pin as possible. Keep the traces for the input capacitor, inductor and the output capacitor, short, direct and wide. • Do not connect the PGND pin directly to the ground plane, instead, connect the PGND pin and the input capacitor's ground pin to the ground plane at the same point. • Minimize the distance between the input capacitor's ground and the ground of the load capacitor. • Keep the trace for the FB (Vout to VDD1V5) away from the switching high current paths. The following is a proposed PC board layout scheme for the PTN3355 which minimizes the area of the two switching current loops and matches the current flow paths for the two loops as closely as possible. Note the smaller capacitors are 0.1 uF caps that must be place as close to the pin as possible. AN11415 Application note All information provided in this document is subject to legal disclaimers. Rev. 1 — 16 December 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 10 of 19 AN11415 NXP Semiconductors PTN3355 PCB Layout Guideline, Reference Schematics and BOM Fig 6. AN11415 Application note Buck converter component placement All information provided in this document is subject to legal disclaimers. Rev. 1 — 16 December 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 11 of 19 AN11415 NXP Semiconductors PTN3355 PCB Layout Guideline, Reference Schematics and BOM Fig 7. AN11415 Application note Buck converter switching current loops All information provided in this document is subject to legal disclaimers. Rev. 1 — 16 December 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 12 of 19 AN11415 NXP Semiconductors PTN3355 PCB Layout Guideline, Reference Schematics and BOM 3.2 Buck converter schematic Fig 8. Buck converter schematics 4. DP receiver interface Main differential pairs and AUX channel are routed with 100 Ohm impedance. The important parameters to calculate the impedance are:. • • • • • PCB thickness Distance to ground plane Trace width Trace spacing PCB permittivity Guard grounds are used to isolate the pair. This helps to eliminate cross talk between traces. Trace lengths are matched on the same pair to 0.01”. Inter pair match to 1”. AC caps for DP lanes and AUX pair should be placed close to the DP interface. When signals change plane, the ground plane need to move along to keep constant trace impedance. On DPVGA a ground island is inserted on the VCC plane for this purpose. AN11415 Application note All information provided in this document is subject to legal disclaimers. Rev. 1 — 16 December 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 13 of 19 AN11415 NXP Semiconductors PTN3355 PCB Layout Guideline, Reference Schematics and BOM 5. VGA interface Table 1. Design guidelines for VGA connector, PWB to cable junction Design guideline number Design guideline description Approximate impact on EMI decrease 1 Define the 2nd PWB layer as ground plane 2 Connect the ground chassis pins of the VGA PWB-connector 3 Use an upper ground plane around VGA connector pins. This design guideline makes no sense when it is not combined with design guideline 4. 4 Use enough vias to connect the upper ground 20 dB plane with main ground plane in 2nd PWB layer. Enough means around every 3 mm (stitching) 5 Ensure proper connection between PWB-connector chassis and upper ground plane by using contact springs (at least 3 contact points). Emission improvement when either 1 or 3 contacts were used was 10 dB! 6 Apply ferrite bead around VGA cable (is already 3 dB very common for typical cables available from the market) 25 dB 10 dB Following the recommended guidelines, all RGB traces on DPVGA board are routed with 75 Ohm impedance from PTN3355 to VGA connector. Ground fills are used to isolate these traces. Ground fills are connected to ground plane with vias. AN11415 Application note All information provided in this document is subject to legal disclaimers. Rev. 1 — 16 December 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 14 of 19 AN11415 NXP Semiconductors PTN3355 PCB Layout Guideline, Reference Schematics and BOM 6. PCB stack up 4-layer FR4 PCB is sufficient for PTN3355 DP-VGA layout. Suggested layers: 1. Signal layer 1 for DPs, with ground cover the entire buck converter area plus power islands or thick traces for Vin and Vout for buck converter. 2. Ground layer 3. Power layer with VDD_3V3 island to cover entire PTN3355, except pin 39, 36, 35 and pin 8. 4. Signal layer 2 Table 2. PCB stack up PCB stack up Impedance Thickness (mil) Solder mask 0.50 mils Single copper + plating 0.70 mils 9.45 mils, 50 10 % 3.55 mils, 75 10 % 53.09 5.9/5.5/5.9 mils, 100 10 % Diff 101.26 Prepreg 4.70 mils copper 1.40 mils core 47.20 mils copper 1.40 mils Prepreg 4.70 mils copper + plating 0.70 mils 9.45 mils, 50 10 % 3.55 mils, 75 10 % 53.09 5.9/5.5/5.9 mils, 100 10 % 101.26 Solder mask 0.50 mils TOTAL 61.80 mils 1.57 mm AN11415 Application note All information provided in this document is subject to legal disclaimers. Rev. 1 — 16 December 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 15 of 19 AN11415 NXP Semiconductors PTN3355 PCB Layout Guideline, Reference Schematics and BOM 7. PTN3355 on notebook BOM Fig 9. AN11415 Application note Notebook BOM All information provided in this document is subject to legal disclaimers. Rev. 1 — 16 December 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 16 of 19 AN11415 NXP Semiconductors PTN3355 PCB Layout Guideline, Reference Schematics and BOM 8. HVQFN exposed center pad solder lands PTN3355 uses HVQFN package. The HVQFN package exposed center pad must be soldered to a corresponding solder land on the board for enhanced thermal, as well as electrical ground, performance. During reflow soldering, solder paste melts and gas or trapped air is released, causing splattering or solder balling. Solder balling and splatter can be minimized if the solder paste is printed as a number of individual dots, instead of one large deposit, and if the solder paste is kept at a sufficient distance from the edge of the solder land. The solder paste pattern area should cover 35 % of the solder land area. When printing solder paste on the exposed die pad solder land, the solder paste dot area should cover no more than 20 % of this solder land area. Furthermore, the paste should be printed away from the solder land edges. This is illustrated in 01; the solder paste pattern area lies within the boundary indicated by the red line and it is divided by the entire solder land area. A A 001aac866 Fig 10. Solder paste dot area (left) and paste pattern area (right) 9. References AN11415 Application note [1] PTN3355 datasheet, 14 July 2014 [2] PTN3355 Reference Design Schematics, rev 0.15 [3] AN10873.pdf, PTN3392 application design reference manual [4] AN10798, DisplayPort PCB Layout Guidelines [5] Intel Huron River Design Guide, Rev. 0.9, March 2010 All information provided in this document is subject to legal disclaimers. Rev. 1 — 16 December 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 17 of 19 AN11415 NXP Semiconductors PTN3355 PCB Layout Guideline, Reference Schematics and BOM 10. Legal information 10.1 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. 10.2 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product AN11415 Application note design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Evaluation products — This product is provided on an “as is” and “with all faults” basis for evaluation purposes only. NXP Semiconductors, its affiliates and their suppliers expressly disclaim all warranties, whether express, implied or statutory, including but not limited to the implied warranties of non-infringement, merchantability and fitness for a particular purpose. The entire risk as to the quality, or arising out of the use or performance, of this product remains with customer. In no event shall NXP Semiconductors, its affiliates or their suppliers be liable to customer for any special, indirect, consequential, punitive or incidental damages (including without limitation damages for loss of business, business interruption, loss of use, loss of data or information, and the like) arising out the use of or inability to use the product, whether or not based on tort (including negligence), strict liability, breach of contract, breach of warranty or any other theory, even if advised of the possibility of such damages. Notwithstanding any damages that customer might incur for any reason whatsoever (including without limitation, all damages referenced above and all direct or general damages), the entire liability of NXP Semiconductors, its affiliates and their suppliers and customer’s exclusive remedy for all of the foregoing shall be limited to actual damages incurred by customer based on reasonable reliance up to the greater of the amount actually paid by customer for the product or five dollars (US$5.00). The foregoing limitations, exclusions and disclaimers shall apply to the maximum extent permitted by applicable law, even if any remedy fails of its essential purpose. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 10.3 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 1 — 16 December 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 18 of 19 AN11415 NXP Semiconductors PTN3355 PCB Layout Guideline, Reference Schematics and BOM 11. Contents 1 2 2.1 2.2 2.3 3 3.1 3.2 4 5 6 7 8 9 10 10.1 10.2 10.3 11 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Reference designs . . . . . . . . . . . . . . . . . . . . . . . 3 ULT notebook design . . . . . . . . . . . . . . . . . . . . 3 Dongle design. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Minimum BOM design . . . . . . . . . . . . . . . . . . . 7 Buck converter. . . . . . . . . . . . . . . . . . . . . . . . . . 9 Buck converter layout guideline . . . . . . . . . . . . 9 Buck converter schematic . . . . . . . . . . . . . . . 13 DP receiver interface . . . . . . . . . . . . . . . . . . . . 13 VGA interface . . . . . . . . . . . . . . . . . . . . . . . . . . 14 PCB stack up . . . . . . . . . . . . . . . . . . . . . . . . . . 15 PTN3355 on notebook BOM . . . . . . . . . . . . . . 16 HVQFN exposed center pad solder lands . . . 17 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Legal information. . . . . . . . . . . . . . . . . . . . . . . 18 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP Semiconductors N.V. 2014. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 16 December 2014 Document identifier: AN11415