Data Sheet

CBTL12131
DisplayPort multiplexer for bidirectional video in all-in-one
computer systems
Rev. 1 — 25 February 2011
Product data sheet
1. General description
CBTL12131 is an integrated DisplayPort high-speed path switch/multiplexer that allows
all-in-one computer systems to efficiently manage path switching between different
display modes of operation. With the CBTL12131, video can be routed either from one
DisplayPort source (GPU1) to an integrated DisplayPort panel and simultaneously from a
second DisplayPort source (GPU2) to an external DisplayPort sink; or from an external
DisplayPort source to the integrated DisplayPort panel.
The device is configured as four main Ports A through D, each providing four high-speed
differential lanes for DisplayPort Main Link (ML) channels, one high-speed differential lane
for the DisplayPort AUX channel, and one single-ended lane for the HPD (Hot Plug
Detect) signal. One port (Port A) provides an additional alternate lane for the AUX
channel, in order to allow bypassing of external AC-coupling capacitors for support of the
DDC channel in case an external connected sink is a ‘++DP’ type cable adapter.
For the path supporting the ‘external source to integrated DisplayPort panel’ mode, a
programmable equalizer is provided which allows compensation for channel loss that the
external source or internal sink are unable to adequately compensate for. The equalizer is
self-biasing and is programmable to five gain-frequency curves, of which one is a flat
response and four are active equalization. The equalizer output can also be set to one of
two levels of pre-emphasis (including flat), and also differential swing level can be set to
one of two levels. All options (EQ, pre-emphasis, level) are easily programmed using
board-strapping (resistor, short or open) of three unique Quinary Input programming pins.
The CBTL12131 includes additional features that support use of the external DisplayPort
connector in both directions: either an external sink (monitor or cable adapter) or external
source (notebook computer) can be connected, while CBTL12131 configures the direction
and termination of the related signals accordingly. The port facing the external DisplayPort
connector (Port B) is equipped with dedicated sensing circuitry which detects and reports
the status of the HPD and AUX lines, to support the system controller in determining and
setting the proper connection status. The AUX channel of Port B also has switchable
integrated termination, to allow the system controller to apply the correct DC termination
in case an external DisplayPort source is connected. Moreover, it affords the system
controller the means to detect the type of system (sink, source or all-in-one computer)
connected at Port B, and apply the proper termination required in each scenario.
The CBTL12131 is powered from a single 3.3 V power supply, consumes very little
current while providing low insertion loss and low return loss high-speed differential switch
channels suitable for use in DisplayPort v1.1a interconnect. All switch and configuration
settings can be performed by board-strapping or driving simple CMOS inputs—no
software or bus configuration is required. CBTL12131 is available in a 6 mm × 6 mm
CBTL12131
NXP Semiconductors
DisplayPort multiplexer for bidirectional video
TFBGA64 package with 0.5 mm ball pitch; owing to its high level of integration and
versatility, it is eminently suitable for use in computers employing bidirectional DisplayPort
video.
2. Features and benefits
2.1 High-speed DisplayPort Main Link multiplexing
„ Switch path topologies supporting:
‹ ‘dual through’ mode (two GPUs to two displays simultaneously)
‹ ‘external source’ mode (external source to internal display)
„ Supports DisplayPort v1.1a at 2.7 Gbit/s
„ High-bandwidth analog pass-gate technology
„ Configurable equalization in ‘external source’ mode path
„ Pre-emphasis level control for equalizer in ‘external source’ mode path
„ Very low intra-pair differential skew of < 5 ps
„ Very low inter-pair skew of < 180 ps
2.2 DDC and AUX multiplexing
„ Switch path topologies supporting:
‹ ‘dual through’ mode (two GPUs to two displays)
‹ ‘external source’ mode (external source to internal display)
„ ‘AC coupling bypass’ mode on Port A (for external ++DP sink)
„ Supports DisplayPort v1.1a AUX channel
„ Supports DDC/I2C-bus multiplexing
„ High-bandwidth analog pass-gate technology
2.3 HPD channel management
„
„
„
„
Active logic management of HPD signals
Bidirectional HPD I/O for external connector (Port B)
HPD input for integrated DisplayPort display (Port D)
Two HPD outputs to both GPUs, one for internal (Port C) and one for external video
(Port A)
„ 5 V tolerance on all HPD inputs
„ 3.3 V LVTTL logic output levels for all HPD outputs
„ Internal 200 kΩ pull-down resistor on Port B and Port D HPD input ensures default
LOW when no sink is connected
2.4 Link state detection, configuration and reporting
„ Detection of DC state of AUX_P and AUX_N lines of external display (Port B)
„ Filtering of HPD interrupt pulse from external display (Port B)
„ Reporting of detected/filtered Port B AUX and HPD states via CMOS outputs (to
external system controller)
„ AUX channel bias control inputs for Port B to allow configuration as source or sink
CBTL12131
Product data sheet
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Rev. 1 — 25 February 2011
© NXP B.V. 2011. All rights reserved.
2 of 28
CBTL12131
NXP Semiconductors
DisplayPort multiplexer for bidirectional video
„ Integrated high-ohmic pull-down (4.7 MΩ) and switchable 100 kΩ and 500 kΩ
resistors for Port B AUX bias control
2.5 Equalizer
„ Programmable equalizer for channel loss compensation from Port B to Port D
(external source mode)
„ Five levels of input equalization (including flat)
„ Two levels of output pre-emphasis (including flat)
„ Two output voltage swing levels
„ Three quinary input control pins allow equalization, pre-emphasis and output voltage
swing selection by simple board strapping
2.6 General
„
„
„
„
„
Power supply 3.3 V ± 10 %
Low active mode supply current of 30 mA typical (Dual-through mode)
Active mode supply current of 120 mA typical (External source mode, EQ = on)
ESD resilience to 4 kV HBM, 1 kV CDM
Available in TFBGA64 6 mm × 6 mm package
3. Typical system configuration
CBTL12131
GPU1
PRIMARY
VIDEO
(source)
DisplayPort
dual
through mode
PORT C
PORT D
eDP
CONNECTOR
DisplayPort
external
source mode
GPU2
SECONDARY
VIDEO
(source)
DisplayPort
dual
through mode
PORT A
PORT B
INTERNAL
DISPLAY
PANEL
(sink)
DP or ++DP
EXTERNAL
DISPLAY
(sink)
DP
CONNECTOR
DisplayPort
DP
NOTEBOOK
(source)
002aae673
Fig 1.
CBTL12131 in typical system configuration
4. Ordering information
Table 1.
Ordering information
Type number
CBTL12131ET
CBTL12131
Product data sheet
Package
Name
Description
Version
TFBGA64
plastic thin fine-pitch ball grid array package; 64 balls; body 6 × 6 × 0.8 mm
SOT543-1
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Rev. 1 — 25 February 2011
© NXP B.V. 2011. All rights reserved.
3 of 28
CBTL12131
NXP Semiconductors
DisplayPort multiplexer for bidirectional video
5. Functional diagram
PATH_SEL
Port C
(faces GPU for
internal video)
Port D
(faces eDP
connector)
DDC_AUX_SEL
TST_REXT
PATH_SEL#
CBTL12131
4
ML_C_[3:0]P
4
ML_D_[3:0]P
ML_C_[3:0]N
ML_D_[3:0]N
PATH_SEL#
4
AUX_C_P
AUX_D_P
AUX_C_N
AUX_D_N
HPD_C
HPD_D
LV5
PL5
EQ5
PATH_SEL = 0: disabled
EQ PATH_SEL = 1: enabled
PATH_SEL
RPD_HPD
200 kΩ
PATH_SEL#
and HPD_B_FLT
4
ML_A_[3:0]P
4
ML_B_[3:0]P
ML_A_[3:0]N
ML_B_[3:0]N
DDC_AUX_SEL#
and PATH_SEL#
and HPD_B_FLT
100 kΩ
500 kΩ
+
RAUX100_P
RAUX500_P
AUX_B_P
AUX_A_P
AUX_A_N
AUX_B_N
100 kΩ
+
RAUX100_N
RAUX4M7N
4.7 MΩ
DDC_AUX_SEL
and PATH_SEL#
and HPD_B_FLT
DDC_A_0
RAUX4M7P
4.7 MΩ
RPD_HPD
200 kΩ
DDC_A_1
PATH_SEL = 0:
High-Z
PATH_SEL = 1:
active
HPD_B
HPD_A
AUX
TERMINATION
CONFIGURATION
AUX_TERM_SRC
AUX_TERM_SNK
VDD
GND
AUX_B_P_STATE
HPD
FILTER
AUX
DETECTION
AUX_B_N_STATE
4
3
HPD_B_FLT
002aae674
Port A
(faces GPU for
external video)
Port B
(faces external DP
connector)
(1) Switch is in ON (conducting) position when qualifier = TRUE.
Fig 2.
Functional diagram
CBTL12131
Product data sheet
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Rev. 1 — 25 February 2011
© NXP B.V. 2011. All rights reserved.
4 of 28
CBTL12131
NXP Semiconductors
DisplayPort multiplexer for bidirectional video
6. Pinning information
6.1 Pinning
ball A1
index area
CBTL12131ET
1 2 3 4 5 6 7 8 9 10
A
B
C
D
E
F
G
H
J
K
002aae675
Transparent top view
Fig 3.
Pin configuration for TFBGA64
Port B
(faces external DP connector)
Port D
(faces eDP connector)
1
2
3
4
5
6
7
8
9
10
A
ML_D_0P
ML_D_1P
ML_D_2P
ML_D_3P
HPD_D
HPD_B
ML_B_0P
ML_B_1P
ML_B_2P
ML_B_3P
B
ML_D_0N
ML_D_1N
ML_D_2N
ML_D_3N
VDD
GND
ML_B_0N
ML_B_1N
ML_B_2N
ML_B_3N
C
AUX_D_P
AUX_D_N
AUX_B_N
AUX_B_P
D
AUX_B_
P_STATE
AUX_B_
N_STATE
PL5
DDC_
AUX_SEL
E
PATH_
SEL
VDD
VDD
EQ5
F
TST_
REXT
GND
LV5
HPD_B_
FLT
G
AUX_
TERM_
SRC
AUX_
TERM_
SNK
DDC_A_1
DDC_A_0
H
AUX_C_P
AUX_C_N
AUX_A_N
AUX_A_P
J
ML_C_0N
ML_C_1N
ML_C_2N
ML_C_3N
VDD
GND
ML_A_0N
ML_A_1N
ML_A_2N
ML_A_3N
K
ML_C_0P
ML_C_1P
ML_C_2P
ML_C_3P
HPD_C
HPD_A
ML_A_0P
ML_A_1P
ML_A_2P
ML_A_3P
Transparent top view
002aae676
Port C
(faces GPU for internal video)
Fig 4.
Port A
(faces GPU for external video)
Ball mapping for TFBGA64
CBTL12131
Product data sheet
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Rev. 1 — 25 February 2011
© NXP B.V. 2011. All rights reserved.
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CBTL12131
NXP Semiconductors
DisplayPort multiplexer for bidirectional video
6.2 Pin description
Table 2.
Pin description
Symbol
Pin
Type
Description
PATH_SEL
E1
3.3 V low-voltage CMOS Input to set the path configuration of the CBTL12131. When LOW,
single-ended input
Ports A and B are mutually connected, as well as Ports C and D.
When HIGH, Port B is connected to Port D.
DDC_AUX_SEL
D10
3.3 V low-voltage CMOS Input to select between DDC and AUX terminals for Port A. When
single-ended input
HIGH, the DDC_A_P and DDC_A_N terminals are connected to their
respective AUX_B_P and AUX_B_N terminals on Port B. When
LOW, the AUX_A_P and AUX_A_N terminals are connected to their
respective AUX_B_P and AUX_B_N terminals on Port B.
EQ5
E10
3.3 V low-voltage CMOS Equalizer setting input pin. This pin can be board-strapped to one of
quinary input
five decode values: short to GND, resistor to GND, open-circuit,
resistor to VDD, short to VDD. See Table 7 for truth table.
PL5
D9
3.3 V low-voltage CMOS Pre-emphasis level setting input pin. This pin can be board-strapped
quinary input
to one of five decode values: short to GND, resistor to GND,
open-circuit, resistor to VDD, short to VDD. See Table 8 for truth
table.
LV5
F9
3.3 V low-voltage CMOS Output differential swing setting input pin. This pin can be
quinary input
board-strapped to one of five decode values: short to GND, resistor
to GND, open-circuit, resistor to VDD, short to VDD. See Table 9 for
truth table.
TST_REXT
F1
3.3 V low-voltage CMOS
single-ended input with
current sensing analog
input
Control inputs
Test pin for NXP use, combined with external current sensing
function. Should be tied to ground via an external resistor of value
10 kΩ ± 1 %. This pin must not be left open-circuit to avoid possible
erroneous engagement of test mode in normal operation.
AUX_TERM_SRC G1
3.3 V low-voltage CMOS Input to enable source-type termination on the Port B AUX pair.
single-ended input
When HIGH, 100 kΩ termination resistors are applied to the Port B
AUX pair. When LOW, the termination resistors will be disabled
(high-impedance).
AUX_TERM_SNK G2
3.3 V low-voltage CMOS Input to enable sink-style termination on the Port B AUX pair. When
single-ended input
HIGH, a 500 kΩ termination resistor to VDD is applied to AUX_B_P.
When LOW, the termination resistor will be disabled
(high-impedance).
Status outputs
HPD_B_FLT
F10
3.3 V low-voltage CMOS This outputs a filtered version of HPD_B.
single-ended output
AUX_B_P_STATE D1
3.3 V low-voltage CMOS DC state (HIGH or LOW) of AUX_B_P signal.
single-ended output
AUX_B_N_STATE D2
3.3 V low-voltage CMOS DC state (HIGH or LOW) of AUX_B_N signal.
single-ended output
CBTL12131
Product data sheet
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Rev. 1 — 25 February 2011
© NXP B.V. 2011. All rights reserved.
6 of 28
CBTL12131
NXP Semiconductors
DisplayPort multiplexer for bidirectional video
Table 2.
Pin description …continued
Symbol
Pin
Type
Description
ML_A_0P
K7
differential port terminal
ML_A_0N
J7
differential port terminal
Four high-speed differential pairs for DisplayPort Main Link signals,
Port A. Designated as port facing the GPU for external video. Port A
will be exclusively connected to Port B when PATH_SEL = LOW, and
will be high-impedance when PATH_SEL = HIGH.
Port A terminals
ML_A_1P
K8
differential port terminal
ML_A_1N
J8
differential port terminal
ML_A_2P
K9
differential port terminal
ML_A_2N
J9
differential port terminal
ML_A_3P
K10
differential port terminal
ML_A_3N
J10
differential port terminal
AUX_A_P
H10
differential port terminal
AUX_A_N
H9
differential port terminal
DDC_A_0
G10
differential port terminal
DDC_A_1
G9
differential port terminal
HPD_A
K6
3.3 V LVTTL
single-ended output
3.3 V LVTTL HPD output for Port A. When PATH_SEL = LOW, this
output follows the state of HPD_B (from external DP or ++DP sink).
When PATH_SEL = HIGH, this output is always LOW.
ML_B_0P
A7
differential port terminal
ML_B_0N
B7
differential port terminal
ML_B_1P
A8
differential port terminal
ML_B_1N
B8
differential port terminal
Four high-speed differential pairs for DisplayPort Main Link signals,
Port B. Designated as port facing the external DP connector. Port B
will be exclusively connected to Port A when PATH_SEL = LOW and
HPD_B_FLT = HIGH, and will be exclusively connected to Port D
when PATH_SEL = HIGH. When PATH_SEL = HIGH, the signal
ordering and association to Port D ML signals is automatically
corrected by internal routing, to map to the DP connector's inverted
signal ordering for a DP sink-side connector.
High-speed differential pair for DisplayPort AUX signals, Port A.
These terminals are active when DDC_AUX_SEL = LOW only;
when DDC_AUX_SEL = HIGH, these are high-impedance.
Port A terminal intended for AUX AC coupling capacitor bypass.
These terminals are active when DDC_AUX_SEL = HIGH only;
when DDC_AUX_SEL = LOW, these are high-impedance.
Port B terminals
ML_B_2P
A9
differential port terminal
ML_B_2N
B9
differential port terminal
ML_B_3P
A10
differential port terminal
ML_B_3N
B10
differential port terminal
AUX_B_P
C10
differential port terminal
AUX_B_N
C9
differential port terminal
HPD_B
A6
3.3 V bidirectional
LVTTL I/O with high-Z
state
CBTL12131
Product data sheet
High-speed differential pair for DisplayPort AUX signals, Port B.
HPD input with 5 V tolerance or output for Port B, to be connected to
the external DP connector. When PATH_SEL = LOW, HPD_B is
configured as input (from external DP or ++DP sink). When
PATH_SEL = HIGH, HPD_B is configured as output and follows the
state of HPD_D (from internal sink), to be connected via DP
connector to an external DP source.
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Rev. 1 — 25 February 2011
© NXP B.V. 2011. All rights reserved.
7 of 28
CBTL12131
NXP Semiconductors
DisplayPort multiplexer for bidirectional video
Table 2.
Pin description …continued
Symbol
Pin
Type
Description
ML_C_0P
K1
differential port terminal
ML_C_0N
J1
differential port terminal
Four high-speed differential pairs for DisplayPort Main Link signals,
Port C. Designated as port facing the GPU for internal video. Port C
will be exclusively connected to Port D when PATH_SEL = LOW, and
will be high-impedance when PATH_SEL = HIGH.
Port C terminals
ML_C_1P
K2
differential port terminal
ML_C_1N
J2
differential port terminal
ML_C_2P
K3
differential port terminal
ML_C_2N
J3
differential port terminal
ML_C_3P
K4
differential port terminal
ML_C_3N
J4
differential port terminal
AUX_C_P
H1
differential port terminal
AUX_C_N
H2
differential port terminal
HPD_C
K5
3.3 V LVTTL
single-ended output
3.3 V LVTTL HPD output for Port C. When PATH_SEL = LOW, this
output follows the state of HPD_D (from internal sink). When
PATH_SEL = HIGH, this output is always LOW.
ML_D_0P
A1
differential port terminal
ML_D_0N
B1
differential port terminal
ML_D_1P
A2
differential port terminal
ML_D_1N
B2
differential port terminal
Four high-speed differential pairs for DisplayPort Main Link signals,
Port D. Designated as port facing the internal eDP display module
connector. Port D will be exclusively connected to Port C when
PATH_SEL = LOW, and will be exclusively connected to Port B when
PATH_SEL = HIGH.
High-speed differential pair for DisplayPort AUX signals, Port C.
Port D terminals
ML_D_2P
A3
differential port terminal
ML_D_2N
B3
differential port terminal
ML_D_3P
A4
differential port terminal
ML_D_3N
B4
differential port terminal
AUX_D_P
C1
differential port terminal
AUX_D_N
C2
differential port terminal
HPD_D
A5
3.3 V LVTTL
single-ended input
5 V tolerant HPD input for Port D, to be connected to the internal
sink.
High-speed differential pair for DisplayPort AUX signals, Port D.
Supply and ground
VDD
B5,
E2,
E9,
J5
power supply
3.3 V power supply pins.
GND
B6,
F2,
J6
ground
Ground pins.
CBTL12131
Product data sheet
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Rev. 1 — 25 February 2011
© NXP B.V. 2011. All rights reserved.
8 of 28
CBTL12131
NXP Semiconductors
DisplayPort multiplexer for bidirectional video
7. Functional description
7.1 General
The CBTL12131 is a high-bandwidth DisplayPort channel switching device designed for
use in all-in-one computers. It contains high-bandwidth switches arranged between four
Ports (A through D) to allow two different channel topologies, where each channel
comprises a Main Link (ML), AUX and HPD path for comprehensive DisplayPort channel
switching. One can select between two basic configurations: either Ports A and C are
connected to Ports B and D respectively, or Port B is connected to Port D while Ports A
and C are high-impedance. In addition, the CBTL12131 includes circuitry to assist in
detection and configuration of Port B designated as the port facing the external
DisplayPort connector. This section describes these functional blocks in detail.
7.2 Main Link DisplayPort switches/multiplexers
The Main Link path topology provides for four differential pairs in each Port, and an
equalizer for each differential pair in the path from Port B to Port D, as shown in Figure 5.
The Main Link switches are operated by CMOS input PATH_SEL and further qualified by
the state of internally derived signal HPD_B_FLT (see Section 7.6 for details). When
PATH_SEL is LOW, Ports C and D are mutually connected, Ports A and B are mutually
connected only when HPD_B_FLT is HIGH, and the equalizer is turned off (isolating).
When PATH_SEL is HIGH, Ports A and C are disconnected (high-impedance) and Port D
is connected to Port B via the equalizer. The equalizer can by bypassed or configured by
quinary input EQ5 to any of five equalizer settings (including a flat response) depending
on specific application conditions. For details on the Equalizer function, please refer to
Section 7.7.
PATH_SEL = 0: pass
PATH_SEL = 1: off
ML port C
ML port D
LV5
PL5
EQ5
EQ
EQ output disabled/no load when PATH_SEL = 0
ML port A
ML port B
PATH_SEL = 0 and
HPD_B_FLT = 1: pass
else: off
Fig 5.
002aae677
Main Link channel topology
Table 3.
Main Link channel configuration
Legend: high-Z = isolating, high-impedance; ACT = active, low-impedance.
Inputs
Channels
Comment
PATH_SEL
HPD_B_FLT
Port C - Port D
Port A - Port B
Port B - Port D
0
0
ACT
high-Z
high-Z
Normal mode; internal display only
0
1
ACT
ACT
high-Z
Normal mode with dual display
1
0
high-Z
high-Z
ACT
External source mode with internal
display not yet asserting HPD
1
1
high-Z
high-Z
ACT
External source mode with internal
display asserting HPD
CBTL12131
Product data sheet
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Rev. 1 — 25 February 2011
© NXP B.V. 2011. All rights reserved.
9 of 28
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NXP Semiconductors
CBTL12131
Product data sheet
Table 4.
Main Link signal mappings
Legend: high-Z = isolating, high-impedance; ACT = active, low-impedance; EQ = active, equalized/re-driven.
Inputs
Channels
PATH_SEL HPD_B_FLT
0
1
X
Port B - Port D[1]
ML_C_0P
ACT
ML_D_0P
ML_A_0P
high-Z
ML_B_0P
ML_B_0P
high-Z
ML_D_3N
ML_C_0N
ACT
ML_D_0N
ML_A_0N
high-Z
ML_B_0N
ML_B_0N
high-Z
ML_D_3P
Comment (all other ports
shall be mutually isolated)
ML_C_1P
ACT
ML_D_1P
ML_A_1P
high-Z
ML_B_1P
ML_B_1P
high-Z
ML_D_2N
ML_C_1N
ACT
ML_D_1N
ML_A_1N
high-Z
ML_B_1N
ML_B_1N
high-Z
ML_C_2P
ACT
ML_D_2P
ML_A_2P
high-Z
ML_B_2P
ML_B_2P
high-Z
ML_D_2P Normal mode;
ML_D_1N internal display only
ML_C_2N
ACT
ML_D_2N
ML_A_2N
high-Z
ML_B_2N
ML_B_2N
high-Z
ML_D_1P
ML_C_3P
ACT
ML_D_3P
ML_A_3P
high-Z
ML_B_3P
ML_B_3P
high-Z
ML_D_0N
ML_C_3N
ACT
ML_D_3N
ML_A_3N
high-Z
ML_B_3N
ML_B_3N
high-Z
ML_D_0P
ML_C_0P
ACT
ML_D_0P
ML_A_0P
ACT
ML_B_0P
ML_B_0P
high-Z
ML_D_3N
ML_C_0N
ACT
ML_D_0N
ML_A_0N
ACT
ML_B_0N
ML_B_0N
high-Z
ML_D_3P
ML_C_1P
ACT
ML_D_1P
ML_A_1P
ACT
ML_B_1P
ML_B_1P
high-Z
ML_D_2N
ML_C_1N
ACT
ML_D_1N
ML_A_1N
ACT
ML_B_1N
ML_B_1N
high-Z
ML_C_2P
ACT
ML_D_2P
ML_A_2P
ACT
ML_B_2P
ML_B_2P
high-Z
ML_D_2P Normal mode with
ML_D_1N dual display
ML_C_2N
ACT
ML_D_2N
ML_A_2N
ACT
ML_B_2N
ML_B_2N
high-Z
ML_D_1P
ML_C_3P
ACT
ML_D_3P
ML_A_3P
ACT
ML_B_3P
ML_B_3P
high-Z
ML_D_0N
ML_C_3N
ACT
ML_D_3N
ML_A_3N
ACT
ML_B_3N
ML_B_3N
high-Z
ML_D_0P
ML_C_0P
high-Z
ML_D_0P
ML_A_0P
high-Z
ML_B_0P
ML_B_0P
EQ
ML_D_3N
ML_C_0N
high-Z
ML_D_0N
ML_A_0N
high-Z
ML_B_0N
ML_B_0N
EQ
ML_D_3P
ML_C_1P
high-Z
ML_D_1P
ML_A_1P
high-Z
ML_B_1P
ML_B_1P
EQ
ML_D_2N
ML_C_1N
high-Z
ML_D_1N
ML_A_1N
high-Z
ML_B_1N
ML_B_1N
EQ
ML_D_2P
ML_C_2P
high-Z
ML_D_2P
ML_A_2P
high-Z
ML_B_2P
ML_B_2P
EQ
ML_D_1N
ML_C_2N
high-Z
ML_D_2N
ML_A_2N
high-Z
ML_B_2N
ML_B_2N
EQ
ML_D_1P
ML_C_3P
high-Z
ML_D_3P
ML_A_3P
high-Z
ML_B_3P
ML_B_3P
EQ
ML_D_0N
ML_C_3N
high-Z
ML_D_3N
ML_A_3N
high-Z
ML_B_3N
ML_B_3N
EQ
ML_D_0P
External source mode
Remark: Signal ordering between Port B and Port D is inverted in order to achieve proper signal-to-pin mapping in accordance with sink side status of connector at Port B.
CBTL12131
10 of 28
© NXP B.V. 2011. All rights reserved.
[1]
1
Port A - Port B
DisplayPort multiplexer for bidirectional video
Rev. 1 — 25 February 2011
All information provided in this document is subject to legal disclaimers.
0
0
Port C - Port D
CBTL12131
NXP Semiconductors
DisplayPort multiplexer for bidirectional video
7.3 AUX and DDC switches/multiplexers
For all ports except Port A, only a single pair of signal lines is provided. The path
configuration for the AUX/DDC channels follows that of the Main Link: when
PATH_SEL = LOW, Ports C and D are connected; when PATH_SEL = LOW and
HPD_B_FLT = HIGH, also Ports A and B are connected; when PATH_SEL = HIGH,
Port D is connected to Port B, and Ports A and C are isolated (see Figure 6).
PATH_SEL = 0: pass
PATH_SEL = 1: off
AUX_C
HPD_B_FLT = 1 and PATH_SEL = 0 and DDC_AUX_SEL = 0: pass
else: off
AUX_D
PATH_SEL = 0: off
PATH_SEL = 1: pass
AUX_A
AUX_B
select between
AUX and DDC
DDC_A
HPD_B_FLT = 1 and PATH_SEL = 0 and DDC_AUX_SEL = 1: pass
else: off
Fig 6.
002aae678
AUX and DDC channel topology
Port A additionally provides a second pair of signal lines, to allow bypassing of external
AC-coupling capacitors (normally placed in series with the AUX channel) in the case when
an external ++DP cable adapter is detected, and therefore a DC path needs to be
provided from the external DP connector’s AUX_P and AUX_N lines, in order to support
DDC communication across those lines between the External Graphics GPU (facing
Port A) and the external ++DP cable adapter. Selection between the DDC and AUX
channels of Port A is determined by the input DDC_AUX_SEL: when
DDC_AUX_SEL = LOW, the active channel is AUX_A; when DDC_AUX_SEL = HIGH,
the active channel is DDC_A. Typically, DDC_AUX_SEL is driven by a qualified version of
the DP ‘Cable Detect’ signal (pin 4 of a miniDP connector or pin 13 of a normal DP
connector) and will be HIGH when such a cable adaptor is connected and powered.
CBTL12131
Product data sheet
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Rev. 1 — 25 February 2011
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11 of 28
CBTL12131
NXP Semiconductors
DisplayPort multiplexer for bidirectional video
Table 5.
AUX/DDC channel configuration
Legend: high-Z = isolating, high-impedance; ACT = active, low-impedance.
Inputs
Channel
PATH_SEL HPD_B_FLT DDC_AUX_SEL Port C - Port D
Comment
Port A - Port B
Port B - Port D (all other ports
shall be mutually
AUX_A DDC_A
isolated)
0
0
X
ACT
high-Z
high-Z
high-Z
Normal mode;
internal display only
0
1
0
ACT
ACT
high-Z
high-Z
Normal mode with
dual display
0
1
1
ACT
high-Z
ACT
high-Z
Normal mode with
dual display using
++DP display
adaptor
1
0
X
high-Z
high-Z
high-Z
ACT
External source
mode with internal
display not yet
asserting HPD
1
1
X
high-Z
high-Z
high-Z
ACT
External source
mode with internal
display asserting
HPD
7.4 HPD signal path
The HPD signal path, unlike the Main Link and AUX/DDC paths, uses active LVTTL logic
rather than passive switching. As shown in Figure 7, the topology follows that of the
Main Link and AUX channels but with the signal direction in reverse direction (since the
HPD signal direction is always from sink to source). When PATH_SEL is LOW, output
HPD_C follows and re-drives input HPD_D and similarly HPD_A follows the logic state of
input HPD_B. An integrated 200 kΩ resistor (RPD_HPD) between HPD_B and GND
ensures a logic LOW when no device is connected to Port B. When PATH_SEL is HIGH,
HPD_B becomes an output and follows the logic state of HPD_D. Please also refer to
Section 7.6 for specific details on the HPD filtering function.
PATH_SEL = 0: active
PATH_SEL = 1: LOW
HPD_C
HPD_D
RPD_HPD
PATH_SEL = 0: high-Z
PATH_SEL = 1: active
HPD_A
HPD_B
RPD_HPD
002aaf999
Fig 7.
CBTL12131
Product data sheet
HPD channel topology
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CBTL12131
NXP Semiconductors
DisplayPort multiplexer for bidirectional video
Table 6.
HPD channel configuration
Inputs
Outputs
Comment
PATH_SEL
HPD_B
HPD_D
HPD_A
HPD_B
HPD_B_FLT[1]
0
0
0
0
high-Z
0
0
Normal mode; internal display
not (yet) asserting HPD
0
0
1
0
high-Z
0
1
Normal mode; internal display
asserting HPD
0
1
0
1
high-Z
1
0
Normal mode but unexpected
condition; internal display not
asserting HPD during normal
operation
0
1
1
1
high-Z
1
1
Normal mode; with external sink
asserting HPD
1
n/a
0
0
0
0
0
External source mode with
internal display not (yet)
asserting HPD
1
n/a
1
0
1
1
0
External source mode with
internal display asserting HPD
[1]
HPD_C
Steady-state is shown only. A HIGH-to-LOW transition will be filtered (~4 ms delay).
7.5 AUX logic state detection
CBTL12131 includes a helpful function to determine the DC state of the AUX_B_P and
AUX_B_N pins thereby aiding in the detection of devices connected to the external DP
connector. The DC state of these pins is output on pins AUX_B_P_STATE and
AUX_B_N_STATE respectively, after the 1 Mbit/s (typ) Manchester-encoded bitstream is
removed by filtering.
7.6 HPD logic state detection
To further aid in detection of externally connected devices on Port B, the HPD_B_FLT pin
outputs a filtered version of pin HPD_B. The filtering function suppresses the 1 ms (typ)
LOW interrupt pulse from a DisplayPort sink, thereby avoiding a false disconnect
detection. Only a LOW pulse greater than 4 ms will result in a LOW output on
HPD_B_FLT.
7.7 Equalizer
The Equalizer function equalizes the signal on the Main Link channel of Port B and
re-drives them to Port D and ultimately to the internal display panel.
The Equalizer is only active when PATH_SEL is HIGH. When PATH_SEL is LOW, the
equalizer is effectively disabled and presents minimum parasitic load to the Main Link
channels.
The Equalizer has configurable Equalization (EQ) settings for its input (Port B side), which
can be set to one of five options by quinary input pin EQ5. See Table 7 for programming
options.
CBTL12131
Product data sheet
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Rev. 1 — 25 February 2011
© NXP B.V. 2011. All rights reserved.
13 of 28
CBTL12131
NXP Semiconductors
DisplayPort multiplexer for bidirectional video
Table 7.
Equalizer settings
Inputs
Quinary notation
Equalizer mode (see Figure 8)
EQ5
short to GND
05
0 dB
10 kΩ resistor to GND
15
2 dB
open-circuit
25
3.5 dB
10 kΩ resistor to VDD
35
6.5 dB
short to VDD
45
9 dB
002aae977
12
Gain
(dB)
EQ9.0
EQ6.5
EQ3.5
EQ2.0
EQ0.0
8
4
0
−4
−8
1
10
102
103
104
f (MHz)
Fig 8.
Equalizer gain versus frequency
The Equalizer also has two different levels of Pre-emphasis for its output (Port D side),
which can be set by quinary input pin PL5; as well as two different output differential swing
levels, which can be set by quinary input pin LV5. See Table 8 and Table 9 for
programming options.
Table 8.
Pre-emphasis settings
Inputs
Quinary notation
Output mode
short to GND
05
0 dB
10 kΩ resistor to GND
15
3.5 dB[1]
PL5
open-circuit
25
reserved
10 kΩ resistor to VDD
35
reserved
short to VDD
45
reserved
[1]
CBTL12131
Product data sheet
Only available with 400 mV output voltage swing setting (see Table 9).
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14 of 28
CBTL12131
NXP Semiconductors
DisplayPort multiplexer for bidirectional video
Table 9.
Output voltage swing settings
Inputs
Quinary notation
Output mode
LV5
short to GND
05
400 mV
10 kΩ resistor to GND
15
600 mV[1]]
open-circuit
25
reserved
10 kΩ resistor to VDD
35
reserved
short to VDD
45
reserved
[1]
CBTL12131
Product data sheet
600 mV level setting overrides pre-emphasis settings.
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© NXP B.V. 2011. All rights reserved.
15 of 28
CBTL12131
NXP Semiconductors
DisplayPort multiplexer for bidirectional video
7.8 AUX channel bias and termination
The AUX lines of Port B can be biased and terminated in accordance with the DisplayPort
Interoperability Guidelines in accordance with the configuration for either a sink or source,
depending on which is required. The control input for the termination and bias are CMOS
inputs AUX_TERM_SRC and AUX_TERM_SNK.
Together with the state of PATH_SEL and HPD_B_FLT (the filtered, steady state of
HPD_B), these signals allow a detection scheme by which the system controller can
resolve different connection scenarios of the external DisplayPort connector at Port B:
• Nothing is connected
• An external source is connected
• An external sink is connected (either with or without source detection being performed
by the sink)
• An external, second all-in-one system (using a topology similar or equivalent to
CBTL12131)
At first connection time, the latter scenario may appear identical to the first. In this case,
AUX_TERM_SNK (which applies a 500 kΩ pull-up on AUX_B_P line provided) can be
toggled HIGH in order to allow the other system to detect a connected sink, and configure
itself accordingly as a source.
Using AUX_TERM_SRC, the system controller is able to check whether the attached
device is a sink which is not asserting HPD (as some sinks will employ source detection
for power saving reasons). By applying the integrated 100 kΩ pull-up and pull-down
resistors, the attached sink will detect a source and assert its HDP when it is ready.
When HPD_B_FLT is HIGH, this means the attached device is asserting HPD and
CBTL12131 will activate its source type 100 kΩ termination resistors.
When PATH_SEL is HIGH, this means the internal DisplayPort sink (embedded panel) is
active, and its 1 MΩ termination resistors will apply the correct AUX bias to represent a
sink device.
In the default condition (PATH_SEL, HPD_B_FLT and AUX_TERM_SNK/SRC are all
LOW), 4.7 MΩ pull-down resistors are applied to the AUX_B pair, in order to avoid floating
conditions in case two similar systems are connected together.
When both AUX_TERM_SRC and AUX_TERM_SNK are HIGH, all integrated termination
resistors will be de-activated. For correct system operation, the system controller needs to
guarantee that AUX_TERM_SRC and AUX_TERM_SNK are never HIGH at the same
time, unless the external termination resistors are implemented.
CBTL12131
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 25 February 2011
© NXP B.V. 2011. All rights reserved.
16 of 28
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NXP Semiconductors
CBTL12131
Product data sheet
Table 10. AUX channel bias and termination
Legend: high-Z = isolating, high-impedance; ACT = active, nominal-impedance.
Inputs
PATH_SEL
HPD_B_FLT
AUX terminations
Comments
RAUX100N
RAUX500P
RAUX4M7P
RAUX4M7N
0
0
0
0
high-Z
high-Z
high-Z
ACT
ACT
Nothing connected.
0
0
0
1
high-Z
high-Z
ACT
high-Z
ACT
Override in scenario of two
systems both using
CBTL12131 connected
together.[2]
0
0
1
0
ACT
ACT
high-Z
high-Z
high-Z
Allow sink to perform source
detection.[3]
0
0
1
1
high-Z
high-Z
high-Z
high-Z
high-Z
[4][5]
0
1
0
0
ACT
ACT
high-Z
high-Z
high-Z
Dual display mode normal condition.
0
1
0
1
ACT
ACT
high-Z
high-Z
high-Z
Not an expected condition.
Already in dual display mode
with source termination
active.
0
1
1
0
ACT
ACT
high-Z
high-Z
high-Z
Not an expected condition.
Already in dual display mode
with source termination
active.
0
1
1
1
high-Z
high-Z
high-Z
high-Z
high-Z
[4][5]
1
X
X
X
high-Z
high-Z
high-Z
high-Z
high-Z
Internal display expected to
exhibit 1 MΩ pull-up and
pull-down, hence no
termination needed.
HPD_B_FLT is an internally derived signal, not an input to CBTL12131. HPD_B_FLT will follow input HPD_B.
[2]
System controller will assert AUX_TERM_SNK HIGH when user action prompts a ‘toggle’, hence system should configure itself as a sink.
[3]
System controller will assert AUX_TERM_SRC HIGH when it has determined that a Sink is connected, hence system should configure itself as a source.
[4]
System controller should guarantee that (AUX_TERM_SNK & AUX_TERM_SRC) is never TRUE for normal operation unless the external termination resistors are used.
[5]
AUX_TERM_SRC and AUX_TERM_SNK = TRUE are used as a disable mechanism for the integrated AUX bias network when external termination resistors are used.
CBTL12131
17 of 28
© NXP B.V. 2011. All rights reserved.
[1]
DisplayPort multiplexer for bidirectional video
Rev. 1 — 25 February 2011
All information provided in this document is subject to legal disclaimers.
AUX_TERM
_SNK
RAUX100P
[1]
AUX_TERM
_SRC
CBTL12131
NXP Semiconductors
DisplayPort multiplexer for bidirectional video
7.9 TST_REXT function
Pin TST_REXT has a dual function. In normal operation, this pin should be tied to analog
GND externally via a 10 kΩ, 1 % accuracy resistor. The external resistor functions as a
reference to establish accurate internal current sources for the EQ output stage. The
second function of this pin is to put CBTL12131 in test mode by driving it HIGH. This test
mode is for internal use only and has no use in normal operation.
8. Limiting values
Table 11. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
VDD
supply voltage
Conditions
Tcase
case temperature
for operation within
specification
VESD
electrostatic discharge
voltage
HBM
CDM
Min
Max
Unit
−0.3
+4.6
V
−40
+85
°C
[1]
-
4000
V
[2]
-
1000
V
[1]
Human Body Model: ANSI/EOS/ESD-S5.1-1994, standard for ESD sensitivity testing. Human Body Model Component level; Electrostatic Discharge Association, Rome, NY, USA.
[2]
Charged-Device Model: ANSI/EOS/ESD-S5.3-1-1999, standard for ESD sensitivity testing,
Charged-Device Model - Component level; Electrostatic Discharge Association, Rome, NY, USA.
9. Recommended operating conditions
CBTL12131
Product data sheet
Table 12.
Operating conditions
Symbol
Parameter
VDD
Conditions
Min
Typ
Max
Unit
supply voltage
3.0
3.3
3.6
V
VI
input voltage
-
-
3.6
V
HPD inputs
-
-
5.5
V
Tamb
ambient temperature
operating in free air
−40
-
+85
°C
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18 of 28
CBTL12131
NXP Semiconductors
DisplayPort multiplexer for bidirectional video
10. Characteristics
10.1 General characteristics
Table 13.
General characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
IDD
supply current
PATH_SEL = 0
-
30
40
mA
PATH_SEL = 1
-
120
150
mA
tstartup
start-up time
supply voltage valid to channel specified
operating characteristics
-
-
10
μs
trcfg
reconfiguration time
PATH_SEL state change to channel
specified operating characteristics
-
-
10
μs
10.2 DisplayPort channel characteristics
Table 14.
DisplayPort channel characteristics
Symbol
Parameter
Min
Typ
Max
Unit
VI
input voltage
Conditions
−0.3
-
+2.6
V
VIC
common-mode input voltage
0
-
2.0
V
VID
differential input voltage
-
-
+1.2
V
DDIL
differential insertion loss
channel is on; 0 Hz ≤ f ≤ 1.0 GHz
−2.0
−1.5
-
dB
channel is on; f = 2.5 GHz
−3.5
-
-
dB
channel is off; 0 Hz ≤ f ≤ 3.0 GHz
-
-
−30
dB
DDRL
differential return loss
channel is on; 0 Hz ≤ f ≤ 1.0 GHz
-
-
−10
dB
DDNEXT
differential near-end crosstalk
adjacent channels are on;
0 Hz ≤ f ≤ 1.0 GHz
-
-
−30
dB
B
bandwidth
−3.0 dB intercept
-
2.6
-
GHz
tPD
propagation delay
from left-side port to right-side
port or vice versa; PATH_SEL = 0
-
-
180
ps
from Port B to Port D;
PATH_SEL = 1
-
-
2
ms
tsk(dif)
differential skew time
intra-pair
-
-
5
ps
tsk
skew time
inter-pair
-
-
180
ps
VTX_DIFFp-p
differential peak-to-peak output Port D output; PATH_SEL = 1
voltage
LV5 short to GND
-
400
-
mV
LV5 10 kΩ resistor to GND
-
600
-
mV
PL5 short to GND
-
0
-
dB
PL5 10 kΩ resistor to GND
-
3.5
-
dB
VTX_PREEMP_RATIO
CBTL12131
Product data sheet
pre-emphasis ratio
Port D output; PATH_SEL = 1
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19 of 28
CBTL12131
NXP Semiconductors
DisplayPort multiplexer for bidirectional video
10.3 AUX and DDC ports
Table 15.
AUX and DDC port characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VI
input voltage
DDC
−0.3
-
+3.6
V
AUX; single-ended; Figure 9
0.16
-
0.7
V
αAUX
AUX attenuation
with 100 Ω termination
-
2
3.5
dB
Vbias(DC)
bias voltage (DC)
AUX_P; Figure 9
0
-
2.0
V
1.5
-
3.6
V
-
180
-
ps
AUX_N; Figure 9
propagation delay
tPD
[1]
between connected ports
[1]
Time from DDC/AUX input changing state to AUX output changing state. Includes DDC/AUX rise/fall time.
VI
AUX_P, AUX_N
Vbias(DC)
GND (0 V)
Fig 9.
002aaf475
AUX_P and AUX_N input voltage waveform
10.4 HPD input, HPD output
Table 16.
HPD input and output characteristics
Symbol
Parameter
VI
tPD
Conditions
Min
Typ
Max
Unit
input voltage
[1]
−0.3
-
3.6
V
propagation delay
[2]
-
40
60
ns
between connected ports
[1]
Low-speed input changes state on cable plug/unplug.
[2]
Time from HPD_SINK changing state to HPD changing state. Includes HPD rise/fall time.
10.5 Control inputs
Table 17.
Control input characteristics
Symbol
Parameter
Min
Typ
Max
Unit
VIH
HIGH-level input voltage CMOS inputs
Conditions
2.0
-
3.6
V
VIL
LOW-level input voltage
CMOS inputs
0
-
0.8
V
ILI
input leakage current
measured with input at
VIH(max) and VIL(min)
-
-
10
μA
Min
Typ
Max
Unit
2.5
-
-
V
10.6 Status outputs
CBTL12131
Product data sheet
Table 18.
Status output characteristics
Symbol
Parameter
VOH
HIGH-level output voltage CMOS outputs
VOL
LOW-level output voltage
CMOS outputs
0
-
0.2
V
tt
transition time
10 % to 90 %
1
-
60
ns
Conditions
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CBTL12131
NXP Semiconductors
DisplayPort multiplexer for bidirectional video
11. Package outline
TFBGA64: plastic thin fine-pitch ball grid array package; 64 balls; body 6 x 6 x 0.8 mm
D
SOT543-1
A
B
ball A1
index area
A
A2
E
A1
detail X
C
e1
e
1/2
∅v M
e b
∅w M
y
y1 C
C A B
C
K
J
H
e
G
F
e2
E
1/2
D
e
C
B
A
ball A1
index area
1
2
3
4
5
6
7
8
9 10
X
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
mm
A
max.
A1
A2
b
D
E
e
e1
e2
v
w
y
y1
1.1
0.25
0.15
0.85
0.75
0.35
0.25
6.1
5.9
6.1
5.9
0.5
4.5
4.5
0.15
0.05
0.08
0.1
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT543-1
---
MO-195
---
EUROPEAN
PROJECTION
ISSUE DATE
00-11-22
02-04-09
Fig 10. Package outline SOT543-1 (TFBGA64)
CBTL12131
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 25 February 2011
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21 of 28
CBTL12131
NXP Semiconductors
DisplayPort multiplexer for bidirectional video
12. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
12.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
12.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•
•
•
•
•
•
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering
12.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
CBTL12131
Product data sheet
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Rev. 1 — 25 February 2011
© NXP B.V. 2011. All rights reserved.
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CBTL12131
NXP Semiconductors
DisplayPort multiplexer for bidirectional video
12.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 11) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 19 and 20
Table 19.
SnPb eutectic process (from J-STD-020C)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm3)
< 350
≥ 350
< 2.5
235
220
≥ 2.5
220
220
Table 20.
Lead-free process (from J-STD-020C)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm3)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 11.
CBTL12131
Product data sheet
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CBTL12131
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DisplayPort multiplexer for bidirectional video
maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 11. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
13. Abbreviations
Table 21.
CBTL12131
Product data sheet
Abbreviations
Acronym
Description
CDM
Charged-Device Model
CMOS
Complementary Metal-Oxide Semiconductor
DDC
Data Display Channel
DP
DisplayPort
eDP
embedded DisplayPort
ESD
ElectroStatic Discharge
GPU
Graphics Processor Unit
HBM
Human Body Model
HPD
Hot Plug Detect
I2C-bus
Inter-Integrated Circuit bus
I/O
Input/Output
LVTTL
Low Voltage Transistor-Transistor Logic
ML
Main Link
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 25 February 2011
© NXP B.V. 2011. All rights reserved.
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DisplayPort multiplexer for bidirectional video
14. Revision history
Table 22.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
CBTL12131 v.1
20110225
Product data sheet
-
-
CBTL12131
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 25 February 2011
© NXP B.V. 2011. All rights reserved.
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CBTL12131
NXP Semiconductors
DisplayPort multiplexer for bidirectional video
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
15.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
CBTL12131
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 25 February 2011
© NXP B.V. 2011. All rights reserved.
26 of 28
CBTL12131
NXP Semiconductors
DisplayPort multiplexer for bidirectional video
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
CBTL12131
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 25 February 2011
© NXP B.V. 2011. All rights reserved.
27 of 28
CBTL12131
NXP Semiconductors
DisplayPort multiplexer for bidirectional video
17. Contents
1
2
2.1
2.2
2.3
2.4
2.5
2.6
3
4
5
6
6.1
6.2
7
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
8
9
10
10.1
10.2
10.3
10.4
10.5
10.6
11
12
12.1
12.2
12.3
12.4
13
14
15
15.1
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 2
High-speed DisplayPort Main Link
multiplexing. . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
DDC and AUX multiplexing. . . . . . . . . . . . . . . . 2
HPD channel management . . . . . . . . . . . . . . . 2
Link state detection, configuration and
reporting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Equalizer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Typical system configuration . . . . . . . . . . . . . . 3
Ordering information . . . . . . . . . . . . . . . . . . . . . 3
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 4
Pinning information . . . . . . . . . . . . . . . . . . . . . . 5
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6
Functional description . . . . . . . . . . . . . . . . . . . 9
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Main Link DisplayPort switches/multiplexers . . 9
AUX and DDC switches/multiplexers . . . . . . . 11
HPD signal path . . . . . . . . . . . . . . . . . . . . . . . 12
AUX logic state detection . . . . . . . . . . . . . . . . 13
HPD logic state detection . . . . . . . . . . . . . . . . 13
Equalizer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
AUX channel bias and termination . . . . . . . . . 16
TST_REXT function . . . . . . . . . . . . . . . . . . . . 18
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 18
Recommended operating conditions. . . . . . . 18
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 19
General characteristics . . . . . . . . . . . . . . . . . . 19
DisplayPort channel characteristics . . . . . . . . 19
AUX and DDC ports . . . . . . . . . . . . . . . . . . . . 20
HPD input, HPD output. . . . . . . . . . . . . . . . . . 20
Control inputs . . . . . . . . . . . . . . . . . . . . . . . . . 20
Status outputs . . . . . . . . . . . . . . . . . . . . . . . . . 20
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 21
Soldering of SMD packages . . . . . . . . . . . . . . 22
Introduction to soldering . . . . . . . . . . . . . . . . . 22
Wave and reflow soldering . . . . . . . . . . . . . . . 22
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 22
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 23
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 25
Legal information. . . . . . . . . . . . . . . . . . . . . . . 26
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 26
15.2
15.3
15.4
16
17
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . .
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact information . . . . . . . . . . . . . . . . . . . .
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
26
26
27
27
28
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2011.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 25 February 2011
Document identifier: CBTL12131