CBTL03SB212 DisplayPort Gen2 sideband signal multiplexer Rev. 1 — 21 February 2011 Product data sheet 1. General description The CBTL03SB212 is a sideband signal multiplexer for DisplayPort Gen2 applications. It provides one differential channel capable of switching or multiplexing (bidirectional and AC-coupled) DisplayPort 1.2 Fast AUX or AUX signal, using high-bandwidth pass-gate technology. Additionally, it provides for switching/multiplexing of the Hot Plug Detect signal as well as the Display Data Channel (DDC) signals, for a total of three channels. A typical application of CBTL03SB212 is on motherboards where one of two GPU display sources needs to be selected to connect to a display sink device or connector. A controller chip selects which path to use by setting a select signal HIGH or LOW. Due to the non-directional nature of the signal paths (which use high-bandwidth pass-gate technology), the CBTL03SB212 can also be used in the reverse topology, e.g., to connect one display source device to one of two display sink devices or connectors. GND CBTL03SB212 AUX1+ AUX1− AUX2+ 100 kΩ AUX+ 2:1 MUX AUX2− AUX− 100 kΩ +3.3 V +3.3 V GPU1 2 kΩ DDC_CLK1 DDC_DAT1 DDC_CLK2 2:1 MUX DDC_CLK DDC_DAT 2:1 MUX HPD DDC_DAT2 HPD_1 HPD_2 SEL, XSD_N GPU2 002aag007 Fig 1. CBTL03SB212 application example CBTL03SB212 NXP Semiconductors DisplayPort Gen2 sideband signal multiplexer 2. Features and benefits 1 : 2 multiplexing of DisplayPort signals 1 high-speed differential channel for Fast AUX or AUX 1 channel for DDC clock and data 1 channel for HPD High-bandwidth analog pass-gate technology Very low intra-pair differential skew (5 ps typical) Switch/MUX position select Shutdown mode CMOS input Shutdown mode minimizes power consumption while switching all channels off Very low operation current of 0.2 mA typical Very low shutdown current of < 10 μA Single 3.3 V power supply ESD 4 kV HBM, 1 kV CDM Available in 4 mm × 4 mm HVQFN20 package 3. Applications Motherboard applications requiring DisplayPort sideband switching/multiplexing Docking stations Notebook computers 4. Ordering information Table 1. Ordering information Type number CBTL03SB212BS [1] Package Name Description Version HVQFN20 plastic thermal enhanced very thin quad flat package; no leads; 20 terminals; body 4 × 4 × 0.85 mm[1] SOT917-1 Total height after printed-circuit board mounting = 1 mm (maximum). CBTL03SB212 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 21 February 2011 © NXP B.V. 2011. All rights reserved. 2 of 16 CBTL03SB212 NXP Semiconductors DisplayPort Gen2 sideband signal multiplexer 5. Functional diagram AUX1+ AUX1− AUX2+ AUX2− DDC_CLK1 DDC_DAT1 DDC_CLK2 DDC_DAT2 2:1 MUX AUX+ 2:1 MUX DDC_CLK AUX− DDC_DAT HPD_1 2:1 MUX HPD HPD_2 SEL, XSD_N 002aag008 Fig 2. Functional diagram 6. Pinning information 16 AUX1− 17 AUX1+ 18 VDD terminal 1 index area 19 GND 20 AUX+ 6.1 Pinning AUX− 1 DDC_CLK 2 15 XSD_N DDC_DAT 3 HPD 4 12 DDC_CLK1 SEL 5 11 DDC_DAT1 14 AUX2+ 7 8 9 DDC_DAT2 DDC_CLK2 HPD_1 10 6 VDD HPD_2 CBTL03SB212BS 13 AUX2− 002aag009 Transparent top view Fig 3. CBTL03SB212 Product data sheet Pin configuration for HVQFN20 All information provided in this document is subject to legal disclaimers. Rev. 1 — 21 February 2011 © NXP B.V. 2011. All rights reserved. 3 of 16 CBTL03SB212 NXP Semiconductors DisplayPort Gen2 sideband signal multiplexer 6.2 Pin description Table 2. Pin Type Description SEL 5 3.3 V CMOS single-ended input Selects between two multiplexer/switch paths. XSD_N 15 3.3 V CMOS single-ended input Shutdown pin. Should be driven HIGH or connected to VDD for normal operation. When LOW, all paths are switched off (non-conducting high-impedance state), and supply current consumption is minimized. AUX+ 20 differential I/O AUX− 1 differential I/O High-speed differential pair for AUX signals, right-side. DDC_CLK 2 differential I/O Product data sheet Pair of single-ended terminals for DDC clock and data signals, right-side. DDC_DAT 3 differential I/O HPD 4 single-ended I/O Single-ended channel for the HPD signal, right-side. AUX1+ 17 differential I/O High-speed differential pair for AUX signals, path 1, left-side. AUX1− 16 differential I/O AUX2+ 14 differential I/O AUX2− 13 differential I/O DDC_CLK1 12 differential I/O High-speed differential pair for AUX signals, path 2, left-side. Pair of single-ended terminals for DDC clock and data signals, path 1, left-side. DDC_DAT1 11 differential I/O DDC_CLK2 9 differential I/O DDC_DAT2 8 differential I/O HPD_1 10 single-ended I/O Single-ended channel for the HPD signal, path 1, left-side. HPD_2 7 single-ended I/O Single-ended channel for the HPD signal, path 2, left-side. VDD 6, 18 power supply 3.3 V power supply. GND[1] 19 ground Ground. [1] CBTL03SB212 Pin description Symbol Pair of single-ended terminals for DDC clock and data signals, path 2, left-side. HVQFN20 package die supply ground is connected to both GND pin and exposed center pad. GND pin and the exposed center pad must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the printed-circuit board in the thermal pad region. All information provided in this document is subject to legal disclaimers. Rev. 1 — 21 February 2011 © NXP B.V. 2011. All rights reserved. 4 of 16 CBTL03SB212 NXP Semiconductors DisplayPort Gen2 sideband signal multiplexer 7. Functional description Refer to Figure 2 “Functional diagram”. The CBTL03SB212 uses 3.3 V power supply. All signal paths are implemented using high-bandwidth pass-gate technology, are bidirectional and no clock or reset signal is needed for the multiplexer to function. The switch position is selected using the select signal (SEL). The detailed operation is described in Section 7.1. 7.1 MUX select (SEL) function The internal multiplexer switch position is controlled by the logic inputs SEL as described below. Table 3. MUX select control SEL Path 2 Path 1 0 high-impedance active 1 active high-impedance 7.2 Shutdown function The CBTL03SB212 provides a shutdown function to minimize power consumption when the application is not active but power to the CBTL03SB212 is provided. Pin XSD_N (active LOW) puts all channels in Off mode (non-conducting high-impedance state) while reducing current consumption to near-zero. Table 4. CBTL03SB212 Product data sheet Shutdown function XSD_N State 0 shutdown 1 active All information provided in this document is subject to legal disclaimers. Rev. 1 — 21 February 2011 © NXP B.V. 2011. All rights reserved. 5 of 16 CBTL03SB212 NXP Semiconductors DisplayPort Gen2 sideband signal multiplexer 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions VDD supply voltage Tcase case temperature for operation within specification VESD electrostatic discharge voltage HBM CDM Min Max Unit −0.3 +5 V −40 +85 °C [1] - 4000 V [2] - 1000 V [1] Human Body Model: ANSI/EOS/ESD-S5.1-1994, standard for ESD sensitivity testing, Human Body Model Component level; Electrostatic Discharge Association, Rome, NY, USA. [2] Charged-Device Model: ANSI/EOS/ESD-S5.3-1-1999, standard for ESD sensitivity testing, Charged-Device Model - Component level; Electrostatic Discharge Association, Rome, NY, USA. 9. Recommended operating conditions CBTL03SB212 Product data sheet Table 6. Recommended operating conditions Symbol Parameter VDD supply voltage 3.0 3.3 3.6 V VI input voltage - - 3.6 V Tamb ambient temperature −40 - +85 °C Conditions operating in free air All information provided in this document is subject to legal disclaimers. Rev. 1 — 21 February 2011 Min Typ Max Unit © NXP B.V. 2011. All rights reserved. 6 of 16 CBTL03SB212 NXP Semiconductors DisplayPort Gen2 sideband signal multiplexer 10. Characteristics 10.1 General characteristics Table 7. General characteristics Symbol Parameter Conditions Min Typ Max Unit IDD supply current operating mode (XSD_N = HIGH); VDD = 3.3 V - 0.2 1 mA shutdown mode (XSD_N = LOW); VDD = 3.3 V - - 10 μA Ptot total power dissipation operating mode (XSD_N = HIGH); VDD = 3.3 V - - 5 mW tstartup start-up time supply voltage valid or XSD_N going HIGH to channel specified operating characteristics - - 10 μs trcfg reconfiguration time SEL state change to channel specified operating characteristics - - 1 μs 10.2 AUX channel characteristics Table 8. AUX channel characteristics Symbol Parameter VI Conditions Min Typ Max Unit input voltage −0.3 - +2.6 V VIC common-mode input voltage 0 - 2.0 V VID differential input voltage peak-to-peak - - +1.4 V DDIL differential insertion loss channel is on; f = 100 MHz - −0.8 - dB channel is on; f = 2.5 GHz - −3 - dB channel is off; 0 Hz ≤ f ≤ 1.0 GHz - - −30 dB channel is on; 0 Hz ≤ f ≤ 1.0 GHz - - −10 dB DDNEXT differential near-end crosstalk adjacent channels are on; 0 Hz ≤ f ≤ 1.0 GHz - - −40 dB B bandwidth −3.0 dB intercept - 2.5 - GHz tPD propagation delay from left-side port to right-side port or vice versa - 100 - ps tsk(dif) differential skew time intra-pair - 5 - ps Conditions Min Typ Max Unit −0.3 - VDD V - 100 - ps DDRL differential return loss 10.3 DDC ports Table 9. DDC port characteristics Symbol Parameter VI input voltage tPD propagation delay CBTL03SB212 Product data sheet from left-side port to right-side port or vice versa All information provided in this document is subject to legal disclaimers. Rev. 1 — 21 February 2011 © NXP B.V. 2011. All rights reserved. 7 of 16 CBTL03SB212 NXP Semiconductors DisplayPort Gen2 sideband signal multiplexer 10.4 HPD input, HPD output Table 10. HPD input and output characteristics Symbol Parameter Conditions [1] VI input voltage tPD propagation delay [1] from left-side port to right-side port or vice versa Min Typ Max Unit −0.3 - 3.6 V - 100 - ps Low-speed input changes state on cable plug/unplug. 10.5 MUX select input Table 11. SEL, XSD_N input characteristics Symbol Parameter Conditions Min Typ Max Unit VIH HIGH-level input voltage SEL, XSD_N 2.0 - 3.6 V VIL LOW-level input voltage SEL, XSD_N 0 - 0.8 V ILI input leakage current measured with input at VIH(max) and VIL(min) - - 10 μA 11. Test information 11.1 Switch test fixture requirements The test fixture for switch S-parameter measurement shall be designed and built to specific requirements, as described below, to ensure good measurement quality and consistency. • The test fixture shall be a FR4-based PCB of the microstrip structure; the dielectric thickness or stack-up shall be about 4 mils. • The total thickness of the test fixture PCB shall be 1.57 mm (0.062 in). • The measurement signals shall be launched into the switch from the top of the test fixture, capturing the through-hole stub effect. • Traces between the DUT and measurement ports (SMA or microprobe) should be uncoupled from each other, as much as possible. Therefore, the traces should be routed in such a way that traces will diverge from each other exiting from the switch pin field. • The trace lengths between the DUT and measurement port shall be minimized. The maximum trace length shall not exceed 1000 mils. The trace lengths between the DUT and measurement port shall be equal. • All of the traces on the test board and add-in card must be held to a characteristic impedance of 50 Ω with a tolerance of ±7 %. • SMA connector is recommended for ease of use. The SMA launch structure shall be designed to minimize the connection discontinuity from SMA to the trace. The impedance range of the SMA connector seen from a TDR with a 60 ps rise time should be within 50 Ω ± 7 Ω. CBTL03SB212 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 21 February 2011 © NXP B.V. 2011. All rights reserved. 8 of 16 CBTL03SB212 NXP Semiconductors DisplayPort Gen2 sideband signal multiplexer 12. Package outline HVQFN20: plastic thermal enhanced very thin quad flat package; no leads; 20 terminals; body 4 x 4 x 0.85 mm B D SOT917-1 A terminal 1 index area A E A1 c detail X C e1 e b 6 10 y y1 C v M C A B w M C L 11 5 e Eh e2 1 15 terminal 1 index area 20 16 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A(1) max. A1 b c D(1) Dh E(1) Eh e e1 e2 L v w y y1 mm 1 0.05 0.00 0.30 0.18 0.2 4.1 3.9 2.45 2.15 4.1 3.9 2.45 2.15 0.5 2 2 0.6 0.4 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. Fig 4. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT917 -1 --- MO-220 --- EUROPEAN PROJECTION ISSUE DATE 05-10-08 05-10-31 Package outline HVQFN20 (SOT917-1) CBTL03SB212 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 21 February 2011 © NXP B.V. 2011. All rights reserved. 9 of 16 CBTL03SB212 NXP Semiconductors DisplayPort Gen2 sideband signal multiplexer 13. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 13.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 13.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • • • • • • Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering 13.3 Wave soldering Key characteristics in wave soldering are: • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities CBTL03SB212 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 21 February 2011 © NXP B.V. 2011. All rights reserved. 10 of 16 CBTL03SB212 NXP Semiconductors DisplayPort Gen2 sideband signal multiplexer 13.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 5) than a SnPb process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 12 and 13 Table 12. SnPb eutectic process (from J-STD-020C) Package thickness (mm) Package reflow temperature (°C) Volume (mm3) < 350 ≥ 350 < 2.5 235 220 ≥ 2.5 220 220 Table 13. Lead-free process (from J-STD-020C) Package thickness (mm) Package reflow temperature (°C) Volume (mm3) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 5. CBTL03SB212 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 21 February 2011 © NXP B.V. 2011. All rights reserved. 11 of 16 CBTL03SB212 NXP Semiconductors DisplayPort Gen2 sideband signal multiplexer maximum peak temperature = MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 5. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 14. Abbreviations Table 14. CBTL03SB212 Product data sheet Abbreviations Acronym Description AUX Auxiliary channel in DisplayPort definition CDM Charged-Device Model CMOS Complementary Metal-Oxide Semiconductor DDC Display Data Channel DUT Device Under Test ESD ElectroStatic Discharge FAUX Fast AUX GPU Graphics Processor Unit HBM Human Body Model HPD Hot Plug Detect I/O Input/Output MUX Multiplexer PCB Printed-Circuit Board SMA SubMiniature, version A (connector) TDR Time-Domain Reflectometry All information provided in this document is subject to legal disclaimers. Rev. 1 — 21 February 2011 © NXP B.V. 2011. All rights reserved. 12 of 16 CBTL03SB212 NXP Semiconductors DisplayPort Gen2 sideband signal multiplexer 15. Revision history Table 15. Revision history Document ID Release date Data sheet status Change notice Supersedes CBTL03SB212 v.1 20110221 Product data sheet - - CBTL03SB212 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 21 February 2011 © NXP B.V. 2011. All rights reserved. 13 of 16 CBTL03SB212 NXP Semiconductors DisplayPort Gen2 sideband signal multiplexer 16. Legal information 16.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 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NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. 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Export might require a prior authorization from national authorities. CBTL03SB212 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 21 February 2011 © NXP B.V. 2011. All rights reserved. 14 of 16 CBTL03SB212 NXP Semiconductors DisplayPort Gen2 sideband signal multiplexer Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. 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Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] CBTL03SB212 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 21 February 2011 © NXP B.V. 2011. All rights reserved. 15 of 16 CBTL03SB212 NXP Semiconductors DisplayPort Gen2 sideband signal multiplexer 18. Contents 1 2 3 4 5 6 6.1 6.2 7 7.1 7.2 8 9 10 10.1 10.2 10.3 10.4 10.5 11 11.1 12 13 13.1 13.2 13.3 13.4 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 2 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 MUX select (SEL) function . . . . . . . . . . . . . . . . 5 Shutdown function . . . . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6 Recommended operating conditions. . . . . . . . 6 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 7 General characteristics . . . . . . . . . . . . . . . . . . . 7 AUX channel characteristics. . . . . . . . . . . . . . . 7 DDC ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 HPD input, HPD output. . . . . . . . . . . . . . . . . . . 8 MUX select input . . . . . . . . . . . . . . . . . . . . . . . 8 Test information . . . . . . . . . . . . . . . . . . . . . . . . . 8 Switch test fixture requirements . . . . . . . . . . . . 8 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 Soldering of SMD packages . . . . . . . . . . . . . . 10 Introduction to soldering . . . . . . . . . . . . . . . . . 10 Wave and reflow soldering . . . . . . . . . . . . . . . 10 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 10 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 11 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 13 Legal information. . . . . . . . . . . . . . . . . . . . . . . 14 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Contact information. . . . . . . . . . . . . . . . . . . . . 15 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2011. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 21 February 2011 Document identifier: CBTL03SB212