Data Sheet

PCA9517A
Level translating I2C-bus repeater
Rev. 4.1 — 24 May 2016
Product data sheet
1. General description
The PCA9517A is a CMOS integrated circuit that provides level shifting between low
voltage (down to 0.9 V) and higher voltage (2.7 V to 5.5 V) I2C-bus or SMBus
applications. While retaining all the operating modes and features of the I2C-bus system
during the level shifts, it also permits extension of the I2C-bus by providing bidirectional
buffering for both the data (SDA) and the clock (SCL) lines, thus enabling two buses of
400 pF. Using the PCA9517A enables the system designer to isolate two halves of a bus
for both voltage and capacitance. The SDA and SCL pins are overvoltage tolerant and are
high-impedance when the PCA9517A is unpowered.
The 2.7 V to 5.5 V bus port B drivers behave much like the drivers on the PCA9515A
device, while the adjustable voltage bus port A drivers drive more current and eliminate
the static offset voltage. This results in a LOW on the port B translating into a nearly 0 V
LOW on the port A which accommodates smaller voltage swings of lower voltage logic.
The static offset design of the port B PCA9517A I/O drivers prevent them from being
connected to another device that has rise time accelerator including the PCA9510,
PCA9511, PCA9512, PCA9513, PCA9514, PCA9515A, PCA9516A, PCA9517A (port B),
or PCA9518. Port A of two or more PCA9517As can be connected together, however, to
allow a star topography with port A on the common bus, and port A can be connected
directly to any other buffer with static or dynamic offset voltage. Multiple PCA9517As can
be connected in series, port A to port B, with no build-up in offset voltage with only time of
flight delays to consider.
The PCA9517A drivers are not enabled unless VCC(A) is above 0.8 V and VCC(B) is above
2.5 V. The EN pin can also be used to turn the drivers on and off under system control.
Caution should be observed to only change the state of the enable pin when the bus is
idle.
The output pull-down on the port B internal buffer LOW is set for approximately 0.5 V,
while the input threshold of the internal buffer is set about 70 mV lower (0.43 V). When the
port B I/O is driven LOW internally, the LOW is not recognized as a LOW by the input.
This prevents a lock-up condition from occurring. The output pull-down on port A drives a
hard LOW and the input level is set at 0.3VCC(A) to accommodate the need for a lower
LOW level in systems where the low voltage side supply voltage is as low as 0.9 V.
Table 1.
PCA9517 and PCA9517A comparison
Parameter
PCA9517[1]
PCA9517A[2]
electrostatic discharge, HBM
> 2 kV
> 5.5 kV
[1]
PCA9517 will be discontinued in several years, so move to the PCA9517A for all new designs and system
updates.
[2]
The PCA9517A is an improved hot swap and ESD version of the PCA9517, but otherwise operates
identically and should be used for all new designs and system updates.
PCA9517A
NXP Semiconductors
Level translating I2C-bus repeater
2. Features and benefits
 2 channel, bidirectional buffer isolates capacitance and allows 400 pF on either side of
the device
 Voltage level translation from 0.9 V to 5.5 V and from 2.7 V to 5.5 V
 Footprint and functional replacement for PCA9515/15A
 I2C-bus and SMBus compatible
 Active HIGH repeater enable input
 Open-drain input/outputs
 Lock-up free operation
 Supports arbitration and clock stretching across the repeater
 Accommodates Standard-mode and Fast-mode I2C-bus devices and multiple masters
 Powered-off high-impedance I2C-bus pins
 Port A operating supply voltage range of 0.9 V to 5.5 V
 Port B operating supply voltage range of 2.7 V to 5.5 V
 5 V tolerant I2C-bus and enable pins
 0 Hz to 400 kHz clock frequency (the maximum system operating frequency may be
less than 400 kHz because of the delays added by the repeater)
 ESD protection exceeds 5500 V HBM per JESD22-A114 and 1000 V CDM per
JESD22-C101
 Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
 Packages offered: SO8, TSSOP8 and HWSON8
3. Ordering information
Table 2.
Ordering information
Tamb = 40 C to +85 C.
Type number
Topside
mark
Package
Name
Description
Version
PA9517A
SO8
plastic small outline package; 8 leads; body width 3.9 mm
SOT96-1
PCA9517ADP
9517A
TSSOP8[1]
plastic thin shrink small outline package; 8 leads;
body width 3 mm
SOT505-1
PCA9517ADP/DG
9517A
TSSOP8[1][2] plastic thin shrink small outline package; 8 leads;
body width 3 mm
SOT505-1
PCA9517ATP
17A
HWSON8
SOT1069-2
PCA9517AD
plastic thermal enhanced very very thin small outline
package; no leads; 8 terminals; body 2  3  0.8 mm
[1]
Also known as MSOP8.
[2]
PCA9517ADP/DG is functionally the same (electrically and mechanically) as the PCA9517ADP, but was initially produced (e.g., “born”)
with Dark Green (lead-free and halogen/antimony-free) package material and is a temporary unique orderable part number for
customers who desire to order and only receive Dark Green package material. The standard part PCA9517ADP will transition to Dark
Green package material in 2Q’12 and then the PCA9517ADP and PCA9517ADP/DG devices will be identical. The PCA9517ADP/DG
part number will be EOL after several years as customers who used this temporary part number update their BOM to the normal part
number.
PCA9517A
Product data sheet
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Rev. 4.1 — 24 May 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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PCA9517A
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Level translating I2C-bus repeater
4. Functional diagram
VCC(A)
VCC(B)
PCA9517A
SDAA
SDAB
SCLA
SCLB
VCC(B)
pull-up
resistor
EN
002aad465
GND
Fig 1.
Functional diagram of PCA9517A
5. Pinning information
5.1 Pinning
PCA9517ADP
PCA9517ADP/DG
VCC(A)
1
8
VCC(B)
SCLA
2
7
SCLB
SDAA
3
6
SDAB
VCC(A)
1
8
VCC(B)
SCLA
2
7
SCLB
SDAA
3
6
SDAB
GND
4
5
EN
PCA9517AD
GND
5
4
EN
002aad467
002aad466
Fig 2.
Pin configuration for SO8
Fig 3.
Pin configuration for TSSOP8
(MSOP8)
PCA9517ATP
terminal 1
index area
SDAA
1
8
SCLA
GND
2
7
VCC(A)
EN
3
6
VCC(B)
SDAB
4
5
SCLB
002aag100
Transparent top view
Fig 4.
PCA9517A
Product data sheet
Pin configuration for HWSON8
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PCA9517A
NXP Semiconductors
Level translating I2C-bus repeater
5.2 Pin description
Table 3.
Symbol
Pin description
Pin
SO8,
TSSOP8
Description
HWSON8
VCC(A)
1
7
port A supply voltage (0.9 V to 5.5 V)
SCLA
2
8
serial clock port A bus
SDAA
3
1
serial data port A bus
GND
4
2[1]
supply ground (0 V)
EN
5
3
active HIGH repeater enable input
SDAB
6
4
serial data port B bus
SCLB
7
5
serial clock port B bus
VCC(B)
8
6
port B supply voltage (2.7 V to 5.5 V)
[1]
HWSON8 package die supply ground is connected to both GND pin and exposed center pad. GND pin
must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and
board level performance, the exposed pad needs to be soldered to the board using a corresponding
thermal pad on the board and for proper head conduction through the board, thermal vias need to be
incorporated in the printed-circuit board in the thermal pad region.
6. Functional description
Refer to Figure 1 “Functional diagram of PCA9517A”.
The PCA9517A enables I2C-bus or SMBus translation down to VCC(A) as low as 0.9 V
without degradation of system performance. The PCA9517A contains two bidirectional
open-drain buffers specifically designed to support up-translation/down-translation
between the low voltage (as low as 0.9 V) and a 3.3 V or 5 V I2C-bus or SMBus. All inputs
and I/Os are overvoltage tolerant to 5.5 V even when the device is unpowered (VCC(B)
and/or VCC(A) = 0 V). The PCA9517A includes a power-up circuit that keeps the output
drivers turned off until VCC(B) is above 2.5 V and the VCC(A) is above 0.8 V. VCC(B) and
VCC(A) can be applied in any sequence at power-up. After power-up and with the enable
(EN) HIGH, a LOW level on port A (below 0.3VCC(A)) turns the corresponding port B driver
(either SDA or SCL) on and drives port B down to about 0.5 V. When port A rises above
0.3VCC(A), the port B pull-down driver is turned off and the external pull-up resistor pulls
the pin HIGH. When port B falls first and goes below 0.4 V the port A driver is turned on
and port A pulls down to 0 V. The port A pull-down is not enabled unless the port B
voltage goes below 0.4 V. If the port B low voltage goes below 0.4 V, the port B pull-down
driver is enabled and port B will only be able to rise to 0.5 V until port A rises above
0.3VCC(A), then port B will continue to rise being pulled up by the external pull-up resistor.
The VCC(A) is only used to provide the 0.3VCC(A) reference to the port A input comparators
and for the power good detect circuit. The PCA9517A logic and all I/Os are powered by
the VCC(B) pin.
PCA9517A
Product data sheet
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PCA9517A
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Level translating I2C-bus repeater
6.1 Enable
The EN pin is active HIGH with an internal pull-up to VCC(B) and allows the user to select
when the repeater is active. This can be used to isolate a badly behaved slave on
power-up until after the system power-up reset. It should never change state during an
I2C-bus operation because disabling during a bus operation will hang the bus and
enabling part way through a bus cycle could confuse the I2C-bus parts being enabled.
The enable pin should only change state when the global bus and the repeater port are in
an idle state to prevent system failures.
6.2 I2C-bus systems
As with the standard I2C-bus system, pull-up resistors are required to provide the logic
HIGH levels on the buffered bus (standard open-collector configuration of the I2C-bus).
The size of these pull-up resistors depends on the system, but each side of the repeater
must have a pull-up resistor. This part designed to work with Standard mode and Fast
mode I2C-bus devices in addition to SMBus devices. Standard mode I2C-bus devices only
specify 3 mA output drive; this limits the termination current to 3 mA in a generic I2C-bus
system where Standard-mode devices and multiple masters are possible. Under certain
conditions higher termination currents can be used.
Please see Application Note AN255, I2C/SMBus Repeaters, Hubs and Expanders for
additional information on sizing resistors and precautions when using more than one
PCA9517A in a system or using the PCA9517A in conjunction with other bus buffers.
7. Application design-in information
A typical application is shown in Figure 5. In this example, the system master is running
on a 3.3 V I2C-bus while the slave is connected to a 1.2 V bus. Both buses run at 400 kHz.
Master devices can be placed on either bus.
3.3 V
1.2 V
10 kΩ
10 kΩ
VCC(A)
SDA
SDAB
SDAA
SDA
SCL
SCLB
SCLA
SCL
BUS
MASTER
400 kHz
PCA9517A
SLAVE
400 kHz
EN
bus B
Fig 5.
10 kΩ
10 kΩ
VCC(B)
bus A
002aad468
Typical application
The PCA9517A is 5 V tolerant, so it does not require any additional circuitry to translate
between 0.9 V to 5.5 V bus voltages and 2.7 V to 5.5 V bus voltages.
PCA9517A
Product data sheet
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Rev. 4.1 — 24 May 2016
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PCA9517A
NXP Semiconductors
Level translating I2C-bus repeater
When port A of the PCA9517A is pulled LOW by a driver on the I2C-bus, a comparator
detects the falling edge when it goes below 0.3VCC(A) and causes the internal driver on
port B to turn on, causing port B to pull down to about 0.5 V. When port B of the
PCA9517A falls, first a CMOS hysteresis type input detects the falling edge and causes
the internal driver on port A to turn on and pull the port A pin down to ground. In order to
illustrate what would be seen in a typical application, refer to Figure 9 and Figure 10. If the
bus master in Figure 5 were to write to the slave through the PCA9517A, waveforms
shown in Figure 9 would be observed on the A bus. This looks like a normal I2C-bus
transmission except that the HIGH level may be as low as 0.9 V, and the turn on and turn
off of the acknowledge signals are slightly delayed.
On the B bus side of the PCA9517A, the clock and data lines would have a positive offset
from ground equal to the VOL of the PCA9517A. After the eighth clock pulse, the data line
will be pulled to the VOL of the slave device which is very close to ground in this example.
At the end of the acknowledge, the level rises only to the LOW level set by the driver in the
PCA9517A for a short delay while the A bus side rises above 0.3VCC(A) then it continues
HIGH. It is important to note that any arbitration or clock stretching events require that the
LOW level on the B bus side at the input of the PCA9517A (VIL) be at or below 0.4 V to be
recognized by the PCA9517A and then transmitted to the A bus side.
Multiple PCA9517A port A sides can be connected in a star configuration (Figure 6),
allowing all nodes to communicate with each other.
Multiple PCA9517As can be connected in series (Figure 7) as long as port A is connected
to port B. I2C-bus slave devices can be connected to any of the bus segments. The
number of devices that can be connected in series is limited by repeater
delay/time-of-flight considerations on the maximum bus speed requirements.
PCA9517A
Product data sheet
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PCA9517A
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Level translating I2C-bus repeater
VCC(A)
VCC(B)
10 kΩ
10 kΩ
10 kΩ
10 kΩ
VCC(A)
VCC(B)
SDA
SDAA
SDAB
SDA
SCL
SCLA
SCLB
SCL
BUS
MASTER
PCA9517A
SLAVE
400 kHz
EN
10 kΩ
10 kΩ
VCC(A)
VCC(B)
SDAA
SDAB
SDA
SCLA
SCLB
SCL
PCA9517A
SLAVE
400 kHz
EN
10 kΩ
10 kΩ
VCC(A)
VCC(B)
SDAA
SDAB
SDA
SCLA
SCLB
SCL
PCA9517A
SLAVE
400 kHz
EN
002aad469
Fig 6.
Typical star application
VCC
10 kΩ
10 kΩ
10 kΩ
10 kΩ
10 kΩ
10 kΩ
10 kΩ
10 kΩ
SDA
SDAA
SDAB
SDAA
SDAB
SDAA
SDAB
SDA
SCL
SCLA
SCLB
SCLA
SCLB
SCLA
SCLB
SCL
BUS
MASTER
PCA9517A
EN
PCA9517A
EN
PCA9517A
SLAVE
400 kHz
EN
002aad470
Fig 7.
Typical series application
PCA9517A
Product data sheet
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PCA9517A
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Level translating I2C-bus repeater
CARD 1
VCC(A)
CARD 2
RPU
VCC(B)
RPU
10 kΩ
VCC(A)
75 Ω
75 Ω
10 kΩ
10 kΩ
(optional)
VCC(B)
SDAA
SCLA
SDAB
SCLB
EN
MASTER
OR
SLAVE
GND
002aad644
Remark: Figure 9 and Figure 10 reference Figure 8 and assume master on Bus B side and slave
on Bus A side.
Fig 8.
Typical application of PCA9517A driving a short cable
9th clock pulse
acknowledge
SCL
SDA
002aac775
Fig 9.
Bus A (0.9 V to 5.5 V bus) waveform
9th clock pulse
acknowledge
SCL
VOL of PCA9517A
SDA
002aad471
VOL of slave
Fig 10. Bus B (2.7 V to 5.5 V) waveform
PCA9517A
Product data sheet
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PCA9517A
NXP Semiconductors
Level translating I2C-bus repeater
8. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Min
Max
Unit
VCC(B)
supply voltage port B
2.7 V to 5.5 V
0.5
+7
V
VCC(A)
supply voltage port A
adjustable
0.5
+7
V
VI/O
voltage on an input/output pin
port A and port B; enable pin (EN)
0.5
+7
V
II/O
input/output current
port A; port B
-
50
mA
II
input current
EN, VCC(A), VCC(B), GND
-
50
mA
Ptot
total power dissipation
-
100
mW
Tstg
storage temperature
55
+125
C
Tamb
ambient temperature
40
+85
C
Tj
junction temperature
-
+125
C
PCA9517A
Product data sheet
operating in free air
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PCA9517A
NXP Semiconductors
Level translating I2C-bus repeater
9. Static characteristics
Table 5.
Static characteristics
VCC = 2.7 V to 5.5 V; GND = 0 V; Tamb = 40 C to +85 C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Supplies
VCC(B)
supply voltage port B
VCC(A)
supply voltage port A
2.7
-
5.5
V
0.9
-
5.5
V
ICC(VCC(A))
supply current on pin VCC(A)
-
-
1
mA
ICCH
HIGH-level supply current
both channels HIGH;
VCC = 5.5 V;
SDAn = SCLn = VCC
-
1.5
5
mA
ICCL
LOW-level supply current
both channels LOW;
VCC = 5.5 V;
one SDA and one SCL = GND;
other SDA and SCL open
-
1.5
5
mA
ICC(A)c
contention port A supply current
VCC = 5.5 V;
SDAn = SCLn = VCC
-
1.5
5
mA
0.7VCC(B)
-
5.5
V
0.5
-
+0.3VCC(B) V
0.5
0.4
-
V
[1]
Input and output SDAB and SCLB
VIH
HIGH-level input voltage
[2]
VIL
LOW-level input voltage
VILc
contention LOW-level input
voltage
VIK
input clamping voltage
II = 18 mA
-
-
1.2
V
ILI
input leakage current
VI = 3.6 V
-
-
1
A
IIL
LOW-level input current
SDA, SCL; VI = 0.2 V
-
-
10
A
VOL
LOW-level output voltage
IOL = 100 A or 6 mA
0.47
0.52
0.6
V
VOLVILc
difference between LOW-level
output and LOW-level input
voltage contention
guaranteed by design
-
-
70
mV
ILOH
HIGH-level output leakage
current
VO = 3.6 V
-
-
10
A
Cio
input/output capacitance
VI = 3 V or 0 V; VCC = 3.3 V
-
6
7
pF
VI = 3 V or 0 V; VCC = 0 V
-
6
7
pF
0.7VCC(A)
-
5.5
V
0.5
-
+0.3VCC(A) V
Input and output SDAA and SCLA
VIH
HIGH-level input voltage
[3]
VIL
LOW-level input voltage
VIK
input clamping voltage
II = 18 mA
-
-
1.2
ILI
input leakage current
VI = 3.6 V
-
-
1
A
IIL
LOW-level input current
SDA, SCL; VI = 0.2 V
-
-
10
A
VOL
LOW-level output voltage
IOL = 6 mA
-
0.1
0.2
V
ILOH
HIGH-level output leakage
current
VO = 3.6 V
-
-
10
A
Cio
input/output capacitance
VI = 3 V or 0 V; VCC = 3.3 V
-
6
7
pF
VI = 3 V or 0 V; VCC = 0 V
-
6
7
pF
PCA9517A
Product data sheet
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V
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PCA9517A
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Level translating I2C-bus repeater
Table 5.
Static characteristics …continued
VCC = 2.7 V to 5.5 V; GND = 0 V; Tamb = 40 C to +85 C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
0.5
-
+0.3VCC(B) V
Enable
VIL
LOW-level input voltage
VIH
HIGH-level input voltage
IIL(EN)
LOW-level input current on
pin EN
ILI
input leakage current
Ci
input capacitance
VI = 0.2 V, EN; VCC = 3.6 V
VI = 3.0 V or 0 V
0.7VCC(B)
-
5.5
V
-
10
30
A
1
-
+1
A
-
6
7
pF
[1]
LOW-level supply voltage.
[2]
VIL specification is for the first LOW level seen by the SDAB/SCLB lines. VILc is for the second and subsequent LOW levels seen by the
SDAB/SCLB lines.
[3]
VIL for port A with envelope noise must be below 0.3VCC(A) for stable performance.
10. Dynamic characteristics
Table 6.
Dynamic characteristics
VCC = 2.7 V to 5.5 V; GND = 0 V; Tamb = 40 C to +85 C; unless otherwise specified.[1][2]
Symbol
Parameter
Min
Typ[3]
Max
Unit
[4]
100
170
250
ns
[5]
30
80
110
ns
VCC(A)  3 V
10
66
300
ns
10
20
30
ns
1
77
105
ns
Conditions
tPLH
LOW to HIGH propagation delay
port B to port A; Figure 13
tPHL
HIGH to LOW propagation delay
port B to port A; Figure 11
VCC(A)  2.7 V
tTLH
LOW to HIGH output transition time
port A; Figure 11
tTHL
HIGH to LOW output transition time
port A; Figure 11
VCC(A)  2.7 V
[5]
VCC(A)  3 V
tPLH
LOW to HIGH propagation delay
port A to port B; Figure 12
[6]
tPHL
HIGH to LOW propagation delay
port A to port B; Figure 12
[6]
tTLH
LOW to HIGH output transition time
port B; Figure 12
tTHL
HIGH to LOW output transition time
port B; Figure 12
tsu
set-up time
EN HIGH before START condition
[7]
th
hold time
EN HIGH after STOP condition
[7]
20
70
175
ns
25
53
110
ns
60
79
230
ns
120
140
170
ns
30
48
90
ns
100
-
-
ns
100
-
-
ns
[1]
Times are specified with loads of 1.35 k pull-up resistance and 57 pF load capacitance on port B, and 167  pull-up resistance and
57 pF load capacitance on port A. Different load resistance and capacitance will alter the RC time constant, thereby changing the
propagation delay and transition times.
[2]
Pull-up voltages are VCC(A) on port A and VCC(B) on port B.
[3]
Typical values were measured with VCC(A) = 3.3 V at Tamb = 25 C, unless otherwise noted.
[4]
The tPLH delay data from port B to port A is measured at 0.5 V on port B to 0.5VCC(A) on port A when VCC(A) is less than 2 V, and 1.5 V
on port A if VCC(A) is greater than 2 V.
[5]
Typical value measured with VCC(A) = 2.7 V at Tamb = 25 C.
[6]
The proportional delay data from port A to port B is measured at 0.3VCC(A) on port A to 1.5 V on port B.
[7]
The enable pin, EN, should only change state when the global bus and the repeater port are in an idle state.
PCA9517A
Product data sheet
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10.1 AC waveforms
3.0 V
input
1.5 V
1.5 V
tPHL
tPLH
80 %
output
0.6 V
20 %
tTHL
0.6 V
20 %
VCC(A)
input
0.1 V
80 %
tTLH
0.3VCC(A)
0.3VCC(A)
tPLH
tPHL
1.2 V
3.0 V
80 %
1.5 V
20 %
1.5 V
20 %
output
VOL
tTHL
tTLH
002aad642
Fig 11. Propagation delay and transition times;
port B to port A
80 %
002aad643
Fig 12. Propagation delay and transition times;
port A to port B
input
SDAB, SCLB
0.5 V
output
SCLA, SDAA
50 % if VCC(A) is less than 2 V
1.5 V if VCC(A) is greater than 2 V
tPLH
002aad641
Fig 13. Propagation delay
11. Test information
VCC(B)
VCC(B)
VCC(A)
PULSE
GENERATOR
VI
RL
VO
DUT
CL
RT
002aab649
RL = load resistor; 1.35 k on port B; 167  on port A (0.9 V to 2.7 V) and 450  on port A (3.0 V
to 5.5 V).
CL = load capacitance includes jig and probe capacitance; 57 pF
RT = termination resistance should be equal to Zo of pulse generators
Fig 14. Test circuit for open-drain outputs
PCA9517A
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12. Package outline
SO8: plastic small outline package; 8 leads; body width 3.9 mm
SOT96-1
D
E
A
X
c
y
HE
v M A
Z
5
8
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
1
L
4
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
mm
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
5.0
4.8
4.0
3.8
1.27
6.2
5.8
1.05
1.0
0.4
0.7
0.6
0.25
0.25
0.1
0.7
0.3
inches
0.069
0.010 0.057
0.004 0.049
0.01
0.019 0.0100
0.014 0.0075
0.20
0.19
0.16
0.15
0.05
0.01
0.01
0.004
0.028
0.012
0.244
0.039 0.028
0.041
0.228
0.016 0.024
θ
8o
o
0
Notes
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT96-1
076E03
MS-012
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-18
Fig 15. Package outline SOT96-1 (SO8)
PCA9517A
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TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm
D
E
SOT505-1
A
X
c
y
HE
v M A
Z
5
8
A2
pin 1 index
(A3)
A1
A
θ
Lp
L
1
4
detail X
e
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D(1)
E(2)
e
HE
L
Lp
v
w
y
Z(1)
θ
mm
1.1
0.15
0.05
0.95
0.80
0.25
0.45
0.25
0.28
0.15
3.1
2.9
3.1
2.9
0.65
5.1
4.7
0.94
0.7
0.4
0.1
0.1
0.1
0.70
0.35
6°
0°
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-04-09
03-02-18
SOT505-1
Fig 16. Package outline SOT505-1 (TSSOP8)
PCA9517A
Product data sheet
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HWSON8: plastic thermal enhanced very very thin small outline package; no leads;
8 terminals; body 2 x 3 x 0.75 mm
SOT1069-2
X
B
D
A
A2
A
E
A1
A3
terminal 1
index area
detail X
e1
terminal 1
index area
e
1
4
C
C A B
C
v
w
b
y
y1 C
L
K
E2
8
5
D2
0
1
Dimensions
Unit
mm
2 mm
scale
A(1)
A1
A2
max 0.80 0.05 0.65
nom 0.75 0.02 0.55
min 0.70 0.00 0.45
A3
b
D(1)
D2
E(1)
E2
e
e1
0.2
0.30
0.25
0.18
2.1
2.0
1.9
1.6
1.5
1.4
3.1
3.0
2.9
1.6
1.5
1.4
0.5
1.5
K
L
0.40 0.45
0.35 0.40
0.30 0.35
v
0.1
w
y
y1
0.05 0.05 0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
References
Outline
version
IEC
JEDEC
JEITA
SOT1069-2
---
MO-229
---
sot1069-2_po
European
projection
Issue date
09-11-18
12-04-18
Fig 17. Package outline SOT1069-2 (HWSON8)
PCA9517A
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13. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
13.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
13.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•
•
•
•
•
•
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering
13.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
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13.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 18) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 7 and 8
Table 7.
SnPb eutectic process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
 350
< 2.5
235
220
 2.5
220
220
Table 8.
Lead-free process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 18.
PCA9517A
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maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 18. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
14. Abbreviations
Table 9.
PCA9517A
Product data sheet
Abbreviations
Acronym
Description
BOM
Bill Of Materials
CDM
Charged-Device Model
CMOS
Complementary Metal-Oxide Semiconductor
EOL
End Of Life
ESD
ElectroStatic Discharge
HBM
Human Body Model
I2C-bus
Inter Integrated Circuit bus
I/O
Input/Output
RC
Resistor-Capacitor network
SMBus
System Management Bus
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15. Revision history
Table 10.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
PCA9517A v.4.1
20160524
Product data sheet
-
PCA9517A v.4
Modifications:
PCA9517A v.4
Modifications:
•
Corrected the text in Section 6 “Functional description” on page 4: “When port B falls first and goes
below 0.3VCC(B)” to “When port B falls first and goes below 0.4 V”; “The port B pull-down” to “The
port A pull-down”; removed sentence “If the port B low voltage does not go below 0.5 V....”
20120509
•
Product data sheet
-
PCA9517A v.3
Table 1 “PCA9517 and PCA9517A comparison”:
– Table note [1] is rewritten
– Table note [2] is rewritten
•
Table 2 “Ordering information”
– Added type number PCA9517ADP/DG
– Added Table note [2]
•
Figure 3 “Pin configuration for TSSOP8 (MSOP8)”: added type number PCA9517ADP/DG
PCA9517A v.3
20120229
Product data sheet
-
PCA9517A v.2
PCA9517A v.2
20080505
Product data sheet
-
PCA9517A v.1
PCA9517A v.1
20080222
Product data sheet
-
-
PCA9517A
Product data sheet
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16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
16.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
PCA9517A
Product data sheet
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
All information provided in this document is subject to legal disclaimers.
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Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I2C-bus — logo is a trademark of NXP B.V.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
PCA9517A
Product data sheet
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18. Contents
1
2
3
4
5
5.1
5.2
6
6.1
6.2
7
8
9
10
10.1
11
12
13
13.1
13.2
13.3
13.4
14
15
16
16.1
16.2
16.3
16.4
17
18
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 2
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional description . . . . . . . . . . . . . . . . . . . 4
Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
I2C-bus systems . . . . . . . . . . . . . . . . . . . . . . . . 5
Application design-in information . . . . . . . . . . 5
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 9
Static characteristics. . . . . . . . . . . . . . . . . . . . 10
Dynamic characteristics . . . . . . . . . . . . . . . . . 11
AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . 12
Test information . . . . . . . . . . . . . . . . . . . . . . . . 12
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13
Soldering of SMD packages . . . . . . . . . . . . . . 16
Introduction to soldering . . . . . . . . . . . . . . . . . 16
Wave and reflow soldering . . . . . . . . . . . . . . . 16
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 16
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 17
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 19
Legal information. . . . . . . . . . . . . . . . . . . . . . . 20
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 20
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Contact information. . . . . . . . . . . . . . . . . . . . . 21
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2016.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 24 May 2016
Document identifier: PCA9517A