PCA9615
2-channel multipoint Fast-mode Plus differential I2C-bus
buffer with hot-swap logic
Rev. 1.1 — 10 May 2016
Product data sheet
1. General description
The PCA9615 is a Fast-mode Plus (Fm+) SMBus/I2C-bus buffer that extends the normal
single-ended SMBus/I2C-bus through electrically noisy environments using a differential
SMBus/I2C-bus (dI2C) physical layer, which is transparent to the SMBus/I2C-bus protocol
layer. It consists of two single-ended to differential driver channels for the SCL (serial
clock) and SDA (serial data).
The use of differential transmission lines between identical dI2C bus buffers removes
electrical noise and common-mode offsets that are present when signal lines must pass
between different voltage domains, are bundled with hostile signals, or run adjacent to
electrical noise sources, such as high energy power supplies and electric motors.
The SMBus/I2C-bus was conceived as a simple slow speed digital link for short runs,
typically on a single PCB or between adjacent PCBs with a common ground connection.
Applications that extend the bus length or run long cables require careful design to
preserve noise margin and reject interference.
The dI2C-bus buffers were designed to solve these problems and are ideally suited for
rugged high noise environments and/or longer cable applications, allow multiple slaves,
and operate at bus speeds up to 1 MHz clock rate. Cables can be extended to at least
3 meters (3 m), or longer cable runs at lower clock speeds. The dI2C-bus buffers are
compatible with existing SMBus/I2C-bus devices and can drive Standard, Fast-mode, and
Fast-mode Plus devices on the single-ended side.
Signal direction is automatic, and requires no external control. To prevent bus latch up,
the standard SMBus/I2C-bus side of the bus buffer, the PCA9615 employs static offset,
care should be taken when connecting these to other SMBus/I2C-bus buffers that may not
operate with offset.
This device is a bridge between the normal 2-wire single-ended wired-OR SMBus/I2C-bus
and the 4-wire dI2C-bus.
Additional circuitry allows the PCA9615 to be used for ‘hot swap’ applications, where
systems are always on, but require insertion or removal of modules or cards without
disruption to existing signals.
The PCA9615 has two supply voltages, VDD(A) and VDD(B). VDD(A), the card side supply,
only serves as a reference and ranges from 2.3 V to 5.5 V. VDD(B), the line side supply,
serves as the majority supply for circuitry and ranges from 3.0 V to 5.5 V.
PCA9615
NXP Semiconductors
2-channel multipoint Fm+ dI2C-bus buffer with hot-swap logic
single-ended
I2C-bus
VDD(A)1 VDD(B)
VDD(B)
dI2C-bus
(differential I2C-bus,
1 of 2 lines shown)
VDD(B)
VDD(B) VDD(A)2
single-ended
I2C-bus
SCL
SCL
PCA9615
PCA9615
SDA
SDA
twisted-pair cable
EN
GND1
EN
GND2
aaa-011961
Fig 1.
SMBus/I2C-bus translation to dI2C-bus and back to SMBus/I2C-bus
2. Features and benefits
New dI2C-bus buffers offer improved resistance to system noise and ground offset up
to 1⁄2 of supply voltage
2 channel dI2C (differential I2C-bus) to Fm+ single-ended buffer operating up to 1 MHz
with 30 mA SDA/SCL drive capability
Hot swap (allows insertion or removal of modules or card without disruption to bus
data)
EN signal (PCA9615 input) controls PCA9615 hot swap sequence
Bus idle detect (PCA9615 internal function) waits for a bus idle condition before
connection is made
Compatible with I2C-bus Standard/Fast-mode and SMBus, Fast-mode Plus up to
1 MHz
Single-ended I2C-bus on card side up to 540 pF
Differential I2C-bus on cable side supporting multi-drop bus
Maximum cable length: 3 m (approximately 10 feet) (longer at lower frequency)
dI2C output: 1.5 V differential output with nominal terminals
Differential line impedance (user defined): 100 nominal suggested
Receive input sensitivity: 200 mV
Hysteresis: 30 mV typical
Input impedance: high-impedance (200 k typical)
Receive input voltage range: 0.5 V to +5.5 V
Lock-up free operation
Supports arbitration and clock stretching across the dI2C-bus buffers
Powered-off and powering-up high-impedance I2C-bus pins
Operating supply voltage (VDD(A)) range of 2.3 V to 5.5 V with single-ended side 5.5 V
tolerant
Differential I2C-bus operating supply voltage (VDD(B)) range of 3.0 V to 5.5 V with
5.5 V tolerant. Best operation is at 5 V.
ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per
JESD22-C101
Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
PCA9615
Product data sheet
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Rev. 1.1 — 10 May 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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PCA9615
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2-channel multipoint Fm+ dI2C-bus buffer with hot-swap logic
Package offering: TSSOP10
3. Applications
Monitor remote temperature/leak detectors in harsh environment
Control of power supplies in high noise environment
Transmission of I2C-bus between equipment cabinets
Commercial lighting and industrial heating/cooling control
Any application that requires long I2C-bus runs in electrically noisy environments
Any application with multiple power suppliers and the potential for ground offsets up to
2.5 V
4. Ordering information
Table 1.
Ordering information
Type number
PCA9615DP
Topside
marking
Package
Name
Description
Version
P9615
TSSOP10
plastic thin shrink small outline package; 10 leads;
body width 3 mm
SOT552-1
4.1 Ordering options
Table 2.
Ordering options
Type number
Orderable part
number
Package
Packing method
Minimum
order quantity
Temperature range
PCA9615DP
PCA9615DPJ
TSSOP10
Reel 13” Q1/T1
*standard mark SMD
2500
Tamb = 40 C to +85 C
PCA9615
Product data sheet
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Rev. 1.1 — 10 May 2016
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PCA9615
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2-channel multipoint Fm+ dI2C-bus buffer with hot-swap logic
5. Block diagram
PCA9615
connect
connect
DSCLP
SCL
DSCLM
DSDAP
SDA
DSDAM
VDD(A)
I2C-BUS
HOT SWAP LOGIC
EN
en
VDD(A)
VDD(B)
POWER-ON RESET,
PLUG-IN DETECTION
AND DEBOUNCING
VSS
002aah765
Fig 2.
Block diagram (level 0)
DSCLP, DSDAP
VDD
DSCLM, DSDAM
aaa-011989
Fig 3.
PCA9615
Product data sheet
Differential output driver simplified circuit
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Rev. 1.1 — 10 May 2016
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PCA9615
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2-channel multipoint Fm+ dI2C-bus buffer with hot-swap logic
6. Pinning information
6.1 Pinning
VDD(A)
1
SDA
2
EN
3
SCL
VSS
10 VDD(B)
9
DSDAM
8
DSDAP
4
7
DSCLP
5
6
DSCLM
PCA9615DP
002aah766
Fig 4.
Pin configuration for TSSOP10
6.2 Pin description
Table 3.
PCA9615
Product data sheet
Pin description
Symbol
Pin
Description
VDD(A)
1
I2C-bus side power supply (2.3 V to 5.5 V)
SDA
2
card side open-drain serial data input/output
EN
3
enable input (active HIGH); internal pull-up resistor to VDD(A)
SCL
4
card side open-drain serial clock input/output
VSS
5
ground supply voltage (0 V)
DSCLM
6
line side differential open-drain clock minus input/output
DSCLP
7
line side differential open-drain clock plus input/output
DSDAP
8
line side differential open-drain data plus input/output
DSDAM
9
line side differential open-drain data minus input/output
VDD(B)
10
differential side power supply (3.0 V to 5.5 V)
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Rev. 1.1 — 10 May 2016
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PCA9615
NXP Semiconductors
2-channel multipoint Fm+ dI2C-bus buffer with hot-swap logic
7. Functional description
Refer to Figure 2.
The PCA9615 is used at each node of the dI2C-bus signal path, to provide conversion
from the dI2C-bus signal format to conventional I2C-bus/SMBus, allowing the connection
of existing I2C-bus/SMBus devices as slaves or the bus master. Because the signal
voltages on the I2C-bus/SMBus bus side may be different from the dI2C-bus side, there
are two power supply pins and a common ground. To prevent bus latch-up, the
I2C-bus/SMBus side employs static offset. Signal direction is determined by the
I2C-bus/SMBus bus protocol, and does not require a direction signal, as these bus buffers
automatically set signal flow direction. An enable pin (EN) is provided to disable the bus
buffer, and is useful for fault finding, power-up sequencing, or reconfiguration of a large
bus system by isolating sections not needed at all times.
Construction of the differential transmission line is not device-dependent. PCB traces,
open wiring, twisted-pair cables or a combination of these may be used. Twisted-pair
cables offer the best performance. A typical twisted-pair transmission line cable has a
characteristic impedance of ‘about 100 ’ and must be terminated at both ends in 100
to prevent unwanted signal reflections. Multiple nodes (each using a dI2C-bus buffer) may
be connected at any point along this transmission line, however, the stub length degrades
the bus performance, and should therefore be minimized.
7.1 I2C-bus/SMBus side
The I2C-bus/SMBus side of the PCA9615 differential bus buffer is connected to other
I2C-bus/SMBus devices and requires pull-up resistors on each of the SCL and SDA
signals. The value of the resistor should be chosen based on the bus capacitance and
desired data speed, being careful not to overload the driver current rating of 3 mA for
Standard and Fast modes, 30 mA for Fast-mode Plus (Fm+). The I2C-bus/SMBus side of
the PCA9615 is powered from the VDD(A) supply pin.
7.2 dI2C-bus side differential pair
In previous I2C-bus/SMBus designs, the nodes (Master and one or more Slaves) are
connected by wired-OR in combination with a single pull-up resistor. This simple
arrangement is not suited for long distances more than 1 meter (1 m) or about 3 feet (3 ft),
due to ringing and reflections on the un-terminated bus. The use of a transmission line
with correct termination eliminates this problem, and is further improved by differential
signaling used in the dI2C-bus scheme. Each node acts as both a driver and a receiver to
allow bidirectional signal flow, but not at the same time. Switching from transmit to receive
is done automatically. The dI2C-bus side of the PCA9615 is powered from the VDD(B)
supply pin.
The dI2C-bus is also biased to an idle state (D+ more positive than D) to be compatible
with the I2C-bus/SMBus wired-OR scheme, when not transmitting traffic (data). This
allows every node to receive broadcast messages from the Master, and return ACK/NACK
and data in response. Biasing is done with additional resistors, connected to VDD(B) and
VSS (the local ground), as shown in Figure 5. The transmission line is terminated in the
characteristic impedance of the cable, typically 100 . This is the value defined by three
resistors, the other two resistors providing the idle condition bias to the twisted pair.
PCA9615
Product data sheet
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Rev. 1.1 — 10 May 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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PCA9615
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2-channel multipoint Fm+ dI2C-bus buffer with hot-swap logic
DxxxP
DxxxP
DxxxM
DxxxM
twisted-pair cable
aaa-011061
Fig 5.
dI2C-bus terminations
7.2.1 Noise rejection
Impulse noise coupled into the I2C-bus/SMBus signals can prevent the I2C-bus/SMBus
bus from operating reliably. The hostile signals may appear on the SCL line, SDA line, or
both. Impulse noise may also enter the common ground connection, or be caused by
current in the ground path caused by DC power supplies, or other signals sharing the
common ground return path. This problem is removed by using a differential transmission
line, in place of the I2C-bus/SMBus signal path. The dI2C-bus receiver (at each dI2C-bus
node) subtracts the signals on the two differential lines (D+ and D), and eliminates any
common-mode noise that is coupled into the dI2C-bus. The receiver amplifies the signals
which are also attenuated by the bulk resistance of the transmission line cable
connection, and does not rely on a common ground connection at each node.
7.2.2 Rejection of ground offset voltage
Hostile signals interfere with the I2C-bus/SMBus bus through the common ground
connection between each node. Current in this ground path causes an offset that may
cause false data or push the I2C-bus/SMBus signals outside of an acceptable range.
Unwanted ground offset can be caused by heavy DC current in the ground path, or
injection of ground current from AC signals, either of which may show up as false signals.
Because the dI2C-bus node receiver responds only to the difference between the two
dI2C-bus transmission lines, common-mode signals are ignored. There is no need to have
a ground connection between each of the nodes, which may be powered locally. Nodes
may also be powered by extra conductors (for VDD and ground) run with the dI2C-bus
signals. Voltage offsets caused by DC current in these additional wires are ignored by the
dI2C-bus receiver, which subtracts the two differential signals (D+ and D).
7.3 EN pin
Enable input to connect the device into the bus. When this pin is LOW, the device never
connects to the bus, and disconnect the SCL/SDA from differential SCL/SDA. When EN is
driven HIGH, and VDD(A) and VDD(B) are stable, the EN pin connects SDA/SCL to
differential SDA/SCL after a stop bit or bus idle has been detected on differential line bus.
It should never change state during an I2C-bus/SMBus operation because disabling
during a bus operation hangs the bus and enabling part way through a bus cycle could
confuse the I2C-bus/SMBus parts being enabled. The EN pin should only change state
when the global bus and the buffer port are in an idle state to prevent system failures.
PCA9615
Product data sheet
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Rev. 1.1 — 10 May 2016
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PCA9615
NXP Semiconductors
2-channel multipoint Fm+ dI2C-bus buffer with hot-swap logic
7.4 Hot swap and power-on reset
During a power-on sequence, an initialization circuit holds the PCA9615 in a disconnected
state, meaning all outputs — SDA, SCL and the differential pins DSCLP/DSCLM and
DSDAP/DSDAM — are in a high-impedance state. As the power supply rises (either
power-up or live insertion), the initialization circuit enters a state where the internal
references are stabilized and an internal timer is triggered. After 1 ms, power is applied to
the rest of the circuitry and the PCA9615 detects the status on the differential
DSCLP/DSCLM and DSDAP/DSDAM lines. When the differential lines are detected as
connected to a bus with valid termination, that is, both DSCLM/DSDAM < 0.9 VDD(B) and
DSCLP/DSDAP > 0.1 VDD(B), another timer is triggered. At the end of 10 ms, hot-swap
logic (Figure 2) is enabled and the EN pin can detect a Stop Bit and Bus Idle condition.
However, there is still no connection between SDA and DSDAP/DSDAM or between SCL
and DSCLP/DSCLM. A successful EN pin sequence must occur for actual connection.
When the EN pin is set HIGH and the DSDAP and DSCLP pins have been HIGH for the
bus idle time or when both the SCL and SDA pins are HIGH and a STOP condition has
been seen on the differential bus (DSDAP/DSDAM and DSCLP/DSCLM pins), a
connection is established between the differential and the single-ended buses. Whenever
disconnected status is detected or the device is unpowered, the PCA9615 disconnects
the single-ended to differential buses, and the hot swap sequence repeats again before
the PCA9615 connects SDA to DSDAP/DSDAM and SCL to DSCLP/DSCLM.
Remark: Start-up process is the same for both PCA9616PW and PCA9615DP, except
that PIDET and READY signals are only available in 16-pin package.
VDD(A), VDD(B)
~11 ms
ten for power-on
and stabilization
~1 ms
pwon
~10 ms
plug-in debouncing time
not allowed
only when EN goes HIGH,
11 ms after plug-in,
will the bus idle/stop detector
start functioning
EN
SCL/SDA,
DSCL/DSDA
100 μs
tidle
tstop
connect differential
to single-ended bus
002aah774
For PCA9615, the ready time is at least 11 ms (1 ms for power ready, 10 ms for plug-in debouncing
delay), which means the device can only be in operation after 11 ms with VDD(A), VDD(B) ON and a
bus idle/stop detected; tidle = 100 s
Fig 6.
PCA9615
Product data sheet
Hot swap related timings
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Rev. 1.1 — 10 May 2016
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PCA9615
NXP Semiconductors
2-channel multipoint Fm+ dI2C-bus buffer with hot-swap logic
8. Application design-in information
8.1 I2C-bus
As with the standard I2C-bus system, pull-up resistors are required to provide the logic
HIGH levels on the single-ended buffered bus (standard open-drain configuration of the
I2C-bus). The size of these pull-up resistors depends on the system. The device is
designed to work with Standard-mode, Fast-mode and Fast-mode Plus I2C-bus devices in
addition to SMBus devices. Standard-mode and Fast-mode I2C-bus and SMBus devices
only specify 3 mA output drive; this limits the termination current to 3 mA in a generic
I2C-bus system where Standard-mode devices and multiple masters are possible. When
only Fast-mode Plus devices are used, then higher termination currents can be used due
to their 30 mA sink capability.
8.2 Differential I2C-bus application
See Figure 7 through Figure 9.
The simple application (Figure 7) shows an existing SMBus/I2C-bus being extended over
a section of dI2C-bus transmission line, containing a dedicated twisted pair for SCL and
SDA. At one end of the transmission line, a resistor network (R1-R2-R1) terminates the
twisted-pair cable and biases D+ positive with respect to D. An identical resistor network
at the other end of the transmission line terminates the twisted-pair cable. DC power for
each end of the transmission line and the VDD(B) of each PCA9615 bus buffer can be from
separate and isolated power supplies, or use the same supply and ground run in separate
wires along the same path as the dI2C-bus signal twisted pairs.
Telecom category 5 (‘CAT 5’) data cable is well suited for this task, but loose wires may
also be used, with a reduction in performance. Assuming VDD(B) is 5 V, and using CAT 5
cable, R2 is 120 , R1 is 600 . The parallel combination yields a termination of 100 at
each end of the twisted pairs.
Either side of the dI2C-bus buffer pair is connected to standard SMBus/I2C buses, which
require their own pull-up resistors to VDD(A) of the PCA9615 bus buffers. VDD(A) and VDD(B)
can be the same supply, however, making them different voltages enables the PCA9615
bus buffers to level translate between the SMBus/I2C-bus and dI2C-bus sections of the
bus, or to have different supply voltages and level translate at either end of the dI2C-bus
and SMBus/I2C-bus system.
For example, the left-hand bus master (and local slave) may operate on a 3.3 V supply
and SMBus/I2C-bus while the dI2C-bus transmission lines are at 5 V, and the right-hand
slave is operated from a different 3.3 V supply and SMBus/I2C-bus, or even a different bus
voltage other than 3.3 V.
Depending upon the timing from the system master, clock toggle rates can vary from
10 kHz for the SMBus (or less for SMBus/I2C-bus protocol) up to 100 kHz (Standard
mode), 400 kHz (Fast mode), or up to 1 MHz (Fast-mode Plus).
The bus path is bidirectional. Assume that the left side SMBus/I2C-bus becomes active. A
START condition (SDA goes LOW while SDA is HIGH) is sent. This upsets the idle
condition on the dI2C-bus section of the bus, because D+ was more positive than D and
PCA9615
Product data sheet
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PCA9615
NXP Semiconductors
2-channel multipoint Fm+ dI2C-bus buffer with hot-swap logic
now they are reversed. The right side bus buffer sees the differential lines change polarity
and in turn pulls SDA LOW on the SMBus/I2C-bus side of the bus buffer, transmitting the
START condition to the slave on that section of the SMBus/I2C-bus.
If the data clocked out by the left side master contains a valid address of the right side
slave, that slave responds by pulling SDA LOW on the ninth clock. This condition is
transmitted across the dI2C-bus section that has now changed flow direction, and
received by the left side bus buffer (again, D+ was more positive than D and now they
are reversed).
This sequence continues until the master sends the STOP condition (SCL HIGH while
SDA goes HIGH), placing the active slave (on the right side) back to idle. When idle, the
normal SMBus/I2C-bus (both left and right sections) are pulled up by their respective
pull-ups. In turn, the dI2C-bus section of the bus rests with D+ more positive than D.
The idle condition can be changed by any node on either SMBus/I2C-bus section or an
additional dI2C-bus node, if present, on the dI2C-bus section of the system. This allows
the existing SMBus/I2C-bus protocol to operate transparently over a mix of SMBus/I2C
and dI2C bus segments.
Due to the SMBus/I2C-bus handshake protocol (ACK/NACK on the ninth clock pulse), the
direction of the SMBus/I2C-bus is reversed often. The ‘time of flight’ for the signals to pass
through each bus buffer and for the target slave to respond defines the maximum speed of
the bus, regardless of how fast the clock toggles. The dI2C-bus section of the bus requires
two additional PCA9615 bus buffers, further delaying the SMBus/I2C-bus traffic. If the
dI2C-bus transmission line section is made longer, the bus operates much slower,
regardless of the clock toggle speed.
It is not necessary to have a ground connection between each end of the dI2C section of
the bus. The dI2C-bus receiver responds to reversal of the polarity of the D+ and D
signals, and ignores the common-mode voltage that may be present.
Ideally, the common-mode voltage is the same at each end of the twisted pairs, and no
current flows along the twisted pair when the bus is idle, because the D+ and D dI2C-bus
drivers are both high-impedance, the bus is biased by R1-R2-R1 at each end. If the
common-mode voltage is not 0 V, current flows along the twisted pair, returning through
the common ground or common power supply connection if present.
If both ends of the twisted pair are powered by the same VDD(B) supply and one end is
remote, there will be a common-mode offset between them. This is ignored by the
dI2C-bus receivers, which only respond to the difference between D+ and D.
However, a large common-mode offset voltage forces the D+ and D signals out of the
range of the receiver, and data are lost. The PCA9615 bus buffers use standard ESD
protection networks to protect the external pins, and therefore should not be biased above
or below the VDD(B) and VSS pins respectively. This limits the common-mode range to
approximately 0.5 VDD(B).
DC resistance of the transmission line attenuates the signals, more so over longer
distances. The loss of signal amplitude is made up by the gain of the dI2C-bus receiver.
There is a limit to how long the dI2C-bus section can be made, as it is necessary for the
driver to overcome the bias on the transmission line, in order to signal a polarity change
(D+ and D reversal) at the receiver end.
PCA9615
Product data sheet
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Rev. 1.1 — 10 May 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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PCA9615
NXP Semiconductors
2-channel multipoint Fm+ dI2C-bus buffer with hot-swap logic
VDD(B)1
optional
R1
VDD(A)1
VDD(B)2
R1
VDD(A)2
DSCLP
R2
R2
R1
R1
DSCLM
SCL
SCL
SDA PCA9615
PCA9615 SDA
R1
R1
R2
R2
DSDAP
MASTER
SLAVE
SLAVE
MASTER
DSDAM
R1
R1
optional
VSS1
CARD
VSS2
CARD
002aah767
Fig 7.
Typical application for PCA9615
PCA9615
Product data sheet
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Rev. 1.1 — 10 May 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
11 of 29
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NXP Semiconductors
PCA9615
Product data sheet
VDD(B)
VDD(A)
DSCLP
termination
SDA
DSDAP
VDD(B)
DSDAM
MASTER
VDD(B)
SLAVE
VSS
VDD
VDD
VSS
VSS
CARD
PCA9615
PCA9615
PCA9615
optional
SLAVE
CARD
MASTER
SLAVE
VDD(A)
CARD
MASTER
SLAVE
VDD(A)
CARD
MASTER
VDD(A)
002aah768
Remark: There is only one ground pin on the PCA9615, so the single-ended I2C-bus signals that are not ground offset tolerant must be referenced to the ground pin on
the part. And any ground offset must be on the differential side where the differential input and output can tolerate a ground offset of up to 0.5 VDD(B).
Fig 8.
PCA9615 application diagram; VDD and VSS are routed through the cable
PCA9615
12 of 29
© NXP Semiconductors N.V. 2016. All rights reserved.
Remark: Keep drops as short as possible.
2-channel multipoint Fm+ dI2C-bus buffer with hot-swap logic
Rev. 1.1 — 10 May 2016
All information provided in this document is subject to legal disclaimers.
SCL
PCA9615
DSCLM
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xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
NXP Semiconductors
PCA9615
Product data sheet
VDD(B)
PCA9615
MASTER
CARD
SLAVE
VDD(A)
MASTER
CARD
SLAVE
VDD(A)
CARD
MASTER
VDD(A)
VDD(B)
VDD(A)
SCL
SDA
MASTER
CARD
SLAVE
PCA9615
DSCLP
DSCLM
DSDAP
DSDAM
VSS
PCA9615
CARD
MASTER
SLAVE
VDD(A)
PCA9615
MASTER
CARD
SLAVE
VDD(A)
CARD
PCA9615
MASTER
SLAVE
VDD(A)
CARD
MASTER
VDD(A)
002aah769
Fig 9.
PCA9615 application diagram; VDD and VSS are not routed through the cable
PCA9615
13 of 29
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SLAVE
PCA9615
2-channel multipoint Fm+ dI2C-bus buffer with hot-swap logic
Rev. 1.1 — 10 May 2016
All information provided in this document is subject to legal disclaimers.
SLAVE
VSS
PCA9615
PCA9615
PCA9615
NXP Semiconductors
2-channel multipoint Fm+ dI2C-bus buffer with hot-swap logic
Backplane connector
PCA9615
3.3 V
5V
VDD(A)
VDD(B)
EN
DSCL
SCL
DSDA
SDA
MASTER
VSS
Differential terminations
are always on backplane.
Card with master.
PCA9615
VDD(A)
VDD(B)
EN
DSCL
SCL
DSDA
SDA
SLAVE
VSS
Card without master.
002aah770
Fig 10. Hot swap application
PCA9615
Product data sheet
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2-channel multipoint Fm+ dI2C-bus buffer with hot-swap logic
aaa-011062
Fig 11. Differential bus waveform
9th clock pulse
acknowledge
SCL
VOL of PCA9615 (from slave)
SDA
002aah771
VOL of master
Fig 12. Single-ended bus waveform (master side of bus)
PCA9615
Product data sheet
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2-channel multipoint Fm+ dI2C-bus buffer with hot-swap logic
9. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Min
Max
Unit
VDD(B)
supply voltage port B
differential bus; 3.0 V to 5.5 V
0.5
+6
V
VDD(A)
supply voltage port A
single-ended bus; 2.3 V to 5.5 V
0.5
+6
V
VO(dif)
differential output voltage
0.5
+6
V
0.5
+6
V
-
80
mA
I2C-bus
Vbus
bus voltage
voltage on
II/O
input/output current
SDA, SCL, Dxxxx
IDD(B)
supply current port B
-
160
mA
Ptot
total power dissipation
-
100
mW
Tstg
storage temperature
55
+125
C
Tamb
ambient temperature
40
+85
C
Tj
junction temperature
-
125
C
PCA9615
Product data sheet
A side, or enable (EN)
operating in free air
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2-channel multipoint Fm+ dI2C-bus buffer with hot-swap logic
10. Static characteristics
Table 5.
Static characteristics
VDD(B) = 3.0 V to 5.5 V; VSS = 0 V; Tamb = 40 C to +85 C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Supplies
VDD(B)
supply voltage port B
differential bus
VDD(A)
supply voltage port A
single-ended bus
IDD(VDDA) supply current on
pin VDD(A)
[1]
3.0
-
5.5
V
2.3
-
5.5
V
-
-
16
A
IDDH(B)
port B HIGH-level supply
current
both channels HIGH; VDD(B) = 5.5 V;
SDAn = SCLn = VDD(A) = 5.5 V
-
0.8
1.6
mA
IDDL(B)
port B LOW-level supply
current
both channels LOW; VDD(B) = 5.5 V;
SDA and SCL = VSS; differential I/Os open
-
1.1
1.8
mA
driving termination; 2 channel
-
70
91
mA
Input and output SDA and SCL
VIH
HIGH-level input voltage
0.7VDD(A) -
5.5
V
VIL
LOW-level input voltage
0.5
+0.4
V
VIK
input clamping voltage
II = 18 mA
1.5
-
0
V
ILI
input leakage current
VI = VDD(A)
-
-
2
A
IIL
LOW-level input current
SDA, SCL; VI = 0.2 V
-
-
12
A
VOL
LOW-level output voltage
IOL = 200 A or 30 mA
0.47
0.52
0.6
V
VOLVIL
difference between
LOW-level output and
LOW-level input voltage
guaranteed by design
-
-
90
mV
ILOH
HIGH-level output leakage VO = VDD(A)
current
-
-
2
A
Cio
input/output capacitance
-
7
10
pF
0
-
VDD(B)
V
VI = VDD(A) or 0 V; disabled or VDD(A) = 0 V
-
Input and output DSDAP/DSDAM and DSCLP/DSCLM
Vcm
common-mode voltage
ILI
input leakage current
VI = VDD(B)
-
-
40
A
IIL
LOW-level input current
VI = 0.2 V
-
-
40
A
RPU
pull-up resistance
internal pull-up resistor on DSCLM and
DSDAM connected to VDD(B) rail
-
200
-
k
Rpd
pull-down resistance
internal pull-down resistor on DSCLP and
DSDAP connected to VSS rail
-
200
-
k
Vth(dif)
differential receiver
threshold voltage
0 V Vcm VDD(B)
200
-
+200
mV
VI(hys)
hysteresis of input voltage receiver; 0 V Vcm VDD(B)
-
30
-
mV
no load
VDD(B)
-
-
V
RL = 54 at VDD(B) = 5 V
5.0
1.5
1.0
V
-
7
10
pF
Vo(dif)(p-p) peak-to-peak differential
output voltage
Cio
input/output capacitance
PCA9615
Product data sheet
single-ended input LOW
VI = VDD(B) or 0 V; disabled or VDD(B) = 0 V
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2-channel multipoint Fm+ dI2C-bus buffer with hot-swap logic
Table 5.
Static characteristics …continued
VDD(B) = 3.0 V to 5.5 V; VSS = 0 V; Tamb = 40 C to +85 C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
0.7VDD(A) -
5.5
V
Input EN
VIH
HIGH-level input voltage
VIL
LOW-level input voltage
0.5
-
+0.3VDD(A) V
ILI
input leakage current
VI = VDD(B)
1
-
+1
A
IIL(EN)
LOW-level input current
on pin EN
VI = 0.2 V, EN; VDD(A) = 5.5 V
-
20
54
A
Ci
input capacitance
VI = VDD(A)
-
6
10
pF
RPU
pull-up resistance
internal pull-up resistor connected to
VDD(A) rail
-
300
-
k
[1]
LOW-level supply voltage.
11. Dynamic characteristics
Table 6.
Dynamic characteristics
VDD = 2.7 V to 5.5 V; VSS = 0 V; Tamb = 40 C to +85 C; unless otherwise specified.[1][2]
Symbol
Parameter
Conditions
tPLH
LOW to HIGH propagation delay single-ended side to differential side;
Figure 15
tPLH2
LOW to HIGH propagation
delay 2
tPHL
HIGH to LOW propagation delay single-ended side to differential side;
Figure 13
SRr
rising slew rate
falling slew rate
SRf
[4]
single-ended side to differential side;
Figure 15
[5]
differential side; Figure 13
differential side; Figure 13
Min
Typ[3]
Max
Unit
140
120
-
ns
-
-
100
ns
-
-
120
ns
-
-
1
V/ns
[5]
-
-
1
V/ns
-
-
150
ns
-
-
150
ns
-
-
0.1
V/ns
-
-
200
ns
tPLH
LOW to HIGH propagation delay differential side to single-ended side;
Figure 14
[6]
tPHL
HIGH to LOW propagation delay differential side to single-ended side;
Figure 14
[6]
SRf
falling slew rate
single-ended side; Figure 14
tdis
disable time
EN LOW to disable
[7]
[1]
Times are specified with loads of 1.35 k pull-up resistance and 50 pF load capacitance on the A side, and 50 termination network
resistance and 50 pF load capacitance on the B side. Different load resistance and capacitance alters the RC time constant, thereby
changing the propagation delay and transition times.
[2]
Pull-up voltages are VDD(A) on the A side and termination network on the B side.
[3]
Typical values were measured with VDD(A) = 3.3 V at Tamb = 25 C, unless otherwise noted.
[4]
The tPLH delay data from B side to A side is measured at 0 V differential on the B side to 0.5VDD(A) on the A side.
[5]
Typical value measured with VDD(A) = 3.3 V at Tamb = 25 C.
[6]
The proportional delay data from A side to B side is measured at 0.5VDD(A) on the A side to 0 V on the B side.
[7]
The enable pin (EN) should only change state when the global bus and the repeater port are in an idle state.
PCA9615
Product data sheet
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2-channel multipoint Fm+ dI2C-bus buffer with hot-swap logic
11.1 AC waveforms
VDD(A)
input
0.5VDD(A)
0.5VDD(A)
tPHL
tPLH
80 %
output
0V
20 %
0V
20 %
tTHL
input
0.1 V
80 %
0.3 V
differential
voltage
−2.5 V
0V
0V
tPHL
tPLH
80 %
output
0.5VDD(A) 0.5VDD(A)
20 %
20 %
tTLH
tTHL
002aag416
0.3 V
differential
voltage
−0.3 V
80 %
VDD(A)
tTLH
002aag417
VDD(A) = 3.0 V.
VDD(A) = 3.0 V.
SRf = 0.6 (Vhigh Vlow) / tTHL
SRf = 0.6 ´ VDD(A) / tTHL
SRr = 0.6 (Vhigh Vlow) / tTLH
Fig 13. Propagation delay and transition times;
single-ended side to differential side
Fig 14. Propagation delay and transition times;
differential side to single-ended side
tPLH
0.5VDD(A)
input
SDA, SCL
0.5 V
0.3 V
output
DSCLP/DSCLM,
DSDAP/DSDAM
0V
tPLH2
−2.5 V
002aag418
Fig 15. Propagation delay
PCA9615
Product data sheet
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2-channel multipoint Fm+ dI2C-bus buffer with hot-swap logic
12. Test information
VDD(B)
VDD(A)
VDD(B)
VDD(A)
I2C-BUS
LEVEL SHIFTER
PULSE
GENERATOR
VI
DUT
300 Ω
VO
P
M
60 Ω
DIFFERENTIAL
PROBE
RT
300 Ω
002aag419
RL = load resistor; 1.35 k on single-ended side.
RT = termination resistance should be equal to Zo of pulse generators.
Fig 16. Test circuit for differential outputs
VDD(A)
VDD(A)
VDD(B)
DIFFERENTIAL
RT
P
DUT
M
RL
VO
CL
002aag420
RL = load resistor; 1.35 k on single-ended side.
CL = load capacitance includes jig and probe capacitance; 50 pF.
RT = termination resistance should be equal to Zo of pulse generators.
Fig 17. Test circuit for open-drain output
PCA9615
Product data sheet
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2-channel multipoint Fm+ dI2C-bus buffer with hot-swap logic
13. Package outline
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627
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=
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SLQLQGH[
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ș
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ES
PP
VFDOH
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81,7
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PD[
$
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$
ES
F
' ( H
+(
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Y
Z
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PP
1RWHV
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3ODVWLFRUPHWDOSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG
287/,1(
9(56,21
627
5()(5(1&(6
,(&
-('(&
-(,7$
(8523($1
352-(&7,21
,668('$7(
Fig 18. Package outline SOT552-1 (TSSOP10)
PCA9615
Product data sheet
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PCA9615
NXP Semiconductors
2-channel multipoint Fm+ dI2C-bus buffer with hot-swap logic
14. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
14.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
14.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•
•
•
•
•
•
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering
14.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
PCA9615
Product data sheet
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PCA9615
NXP Semiconductors
2-channel multipoint Fm+ dI2C-bus buffer with hot-swap logic
14.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 19) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 7 and 8
Table 7.
SnPb eutectic process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
350
< 2.5
235
220
2.5
220
220
Table 8.
Lead-free process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 19.
PCA9615
Product data sheet
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NXP Semiconductors
2-channel multipoint Fm+ dI2C-bus buffer with hot-swap logic
temperature
maximum peak temperature
= MSL limit, damage level
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 19. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
PCA9615
Product data sheet
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PCA9615
NXP Semiconductors
2-channel multipoint Fm+ dI2C-bus buffer with hot-swap logic
15. Soldering: PCB footprints
)RRWSULQWLQIRUPDWLRQIRUUHIORZVROGHULQJRI76623SDFNDJH
627
+[
3
+\
*\
VROGHUODQG
RFFXSLHGDUHD
'LPHQVLRQVLQPP
*\
+\
+[
3
,VVXHGDWH
VRWBIU
Fig 20. PCB footprint for SOT552-1 (TSSOP10); reflow soldering
PCA9615
Product data sheet
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Rev. 1.1 — 10 May 2016
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NXP Semiconductors
2-channel multipoint Fm+ dI2C-bus buffer with hot-swap logic
16. Abbreviations
Table 9.
Abbreviations
Acronym
Description
CDM
Charged-Device Model
dI2C-bus
differential Inter-Integrated Circuit bus
ESD
ElectroStatic Discharge
HBM
Human Body Model
I2C-bus
Inter-Integrated Circuit bus
I/O
Input/Output
LED
Light Emitting Diode
SMBus
System Management Bus
17. Revision history
Table 10.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
PCA9615 v.1.1
20160510
Product data sheet
-
PCA9615 v.1
Modifications:
PCA9615 v.1
PCA9615
Product data sheet
•
Added “tidle = 100 s” to Figure 6 “Hot swap related timings”
20140502
Product data sheet
-
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Rev. 1.1 — 10 May 2016
-
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2-channel multipoint Fm+ dI2C-bus buffer with hot-swap logic
18. Legal information
18.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
18.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
18.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
PCA9615
Product data sheet
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 10 May 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
27 of 29
PCA9615
NXP Semiconductors
2-channel multipoint Fm+ dI2C-bus buffer with hot-swap logic
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
18.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I2C-bus — logo is a trademark of NXP B.V.
19. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
PCA9615
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 10 May 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
28 of 29
PCA9615
NXP Semiconductors
2-channel multipoint Fm+ dI2C-bus buffer with hot-swap logic
20. Contents
1
2
3
4
4.1
5
6
6.1
6.2
7
7.1
7.2
7.2.1
7.2.2
7.3
7.4
8
8.1
8.2
9
10
11
11.1
12
13
14
14.1
14.2
14.3
14.4
15
16
17
18
18.1
18.2
18.3
18.4
19
20
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 2
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Ordering information . . . . . . . . . . . . . . . . . . . . . 3
Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pinning information . . . . . . . . . . . . . . . . . . . . . . 5
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
Functional description . . . . . . . . . . . . . . . . . . . 6
I2C-bus/SMBus side . . . . . . . . . . . . . . . . . . . . . 6
dI2C-bus side differential pair . . . . . . . . . . . . . . 6
Noise rejection . . . . . . . . . . . . . . . . . . . . . . . . . 7
Rejection of ground offset voltage . . . . . . . . . . 7
EN pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Hot swap and power-on reset. . . . . . . . . . . . . . 8
Application design-in information . . . . . . . . . . 9
I2C-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Differential I2C-bus application . . . . . . . . . . . . . 9
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 16
Static characteristics. . . . . . . . . . . . . . . . . . . . 17
Dynamic characteristics . . . . . . . . . . . . . . . . . 18
AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . 19
Test information . . . . . . . . . . . . . . . . . . . . . . . . 20
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 21
Soldering of SMD packages . . . . . . . . . . . . . . 22
Introduction to soldering . . . . . . . . . . . . . . . . . 22
Wave and reflow soldering . . . . . . . . . . . . . . . 22
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 22
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 23
Soldering: PCB footprints. . . . . . . . . . . . . . . . 25
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 26
Legal information. . . . . . . . . . . . . . . . . . . . . . . 27
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 27
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Contact information. . . . . . . . . . . . . . . . . . . . . 28
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2016.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 10 May 2016
Document identifier: PCA9615