PCA9537 4-bit I2C-bus and SMBus low power I/O port with interrupt and reset Rev. 05 — 7 May 2009 Product data sheet 1. General description The PCA9537 is a 10-pin CMOS device that provides 4 bits of General Purpose parallel Input/Output (GPIO) expansion with interrupt and reset for I2C-bus/SMBus applications and was developed to enhance the NXP Semiconductors family of I2C-bus I/O expanders. I/O expanders provide a simple solution when additional I/O is needed for ACPI power switches, sensors, push-buttons, LEDs, fans, etc. The PCA9537 consists of a 4-bit Configuration register (input or output selection), 4-bit Input Port register, 4-bit Output Port register and a 4-bit Polarity Inversion register (active HIGH or active LOW operation). The system master can enable the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for each input or output is kept in the corresponding Input Port or Output Port register. The polarity of the Input Port register can be inverted with the Polarity Inversion register. All registers can be read by the system master. The PCA9537 open-drain interrupt output (INT) is activated when any input state differs from its corresponding Input Port register state and is used to indicate to the system master that an input state has changed. The power-on reset sets the registers to their default values and initializes the device state machine. The RESET pin causes the same reset/initialization to occur without de-powering the device. The I2C-bus address is fixed and allows only one device on the same I2C-bus/SMBus. 2. Features n n n n n n n n n n n n n 4-bit I2C-bus GPIO with interrupt and reset Operating power supply voltage range of 2.3 V to 5.5 V 5 V tolerant I/Os Polarity Inversion register Active LOW interrupt output Active LOW reset input Low standby current Noise filter on SCL/SDA inputs No glitch on power-up Internal power-on reset 4 I/O pins that default to 4 inputs 0 Hz to 400 kHz clock frequency ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101 PCA9537 NXP Semiconductors 4-bit I2C-bus and SMBus low power I/O port with interrupt and reset n Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA n Offered in TSSOP10 package 3. Ordering information Table 1. Ordering information Tamb = −40 °C to +85 °C Type number PCA9537DP Topside mark Package Name Description Version 9537 TSSOP10 plastic thin shrink small outline package; 10 leads; body width 3 mm SOT552-1 4. Block diagram PCA9537 IO0 SCL SDA INPUT FILTER IO1 4-bit I2C-BUS/SMBus CONTROL write pulse VDD RESET POWER-ON RESET VSS IO2 INPUT/ OUTPUT PORTS IO3 read pulse VDD INT LP FILTER 002aae634 Remark: All I/Os are set to inputs at reset. Fig 1. Block diagram of PCA9537 PCA9537_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 7 May 2009 2 of 24 PCA9537 NXP Semiconductors 4-bit I2C-bus and SMBus low power I/O port with interrupt and reset 5. Pinning information 5.1 Pinning 10 VDD 9 SDA IO0 1 IO1 2 IO2 3 8 SCL IO3 4 7 INT VSS 5 6 RESET PCA9537DP 002aae633 Fig 2. Pin configuration for TSSOP10 5.2 Pin description Table 2. Pin description Symbol Pin Description IO0 1 input/output 0 IO1 2 input/output 1 IO2 3 input/output 2 IO3 4 input/output 3 VSS 5 supply ground RESET 6 active LOW reset input INT 7 interrupt output (open-drain) SCL 8 serial clock line SDA 9 serial data line VDD 10 supply voltage PCA9537_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 7 May 2009 3 of 24 PCA9537 NXP Semiconductors 4-bit I2C-bus and SMBus low power I/O port with interrupt and reset 6. Functional description Refer to Figure 1 “Block diagram of PCA9537”. 6.1 Device address slave address 1 0 0 1 0 0 1 R/W fixed 002aae635 Fig 3. PCA9537 address 6.2 Registers 6.2.1 Command byte The command byte is the first byte to follow the address byte during a write transmission. It is used as a pointer to determine which of the registers will be written or read. Table 3. Command byte Command Protocol Function 0 read byte Input Port register 1 read/write byte Output Port register 2 read/write byte Polarity Inversion register 3 read/write byte Configuration register 6.2.2 Register 0 - Input Port register This register is a read-only port. It reflects the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by Register 3. Writes to this register have no effect. The default value ‘X’ is determined by the externally applied logic level. Table 4. Register 0 - Input Port register bit description Legend: * default value. Bit Symbol Access Value Description 7 I7 read only 1* not used 6 I6 read only 1* 5 I5 read only 1* 4 I4 read only 1* 3 I3 read only X* 2 I2 read only X* 1 I1 read only X* 0 I0 read only X* PCA9537_5 Product data sheet value ‘X’ is determined by externally applied logic level © NXP B.V. 2009. All rights reserved. Rev. 05 — 7 May 2009 4 of 24 PCA9537 NXP Semiconductors 4-bit I2C-bus and SMBus low power I/O port with interrupt and reset 6.2.3 Register 1 - Output Port register This register reflects the outgoing logic levels of the pins defined as outputs by Register 3. Bit values in this register have no effect on pins defined as inputs. Reads from this register return the value that is in the flip-flop controlling the output selection, not the actual pin value. Table 5. Register 1 - Output Port register bit description Legend: * default value. Bit Symbol Access Value Description 7 O7 R 1* not used 6 O6 R 1* 5 O5 R 1* 4 O4 R 1* 3 O3 R 1* 2 O2 R 1* 1 O1 R 1* 0 O0 R 1* reflects outgoing logic levels of pins defined as outputs by Register 3 6.2.4 Register 2 - Polarity Inversion register This register allows the user to invert the polarity of the Input Port register data. If a bit in this register is set (written with 1), the corresponding Input Port data is inverted. If a bit in this register is cleared (written with a 0), the Input Port data polarity is retained. Table 6. Register 2 - Polarity Inversion register bit description Legend: * default value. Bit Symbol Access Value Description 7 N7 R/W 0* not used 6 N6 R/W 0* 5 N5 R/W 0* 4 N4 R/W 0* 3 N3 R/W 0* 2 N2 R/W 0* 0 = Input Port register data retained (default value) 1 N1 R/W 0* 1 = Input Port register data inverted 0 N0 R/W 0* inverts polarity of Input Port register data PCA9537_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 7 May 2009 5 of 24 PCA9537 NXP Semiconductors 4-bit I2C-bus and SMBus low power I/O port with interrupt and reset 6.2.5 Register 3 - Configuration register This register configures the directions of the I/O pins. If a bit in this register is set, the corresponding port pin is enabled as an input with high-impedance output driver. If a bit in this register is cleared, the corresponding port pin is enabled as an output. At reset, the I/Os are configured as inputs. Table 7. Register 3 - Configuration register bit description Legend: * default value. Bit Symbol Access Value Description 7 C7 R/W 1* not used 6 C6 R/W 1* 5 C5 R/W 1* 4 C4 R/W 1* 3 C3 R/W 1* 2 C2 R/W 1* 0 = corresponding port pin enabled as an output 1 C1 R/W 1* 0 C0 R/W 1* 1 = corresponding port pin configured as an input (default value) configures the directions of the I/O pins 6.3 Power-on reset When power is applied to VDD, an internal Power-On Reset (POR) holds the PCA9537 in a reset condition until VDD has reached VPOR. At that point, the reset condition is released and the PCA9537 registers and state machine will initialize to their default states. Thereafter, VDD must be lowered below 0.2 V to reset the device. For a power reset cycle, VDD must be lowered below 0.2 V and then restored to the operating voltage. 6.4 RESET input A reset can be accomplished by holding the RESET pin LOW for a minimum of tw(rst). The PCA9537 registers and SMBus/I2C-bus state machine will be held in their default state until the RESET input is once again HIGH. This input requires a pull-up resistor to VDD if no active connection is used. 6.5 Interrupt output The open-drain interrupt output (INT) is activated when one of the port pins changes state and the pin is configured as an input. The interrupt is de-activated when the input returns to its previous state or the Input Port register is read. Note that changing an I/O from an output to an input may cause a false interrupt to occur if the state of the pin does not match the contents of the Input Port register. PCA9537_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 7 May 2009 6 of 24 PCA9537 NXP Semiconductors 4-bit I2C-bus and SMBus low power I/O port with interrupt and reset 6.6 I/O port When an I/O is configured as an input, FETs Q1 and Q2 are off, creating a high-impedance input. The input voltage may be raised above VDD to a maximum of 5.5 V. If the I/O is configured as an output, then either Q1 or Q2 is enabled, depending on the state of the Output Port register. Care should be exercised if an external voltage is applied to an I/O configured as an output because of the low-impedance paths that exist between the pin and either VDD or VSS. data from shift register output port register data configuration register data from shift register D VDD Q1 Q FF write configuration pulse write pulse CK Q D Q FF I/O pin Q2 CK output port register input port register D Q FF read pulse VSS input port register data CK to INT polarity inversion register data from shift register D Q FF write polarity pulse polarity inversion register data CK 002aad723 Remark: At power-on reset, all registers return to default values. Fig 4. Simplified schematic of IO0 to IO3 PCA9537_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 7 May 2009 7 of 24 PCA9537 NXP Semiconductors 4-bit I2C-bus and SMBus low power I/O port with interrupt and reset 6.7 Bus transactions Data is transmitted to the PCA9537 registers using the write mode as shown in Figure 5 and Figure 6. Data is read from the PCA9537 registers using the read mode as shown in Figure 7 and Figure 8. These devices do not implement an auto-increment function so once a command byte has been sent, the register which was addressed will continue to be accessed by reads until a new command byte has been sent. SCL 1 2 3 4 5 6 7 8 9 slave address SDA S 1 0 0 1 0 0 1 START condition 0 R/W A 0 0 0 0 0 0 STOP condition data to port command byte 0 1 A DATA 1 A acknowledge from slave acknowledge from slave acknowledge from slave P write to port tv(Q) data out from port DATA 1 VALID 002aae636 Expanded diagram is shown in Figure 16. Fig 5. Write to output port register SCL 1 2 3 4 5 6 7 8 9 slave address SDA S 1 0 0 1 START condition 0 0 1 0 R/W A 0 0 0 0 0 0 STOP condition data to register command byte 1 1/0 A acknowledge from slave acknowledge from slave DATA 1 A P acknowledge from slave data to register 002aae637 Fig 6. Write to configuration or polarity inversion registers PCA9537_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 7 May 2009 8 of 24 PCA9537 NXP Semiconductors 4-bit I2C-bus and SMBus low power I/O port with interrupt and reset slave address SDA S 1 0 0 1 0 0 1 START condition 0 A acknowledge from slave R/W acknowledge from slave slave address (cont.) S 1 0 0 1 0 Fig 7. data from register 0 (repeated) START condition (cont.) A COMMAND BYTE 1 1 A data from register DATA (first byte) A R/W DATA (last byte) acknowledge from master acknowledge from slave NA P no acknowledge from master at this moment master-transmitter becomes master-receiver and slave-receiver becomes slave-transmitter STOP condition 002aae638 Read from register SCL 1 2 3 4 5 6 7 8 9 slave address SDA S 1 0 0 1 0 START condition data from port 0 1 1 R/W A data from port A DATA 1 DATA 4 acknowledge from master acknowledge from slave no acknowledge from master 1 P STOP condition read from port data into port DATA 2 DATA 1 th(D) DATA 3 DATA 4 tsu(D) INT tv(INT) trst(INT) 002aae639 This figure assumes the command byte has previously been programmed with 00h. Transfer of data can be stopped at any moment by a STOP condition. Expanded diagram is shown in Figure 15. Fig 8. Read input port register PCA9537_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 7 May 2009 9 of 24 PCA9537 NXP Semiconductors 4-bit I2C-bus and SMBus low power I/O port with interrupt and reset 7. Application design-in information VDD (5 V) 10 kΩ 10 kΩ 10 kΩ 10 kΩ 2 kΩ VDD VDD MASTER CONTROLLER PCA9537 INT SCL SCL IO0 SDA SDA IO1 INT INT RESET SUB-SYSTEM 1 (e.g., temp sensor) 100 kΩ SUB-SYSTEM 2 (e.g., counter) IO2 RESET RESET IO3 VSS VSS A controlled switch (e.g., CBT device) enable B 002aae640 Device address is 1001 001x for this example. IO0, IO2, IO3 configured as outputs. IO1 configured as input. Fig 9. Typical application 7.1 Minimizing IDD when the I/Os are used to control LEDs When the I/Os are used to control LEDs, they are normally connected to VDD through a resistor as shown in Figure 9. Since the LED acts as a diode, when the LED is off the I/O VI is about 1.2 V less than VDD. The supply current, IDD, increases as VI becomes lower than VDD. Designs needing to minimize current consumption, such as battery power applications, should consider maintaining the I/O pins greater than or equal to VDD when the LED is off. Figure 10 shows a high value resistor in parallel with the LED. Figure 11 shows VDD less than the LED supply voltage by at least 1.2 V. Both of these methods maintain the I/O VI at or above VDD and prevents additional supply current consumption when the LED is off. VDD VDD LED 100 kΩ IOn VDD 5V LED IOn 002aac660 Fig 10. High value resistor in parallel with the LED PCA9537_5 Product data sheet 3.3 V 002aac661 Fig 11. Device supplied by a lower voltage © NXP B.V. 2009. All rights reserved. Rev. 05 — 7 May 2009 10 of 24 PCA9537 NXP Semiconductors 4-bit I2C-bus and SMBus low power I/O port with interrupt and reset 8. Limiting values Table 8. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDD Conditions Min Max Unit supply voltage −0.5 +6.0 V II input current - ±20 mA VI/O voltage on an input/output pin VSS − 0.5 5.5 V IO(IOn) output current on pin IOn - ±50 mA IDD supply current - 85 mA ISS ground supply current - 100 mA Ptot total power dissipation - 200 mW Tstg storage temperature −65 +150 °C Tamb ambient temperature −40 +85 °C Tj(max) maximum junction temperature - +125 °C operating 9. Static characteristics Table 9. Static characteristics VDD = 2.3 V to 5.5 V; VSS = 0 V; Tamb = −40 °C to +85 °C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Supplies VDD supply voltage 2.3 - 5.5 V IDD supply current operating mode; VDD = 5.5 V; no load; fSCL = 100 kHz - 104 175 µA IstbL LOW-level standby current Standby mode; VDD = 5.5 V; no load; VI = VSS; fSCL = 0 kHz; I/O = inputs - 0.25 1 µA IstbH HIGH-level standby current Standby mode; VDD = 5.5 V; no load; VI = VDD; fSCL = 0 kHz; I/O = inputs - 0.25 1 µA VPOR power-on reset voltage no load; VI = VDD or VSS - 1.5 1.65 V −0.5 - +0.3VDD V [1] Input SCL; input/output SDA VIL LOW-level input voltage VIH HIGH-level input voltage 0.7VDD - 5.5 V IOL LOW-level output current VOL = 0.4 V 3 7 - mA IL leakage current VI = VDD = VSS −1 - +1 µA Ci input capacitance VI = VSS - 5 10 pF PCA9537_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 7 May 2009 11 of 24 PCA9537 NXP Semiconductors 4-bit I2C-bus and SMBus low power I/O port with interrupt and reset Table 9. Static characteristics …continued VDD = 2.3 V to 5.5 V; VSS = 0 V; Tamb = −40 °C to +85 °C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit −0.5 - +0.8 V 2.0 - 5.5 V I/Os VIL LOW-level input voltage VIH HIGH-level input voltage IOL LOW-level output current VOL = 0.5 V VDD = 2.3 V [2] 8 10 - mA VDD = 3.0 V [2] 8 14 - mA VDD = 4.5 V [2] 8 17 - mA VDD = 2.3 V [2] 10 13 - mA VDD = 3.0 V [2] 10 19 - mA VDD = 4.5 V [2] 10 24 - mA VDD = 2.3 V [3] 1.8 - - V VDD = 3.0 V [3] 2.6 - - V VDD = 4.5 V [3] 4.1 - - V VDD = 2.3 V [3] 1.7 - - V VDD = 3.0 V [3] 2.5 - - V VDD = 4.5 V [3] 4.0 - - V −1 - +1 µA - 5 10 pF VOL = 0.7 V VOH HIGH-level output voltage IOH = −8 mA IOH = −10 mA IL leakage current Ci input capacitance VI = VDD = VSS Interrupt INT IOL LOW-level output current VOL = 0.4 V 3 13 - mA IOH HIGH-level output current VOL = 0.4 V −1 - +1 µA −0.5 - +0.8 V 2.0 - 5.5 V −1 - +1 µA Select input RESET VIL LOW-level input voltage VIH HIGH-level input voltage IL leakage current VI = VDD = VSS [1] VDD must be lowered to 0.2 V in order to reset part. [2] Each I/O must be externally limited to a maximum of 25 mA and the device must be limited to a maximum current of 100 mA. [3] The total current sourced by all I/Os must be limited to 85 mA. PCA9537_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 7 May 2009 12 of 24 PCA9537 NXP Semiconductors 4-bit I2C-bus and SMBus low power I/O port with interrupt and reset 10. Dynamic characteristics Table 10. Dynamic characteristics Symbol Parameter Conditions Standard-mode I2C-bus Min Max Fast-mode I2C-bus Min Max Unit fSCL SCL clock frequency 0 100 0 400 tBUF bus free time between a STOP and START condition 4.7 - 1.3 - kHz µs tHD;STA hold time (repeated) START condition 4.0 - 0.6 - µs tSU;STA set-up time for a repeated START condition 4.7 - 0.6 - µs tSU;STO set-up time for STOP condition 4.0 - 0.6 - µs tHD;DAT data hold time 0 - 0 - ns 0.3 3.45 0.1 0.9 µs 300 - 50 - ns tVD;ACK data valid acknowledge time [1] tVD;DAT data valid time [2] tSU;DAT data set-up time 250 - 100 - ns tLOW LOW period of the SCL clock 4.7 - 1.3 - µs tHIGH HIGH period of the SCL clock 4.0 - 0.6 - µs tr rise time of both SDA and SCL signals - 1000 20 + 0.1Cb[3] 300 ns tf fall time of both SDA and SCL signals - 300 20 + 0.1Cb[3] 300 ns tSP pulse width of spikes that must be suppressed by the input filter - 50 - 50 ns Port timing tv(Q) data output valid time - 200 - 200 ns tsu(D) data input set-up time 100 - 100 - ns th(D) data input hold time 1 - 1 - µs Interrupt timing tv(INT) valid time on pin INT - 4 - 4 µs trst(INT) reset time on pin INT - 4 - 4 µs tw(rst) reset pulse width 4 - 4 - ns trec(rst) reset recovery time 0 - 0 - ns trst reset time 400 - 400 - ns RESET [1] tVD;ACK = time for Acknowledgement signal from SCL LOW to SDA (out) LOW. [2] tVD;DAT = minimum time for the SDA data out to be valid following SCL LOW. [3] Cb = total capacitance of one bus line in pF. PCA9537_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 7 May 2009 13 of 24 PCA9537 NXP Semiconductors 4-bit I2C-bus and SMBus low power I/O port with interrupt and reset SDA tr tBUF tf tHD;STA tSP tLOW SCL tHD;STA P tSU;STA tHD;DAT S tHIGH tSU;DAT tSU;STO Sr P 002aaa986 Fig 12. Definition of timing protocol START condition (S) tSU;STA bit 7 MSB (A7) tLOW bit 6 (A6) tHIGH bit 1 (D1) bit 0 (D0) STOP condition (P) acknowledge (A) 1 / fSCL SCL tBUF tr tf SDA tHD;STA tSU;DAT tHD;DAT tVD;DAT tVD;ACK tSU;STO 002aab285 Rise and fall times refer to VIL and VIH. Fig 13. I2C-bus timing diagram ACK or read cycle START SCL SDA 30 % trst RESET 50 % 50 % trec(rst) 50 % tw(rst) trst IOn 50 % after reset, I/Os reconfigured as inputs 002aad732 Fig 14. Definition of RESET timing PCA9537_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 7 May 2009 14 of 24 PCA9537 NXP Semiconductors 4-bit I2C-bus and SMBus low power I/O port with interrupt and reset SCL 2 1 0 A P 70 % 30 % SDA tsu(D) th(D) input 50 % tv(INT) trst(INT) INT 002aae641 Fig 15. Expanded view of read input port register SCL 2 1 0 A P 70 % SDA tv(Q) output 50 % 002aad735 Fig 16. Expanded view of write to output port register PCA9537_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 7 May 2009 15 of 24 PCA9537 NXP Semiconductors 4-bit I2C-bus and SMBus low power I/O port with interrupt and reset 11. Test information VDD PULSE GENERATOR VI RL 500 Ω VO 6.0 V open VSS DUT CL 50 pF RT 002aab393 RL = load resistor. CL = load capacitance includes jig and probe capacitance. RT = termination resistance should be equal to the output impedance Zo of the pulse generators. Fig 17. Test circuitry for switching times RL from output under test 500 Ω CL 50 pF S1 2VDD open GND RL 500 Ω 002aac226 Fig 18. Test circuit Table 11. Test tv(Q) Test data Load RL CL 500 Ω 50 pF PCA9537_5 Product data sheet Switch 2 × VDD © NXP B.V. 2009. All rights reserved. Rev. 05 — 7 May 2009 16 of 24 PCA9537 NXP Semiconductors 4-bit I2C-bus and SMBus low power I/O port with interrupt and reset 12. Package outline TSSOP10: plastic thin shrink small outline package; 10 leads; body width 3 mm D E SOT552-1 A X c y HE v M A Z 6 10 A2 (A3) A1 A pin 1 index θ Lp L 1 5 detail X e w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.15 0.23 0.15 3.1 2.9 3.1 2.9 0.5 5.0 4.8 0.95 0.7 0.4 0.1 0.1 0.1 0.67 0.34 6° 0° Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-07-29 03-02-18 SOT552-1 Fig 19. Package outline SOT552-1 (TSSOP10) PCA9537_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 7 May 2009 17 of 24 PCA9537 NXP Semiconductors 4-bit I2C-bus and SMBus low power I/O port with interrupt and reset 13. Handling information All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling ensure that the appropriate precautions are taken as described in JESD625-A or equivalent standards. 14. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 14.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 14.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • • • • • • Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering 14.3 Wave soldering Key characteristics in wave soldering are: PCA9537_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 7 May 2009 18 of 24 PCA9537 NXP Semiconductors 4-bit I2C-bus and SMBus low power I/O port with interrupt and reset • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities 14.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 20) than a SnPb process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 12 and 13 Table 12. SnPb eutectic process (from J-STD-020C) Package thickness (mm) Package reflow temperature (°C) Volume (mm3) < 350 ≥ 350 < 2.5 235 220 ≥ 2.5 220 220 Table 13. Lead-free process (from J-STD-020C) Package thickness (mm) Package reflow temperature (°C) Volume (mm3) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 20. PCA9537_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 7 May 2009 19 of 24 PCA9537 NXP Semiconductors 4-bit I2C-bus and SMBus low power I/O port with interrupt and reset maximum peak temperature = MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 20. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 15. Abbreviations Table 14. Abbreviations Acronym Description ACPI Advanced Configuration and Power Interface CBT Cross-Bar Technology CDM Charged-Device Model CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge FET Field-Effect Transistor FF Flip-Flop GPIO General Purpose Input/Output HBM Human Body Model I2C-bus Inter-Integrated Circuit bus I/O Input/Output LED Light Emitting Diode LP Low-Pass MM Machine Model POR Power-On Reset SMBus System Management Bus PCA9537_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 7 May 2009 20 of 24 PCA9537 NXP Semiconductors 4-bit I2C-bus and SMBus low power I/O port with interrupt and reset 16. Revision history Table 15. Revision history Document ID Release date Data sheet status Change notice Supersedes PCA9537_5 20090507 Product data sheet - PCA9537_4 Modifications: • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • • • • • Legal texts have been adapted to the new company name where appropriate. Pin names changed from “I/O0, I/O1, I/O2, I/O3” to “IO0, IO1, IO2, IO3”, respectively Section 6.4 “RESET input”, 1st sentence: changed symbol from “tW” to “tw(rst)” Figure 5 “Write to output port register”: changed symbol from “tpv” to “tv(Q)” Figure 8 “Read input port register”: – changed symbol from “tph” to “th(D)” – changed symbol from “tps” to “tsu(D)” – changed symbol from “tiv” to “tv(INT)” – changed symbol from “tir” to “trst(INT)” • Table 8 “Limiting values”: – parameter description for symbol VI/O changed from “DC voltage on an I/O” to “voltage on an input/output pin” – parameter description for symbol ISS changed from “supply current” to “ground supply current” – symbol/parameter changed from “II/O, DC output current on an I/O” to “IO(IOn), output current on pin IOn” • Table 9 “Static characteristics”, sub-section “Supplies”: – symbol/parameter changed from “Istbl, Standby current” to “IstbL, LOW-level standby current” – symbol/parameter changed from “Istbh, Standby current” to “IstbH, HIGH-level standby current” • Table 10 “Dynamic characteristics”, sub-section “Port timing”: – symbol/parameter changed from “tPV, Output data valid” to “tv(Q), data output valid time” – symbol/parameter changed from “tPS, Input data setup time” to “tsu(D), data input set-up time” – symbol/parameter changed from “tPH, Input data hold time” to “th(D), data input hold time” • Table 10 “Dynamic characteristics”, sub-section “Interrupt timing”: – symbol/parameter changed from “tIV, Interrupt valid” to “tv(INT), valid time on pin INT” – symbol/parameter changed from “tIR, Interrupt reset” to “trst(INT), reset time on pin INT” • Table 10 “Dynamic characteristics”, sub-section “RESET”: – symbol changed from “tW” to “tw(rst)” – symbol changed from “tREC” to “trec(rst)” – symbol/parameter changed from “tRESET, Time to reset” to “trst, reset time” • Figure 14 “Definition of RESET timing”: – symbol changed from “tW” to “tw(rst)” – symbol changed from “tREC” to “trec(rst)” – symbol changed from “tRESET” to “trst” • Figure 15 “Expanded view of read input port register”: – changed symbol from “tPH” to “th(D)” – changed symbol from “tPS” to “tsu(D)” – changed symbol from “tIV” to “tv(INT)” – changed symbol from “tIR” to “trst(INT)” PCA9537_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 7 May 2009 21 of 24 PCA9537 NXP Semiconductors 4-bit I2C-bus and SMBus low power I/O port with interrupt and reset Table 15. Revision history …continued Document ID Modifications (continued): Release date • • Data sheet status Change notice Supersedes Figure 16 “Expanded view of write to output port register”: changed symbol from “tPV” to “tv(Q)” (Old) Figure 18, “Test circuit” split into Figure 18 “Test circuit” and Table 11 “Test data” – symbol changed from “tpv” to “tv(Q)” • • Added soldering information Added Table 14 “Abbreviations” PCA9537_4 20060921 Product data sheet - PCA9537_3 PCA9537_3 (9397 750 14259) 20041129 Product data sheet - PCA9537_2 PCA9537_2 (9397 750 14052) 20040930 Objective data sheet - PCA9537_1 PCA9537_1 (9397 750 12894) 20040820 Objective data sheet - - PCA9537_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 7 May 2009 22 of 24 PCA9537 NXP Semiconductors 4-bit I2C-bus and SMBus low power I/O port with interrupt and reset 17. Legal information 17.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 17.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 17.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 17.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus — logo is a trademark of NXP B.V. 18. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] PCA9537_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 7 May 2009 23 of 24 PCA9537 NXP Semiconductors 4-bit I2C-bus and SMBus low power I/O port with interrupt and reset 19. Contents 1 2 3 4 5 5.1 5.2 6 6.1 6.2 6.2.1 6.2.2 6.2.3 6.2.4 6.2.5 6.3 6.4 6.5 6.6 6.7 7 7.1 8 9 10 11 12 13 14 14.1 14.2 14.3 14.4 15 16 17 17.1 17.2 17.3 17.4 18 19 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Device address . . . . . . . . . . . . . . . . . . . . . . . . . 4 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Command byte . . . . . . . . . . . . . . . . . . . . . . . . . 4 Register 0 - Input Port register . . . . . . . . . . . . . 4 Register 1 - Output Port register. . . . . . . . . . . . 5 Register 2 - Polarity Inversion register . . . . . . . 5 Register 3 - Configuration register . . . . . . . . . . 6 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 6 RESET input . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Interrupt output . . . . . . . . . . . . . . . . . . . . . . . . . 6 I/O port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Bus transactions . . . . . . . . . . . . . . . . . . . . . . . . 8 Application design-in information . . . . . . . . . 10 Minimizing IDD when the I/Os are used to control LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 11 Static characteristics. . . . . . . . . . . . . . . . . . . . 11 Dynamic characteristics . . . . . . . . . . . . . . . . . 13 Test information . . . . . . . . . . . . . . . . . . . . . . . . 16 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 17 Handling information. . . . . . . . . . . . . . . . . . . . 18 Soldering of SMD packages . . . . . . . . . . . . . . 18 Introduction to soldering . . . . . . . . . . . . . . . . . 18 Wave and reflow soldering . . . . . . . . . . . . . . . 18 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 18 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 19 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 21 Legal information. . . . . . . . . . . . . . . . . . . . . . . 23 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 23 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Contact information. . . . . . . . . . . . . . . . . . . . . 23 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 7 May 2009 Document identifier: PCA9537_5