AN2267
Application note
Implementation of current regulator for BLDC
motor control with ST7FMC
Introduction
A conventional method of controlling BLDC motors is to implement an inner current loop for
torque / current control. Reference to this inner loop is provided either by an outer speed
loop or by some other means based on application requirement. The linearity of inner
current / torque loop is greatly affected by the faithfulness of current feedback. In the first
section, an outline to various approaches for obtaining current feedback is presented and
analyzed with the limitations of each. In the subsequent sections, a presentation is given of
a simple, linear and cost effective approach of implementing the inner current loop by
sampling the DC link current at the mid-point of PWM “on time” with ST7FMC. Experimental
results are also discussed.
An accompanying software file is available with this application note and can be downloaded
from www.st.com/mcu
June 2006
Rev 1
1/19
www.st.com
Contents
AN2267
Contents
1
Outline to various approaches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Obtaining the average current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3
BLDC motor control using ST7FMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4
Implementation using ST7FMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5
Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6
Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
7
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Appendix A Sampling inner current loop procedure . . . . . . . . . . . . . . . . . . . . . 14
Appendix B Event U interrupt service routine . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Appendix C ST7MC 3-phase motor control schematics . . . . . . . . . . . . . . . . . . . 16
2/19
AN2267
1
Outline to various approaches
Outline to various approaches
A BLDC motor driven in a conventional 6-step method greatly resembles a brushed DC
motor. Hence, one may choose to regulate the average DC link current. But this actually
results in constant power operation for the motor because at constant DC link voltage, if the
average link current is regulated at a certain value, it effectively regulates the power at that
point for any variation in motor load, and the average load current / motor torque varies
inversely with speed depending on the load. Any effort to compensate the average DC link
current data with the duty cycle to obtain average phase current will be impaired by a filter
time constant, rendering this option ineffective.
Since the DC link current does not reveal winding currents during PWM “off time”, one may
choose to monitor all 3 winding currents and build a regulator. But this requires two current
sensors to monitor any two phase currents, while the third phase current can be
reconstructed from these two. However, the cost of these sensors makes this option
expensive.
A third option would then be to regulate the peak current per PWM period. Though it is
inexpensive and easy to implement, it is not exactly linear. During PWM on time, at lower
duty cycles, when both speed and BEMF are small, the phase current rises much faster
than at higher duty cycles when the speed and BEMF are large. The same peak currents
per PWM period represent different average currents at different duty cycles. An intuitive
geometric approach will reveal this as shown in Figure 1. A typical variation in average
current vs duty cycle at a given peak current reference is shown in Figure 2.
Figure 1.
Iphase
Peak current regulation at different duty cycles with BEMF load
Iphase
Ipeak
Ipeak
t
Figure 2.
t
Iave vs duty cycle at a given Ipeak
Iave
Ipeak
dutycycle
0
0.5
1.0
3/19
Obtaining the average current
2
AN2267
Obtaining the average current
For linear torque control, it is important that we sample the average phase current as
feedback to the current regulator. It is best to get this information from the DC link current
using only a shunt resistor because of its low cost and simplicity. However, the DC link
current is not continuous and is present only during PWM on time. As a simple model for
current control, assume a simple buck converter feeding an RL load as shown in Figure 3.
Figure 3.
Buck converter feeding an RL load
PWM
CONTROL
SW1
1
2
R1
D1
BT1
VL
L1
Rsh
IL
Ish
The switching frequency, PWM on time and load inductance are such that the load current is
continuous. Figure 4 shows the load voltage, load current and DC link current waveforms. A
close look at the load current waveform reveals that its average value is equal to its
instantaneous value during the middle of PWM on time or off time. Since the load current
flows through the DC link during PWM on time, sampling the DC link current during the
middle of PWM on time gives the average load current.
Figure 4.
Buck Converter - Waveforms
V
IL
IL(ave
IS
To
4/19
Toff
AN2267
3
BLDC motor control using ST7FMC
BLDC motor control using ST7FMC
The main feature of ST7FMC is its powerful motor control macro cell, capable of generating
control signals to drive a sensorless or sensored 3 phase BLDC or AC motor.
STMicroelectronics application notes AN1946 [1] and AN2030 [2] explain, in detail, the
procedure to control a 3 phase BLDC motor using ST7FMC.
Figure 5 shows the simplified block diagram of the hardware motor control macro cell. The
macrocell has multiple timers performing various functions in parallel to generate control
pulses for the motor. An auto scalable 8-bit timer (MTIM) monitors the time difference
between successive phase back EMF zero crossings (Z events) of the motor. When a Z
event occurs, the timer value is captured into MZREG and the timer restarts counting from
zero, and, the previous content of MZREG is transferred to MZPRV. This timer is a part of
what is called DELAY MANAGER that, based on this time difference and a delay coefficient
(MWGHT), identifies the timing for next phase commutation instant (C events). All in
parallel, a 12-bit free running counter generates the PWM carrier for inverter switching.
Figure 5.
Simplified block diagram of Motor control Macro cell for BLDC motors
BEMF ZERO-CROSSING
DELAY
or SPEED MEASURE UNIT (not
WEIGH
MCI
MCI
MCI
BEMF=
[Z
MTI
TIME
CAPTURE
In
DELAY = WEIGHT x
=
Encoder
MCO
MCO
MCO
MCO
MCO
MCO
P
H
A
S
CURRENT
VOLTAGE
(I
MCVRE
INPUT DETECTION
COMMUTE
MEASUREMENT
WINDOW
GENERATOR
Ex
Vre
TACH
(V
U, V,
Phase
MOD
NMCE
OAON
CFAV
PWM
+
MCAO
-
MCAO
MCAOZ/
MCCFI
Vdd
AD
Phase
MCCRE
CHANNEL
12-bit
Phase
Phase V
Phase W
(V
PCN
(V
(I
C
R
12-bit THREE-PHASE
PWM GENERATOR
3
MCPWM
MCPWM
MCPWM
[Z] : Back EMF Zero-crossing
Z n : Time elapsed between two consecutive Z
[C] : Commutation
C n : Time delayed after Z event to generate C
(I): Current
(V): Voltage
5/19
BLDC motor control using ST7FMC
Figure 6.
AN2267
Motor Control Macro cell - BLDC motor control configuration
Board + Motor
Mi crocontroll er
Z V D b it CPBn bit P Z b it
EF [2 : 0]
REO bi t
IS nbit
DS,H
F ilte r / D
MCIA
CS,H
or
MCIB
or
+
-
2
E F [2 :0 ]
F ilt e r / C
Q
D
1
SR bit
DH
2
CPBn bit
1
HDM n bit
XT16 bi t
MCVREF
CS,HVREF
SPLG
Fcpu
MCIC
CP
or
MPWME Reg
or
ZH
DS,H
VR2-0
1/ 4
I
V
R+
MCPWMU
12- bit P W M ge nera tor
1 /20
Compare U
SA3-0 &
ck
A x B/ 256
D
S
ZS
R-/+
E
ZS,H
MISR Reg
CS,H
MI MR Reg
CL
A
MCO1
C
MCO3
MCO5
2
CFF[ 2: 0] bit
8
MCOMP Reg [Cn+1]
B
8
6
SWA bit
Compare
Ch2
n
Ch5
DS,H
MCO2
MCO4
NMCES
MCPWMU/V/W
+
MCAOP
-
MCAON
MCCFI
+
-
S,H
6
1
MCAOZ
CL
D
6
MOE bit
8
MPAR Reg
]
n
EF[2:0]
F ilter / C
EF [2:0]
Filter / C
n+
1
8
SDM bit
x6
MPOL Reg
SZn
bit
n-1 n
R
Compare
Ch4
Compare
S Q
x6
AO bit
n
Ch3
MDREG Reg [D ]
ZS,H
MWGHT Reg [a
MPHST Reg
DH
MZREG Reg [Zn]
DCB bit
MREF
Reg
Ch1
8
High Frequency Chopper
0
ZH
MZPRV Reg [ Zn-1 ]
MCO0
Dead
Time
CH
V
1
cl r
I
MTI M [ 8-bit Up Count er]
HV
Z
Dead
Time
R-
3
SWA bit
OT1-0 bits
Dead
Time
MZREG
< 55h?
MCPWMV
MCPWMW
PCN bit =0
1/ 2
n
1 ¾ 1/ 128
Ch0
-1
Ratio
bits
4
ST3-0 bits
OS
1 /2
DTG register
MTIM
= FFh?
SR bit
+1
CFAV bit
VDD
A
(I) R1ext
MCCREF
Filt er / PWM
CS,H
(V)
Cext
R2ext
A PWM output is generated as a result of comparison between this carrier and a compare
register (MCPUH:MCPUL) that carries pulse width (duty cycle) information. This PWM
signal is directed to one of the six inverter switches by a CHANNEL MANAGER that acts as
a traffic diverter on the PWM output. The channel manager also selects a complementary
switch, as programmed by the user, which together with the switch receiving PWM will force
current into the motor windings. Based on the motor terminal voltages or Hall sensor
outputs, an analog block identifies the motor phase BEMF Z events and captures the
contents of MTIM timer into MZREG and the previous value of MZREG into MZPRV and this
cycle repeats all over again.
6/19
AN2267
4
Implementation using ST7FMC
Implementation using ST7FMC
A typical schematic block diagram of ST7FMC based sensorless control of BLDC motor [2]
is shown in Figure 7. Refer to Appendix C on page 16 for a complete schematic of the
experimental hardware. This schematic resembles the motor control starter kit schematic
from Softec Microsystems, with matching I/O assignments wherever possible.
Figure 7.
Schematic block diagram of ST7FMC based sensorless control of BLDC
motor
Vdclink
VCC
MCO0
MCO1
MCO2
MCO3
MCO4
MCO5
Speed Ref
AINy
BLDC
Shut Down
ST7FMC
VCC
Max Current
Limit
AINx
PE0
PE1
PE2
MCIA
MCIB
MCIC
Figure 8a shows the PWM carrier configured in center aligned mode, where the counter
counts up to a maximum value (as defined by MCP0) and starts counting down to zero and
repeats this cycle again. (See Appendix A for information on setting the PWM frequency).
The PWM generator is set to generate a duty cycle update interrupt (U event) upon
completion of every N carrier cycles as specified by MREP register. (See Appendix A for
information on setting the periodicity of this interrupt). The timing of the U event or interrupt
is positioned as shown in Figure 8a. The carrier is compared with MCPU and PWM pulses
are generated as shown in Figure 8b. Due to the application of PWM voltage on motor
windings, a current flows in its windings as shown in Figure 8c.
7/19
Implementation using ST7FMC
Figure 8.
AN2267
PWM on time midpoint identification and control
U event
MCP0
U event
Carrier
Ref
Fig 8a
t
Fig 8b
PWM
t
Fig 8c
Current
t
Fig 8d
U ISR
t
T
From Figure 8a and Figure 8b, it is clear that the U event takes place at the center of PWM
on time. Based on the previous discussions, this is the right instant to read the
instantaneous DC link current in order to get the average phase current value. Hence the
interrupt associated with U event should be set to the highest priority and the very first
instruction in this Interrupt Service Routine (ISR) should read the DC link current value. In
any case, there is an interrupt latency time of approximately 3-4µs, which is also the typical
conversion time of on-chip Analog to Digital Converter (ADC). If the current feedback analog
input channel was previously selected and set for sampling continuously, then, when the first
instruction in U event interrupt subroutine reads the ADC data register, it will aptly hold the
DC link current value fairly close to that during the middle of PWM on time.
8/19
AN2267
Implementation using ST7FMC
Figure 9.
Update (U) event interrupt subroutine flow chart
Start U
Read current feedback
Set U ISR priority lower if required
Read other Analog inputs
Current loop PI regulator
Dutycycle update
Set ADC Channel back to Sample current feedback
Restore ISR priority to the highest
End U
The flowchart in Figure 9 shows the actions within the U event interrupt service routine. To
coordinate the reading of any other analog inputs to the ADC, it is recommended that they
are all read within this U event subroutine after the DC link current read. However, before
returning from the interrupt, it is important to restore the ADC to sample the DC link current
channel again so that on re-entry in the next U event, the DC link current value can be read
from ADC right away. If required, interrupt priority of this routine can be lowered after
reading the current value upon entry, but should be restored to the highest value before
returning for obvious reasons.
Refer to the accompanying file for a complete listing of the code and experimental
workspace.
9/19
Results
5
AN2267
Results
Experimental implementation of this scheme yielded satisfactory results. A closed loop
regulator for BLDC motor control with inner current and outer speed loops as shown in
Figure 10 was implemented. Current loop sampling time of 500µs and speed loop sampling
time of 2ms was chosen. The amount of computing time required within a 2ms time window
to execute through a full cycle of control loop and all motor control ISRs at an electrical
frequency of 200Hz is less than 1ms. The important waveforms obtained are shown in
figures 11 and 12. Figure 11 shows the convergence of reference and actual phase current
values at the instant of occurrence of U event which is the feedback sampling instant. Notice
that the U event occurs during the middle of PWM ON time. Figure 12 shows the tight
control of motor average phase current for a given current reference.
Figure 10. Closed loop current and speed control - block diagram
ST7FMC controller
PI reg
ω
+
-
I*
duty
+
-
ω
10/19
Vdclink
PI reg
BLDC
Speed
estimator
AN2267
Results
Figure 11. DC link current sampling at U event and closed loop convergence
Figure 12. Tight control of average phase current vs reference
11/19
Conclusion
6
AN2267
Conclusion
The experiments performed based on the described method gave fairly linear current
control. One limitation of this sampling method is when the motor current becomes
discontinuous, in which case the actual average current is less than the instantaneous value
at the mid point of PWM on time, and correcting this error is quite cumbersome.
12/19
AN2267
7
References
References
[1]. STMicroelectronics AN1946 - Sensorless BLDC motor control and BEMF sampling
methods with ST7MC
[2]. STMicroelectronics AN2030 - Back EMF detection during PWM on time by ST7MC
13/19
Sampling inner current loop procedure
Appendix A
AN2267
Sampling inner current loop procedure
Procedure to set carrier frequency (Fpwm) and periodicity of U event (TU) for sampling inner
current loop:
Chosen Fpwm = 16KHz
where,
Fpwm = Fmtc / (Prescaler . 2 . MCP0)
U
U
MCP0
MREP
Repeat
Counter
Fmtc
Prescaler
MPCR
PCP[2:0]
Given Fmtc = 16MHz,
and choosing Prescaler = 1,
then,
MCP0 = 500
Choosing TU = 500µS
where,
TU = Tpwm . (MREP + 1) / 2
Substituting for TU and Tpwm,
MREP = 15
14/19
Up/ Down
counter
Fpwm
MPCR
CMS = 1
U
AN2267
Event U interrupt service routine
Appendix B
Event U interrupt service routine
/***************************************************
Motor control - Event U interrupt service routine
***************************************************/
@interrupt @nosvf void mtcU_CL_SO_ISR(void)
{
if (bitTest_TRUE(MISR, PUI) )
// check for U event presence
{
/* ===
Current loop PI Controller begins here
=== */
currentFb = (ADCDRMSB << 2) + ADCDRLSB; // get new value of currentFb
piconCur();
// call current loop PI regulator
to get new dutycycle
MCPUL = PIconCur.byte.b2;
// update MCPUH :MCPUL with new dutycycle
MCPUH = PIconCur.byte.b3;
/* ===
Current Loop PI controller ends here
=== */
// Read potentiometer to get latest speed reference
getADC_10bit (speedRef , SPEED_REF_CHNL);
if (speedRef > SPEED_REF_MAX)
speedRef = SPEED_REF_MAX;
// Current Feedback measurement setup for next cycle
ADCCSR = ADON + CURRENT_FDBK_CHNL;
ADCDRMSB; // to clear EOC of prev conv
MISR = 0xff - PUI;
//reset IT flag
}
return;
}
15/19
A
B
+5V
PB3
C41
0.1uF
R75
100E
1
2
C
5K
+5V
CD3
0.1uF
0.01uF
C42
0.1uF
C45
R74
20K
RV1
+5V
5
CD1
0.1uF
CD2
0.1uF
0.01uF
C49
R82
20K
+5V
C43
0.1uF
0.1uF
C36
1
CD4
0.1uF
0.01uF
C48
R81
20K
C44
0.1uF
2
R68
470K
+5V
1
3
5
7
9
J3
CON10A
1
RV1
RV2
RV3
SIG18
SIG7
SIG5
SIG2
SIG17
SIG21
PE1
SIG13
R73 10K
D26
RED
SW1
SW2
SW3
SW4
1
1
SIG21
SIG20
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
HEADER34
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
P9
SIG5
SIG6
SIG7
SIG17
Temprtr
C38
0.1uF
SW1
SW2
SW3
SW4
GREEN
D27
0.01uF
C50
R83
20K
R61
680E
R60
470E
2
2
R72 10K
Y1
16.00MHz
Ceramic
resonator
Vdclink
+5V
PB2
2
4
6
8
10
ICC Interface
1
+5V
2
D
1
2
2
1
5K
RV3
5K
RV2
1
2
2
SW10
1
1
2
2
SW8
1
4
+5V
36
7
53
35
34
54
8
37
21
22
23
24
12
14
16
25
15
13
60
5
6
61
50
49
38
R64
10K
4
SIG20
PE0
PE2
SIG12
SIG4
SIG19
SIG6
SIG1
SIG3
+5V
Vss_0
Vss_1
Vss_2
Vss_A
VAREF
Vdd_2
Vdd_1
Vdd_0
MISO / PB4
AIN3 / MOSI / PB5
SCK / (HS) PB6
AIN4 / SS/(HS)PB7
AIN0 / PWM0 / PA3
AIN1 / ARTIC1 / PA5
AIN2 / PA7
(HS) PC0
ARTIC2 / PA6
ARTCLK / (HS)PA4
PE5 /
OSC1
OSC2
C46
10K R79
0.1uF
2
1
P7
Vpp/
PD5/AIN15 / ICCDATA
PD4 / EXTCLK_A / AIN14 / ICCCLK
RESET
U2
3
PD7(HS) / TDO
PD6(HS) / RDI
PC7 / MCPWMW / AIN7
MCPWMU / PC5
MCES
(HS)MCO5
(HS)MCO4
(HS)MCO3
(HS)MCO2
(HS)MCO1
(HS)MCO0
AIN5 / MCCFI0 / PC1
MCIC / PB3
MCIB / PB2
MCIA / PB1
MCVREF / PB0
PF1 / MCZEM / AIN9
PF0 / MCDEM / AIN8
OAP / PC2
OAN / PC3
AIN6 / MCCFI1 / OAZ
MCCREF / PC4
MCPWMV / PC6
3
C34
st72mc_qfp64
52
51
680pF
SHUTDOWN
4
R59
2K2
+5V
U3
RV3
SIG19
CL
CH
BL
BH
AL
AH
3
2
1
64
63
62
33
31
Vref
Idc1
Vc
Vb
Va
1
TP1
C32
22pF
26
20
19
18
17
40
39
27
28
29
30
32
R54
10K
U4
C47
1K5
R57
NEC2501
R63
8K2
R58
1K5
200E
+5V
5K
RV4
10K
R52
0.1uF
R50
10K
R69
R51
51K
D28
NEC2501
4
3
1
2
1
2
2
SW9
1
PWM3 / PA0
PWM2 / (HS) PA1
PWM1 / PA2
9
10
11
SIG1
SIG2
SIG3
PF2 / MCO / AIN10
PF3 (HS) / BEEP
PF4 (HS)
PF5 (HS)
SIG4
41
42
43
44
OVER_cur
OVER_volt
PD0 / OCMP2_A / AIN11
PD1(HS) / OCMP1_A
PD2 / ICAP2_A / AIN12
PD3 / ICAP1_A / AIN13
45
46
47
48
RV2
SIG18
OVER_temp
RV1
PE4 / EXTCLK_B
PE3 / ICAP1_B
PE2 / ICAP2_B
PE1 / OCMP1_B
PE0(HS) / OCMP2_B
59
58
57
56
55
SIG12
SIG13
PE2
PE1
PE0
1
2
4
16/19
2
R62
8K2
D32
30V
D33
10K
R80
+5V
1
2
D29
2
1
P8
J1
2
SW6
SW DIP-2
2
1
6
2
7
3
8
4
9
5
Date:
Size
B
Title
DB9
P5
C28
0.1uF
Idc
ST7MC control of 3 phase motor
Tuesday, January 03, 2006
Document Number
<Doc>
1
Sheet
1
3
of
3
Rev
3.0
A
B
C
D
Appendix C
3
5
ST7MC 3-phase motor control schematics
AN2267
ST7MC 3-phase motor control schematics
Figure 13. Schematic 1 of 3
A
B
C
D
5 +
6 -
5
Temprtr
OVER_temp
SHUTDOWN
IC5B
TS272
7
Idc1
OVER_cur
OVER_volt
Idc
1
2
R40
1K5
C33
0.1uF
HEADER 2
SW NEU
L1
P2
AC POWER IN
N
3 +
2 -
C20
R46
51K
+5V R2 NTC
10K
1
C25
0.01uF
1K
R34
0.1uF/400V
IC5A
TS272
+5V
LINE
FILTER
F1
FUSE
1
3
0.1uF
C19
2
R39
10K
C17
0.1uF
J2
D7
IR8GBU06
4
W1
680uF/200V
C1
2
R38
1K
Q1
2N4403
+5V
1nF
1nF
R33
C16
0.1uF/400V
1K
1K
1K
R47
27K
1nF
C18
+5V
R45
27K
+5V
0.015E/2W
1%
R20
C2
R19
100K/2W
R1
100K/2W
+5V
R48
2K
R37
8K2
R30
R27
C14
PB1
680uF/200V
C13
3
1
POWER_JUMPER
R49
1K
MAIN
RECTIFIER
+ 4
1 -
1K
1K
+15V
R32
R31
D13
1N4148WS
CH
CL
1K
1K
+15V
R29
R28
C15
0.1uF
D12
1N4148WS
BH
BL
1K
1K
+15V
R26
R25
C30
22nF
3
7
6
5
4
3
2
1
GND
CIN
DIAG
VCC
HIN
SD
LIN
14
8
9
10
11
12
13
14
8
9
10
11
12
13
GND
LVG
NC
NC
OUT
HVG
VBOOT
8
9
10
11
12
13
14
D10
STTA106U
GND
LVG
NC
NC
OUT
HVG
VBOOT
D9
STTA106U
GND
LVG
NC
NC
OUT
HVG
L6386
GND
CIN
DIAG
VCC
HIN
SD
LIN
+
D8
STTA106U
VBOOT
L6386
GND
IC3
+15V
7
6
5
4
3
2
1
DIAG
CIN
FB
VDD
0.23V
L6386
VCC
HIN
SD
LIN
IC2
+15V
7
6
5
4
3
2
1
IC1
+15V
3
1N4148WS
RES
SET
SOURCE
DRAIN
IC4
VIPER12AS
15v REGULATED SUPPLY
STTA106U
C26
D24
22uF/25V
15V
D11
1N4148WS
AH
AL
22uF/25V
Vprot
C9
C29
D22
D23
3
4
4
8
7
6
5
R7
47E
R11
47E
1N4148WS
C4
0.01uF
R9
47E
1N4148WS
C3
0.01uF
R13
47E
R15
47E
1N4148WS
C6
0.01uF
R18
22E
C8
0.01uF
R17
47E
C7
R16 0.01uF
22E
D6
1N4148WS
Tantalum
C12
D5
0.47uF/50V
R14
22E
C31
1N4148WS
D20
STTA106U
L1
1mH
100uF/25V
C5
R12 0.01uF
22E
D4
1N4148WS
Tantalum
C11
D3
0.47uF/50V
R10
22E
R8
22E
D2
Tantalum
C10
D1
0.47uF/50V
1
2
5
8
4
1
2
T6
T5
Vdc
T4
T3
Vdc
T2
T1
Vdc
D25
18V
2
2
STGP7NB60HD
STGP7NB60HD
STGP7NB60HD
STGP7NB60HD
STGP7NB60HD
+15V
D21
U1
L7805
5V
1 Vi
Vo
Date:
Size
B
Title
CP1
CP3
+5V
3
2
1
P1
Tuesday, January 03, 2006
Document Number
<Doc>
2
1
P3
C27 10uF/25V
3
Vdc
+15V
ST7MC control of 3 phase motor
VA_OUT
VB_OUT
VC_OUT
CP2
1uF/25V 1uF/25V 1uF/25V
+15V
GND
2
1
Sheet
1
2
of
3
Rev
3.0
A
B
C
D
Figure 14.
STGP7NB60HD
AN2267
ST7MC 3-phase motor control schematics
Schematic 2 of 3
17/19
0.1uF/400V
A
5
C24
0.1uF
1
2
P6
C23
0.1uF
C37
0.1uF
C22
0.1uF
R67
10K
C21
0.1uF
+5V
D30
B
1N4148WS
C
R23
1K
10K
R78
R41
1K
R22
100K/2W
R24
1K
D31
1N4148WS
18/19
R77
0(NC)
SW DIP-4
SW1
R42
1K
R6
1K
4
C40
0.1uF
R43
1K
4
+5V
R76
100E
R66
10K
R44
1K
C39
2.2nF
Q2
2N2222
Vc
Vb
Va
Vref
+5V
RV5
5K
SW7
SW DIP-2
SW2
SW DIP-4
Vdc
+5V
PE1
3
Vdclink
R21
330K/2W
PE2
D17
1N4148WS
D19
1N4148WS
R65
47K
D16
1N4148WS
R36
39K
R70
47K
PE0
Vprot
R71
47K
SW5
SW DIP-4
SW3
SW DIP-3
D14
1N4148WS
D18
1N4148WS
R4
180K/2W
D15
1N4148WS
R3
180K/2W
3
R35
470E
R5
180K/2W
R53
4K7
C35
+5V
SW4
SW DIP-3
R56
4K7
+5V
R55
4K7
VC_OUT
VB_OUT
VA_OUT
0.01uF
D
5
2
2
HEADER 5
P4
Date:
Size
B
Title
Tuesday, January 03, 2006
Document Number
<Doc>
ST7MC control of 3 phase motor
1
Sheet
1
of
3
** SW3 and SW5 are fully CLOSED
5
4
3
2
1
1
Rev
3.0
A
B
C
D
ST7MC 3-phase motor control schematics
AN2267
Figure 15. Schematic 3 of 3
AN2267
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