PCF85134
Universal 60 x 4 LCD segment driver for multiplex rates up to
1:4
Rev. 3 — 12 May 2014
Product data sheet
1. General description
The PCF85134 is a peripheral device which interfaces to almost any Liquid Crystal
Display (LCD)1 with low multiplex rates. It generates the drive signals for any static or
multiplexed LCD containing up to four backplanes and up to 60 segments. It can be easily
cascaded for larger LCD applications. The PCF85134 is compatible with most
microcontrollers and communicates via the two-line bidirectional I2C-bus. Communication
overheads are minimized by a display RAM with auto-incremented addressing, by
hardware subaddressing, and by display memory switching (static and duplex drive
modes).
For a selection of NXP LCD segment drivers, see Table 26 on page 45.
2. Features and benefits
Single-chip LCD controller and driver
Selectable backplane drive configurations: static, 2, 3, or 4 backplane multiplexing
60 segment outputs allowing to drive:
30 7-segment alphanumeric characters
15 14-segment alphanumeric characters
Any graphics of up to 240 elements
Cascading supported for larger applications
60 4-bit display data storage RAM
Wide LCD supply range: from 2.5 V for low threshold LCDs up to 6.5 V for high
threshold twisted nematic LCDs
Internal LCD bias generation with voltage follower buffers
Selectable display bias configurations: static, 1⁄2, or 1⁄3
Wide logic power supply range: from 1.8 V to 5.5 V
LCD and logic supplies may be separated
Low power consumption
400 kHz I2C-bus interface
No external components required
Display memory bank switching in static and duplex drive mode
Versatile blinking modes
Silicon gate CMOS process
1.
The definition of the abbreviations and acronyms used in this data sheet can be found in Section 20.
PCF85134
NXP Semiconductors
Universal 60 x 4 LCD segment driver for low multiplex rates
3. Ordering information
Table 1.
Ordering information
Type number
Package
PCF85134HL
Name
Description
Version
LQFP80
plastic low profile quad flat package;
80 leads; body 12 12 1.4 mm
SOT315-1
3.1 Ordering options
Table 2.
Ordering options
Product type number
Orderable part number Sales item
(12NC)
Delivery form
IC
revision
PCF85134HL/1
PCF85134HL/1,118
tape and reel, 13 inch
1
935290742118
4. Marking
Table 3.
PCF85134
Product data sheet
Marking codes
Type number
Marking code
PCF85134HL/1
PCF85134HL
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Rev. 3 — 12 May 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
2 of 53
PCF85134
NXP Semiconductors
Universal 60 x 4 LCD segment driver for low multiplex rates
5. Block diagram
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Block diagram of PCF85134
PCF85134
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 12 May 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
3 of 53
PCF85134
NXP Semiconductors
Universal 60 x 4 LCD segment driver for low multiplex rates
6. Pinning information
6
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6.1 Pinning
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Top view. For mechanical details, see Figure 24.
Fig 2.
PCF85134
Product data sheet
Pin configuration for SOT315-1 (PCF85134)
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Rev. 3 — 12 May 2014
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4 of 53
PCF85134
NXP Semiconductors
Universal 60 x 4 LCD segment driver for low multiplex rates
6.2 Pin description
Table 4.
Pin description
Input or input/output pins must always be at a defined level (VSS or VDD) unless otherwise specified.
PCF85134
Product data sheet
Symbol
Pin
Type
Description
S31 to S59
1 to 29
output
LCD segment output 31 to 59
BP0 to BP3
30 to 33
output
LCD backplane output 0 to 3
n.c.
34 to 37
-
not connected; do not connect and do not use as
feed through
SDA
38
input/output
I2C-bus serial data input and output
SCL
39
input
I2C-bus serial clock input
CLK
40
input/output
external clock input and internal clock output
VDD
41
supply
supply voltage
SYNC
42
input/output
cascade synchronization input and output (active
LOW)
OSC
43
input
enable input for internal oscillator
A0 to A2
44 to 46
input
subaddress counter input 0 to 2
SA0
47
input
I2C-bus slave address input 0
VSS
48
supply
ground supply voltage
VLCD
49
supply
input of LCD supply voltage
S0 to S30
50 to 80
output
LCD segment output 0 to 30
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Rev. 3 — 12 May 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
5 of 53
PCF85134
NXP Semiconductors
Universal 60 x 4 LCD segment driver for low multiplex rates
7. Functional description
The PCF85134 is a versatile peripheral device designed to interface between any
microcontroller to a wide variety of LCD segment or dot matrix displays (see Figure 3). It
can directly drive any static or multiplexed LCD containing up to four backplanes and up to
60 segments.
The display configurations possible with the PCF85134 depend on the required number of
active backplane outputs. A selection of display configurations is given in Table 5.
All of the display configurations given in Table 5 can be implemented in a typical system
as shown in Figure 4.
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Fig 3.
Example of displays suitable for PCF85134
Table 5.
Selection of possible display configurations
Number of
Backplanes
PCF85134
Product data sheet
Icons
Digits/Characters
7-segment[1]
14-segment[2]
Dot matrix/
Elements
4
240
30
15
240 (4 60)
3
180
22
11
180 (3 60)
2
120
15
7
120 (2 60)
1
60
7
3
60 (1 60)
[1]
7-segment display has eight elements including the decimal point.
[2]
14-segment display has 16 elements including decimal point and accent dot.
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Rev. 3 — 12 May 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
6 of 53
PCF85134
NXP Semiconductors
Universal 60 x 4 LCD segment driver for low multiplex rates
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Fig 4.
Typical system configuration
The host microcontroller maintains the 2-line I2C-bus communication channel with the
PCF85134.
Biasing voltages for the multiplexed LCD waveforms are generated internally, removing
the need for an external bias generator. The internal oscillator is selected by connecting
pin OSC to VSS. The only other connections required to complete the system are the
power supplies (pins VDD, VSS, and VLCD) and the LCD panel selected for the application.
7.1 Power-On Reset (POR)
At power-on the PCF85134 resets to the following starting conditions:
•
•
•
•
•
•
•
All backplane and segment outputs are set to VLCD
The selected drive mode is: 1:4 multiplex with 1⁄3 bias
Blinking is switched off
Input and output bank selectors are reset
The I2C-bus interface is initialized
The data pointer and the subaddress counter are cleared (set to logic 0)
The display is disabled (bit E = 0, see Table 12)
Remark: Do not transfer data on the I2C-bus for at least 1 ms after a power-on to allow
the reset action to complete.
7.2 LCD bias generator
Fractional LCD biasing voltages are obtained from an internal voltage divider consisting of
three impedances connected in series between VLCD and VSS. If the 1⁄2 bias voltage level
for the 1:2 multiplex drive mode configuration is selected, the center impedance is
bypassed by switch. The LCD voltage can be temperature compensated externally, using
the supply to pin VLCD.
PCF85134
Product data sheet
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Rev. 3 — 12 May 2014
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7 of 53
PCF85134
NXP Semiconductors
Universal 60 x 4 LCD segment driver for low multiplex rates
7.3 LCD voltage selector
The LCD voltage selector coordinates the multiplexing of the LCD in accordance with the
selected LCD drive configuration. The operation of the voltage selector is controlled by the
mode-set command from the command decoder. The biasing configurations that apply to
the preferred modes of operation, together with the biasing characteristics as functions of
VLCD and the resulting discrimination ratios (D) are given in Table 6.
Discrimination is a term which is defined as the ratio of the on and off RMS voltage across
a segment. It can be thought of as a measurement of contrast.
Table 6.
Biasing characteristics
LCD drive
mode
Number of:
LCD bias
Backplanes Levels configuration
V off RMS
------------------------V LCD
V on RMS
-----------------------V LCD
V on RMS
D = -----------------------V off RMS
static
1
2
static
0
1
3
1⁄
2
0.354
0.791
2.236
1:2 multiplex 2
4
1⁄
3
0.333
0.745
2.236
1:3 multiplex 3
4
1⁄
3
0.333
0.638
1.915
1:4 multiplex 4
4
1⁄
3
0.333
0.577
1.732
1:2 multiplex 2
A practical value for VLCD is determined by equating Voff(RMS) with a defined LCD
threshold voltage (Vth(off)), typically when the LCD exhibits approximately 10 % contrast. In
the static drive mode, a suitable choice is VLCD > 3Vth(off).
Multiplex drive modes of 1:3 and 1:4 with 1⁄2 bias are possible but the discrimination and
hence the contrast ratios are smaller.
1
Bias is calculated by ------------- , where the values for a are
1+a
a = 1 for 1⁄2 bias
a = 2 for 1⁄3 bias
The RMS on-state voltage (Von(RMS)) for the LCD is calculated with Equation 1:
V on RMS =
V LCD
a 2 + 2a + n
-----------------------------2
n 1 + a
(1)
where the values for n are
n = 1 for static drive mode
n = 2 for 1:2 multiplex drive mode
n = 3 for 1:3 multiplex drive mode
n = 4 for 1:4 multiplex drive mode
The RMS off-state voltage (Voff(RMS)) for the LCD is calculated with Equation 2:
V off RMS =
V LCD
a 2 – 2a + n
-----------------------------2
n 1 + a
(2)
Discrimination is the ratio of Von(RMS) to Voff(RMS) and is determined from Equation 3:
PCF85134
Product data sheet
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Rev. 3 — 12 May 2014
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8 of 53
PCF85134
NXP Semiconductors
Universal 60 x 4 LCD segment driver for low multiplex rates
V on RMS
D = ---------------------- =
V off RMS
2
a + 2a + n
--------------------------2
a – 2a + n
(3)
Using Equation 3, the discrimination for an LCD drive mode of 1:3 multiplex with
1⁄
2
bias is
1⁄
2
21
bias is ---------- = 1.528 .
3
3 = 1.732 and the discrimination for an LCD drive mode of 1:4 multiplex with
The advantage of these LCD drive modes is a reduction of the LCD full scale voltage VLCD
as follows:
• 1:3 multiplex (1⁄2 bias): V LCD =
6 V off RMS = 2.449V off RMS
4 3
- = 2.309V off RMS
• 1:4 multiplex (1⁄2 bias): V LCD = --------------------3
These compare with V LCD = 3V off RMS when 1⁄3 bias is used.
VLCD is sometimes referred as the LCD operating voltage.
7.3.1 Electro-optical performance
Suitable values for Von(RMS) and Voff(RMS) are dependent on the LCD liquid used. The
RMS voltage, at which a pixel is switched on or off, determines the transmissibility of the
pixel.
For any given liquid, there are two threshold values defined. One point is at 10 % relative
transmission (at Vth(off)) and the other at 90 % relative transmission (at Vth(on)), see
Figure 5. For a good contrast performance, the following rules should be followed:
V on RMS V th on
(4)
V off RMS V th off
(5)
Von(RMS) and Voff(RMS) are properties of the display driver and are affected by the selection
of a, n (see Equation 1 to Equation 3) and the VLCD voltage.
Vth(off) and Vth(on) are properties of the LCD liquid and can be provided by the module
manufacturer. Vth(off) is sometimes just named Vth. Vth(on) is sometimes named saturation
voltage Vsat.
It is important to match the module properties to those of the driver in order to achieve
optimum performance.
PCF85134
Product data sheet
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Rev. 3 — 12 May 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
9 of 53
PCF85134
NXP Semiconductors
Universal 60 x 4 LCD segment driver for low multiplex rates
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Fig 5.
PCF85134
Product data sheet
Electro-optical characteristic: relative transmission curve of the liquid
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Rev. 3 — 12 May 2014
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10 of 53
PCF85134
NXP Semiconductors
Universal 60 x 4 LCD segment driver for low multiplex rates
7.4 LCD drive mode waveforms
7.4.1 Static drive mode
The static LCD drive mode is used when a single backplane is provided in the LCD.
Backplane and segment drive waveforms for this mode are shown in Figure 6.
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Vstate1(t) = VSn(t) VBP0(t).
Von(RMS) = VLCD.
Vstate2(t) = V(Sn + 1)(t) VBP0(t).
Voff(RMS) = 0 V.
Fig 6.
PCF85134
Product data sheet
Static drive mode waveforms
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Rev. 3 — 12 May 2014
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11 of 53
PCF85134
NXP Semiconductors
Universal 60 x 4 LCD segment driver for low multiplex rates
7.4.2 1:2 Multiplex drive mode
When two backplanes are provided in the LCD, the 1:2 multiplex mode applies. The
PCF85134 allows the use of 1⁄2 bias or 1⁄3 bias in this mode as shown in Figure 7 and
Figure 8.
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Vstate1(t) = VSn(t) VBP0(t).
Von(RMS) = 0.791VLCD.
Vstate2(t) = VSn(t) VBP1(t).
Voff(RMS) = 0.354VLCD.
Fig 7.
PCF85134
Product data sheet
Waveforms for the 1:2 multiplex drive mode with 1⁄2 bias
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Rev. 3 — 12 May 2014
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12 of 53
PCF85134
NXP Semiconductors
Universal 60 x 4 LCD segment driver for low multiplex rates
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Vstate1(t) = VSn(t) VBP0(t).
Von(RMS) = 0.745VLCD.
Vstate2(t) = VSn(t) VBP1(t).
Voff(RMS) = 0.333VLCD.
Fig 8.
PCF85134
Product data sheet
Waveforms for the 1:2 multiplex drive mode with 1⁄3 bias
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Rev. 3 — 12 May 2014
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13 of 53
PCF85134
NXP Semiconductors
Universal 60 x 4 LCD segment driver for low multiplex rates
7.4.3 1:3 Multiplex drive mode
When three backplanes are provided in the LCD, the 1:3 multiplex drive mode applies, as
shown in Figure 9.
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Vstate1(t) = VSn(t) VBP0(t).
Von(RMS) = 0.638VLCD.
Vstate2(t) = VSn(t) VBP1(t).
Voff(RMS) = 0.333VLCD.
Fig 9.
PCF85134
Product data sheet
Waveforms for the 1:3 multiplex drive mode with 1⁄3 bias
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Rev. 3 — 12 May 2014
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14 of 53
PCF85134
NXP Semiconductors
Universal 60 x 4 LCD segment driver for low multiplex rates
7.4.4 1:4 Multiplex drive mode
When four backplanes are provided in the LCD, the 1:4 multiplex drive mode applies, as
shown in Figure 10.
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Vstate1(t) = VSn(t) VBP0(t).
Von(RMS) = 0.577VLCD.
Vstate2(t) = VSn(t) VBP1(t).
Voff(RMS) = 0.333VLCD.
Fig 10. Waveforms for the 1:4 multiplex drive mode with 1⁄3 bias
PCF85134
Product data sheet
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Rev. 3 — 12 May 2014
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15 of 53
PCF85134
NXP Semiconductors
Universal 60 x 4 LCD segment driver for low multiplex rates
7.5 Oscillator
The internal logic and the LCD drive signals of the PCF85134 are timed by the frequency
fclk. It equals either the built-in oscillator frequency fosc or the external clock frequency
fclk(ext). The clock frequency fclk determines the LCD frame frequency (ffr).
7.5.1 Internal clock
The internal oscillator is enabled by connecting pin OSC to pin VSS. In this case, the
output from pin CLK is the clock signal for any cascaded PCF85134 in the system.
7.5.2 External clock
Pin CLK is enabled as an external clock input by connecting pin OSC to VDD.
Remark: A clock signal must always be supplied to the device. Removing the clock may
freeze the LCD in a DC state, which is not suitable for the liquid crystal.
7.6 Timing and frame frequency
The PCF85134 timing controls the internal data flow of the device. This includes the
transfer of display data from the display RAM to the display segment outputs. In cascaded
applications, the correct timing relationship between each PCF85134 in the system is
maintained by the synchronization signal at pin SYNC. The timing also generates the LCD
frame signal whose frequency is derived from the clock frequency. The frame signal
frequency is a fixed division of the clock frequency from either the internal or an external
clock.
Table 7.
LCD frame frequencies
Operating mode ratio
Frame frequency with respect to fclk (typical)
Unit
fclk = 1970 Hz
f clk
f fr = ------24
82
Hz
7.7 Display register
The display register holds the display data while the corresponding multiplex signals are
generated.
7.8 Segment outputs
The LCD drive section includes 60 segment outputs (S0 to S59) which should be
connected directly to the LCD. The segment output signals are generated based on the
multiplexed backplane signals and with data resident in the display register. When less
than 60 segment outputs are required, the unused segment outputs must be left
open-circuit.
PCF85134
Product data sheet
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Rev. 3 — 12 May 2014
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PCF85134
NXP Semiconductors
Universal 60 x 4 LCD segment driver for low multiplex rates
7.9 Backplane outputs
The LCD drive section includes four backplane outputs BP0 to BP3 which must be
connected directly to the LCD. The backplane output signals are generated in accordance
with the selected LCD drive mode.
• In 1:4 multiplex drive mode: BP0 to BP3 must be connected directly to the LCD.
If less than four backplane outputs are required, the unused outputs can be left
open-circuit.
• In 1:3 multiplex drive mode BP3 carries the same signal as BP1, therefore these two
adjacent outputs can be tied together to give enhanced drive capabilities.
• In 1:2 multiplex drive mode BP0 and BP2, respectively, BP1 and BP3 carry the same
signals and can also be paired to increase the drive capabilities.
• In static drive mode, the same signal is carried by all four backplane outputs and they
can be connected in parallel for very high drive requirements.
7.10 Display RAM
The display RAM is a static 60 4-bit RAM which stores LCD data. A logic 1 in the RAM
bit map indicates the on-state (Von(RMS)) of the corresponding LCD element. Similarly, a
logic 0 indicates the off-state (Voff(RMS)). For more information on Von(RMS) and Voff(RMS),
see Section 7.3.
There is a one-to-one correspondence between
• the bits in the RAM bitmap and the LCD elements
• the RAM columns and the segment outputs
• the RAM rows and the backplane outputs.
The display RAM bit map, Figure 11, shows row 0 to row 3 which correspond with the
backplane outputs BP0 to BP3, and column 0 to column 59 which correspond with the
segment outputs S0 to S59. In multiplexed LCD applications, the data of each row of the
display RAM is time-multiplexed with the corresponding backplane (row 0 with BP0, row 1
with BP1, and so on).
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The display RAM bit map shows the direct relationship between the display RAM addresses and
the segment outputs and between the bits in a RAM word and the backplane outputs.
Fig 11. Display RAM bit map
PCF85134
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 12 May 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
17 of 53
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Fig 12. Relationship between LCD layout, drive mode, display RAM filling order and display data transmitted over the I2C-bus
PCF85134
18 of 53
© NXP Semiconductors N.V. 2014. All rights reserved.
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Universal 60 x 4 LCD segment driver for low multiplex rates
Rev. 3 — 12 May 2014
All information provided in this document is subject to legal disclaimers.
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NXP Semiconductors
PCF85134
Product data sheet
GULYHPRGH
PCF85134
NXP Semiconductors
Universal 60 x 4 LCD segment driver for low multiplex rates
When display data is transmitted to the PCF85134, the display bytes received are stored
in the display RAM in accordance with the selected LCD multiplex drive mode. The data is
stored as it arrives and depending on the current multiplex drive mode, data is stored
singularly, in pairs, triples, or quadruples. To illustrate the filling order, an example of a
7-segment display showing all drive modes is given in Figure 12. The RAM filling
organization depicted applies equally to other LCD types.
The following applies to Figure 12:
• In static drive mode the eight transmitted data bits are placed into row 0 as one byte.
• In 1:2 multiplex drive mode the eight transmitted data bits are placed in pairs into
row 0 and row 1 as four successive 2-bit RAM words.
• In 1:3 multiplex drive mode the eight bits are placed in triples into row 0, row
1, and row 2 as three successive 3-bit RAM words, with bit 3 of the third address left
unchanged. It is not recommended to use this bit in a display because of the difficult
addressing. This last bit may, if necessary, be controlled by an additional transfer to
this address. But care should be taken to avoid overwriting adjacent data because
always full bytes are transmitted (see Section 7.10.3).
• In 1:4 multiplex drive mode, the eight transmitted data bits are placed in quadruples
into row 0, row 1, row 2, and row 3 as two successive 4-bit RAM words.
7.10.1 Data pointer
The addressing mechanism for the display RAM is realized using the data pointer. This
allows the loading of an individual display data byte, or a series of display data bytes, into
any location of the display RAM. The sequence commences with the initialization of the
data pointer by the load-data-pointer command (see Table 11). Following this command,
an arriving data byte is stored at the display RAM address indicated by the data pointer.
The filling order is shown in Figure 12. After each byte is stored, the content of the data
pointer is automatically incremented by a value dependent on the selected LCD drive
mode:
•
•
•
•
In static drive mode by eight.
In 1:2 multiplex drive mode by four.
In 1:3 multiplex drive mode by three.
In 1:4 multiplex drive mode by two.
If an I2C-bus data access terminates early, then the state of the data pointer is unknown.
Consequently, the data pointer must be rewritten before further RAM accesses.
7.10.2 Subaddress counter
The storage of display data is determined by the content of the subaddress counter.
Storage is allowed only when the content of the subaddress counter matches with the
hardware subaddress applied to A0, A1, and A2. The subaddress counter value is defined
by the device-select command (see Table 14). If the content of the subaddress counter
and the hardware subaddress do not match, then data storage is inhibited but the data
pointer is incremented as if data storage had taken place. The subaddress counter is also
incremented when the data pointer overflows.
PCF85134
Product data sheet
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Rev. 3 — 12 May 2014
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19 of 53
PCF85134
NXP Semiconductors
Universal 60 x 4 LCD segment driver for low multiplex rates
In cascaded applications each PCF85134 in the cascade must be addressed separately.
Initially, the first PCF85134 is selected by sending the device-select command matching
the first hardware subaddress. Then the data pointer is set to the preferred display RAM
address by sending the load-data-pointer command.
Once the display RAM of the first PCF85134 has been written, the second PCF85134 is
selected by sending the device-select command again. This time however the command
matches the hardware subaddress of the second device. Next the load-data-pointer
command is sent to select the preferred display RAM address of the second PCF85134.
This last step is very important because during writing data to the first PCF85134, the data
pointer of the second PCF85134 is incremented. In addition, the hardware subaddress
should not be changed while the device is being accessed on the I2C-bus interface.
7.10.3 RAM writing in 1:3 multiplex drive mode
In 1:3 multiplex drive mode, the RAM is written as shown in Table 8 (see Figure 12 as
well).
Table 8.
Standard RAM filling in 1:3 multiplex drive mode
Assumption: BP2/S2, BP2/S5, BP2/S8 etc. are not connected to any elements on the display.
Display RAM
bits (rows)/
backplane
outputs (BPn)
Display RAM addresses (columns)/segment outputs (Sn)
0
1
2
3
4
5
6
7
8
9
:
0
a7
a4
a1
b7
b4
b1
c7
c4
c1
d7
:
1
a6
a3
a0
b6
b3
b0
c6
c3
c0
d6
:
2
a5
a2
-
b5
b2
-
c5
c2
-
d5
:
3
-
-
-
-
-
-
-
-
-
-
:
If the bit at position BP2/S2 would be written by a second byte transmitted, then the
mapping of the segment bits would change as illustrated in Table 9.
Table 9.
Entire RAM filling by rewriting in 1:3 multiplex drive mode
Assumption: BP2/S2, BP2/S5, BP2/S8 etc. are connected to elements on the display.
Display RAM
bits (rows)/
backplane
outputs (BPn)
Display RAM addresses (columns)/segment outputs (Sn)
0
1
2
0
a7
a4
a1/b7 b4
b1/c7 c4
1
a6
a3
a0/b6 b3
2
a5
a2
b5
b2
3
-
-
-
-
3
4
5
6
7
8
9
:
c1/d7 d4
d1/e7 e4
:
b0/c6 c3
c0/d6 d3
d0/e6 e3
:
c5
c2
d5
d2
e5
e2
:
-
-
-
-
-
-
:
In the case described in Table 9 the RAM has to be written entirely and BP2/S2, BP2/S5,
BP2/S8, and so on, have to be connected to elements on the display. This can be
achieved by a combination of writing and rewriting the RAM like follows:
• In the first write to the RAM, bits a7 to a0 are written.
• In the second write, bits b7 to b0 are written, overwriting bits a1 and a0 with bits b7
and b6.
• In the third write, bits c7 to c0 are written, overwriting bits b1 and b0 with bits c7 and
c6.
PCF85134
Product data sheet
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Rev. 3 — 12 May 2014
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20 of 53
PCF85134
NXP Semiconductors
Universal 60 x 4 LCD segment driver for low multiplex rates
Depending on the method of writing to the RAM (standard or entire filling by rewriting),
some elements remain unused or can be used. But it has to be considered in the module
layout process as well as in the driver software design.
7.10.4 Bank selector
7.10.4.1
Output bank selector
The output bank selector (see Table 15) selects one of the four rows per display RAM
address for transfer to the display register. The actual row selected depends on the
particular LCD drive mode in operation and on the instant in the multiplex sequence.
• In 1:4 multiplex mode, all RAM addresses of row 0 are selected, these are followed by
the contents of row 1, 2, and then 3
• In 1:3 multiplex mode, rows 0, 1, and 2 are selected sequentially
• In 1:2 multiplex mode, rows 0 and 1 are selected
• In static mode, row 0 is selected
The SYNC signal resets these sequences to the following starting points:
•
•
•
•
row 3 for 1:4 multiplex
row 2 for 1:3 multiplex
row 1 for 1:2 multiplex
row 0 for static mode
The PCF85134 includes a RAM bank switching feature in the static and 1:2 multiplex drive
modes. In the static drive mode, the bank-select command may request the contents of
row 2 to be selected for display instead of the contents of row 0. In the 1:2 multiplex mode,
the contents of rows 2 and 3 may be selected instead of rows 0 and 1. This gives the
provision for preparing display information in an alternative bank and to be able to switch
to it once it is assembled.
7.10.4.2
Input bank selector
The input bank selector loads display data into the display data in accordance with the
selected LCD drive configuration. Display data can be loaded in row 2 in static drive mode
or in rows 2 and 3 in 1:2 multiplex drive mode by using the bank-select command (see
Table 15). The input bank selector functions independently to the output bank selector.
7.11 Blinking
The display blinking capabilities of the PCF85134 are very versatile. The whole display
can blink at frequencies selected by the blink-select command (see Table 16). The blink
frequencies are derived from the clock frequency. The ratio between the clock and blink
frequency depends on the blink mode selected (see Table 10).
PCF85134
Product data sheet
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PCF85134
NXP Semiconductors
Universal 60 x 4 LCD segment driver for low multiplex rates
Table 10.
Blink frequencies
Blink mode
Operating mode ratio
Blink frequency with respect to fclk (typical)
Unit
fclk = 1970 Hz
off
-
blinking off
Hz
1
f clk
f blink = -------768
2.5
Hz
2
f clk
f blink = ----------1536
1.3
Hz
3
f clk
f blink = ----------3072
0.6
Hz
An additional feature is for an arbitrary selection of LCD segments to blink. This applies to
the static and 1:2 multiplex drive modes and can be implemented without any
communication overheads. With the output bank selector, the displayed RAM banks are
exchanged with alternate RAM banks at the blink frequency. This mode can also be
specified by the blink-select command.
In the 1:3 and 1:4 multiplex modes, where no alternate RAM bank is available, groups of
LCD elements can blink by selectively changing the display RAM data at fixed time
intervals.
The entire display can blink at a frequency other than the nominal blink frequency. This
can be effectively performed by resetting and setting the display enable bit E at the
required rate using the mode-set command (see Table 12).
7.12 Command decoder
The command decoder identifies command bytes that arrive on the I2C-bus. There are
five commands:
Table 11.
PCF85134
Product data sheet
Definition of commands
Command
Operation code
Bit
7
6
5
4
3
2
1
Reference
mode-set
1
1
0
0
E
B
M[1:0]
load-data-pointer
0
P[6:0]
0
Table 12
Table 13
device-select
1
1
1
0
0
A[2:0]
bank-select
1
1
1
1
1
0
I
blink-select
1
1
1
1
0
AB
BF[1:0]
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Table 14
O
Table 15
Table 16
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PCF85134
NXP Semiconductors
Universal 60 x 4 LCD segment driver for low multiplex rates
Table 12.
Mode-set command bit description
Bit
Symbol
Value
Description
7 to 4
-
1100
fixed value
3
E
2
display status[1]
0[2]
disabled (blank)[3]
1
enable
LCD bias configuration[4]
B
1 to 0
0[2]
1⁄
3
bias
1
1⁄
2
bias
M[1:0]
LCD drive mode selection
01
static; one backplane
10
1:2 multiplex; two backplanes
11
1:3 multiplex; three backplanes
00[2]
1:4 multiplex; four backplanes
[1]
The possibility to disable the display allows implementation of blinking under external control.
[2]
Default value.
[3]
The display is disabled by setting all backplane and segment outputs to VLCD.
[4]
Not applicable for static drive mode.
Table 13. Load-data-pointer command bit description
See Section 7.10.1 on page 19.
Bit
Symbol
Value
7
-
0
fixed value
6 to 0
P[6:0]
0000000[1] to
0111011
7-bit binary value, 0 to 59; transferred to the
data pointer to define one of 60 display RAM
addresses
[1]
Description
Default value.
Table 14. Device-select command bit description
See Section 7.10.2 on page 19.
Bit
Symbol
Value
Description
7 to 3
-
11100
fixed value
A[2:0]
000[1]
2 to 0
[1]
PCF85134
Product data sheet
to 111
3-bit binary value, 0 to 7; transferred to the
subaddress counter to define one of eight
hardware subaddresses
Default value.
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PCF85134
NXP Semiconductors
Universal 60 x 4 LCD segment driver for low multiplex rates
Table 15. Bank-select command bit description
See Section 7.10.4 on page 21.
Bit
Symbol
Value
Description
1:2 multiplex[1]
Static
7 to 2
-
1
I
0
111110
fixed value
input bank selection: storage of arriving
display data
0[2]
RAM row 0
RAM rows 0 and 1
1
RAM row 2
RAM rows 2 and 3
O
output bank selection: retrieval of LCD display
data
0[2]
RAM row 0
RAM rows 0 and 1
1
RAM row 2
RAM rows 2 and 3
[1]
The bank-select command has no effect in 1:3 or 1:4 multiplex drive modes.
[2]
Default value.
Table 16. Blink-select command bit description
See Section 7.11 on page 21.
Bit
Symbol
Value
Description
7 to 3
-
11110
fixed value
2
AB
1 to 0
blink mode selection
0[1]
normal blinking[2]
1
alternate RAM bank blinking[3]
blink frequency selection[4]
BF[1:0]
00[1]
off
01
1
10
2
11
3
[1]
Default value.
[2]
Normal blinking is assumed when the LCD multiplex drive modes 1:3 or 1:4 are selected.
[3]
Alternate RAM bank blinking does not apply in 1:3 and 1:4 multiplex drive modes.
[4]
For the blink frequencies, see Table 10.
7.13 Display controller
The display controller executes the commands identified by the command decoder. It
contains the status registers of the PCF85134 and coordinates their effects. The display
controller is also responsible for loading display data into the display RAM in the correct
filling order.
PCF85134
Product data sheet
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Rev. 3 — 12 May 2014
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PCF85134
NXP Semiconductors
Universal 60 x 4 LCD segment driver for low multiplex rates
8. Characteristics of the I2C-bus
The I2C-bus is for bidirectional, two-line communication between different ICs or modules.
The two lines are a Serial DAta line (SDA) and a Serial CLock line (SCL). Both lines must
be connected to a positive supply via a pull-up resistor when connected to the output
stages of a device. Data transfer may be initiated only when the bus is not busy.
8.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as a control signal. Bit transfer is illustrated in Figure 13.
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Fig 13. Bit transfer
8.1.1 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy.
A HIGH-to-LOW change of the data line, while the clock is HIGH, is defined as the START
condition (S).
A LOW-to-HIGH change of the data line, while the clock is HIGH, is defined as the STOP
condition (P).
The START and STOP conditions are illustrated in Figure 14.
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Fig 14. Definition of START and STOP conditions
8.2 System configuration
A device generating a message is a transmitter, a device receiving a message is the
receiver. The device that controls the message is the master; and the devices which are
controlled by the master are the slaves. The system configuration is shown in Figure 15.
PCF85134
Product data sheet
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Rev. 3 — 12 May 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
25 of 53
PCF85134
NXP Semiconductors
Universal 60 x 4 LCD segment driver for low multiplex rates
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Fig 15. System configuration
8.3 Acknowledge
The number of data bytes transferred between the START and STOP conditions from
transmitter to receiver is unlimited. Each byte of 8 bits is followed by an acknowledge
cycle.
• A slave receiver, which is addressed, must generate an acknowledge after the
reception of each byte.
• A master receiver must generate an acknowledge after the reception of each byte that
has been clocked out of the slave transmitter.
• The device that acknowledges must pull-down the SDA line during the acknowledge
clock pulse, so that the SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times must be considered).
• A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
Acknowledgement on the I2C-bus is illustrated in Figure 16.
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Fig 16. Acknowledgement of the I2C-bus
PCF85134
Product data sheet
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Rev. 3 — 12 May 2014
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PCF85134
NXP Semiconductors
Universal 60 x 4 LCD segment driver for low multiplex rates
8.4 I2C-bus controller
The PCF85134 acts as an I2C-bus slave receiver. It does not initiate I2C-bus transfers or
transmit data to an I2C-bus master receiver. The only data output from the PCF85134 are
the acknowledge signals of the selected devices. Device selection depends on the
I2C-bus slave address, on the transferred command data and on the hardware
subaddress.
In single device applications, the hardware subaddress inputs A0, A1, and A2 are
normally tied to VSS which defines the hardware subaddress 0. In multiple device
applications A0, A1, and A2 are tied to VSS or VDD using a binary coding scheme, so that
no two devices with a common I2C-bus slave address have the same hardware
subaddress.
8.5 Input filters
To enhance noise immunity in electrically adverse environments, RC low-pass filters are
provided on the SDA and SCL lines.
8.6 I2C-bus protocol
Two I2C-bus slave addresses (0111 000 and 0111 001) are used to address the
PCF85134. The entire I2C-bus slave address byte is shown in Table 17.
Table 17.
I2C slave address byte
Slave address
Bit
7
6
5
4
3
2
1
MSB
0
0
LSB
1
1
1
0
0
SA0
R/W
The PCF85134 is a write-only device and does not respond to a read access, therefore
bit 0 should always be logic 0. Bit 1 of the slave address byte, that a PCF85134 will
respond to, is defined by the level tied to its SA0 input (VSS for logic 0 and VDD for logic 1).
Having two reserved slave addresses allows the following on the same I2C-bus:
• Up to 16 PCF85134 for very large LCD applications
• The use of two types of LCD multiplex drive
The I2C-bus protocol is shown in Figure 17. The sequence is initiated with a START
condition (S) from the I2C-bus master which is followed by one of the available PCF85134
slave addresses. All PCF85134 with the same SA0 level acknowledge in parallel to the
slave address. All PCF85134 with the alternative SA0 level ignore the whole I2C-bus
transfer.
PCF85134
Product data sheet
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Rev. 3 — 12 May 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
27 of 53
PCF85134
NXP Semiconductors
Universal 60 x 4 LCD segment driver for low multiplex rates
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Fig 17. I2C-bus protocol
After acknowledgement, the control byte is sent defining if the next byte is a RAM or
command information. The control byte also defines if the next byte is a control byte or
further RAM or command data (see Figure 18 and Table 18). In this way, it is possible to
configure the device and then fill the display RAM with little overhead.
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Fig 18. Control byte format
Table 18.
Control byte description
Bit
Symbol
7
CO
6
Value
continue bit
0
last control byte
1
control bytes continue
RS
register selection
0
1
5 to 0
-
Description
command register
data register
unused
The command bytes and control bytes are also acknowledged by all addressed
PCF85134 connected to the bus.
The display bytes are stored in the display RAM at the address specified by the data
pointer and the subaddress counter. Both data pointer and subaddress counter are
automatically updated.
PCF85134
Product data sheet
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Rev. 3 — 12 May 2014
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28 of 53
PCF85134
NXP Semiconductors
Universal 60 x 4 LCD segment driver for low multiplex rates
The acknowledgement, after each byte, is made only by the A0, A1, and A2 addressed
PCF85134. After the last display byte, the I2C-bus master issues a STOP condition (P).
Alternatively a START may be issued to RESTART I2C-bus access.
9. Internal circuitry
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Fig 19. Device protection diagram
PCF85134
Product data sheet
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29 of 53
PCF85134
NXP Semiconductors
Universal 60 x 4 LCD segment driver for low multiplex rates
10. Safety notes
CAUTION
This device is sensitive to ElectroStatic Discharge (ESD). Observe precautions for handling
electrostatic sensitive devices.
Such precautions are described in the ANSI/ESD S20.20, IEC/ST 61340-5, JESD625-A or
equivalent standards.
CAUTION
Static voltages across the liquid crystal display can build up when the LCD supply voltage
(VLCD) is on while the IC supply voltage (VDD) is off, or vice versa. This may cause unwanted
display artifacts. To avoid such artifacts, VLCD and VDD must be applied or removed together.
PCF85134
Product data sheet
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PCF85134
NXP Semiconductors
Universal 60 x 4 LCD segment driver for low multiplex rates
11. Limiting values
Table 19. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).[1]
Symbol
Parameter
VDD
Conditions
Min
Max
Unit
supply voltage
0.5
+6.5
V
IDD
supply current
50
+50
mA
VLCD
LCD supply voltage
0.5
+7.5
V
IDD(LCD)
LCD supply current
50
+50
mA
ISS
ground supply current
50
+50
mA
VI
input voltage
[2]
0.5
+6.5
V
II
input current
[2]
10
+10
mA
VO
output voltage
[2]
0.5
+6.5
V
[3]
0.5
+7.5
V
IO
output current
10
+10
mA
Ptot
total power dissipation
-
400
mW
P/out
power dissipation per
output
-
100
mW
VESD
electrostatic
discharge voltage
latch-up current
Ilu
Tstg
storage temperature
Tamb
ambient temperature
[2][3]
HBM
[4]
-
2500
V
CDM
[5]
-
1000
V
Vlu = 11.5 V
[6]
-
200
mA
[7]
65
+150
C
40
+85
C
operating device
[1]
Stresses above these values listed may cause permanent damage to the device.
[2]
Pins SDA, SCL, CLK, SYNC, SA0, OSC, and A0 to A2.
[3]
Pins S0 to S59 and BP0 to BP3.
[4]
Pass level; Human Body Model (HBM), according to Ref. 8 “JESD22-A114”.
[5]
Pass level; Charged-Device Model (CDM), according to Ref. 9 “JESD22-C101”.
[6]
Pass level; latch-up testing according to Ref. 10 “JESD78” at maximum ambient temperature (Tamb(max)).
[7]
According to the store and transport requirements (see Ref. 13 “UM10569”) the devices have to be stored at a temperature of +8 C to
+45 C and a humidity of 25 % to 75 %.
PCF85134
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PCF85134
NXP Semiconductors
Universal 60 x 4 LCD segment driver for low multiplex rates
12. Static characteristics
Table 20. Static characteristics
VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 6.5 V; Tamb = 40 C to +85 C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Supplies
VDD
supply voltage
1.8
-
5.5
V
VLCD
LCD supply voltage
2.5
-
6.5
V
fclk(ext) = 1536 Hz
[1]
-
8
20
A
fclk(ext) = 1536 Hz
[1]
-
24
60
A
VSS 0.5
-
VDD + 0.5
V
IDD
IDD(LCD)
supply current
LCD supply current
Logic
VI
input voltage
VIL
LOW-level input
voltage
on pins CLK, SYNC, OSC, A0 to
A2 and SA0
VSS
-
0.3VDD
V
VIH
HIGH-level input
voltage
on pins CLK, SYNC, OSC, A0 to
A2 and SA0
0.7VDD
-
VDD
V
VPOR
power-on reset
voltage
1.0
1.3
1.6
V
IOL
LOW-level output
current
output sink current; VOL = 0.4 V;
VDD = 5 V; on pins CLK and
SYNC
1
-
-
mA
IOH
HIGH-level output
current
output source current; VOH = 4.6
V;
VDD = 5 V; on pin CLK
1
-
-
mA
IL
leakage current
VI = VDD or VSS; on pins SA0, A0
to A2 and CLK
1
-
+1
A
1
-
+1
A
CI
input capacitance
-
-
7
pF
VSS 0.5
-
5.5
V
pin SCL
VSS
-
0.3VDD
V
pin SDA
VSS
-
0.2VDD
V
0.7VDD
-
5.5
V
3
-
-
mA
VI = VDD; on pin OSC
I2C-bus;
pins SDA and
[2]
SCL[3]
VI
input voltage
VIL
LOW-level input
voltage
VIH
HIGH-level input
voltage
IOL
LOW-level output
current
output sink current; VOL = 0.4 V;
VDD = 5 V; on pin SDA
IL
leakage current
VI = VDD or VSS
Ci
1
-
+1
A
[2]
-
-
7
pF
Cbpl = 35 nF
[4]
100
-
+100
mV
VLCD = 5 V
[5]
-
1.5
10
k
Csgm = 35 nF
[6]
100
-
+100
mV
VLCD = 5 V
[5]
-
6.0
13.5
k
input capacitance
LCD outputs
Output pins BP0 to BP3
VBP
RBP
voltage on pin BP
resistance on pin BP
Output pins S0 to S59
VS
RS
voltage on pin S
resistance on pin S
PCF85134
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PCF85134
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Universal 60 x 4 LCD segment driver for low multiplex rates
[1]
LCD outputs are open-circuit; inputs at VSS or VDD; external clock with 50 % duty factor; I2C-bus inactive.
[2]
Not tested, design specification only.
[3]
The I2C-bus interface of PCF85134 is 5 V tolerant.
[4]
Cbpl = backplane capacitance.
[5]
Measured on sample basis only.
[6]
Csgm = segment capacitance.
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PCF85134
NXP Semiconductors
Universal 60 x 4 LCD segment driver for low multiplex rates
13. Dynamic characteristics
Table 21. Dynamic characteristics
VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 6.5 V; Tamb = 40 C to +85 C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
1440
1970
2640
Hz
800
-
3600
Hz
Clock
Internal: output pin CLK
fosc
oscillator frequency
[1]
VDD = 5 V
External: input pin CLK
fclk(ext)
external clock
frequency
VDD = 5 V
tclk(H)
HIGH-level clock time
130
-
-
s
tclk(L)
LOW-level clock time
130
-
-
s
-
30
-
ns
1
-
-
s
-
-
30
s
Synchronization: input pin SYNC
tPD(SYNC_N) SYNC propagation
delay
tSYNC_NL
SYNC LOW time
Outputs: pins BP0 to BP3 and S0 to S59
tPD(drv)
driver propagation
delay
VLCD = 5 V
I2C-bus: timing[2]
Pin SCL
fSCL
SCL frequency
-
-
400
kHz
tLOW
LOW period of the
SCL clock
1.3
-
-
s
tHIGH
HIGH period of the
SCL clock
0.6
-
-
s
tSU;DAT
data set-up time
100
-
-
ns
tHD;DAT
data hold time
0
-
-
ns
Pin SDA
Pins SCL and SDA
tBUF
bus free time between
a STOP and START
condition
1.3
-
-
s
tSU;STO
set-up time for STOP
condition
0.6
-
-
s
tHD;STA
hold time (repeated)
START condition
0.6
-
-
s
tSU;STA
set-up time for a
repeated START
condition
0.6
-
-
s
tr
rise time of both SDA
and SCL signals
-
-
0.3
s
PCF85134
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PCF85134
NXP Semiconductors
Universal 60 x 4 LCD segment driver for low multiplex rates
Table 21. Dynamic characteristics …continued
VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 6.5 V; Tamb = 40 C to +85 C; unless otherwise specified.
Symbol
Parameter
tf
Conditions
Min
Typ
Max
Unit
fall time of both SDA
and SCL signals
-
-
0.3
s
Cb
capacitive load for
each bus line
-
-
400
pF
tw(spike)
spike pulse width
-
-
50
ns
[1]
Typical output (duty cycle = 50 %).
[2]
All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH with an
input voltage swing of VSS to VDD.
IFON
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Fig 20. Driver timing waveforms
PCF85134
Product data sheet
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PCF85134
NXP Semiconductors
Universal 60 x 4 LCD segment driver for low multiplex rates
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Fig 21. I2C-bus timing waveforms
PCF85134
Product data sheet
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PCF85134
NXP Semiconductors
Universal 60 x 4 LCD segment driver for low multiplex rates
14. Application information
14.1 Cascaded operation
Large display configurations of up to 16 PCF85134s can be recognized on the same
I2C-bus by using the 3-bit hardware subaddress (A0, A1 and A2) and the programmable
I2C-bus slave address (SA0).
Table 22.
Addressing cascaded PCF85134
Cluster
Bit SA0
Pin A2
Pin A1
Pin A0
Device
1
0
0
0
0
0
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
6
2
1
1
1
1
7
0
0
0
8
0
0
1
9
0
1
0
10
0
1
1
11
1
0
0
12
1
0
1
13
1
1
0
14
1
1
1
15
When cascaded PCF85134 are synchronized, they can share the backplane signals from
one of the devices in the cascade. Such an arrangement is cost-effective in large LCD
applications since the backplane outputs of only one device need to be through-plated to
the backplane electrodes of the display. The other PCF85134 of the cascade contribute
additional segment outputs. The backplanes can either be connected together to enhance
the drive capability or some can be left open-circuit (such as the ones from the slave
in Figure 22) or just some of the master and some of the slave will be taken to facilitate the
layout of the display.
PCF85134
Product data sheet
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Rev. 3 — 12 May 2014
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37 of 53
PCF85134
NXP Semiconductors
Universal 60 x 4 LCD segment driver for low multiplex rates
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(1) Is master (OSC connected to VSS).
(2) Is slave (OSC connected to VDD).
Fig 22. Cascaded PCF85134 configuration
The SYNC line is provided to maintain the correct synchronization between all cascaded
PCF85134. Synchronization is guaranteed after a power-on reset. The only time that
SYNC is likely to be needed is if synchronization is accidentally lost (for example, by noise
in adverse electrical environments or by defining a multiplex drive mode when PCF85134
with different SA0 levels are cascaded).
SYNC is organized as an input/output pin. The output selection is realized as an
open-drain driver with an internal pull-up resistor. A PCF85134 asserts the SYNC line at
the onset of its last active backplane signal and monitors the SYNC line at all other times.
If synchronization in the cascade is lost, it is restored by the first PCF85134 to assert
SYNC. The timing relationship between the backplane waveforms and the SYNC signal
for the various drive modes of the PCF85134 are shown in Figure 23.
The contact resistance between the SYNC on each cascaded device must be controlled.
If the resistance is too high, the device is not able to synchronize properly; this is
applicable to chip-on-glass applications. The maximum SYNC contact resistance allowed
for the number of devices in cascade is given in Table 23.
PCF85134
Product data sheet
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PCF85134
NXP Semiconductors
Universal 60 x 4 LCD segment driver for low multiplex rates
Table 23.
SYNC contact resistance
Number of devices
Maximum contact resistance
2
6000
3 to 5
2200
6 to 10
1200
11 to 16
700
The PCF85134 can always be cascaded with other devices of the same type or
conditionally with other devices of the same family. This allows optimal drive selection for
a given number of pixels to display. Figure 21 and Figure 23 show the timing of the
synchronization signals.
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Fig 23. Synchronization of the cascade for various PCF85134 drive modes
Only one master but multiple slaves are allowed in a cascade. All devices in the cascade
have to use the same clock whether it is supplied externally or provided by the master.
PCF85134
Product data sheet
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PCF85134
NXP Semiconductors
Universal 60 x 4 LCD segment driver for low multiplex rates
If an external clock source is used, all PCF85134 in the cascade must be configured such
as to receive the clock from that external source (pin OSC connected to VDD). It must be
ensured that the clock tree is designed such that on all PCF85134 the clock propagation
delay from the clock source to all PCF85134 in the cascade is as equal as possible since
otherwise synchronization artifacts may occur.
In mixed cascading configurations, care has to be taken that the specifications of the
individual cascaded devices are met at all times.
PCF85134
Product data sheet
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40 of 53
PCF85134
NXP Semiconductors
Universal 60 x 4 LCD segment driver for low multiplex rates
15. Package outline
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Fig 24. Package outline SOT315-1 (LQFP80)
PCF85134
Product data sheet
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PCF85134
NXP Semiconductors
Universal 60 x 4 LCD segment driver for low multiplex rates
16. Handling information
All input and output pins are protected against ElectroStatic Discharge (ESD) under
normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that
all normal precautions are taken as described in JESD625-A, IEC 61340-5 or equivalent
standards.
17. Packing information
For tape and reel packing information, please see Ref. 12 “SOT315-1_118” on page 48.
18. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
18.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
18.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•
•
•
•
PCF85134
Product data sheet
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
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PCF85134
NXP Semiconductors
Universal 60 x 4 LCD segment driver for low multiplex rates
• Inspection and repair
• Lead-free soldering versus SnPb soldering
18.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
18.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 25) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 24 and 25
Table 24.
SnPb eutectic process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
350
< 2.5
235
220
2.5
220
220
Table 25.
Lead-free process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 25.
PCF85134
Product data sheet
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PCF85134
NXP Semiconductors
Universal 60 x 4 LCD segment driver for low multiplex rates
temperature
maximum peak temperature
= MSL limit, damage level
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 25. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
PCF85134
Product data sheet
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44 of 53
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
NXP Semiconductors
PCF85134
Product data sheet
19. Appendix
19.1 LCD segment driver selection
Table 26.
Selection of LCD segment drivers
Type name
Number of elements at MUX
ffr (Hz)
Interface Package
AECQ100
40
80
120 160 -
-
-
1.8 to 5.5 1.8 to 5.5 32 to 256[1]
N
N
40 to 105 I2C / SPI
TSSOP56 Y
PCA8546ATT
-
-
-
176 -
-
-
1.8 to 5.5 2.5 to 9
60 to 300[1]
N
N
40 to 95
I2C
TSSOP56 Y
PCA8546BTT
-
-
-
176 -
-
-
1.8 to 5.5 2.5 to 9
60 to 300[1]
N
N
40 to 95
SPI
TSSOP56 Y
1.8 to 5.5 2.5 to 9
60 to
300[1]
Y
40 to 95
I2C
TQFP64
Y
60 to
300[1]
Y
Y
40 to 95
SPI
TQFP64
Y
N
N
40 to 85
I2C
LQFP80
N
N
40 to 95
I2C
LQFP80
Y
Y
40 to 105
I2C
LQFP80
Y
TSSOP56 N
-
-
-
Rev. 3 — 12 May 2014
All information provided in this document is subject to legal disclaimers.
PCA8547BHT
44
88
176 -
-
-
1.8 to 5.5 2.5 to 9
PCF85134HL
60
120 180 240 -
-
-
1.8 to 5.5 2.5 to 6.5 82
PCA85134H
PCA8543AHL
60
60
-
176 -
120 180 240 120 -
240 -
-
-
1.8 to 5.5 2.5 to 8
2.5 to 5.5 2.5 to 9
82
Y
N
60 to
300[1]
300[1]
Y
PCF8545ATT
-
-
-
176 252 320 -
1.8 to 5.5 2.5 to 5.5 60 to
N
N
40 to 85
I2C
PCF8545BTT
-
-
-
176 252 320 -
1.8 to 5.5 2.5 to 5.5 60 to 300[1]
N
N
40 to 85
SPI
TSSOP56 N
PCF8536AT
-
-
-
176 252 320 -
1.8 to 5.5 2.5 to 9
60 to 300[1]
N
N
40 to 85
I2C
TSSOP56 N
1.8 to 5.5 2.5 to 9
60 to
300[1]
N
N
40 to 85
SPI
TSSOP56 N
300[1]
TSSOP56 Y
PCF8536BT
-
-
-
176 252 320 -
-
-
-
176 252 320 -
1.8 to 5.5 2.5 to 9
60 to
N
N
40 to 95
PCA8536BT
-
-
-
176 252 320 -
1.8 to 5.5 2.5 to 9
60 to 300[1]
N
N
40 to 95
SPI
TSSOP56 Y
PCF8537AH
44
88
-
176 276 352 -
1.8 to 5.5 2.5 to 9
60 to 300[1]
Y
Y
40 to 85
I2C
TQFP64
N
1.8 to 5.5 2.5 to 9
60 to
300[1]
Y
Y
40 to 85
SPI
TQFP64
N
300[1]
Y
Y
40 to 95
I2C
TQFP64
Y
Y
Y
40 to 95
SPI
TQFP64
Y
Y
40 to 105
I2C
LQFP80
Y
Y
40 to 105
I2C
Bare die
Y
PCF8537BH
44
88
-
176 276 352 -
45 of 53
© NXP Semiconductors N.V. 2014. All rights reserved.
PCA8537AH
44
88
-
176 276 352 -
1.8 to 5.5 2.5 to 9
60 to
PCA8537BH
44
88
-
176 276 352 -
1.8 to 5.5 2.5 to 9
60 to 300[1]
2.5 to 5.5 2.5 to 9
60 to
300[1]
60 to
300[1]
PCA9620H
PCA9620U
60
60
120 120 -
240 320 480 240 320 480 -
2.5 to 5.5 2.5 to 9
Y
Y
PCF8576DU
40
80
120 160 -
-
-
1.8 to 5.5 2.5 to 6.5 77
N
N
40 to 85
I2C
Bare die
N
PCF8576EUG
40
80
120 160 -
-
-
1.8 to 5.5 2.5 to 6.5 77
N
N
40 to 85
I2C
Bare die
N
N
40 to 105
I2C
Bare die
Y
N
40 to 85
I2C
Bare die
N
N
40 to 95
I2C
Bare die
Y
PCA8576FUG
PCF85133U
PCA85133U
40
80
80
80
120 160 -
160 240 320 160 240 320 -
-
-
1.8 to 5.5 2.5 to 8
200
1.8 to 5.5 2.5 to 6.5 82,
110[2]
1.8 to 5.5 2.5 to 8
110[2]
82,
N
N
N
PCF85134
PCA8536AT
I2C
Universal 60 x 4 LCD segment driver for low multiplex rates
PCA8553DTT
88
1:9
VLCD (V) VLCD (V)
Tamb (C)
charge temperature
pump
compensat.
1:2 1:3
44
1:6 1:8
VLCD (V)
1:1
PCA8547AHT
1:4
VDD (V)
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Selection of LCD segment drivers …continued
Type name
Number of elements at MUX
ffr (Hz)
VLCD (V) VLCD (V)
Tamb (C)
charge temperature
pump
compensat.
AECQ100
PCA85233UG
80
160 240 320 -
-
-
1.8 to 5.5 2.5 to 8
150, 220[2]
N
N
40 to 105 I2C
Bare die
Y
PCF85132U
160 320 480 640 -
-
-
1.8 to 5.5 1.8 to 8
60 to 90[1]
N
N
40 to 85
I2C
Bare die
N
Y
40 to 105
I2C
Bare die
Y
N
40 to 95
I2C
Bare die
Y
N
N
40 to 95
I2C
Bare die
Y
Y
Y
40 to 85
I2C / SPI
Bare die
N
Y
40 to 105
I2C
Bare die
Y
PCA85132U
408 -
160 320 480 640 -
PCA85232U
160 320 480 640 -
PCF8538UG
102 204 -
PCA8538UG
102 204 -
Software programmable.
[2]
Hardware selectable.
-
-
2.5 to 5.5 4 to 12
1.8 to 5.5 1.8 to 8
1.8 to 5.5 1.8 to 8
45 to
300[1]
60 to
90[1]
117 to
176[1]
408 612 816 918 2.5 to 5.5 4 to 12
45 to 300[1]
408 612 816 918 2.5 to 5.5 4 to 12
300[1]
45 to
Y
N
Y
/ SPI
/ SPI
PCF85134
46 of 53
© NXP Semiconductors N.V. 2014. All rights reserved.
Universal 60 x 4 LCD segment driver for low multiplex rates
Rev. 3 — 12 May 2014
All information provided in this document is subject to legal disclaimers.
[1]
-
1:9
Interface Package
1:2 1:3
102 204 -
1:6 1:8
VLCD (V)
1:1
PCA8530DUG
1:4
VDD (V)
NXP Semiconductors
PCF85134
Product data sheet
Table 26.
PCF85134
NXP Semiconductors
Universal 60 x 4 LCD segment driver for low multiplex rates
20. Abbreviations
Table 27.
Acronym
PCF85134
Product data sheet
Abbreviations
Description
CDM
Charged-Device Model
CMOS
Complementary Metal-Oxide Semiconductor
DC
Direct Current
EMC
ElectroMagnetic Compatibility
ESD
ElectroStatic Discharge
HBM
Human Body Model
I2C
Inter-Integrated Circuit bus
IC
Integrated Circuit
LCD
Liquid Crystal Display
LSB
Least Significant Bit
MOS
Metal-Oxide Semiconductor
MSB
Most Significant Bit
MSL
Moisture Sensitivity Level
POR
Power-On Reset
RC
Resistance-Capacitance
RAM
Random Access Memory
RMS
Root Mean Square
RTC
Real-Time Clock
SCL
Serial CLock line
SDA
Serial DAta line
SMD
Surface-Mount Device
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 12 May 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
47 of 53
PCF85134
NXP Semiconductors
Universal 60 x 4 LCD segment driver for low multiplex rates
21. References
[1]
AN10365 — Surface mount reflow soldering description
[2]
AN10853 — ESD and EMC sensitivity of IC
[3]
AN11267 — EMC and system level ESD design guidelines for LCD drivers
[4]
AN11494 — Cascading NXP LCD segment drivers
[5]
IEC 60134 — Rating systems for electronic tubes and valves and analogous
semiconductor devices
[6]
IEC 61340-5 — Protection of electronic devices from electrostatic phenomena
[7]
IPC/JEDEC J-STD-020D — Moisture/Reflow Sensitivity Classification for
Nonhermetic Solid State Surface Mount Devices
[8]
JESD22-A114 — Electrostatic Discharge (ESD) Sensitivity Testing Human Body
Model (HBM)
[9]
JESD22-C101 — Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components
[10] JESD78 — IC Latch-Up Test
[11] JESD625-A — Requirements for Handling Electrostatic-Discharge-Sensitive
(ESDS) Devices
[12] SOT315-1_118 — LQFP80; Reel pack; SMD, 13", packing information
[13] UM10569 — Store and transport requirements
[14] UM10204 — I2C-bus specification and user manual
22. Revision history
Table 28.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
PCF85134 v.3
20140512
Product data sheet
-
PCF85134 v.2
Modifications:
•
•
•
•
•
•
•
Improved description of bit E
Added ordering information (Section 3.1)
Updated store and transport requirements (Table 19)
Adjusted Vlu value (Table 19)
Enhanced description about cascading (Section 14.1)
Added Section 17
Fixed typos
PCF85134 v.2
20110725
Product data sheet
-
PCF85134_1
PCF85134_1
20091217
Product data sheet
-
-
PCF85134
Product data sheet
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Rev. 3 — 12 May 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
48 of 53
PCF85134
NXP Semiconductors
Universal 60 x 4 LCD segment driver for low multiplex rates
23. Legal information
23.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
23.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
23.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
PCF85134
Product data sheet
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 12 May 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
49 of 53
PCF85134
NXP Semiconductors
Universal 60 x 4 LCD segment driver for low multiplex rates
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
23.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I2C-bus — logo is a trademark of NXP Semiconductors N.V.
24. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
PCF85134
Product data sheet
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Rev. 3 — 12 May 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
50 of 53
PCF85134
NXP Semiconductors
Universal 60 x 4 LCD segment driver for low multiplex rates
25. Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Ordering information . . . . . . . . . . . . . . . . . . . . .2
Ordering options . . . . . . . . . . . . . . . . . . . . . . . . .2
Marking codes . . . . . . . . . . . . . . . . . . . . . . . . . .2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5
Selection of possible display configurations . . . .6
Biasing characteristics . . . . . . . . . . . . . . . . . . . .8
LCD frame frequencies . . . . . . . . . . . . . . . . . .16
Standard RAM filling in 1:3 multiplex drive
mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Entire RAM filling by rewriting in 1:3 multiplex
drive mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Blink frequencies . . . . . . . . . . . . . . . . . . . . . . .22
Definition of commands . . . . . . . . . . . . . . . . . .22
Mode-set command bit description . . . . . . . . .23
Load-data-pointer command bit description . .23
Device-select command bit description . . . . . .23
Bank-select command bit description . . . . . . . .24
Blink-select command bit description . . . . . . .24
I2C slave address byte . . . . . . . . . . . . . . . . . . .27
Control byte description . . . . . . . . . . . . . . . . . .28
Limiting values . . . . . . . . . . . . . . . . . . . . . . . . .31
Static characteristics . . . . . . . . . . . . . . . . . . . .32
Dynamic characteristics . . . . . . . . . . . . . . . . . .34
Addressing cascaded PCF85134 . . . . . . . . . .37
SYNC contact resistance . . . . . . . . . . . . . . . . .39
SnPb eutectic process (from J-STD-020D) . . .43
Lead-free process (from J-STD-020D) . . . . . .43
Selection of LCD segment drivers . . . . . . . . . .45
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .47
Revision history . . . . . . . . . . . . . . . . . . . . . . . .48
PCF85134
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 12 May 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
51 of 53
PCF85134
NXP Semiconductors
Universal 60 x 4 LCD segment driver for low multiplex rates
26. Figures
Fig 1.
Fig 2.
Fig 3.
Fig 4.
Fig 5.
Fig 6.
Fig 7.
Fig 8.
Fig 9.
Fig 10.
Fig 11.
Fig 12.
Fig 13.
Fig 14.
Fig 15.
Fig 16.
Fig 17.
Fig 18.
Fig 19.
Fig 20.
Fig 21.
Fig 22.
Fig 23.
Fig 24.
Fig 25.
Block diagram of PCF85134 . . . . . . . . . . . . . . . . .3
Pin configuration for SOT315-1 (PCF85134). . . . .4
Example of displays suitable for PCF85134 . . . . .6
Typical system configuration . . . . . . . . . . . . . . . . .7
Electro-optical characteristic: relative
transmission curve of the liquid . . . . . . . . . . . . . .10
Static drive mode waveforms . . . . . . . . . . . . . . . . 11
Waveforms for the 1:2 multiplex drive mode
with 1⁄2 bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Waveforms for the 1:2 multiplex drive mode
with 1⁄3 bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Waveforms for the 1:3 multiplex drive mode
with 1⁄3 bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Waveforms for the 1:4 multiplex drive mode
with 1⁄3 bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Display RAM bit map . . . . . . . . . . . . . . . . . . . . . .17
Relationship between LCD layout, drive mode,
display RAM filling order and display data
transmitted over the I2C-bus . . . . . . . . . . . . . . . .18
Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Definition of START and STOP conditions. . . . . .25
System configuration . . . . . . . . . . . . . . . . . . . . . .26
Acknowledgement of the I2C-bus . . . . . . . . . . . .26
I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . .28
Control byte format . . . . . . . . . . . . . . . . . . . . . . .28
Device protection diagram . . . . . . . . . . . . . . . . . .29
Driver timing waveforms . . . . . . . . . . . . . . . . . . .35
I2C-bus timing waveforms . . . . . . . . . . . . . . . . . .36
Cascaded PCF85134 configuration . . . . . . . . . . .38
Synchronization of the cascade for various
PCF85134 drive modes . . . . . . . . . . . . . . . . . . . .39
Package outline SOT315-1 (LQFP80) . . . . . . . . .41
Temperature profiles for large and small
components . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
PCF85134
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 12 May 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
52 of 53
PCF85134
NXP Semiconductors
Universal 60 x 4 LCD segment driver for low multiplex rates
27. Contents
1
General description . . . . . . . . . . . . . . . . . . . . . . 1
2
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
3.1
Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2
4
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
5
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
6
Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
6.1
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
6.2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
7
Functional description . . . . . . . . . . . . . . . . . . . 6
7.1
Power-On Reset (POR) . . . . . . . . . . . . . . . . . . 7
7.2
LCD bias generator . . . . . . . . . . . . . . . . . . . . . 7
7.3
LCD voltage selector . . . . . . . . . . . . . . . . . . . . 8
7.3.1
Electro-optical performance . . . . . . . . . . . . . . . 9
7.4
LCD drive mode waveforms . . . . . . . . . . . . . . 11
7.4.1
Static drive mode . . . . . . . . . . . . . . . . . . . . . . 11
7.4.2
1:2 Multiplex drive mode. . . . . . . . . . . . . . . . . 12
7.4.3
1:3 Multiplex drive mode. . . . . . . . . . . . . . . . . 14
7.4.4
1:4 Multiplex drive mode. . . . . . . . . . . . . . . . . 15
7.5
Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.5.1
Internal clock . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.5.2
External clock . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.6
Timing and frame frequency . . . . . . . . . . . . . . 16
7.7
Display register . . . . . . . . . . . . . . . . . . . . . . . . 16
7.8
Segment outputs. . . . . . . . . . . . . . . . . . . . . . . 16
7.9
Backplane outputs . . . . . . . . . . . . . . . . . . . . . 17
7.10
Display RAM . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.10.1
Data pointer . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.10.2
Subaddress counter . . . . . . . . . . . . . . . . . . . . 19
7.10.3
RAM writing in 1:3 multiplex drive mode. . . . . 20
7.10.4
Bank selector . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.10.4.1 Output bank selector . . . . . . . . . . . . . . . . . . . 21
7.10.4.2 Input bank selector . . . . . . . . . . . . . . . . . . . . . 21
7.11
Blinking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.12
Command decoder . . . . . . . . . . . . . . . . . . . . . 22
7.13
Display controller . . . . . . . . . . . . . . . . . . . . . . 24
8
Characteristics of the I2C-bus . . . . . . . . . . . . 25
8.1
Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
8.1.1
START and STOP conditions . . . . . . . . . . . . . 25
8.2
System configuration . . . . . . . . . . . . . . . . . . . 25
8.3
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 26
8.4
I2C-bus controller . . . . . . . . . . . . . . . . . . . . . . 27
8.5
Input filters . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8.6
I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 27
9
Internal circuitry. . . . . . . . . . . . . . . . . . . . . . . . 29
10
Safety notes . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
11
12
13
14
14.1
15
16
17
18
18.1
18.2
18.3
18.4
19
19.1
20
21
22
23
23.1
23.2
23.3
23.4
24
25
26
27
Limiting values . . . . . . . . . . . . . . . . . . . . . . . .
Static characteristics . . . . . . . . . . . . . . . . . . .
Dynamic characteristics. . . . . . . . . . . . . . . . .
Application information . . . . . . . . . . . . . . . . .
Cascaded operation. . . . . . . . . . . . . . . . . . . .
Package outline. . . . . . . . . . . . . . . . . . . . . . . .
Handling information . . . . . . . . . . . . . . . . . . .
Packing information . . . . . . . . . . . . . . . . . . . .
Soldering of SMD packages . . . . . . . . . . . . . .
Introduction to soldering. . . . . . . . . . . . . . . . .
Wave and reflow soldering. . . . . . . . . . . . . . .
Wave soldering . . . . . . . . . . . . . . . . . . . . . . .
Reflow soldering . . . . . . . . . . . . . . . . . . . . . .
Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LCD segment driver selection . . . . . . . . . . . .
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . .
References. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Revision history . . . . . . . . . . . . . . . . . . . . . . .
Legal information . . . . . . . . . . . . . . . . . . . . . .
Data sheet status . . . . . . . . . . . . . . . . . . . . . .
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . .
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact information . . . . . . . . . . . . . . . . . . . .
Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
31
32
34
37
37
41
42
42
42
42
42
43
43
45
45
47
48
48
49
49
49
49
50
50
51
52
53
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2014.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 12 May 2014
Document identifier: PCF85134