ST33GxxxA Secure MCU with 32-bit ARM® SecurCore® SC300™ CPU, SWP interface and high-density Flash memory, automotive grade Data brief Security features Active shield Memory protection unit (MPU) Monitoring of environmental parameters Protection against faults 16- and 32-bit CRC calculation block (ISO 13239, IEEE 802.3, etc.) DFN8 6 × 5 mm Features True random number generator Hardware features Hardware security-enhanced DES accelerator ARM® Unique serial number on each die SecurCore® SC300™ 32-bit RISC core cadenced at 25 MHz 30 Kbytes of user RAM Up to 1280 Kbytes of user Flash memory with OTP area Asynchronous receiver transmitter supporting ISO/IEC 7816-3 T=0 and T=1 protocols (Slave mode supported) Hardware security-enhanced AES accelerator NESCRYPT coprocessor for public key cryptography algorithm Applications Major ST33G1M2A applications include: Mobile communications (Automotive grade) Java Card™ applications Single wire protocol (SWP) interface for communications with NFC router (ETSI 102-613 compliant) AECQ100 compliant Table 1. Device summary Serial peripheral interface (SPI) master/slave interface Part number Memory size in Kbytes Three 16-bit timers with interrupt capability ST33G1M2A 1280 Seven general-purpose I/Os enabling proprietary protocol implementation ST33G1M0A 1024 ST33G896A 896 1.8 V, 3 V and 5 V supply voltage ranges ST33G768A 768 External clock frequency from 1 up to 10 MHz Current consumption compatible with GSM and ETSI specifications Power-saving standby state ST33G640A 640 ST33G512A 512 ST33G384A 384 Contact assignment compatible with ISO/IEC 7816-2 ESD protection greater than 4 kV (HBM) March 2016 DocID027118 Rev 2 For further information contact your local STMicroelectronics sales office. 1/6 www.st.com Description 1 ST33GxxxA Description The ST33GxxxA (see Table 1) is a serial access microcontroller designed for secure mobile applications that incorporates the most recent generation of ARM® processors for embedded secure systems. Its SecurCore® SC300™ 32-bit RISC core is built on the Cortex® M3 core with additional security features to help to protect against advanced forms of attacks. The SC300™ core brings great performance and excellent code density thanks to the Thumb®-2 instruction set. The high-speed embedded Flash memory introduces more flexibility to the system. The ST33GxxxA also offers a serial communication interface fully compatible with the ISO/IEC 7816-3 standard (T=0, T=1) and a single-wire protocol (SWP) interface for communication with a near field communication (NFC) router in SIM/NFC applications. An SPI Master/Slave interface is also available for communication in non-SIM applications. The ST33GxxxA features hardware accelerators for advanced cryptographic functions. The EDES peripheral provides a secure DES (Data Encryption Standard) algorithm implementation, while the NESCRYPT cryptoprocessor efficiently supports the public key algorithm. The AES peripheral ensures secure and fast AES algorithm implementation. The device operates in the –40 to +105 °C temperature range and 1.8 V, 3 V and 5 V supply voltage ranges. A comprehensive range of power-saving modes enables the design of efficient low-power applications. The ST33GxxxA’s automotive grade is AEQ100 compliant and provides user Flash memory capability up to 500 kcycles with 15 years’ data retention. In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 2/6 DocID027118 Rev 2 9&& *1' 6:,2 DocID027118 Rev 2 ,$57ZLWK5$0EXIIHU 63,0DVWHU6ODYH ZLWK5$0EXIIHU 6EXV 1(6&5<37 5$0 1(6&5<37 0,)$5(DFFHOHUDWRU 038 $(6DFFHOHUDWRU 5$0 )ODVKPHPRU\ 6HFXU&RUH 6& &38&RUH ('(6DFFHOHUDWRU $3%$+% EULGJH 7UXH5DQGRP1XPEHU *HQHUDWRU 6HFXULW\DGPLQLVWUDWRU 6:3ZLWK5$0EXIIHU 7KUHHELWWLPHUV &ORFNJHQHUDWRU0RGXOH &5&PRGXOH ST33GxxxA Description Figure 1. Block diagram 67520 67520 ILUHZDOO ,'EXV &RGH'DWDVLJQDWXUH $3% *3,2V 069 3/6 6 Software development tool description 2 ST33GxxxA Software development tool description Dedicated SecurCore® SC300™ software development tools are provided by ARM and Keil®. This includes the Instruction Set Simulator (ISS) and C compiler. The documentation is available on the ARM and Keil websites. Moreover, STMicroelectronics provides: A time-accurate hardware emulator controlled by the Keil debugger and the STMicroelectronics development environment. A complete product simulator based on Keil’s ISS simulator for the SecurCore® SC300™ CPU. A secured ROMed Flash memory loader with very high-speed software downloading capabilities. 4/6 DocID027118 Rev 2 ST33GxxxA 3 Revision history Revision history Table 2. Document revision history Date Revision Changes 19-Nov-2014 1 Initial release. 10-Mar-2016 2 Added Figure 1: Block diagram. Small text changes. DocID027118 Rev 2 5/6 6 ST33GxxxA IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgment. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2016 STMicroelectronics – All rights reserved 6/6 DocID027118 Rev 2