PTN5150
CC logic for USB Type-C applications
Rev. 1 — 3 February 2016
Product data sheet
1. General description
PTN5150 is a small thin low power CC Logic chip supporting the USB Type-C connector
application with Configuration Channel (CC) control logic detection and indication
functions. The features of PTN5150 enable USB Type-C connector to be used in both
host and device ends of the Type-C cable. It can support Type-C to USB legacy cables
and adapters defined in USB Type-C Spec. PTN5150 can work autonomously, or can
connect to a controller through I2C-bus interface.
PTN5150 can be configured to dual role, host, or device mode through external
configuration pin or through I2C interface. The CC control logic detection and indication
block supports 3 current modes (default current 500 mA/900 mA, medium current 1.5 A
and high current 3.0 A) in DFP advertisement's perspective. When in UFP
advertisement's perspective, the control logic will detect if a DFP with different pull-up Rp
current source is connected. In addition, it will detect if Ra is present on CC1/CC2 pins.
Upon detection of plug orientation, pin ID will indicate if PTN5150 is working under either
host role or device role, and other status will also be reflected in I2C registers.
2. Features and benefits
Support type C connector with existing chipsets
USB Type-C Rev 1.1 compliance
Compatible with legacy OTG hardware and software
Support plug, orientation, role and charging current detection.
USB-ID pin for OTG application
I2C-bus interface support for fast mode
CC control logic detection and indication
PORT input pin to configure in DRP (Hi-Z), UFP (low) or DFP (high)
Current mode detection when PTN5150 is operating under UFP (device) role:
default current mode (<0.5 A/0.9 A); medium current mode (<1.5 A); high current
mode (<3.0 A)
Integrated accurate Rp current sources to support default mode and high current
mode under host mode: default current mode at 80 A; medium current mode at
180 A; high current mode at 330 A
Integrate Rd resistor in UFP mode
Report detail port states and accessory modes in I2C registers
Support VCONN1/2 power detected status through VCONN Status I2C register
0AH
Current consumption:
Hibernation mode: 4.5 A
Standby in DRP mode: 15 A
PTN5150
NXP Semiconductors
CC logic for USB Type-C applications
Standby in DFP mode: 15 A
Standby in UFP mode: 15 A
Power supply: VDD = 2.7 V to 5.5 V
VBUS_DET: 28 V Absolute Max Tolerance
High ESD protection for VBUS and CC1/2 pins
ESD protection exceeds 7000 V HBM per JDS-001-2012 and 500 V CDM per
JESD22-C101
Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
Operating Temperature Range: 40 C to +85 C
X2QFN12 package 1.6 mm 1.6 mm 0.35 mm, 0.4 mm pitch
3. Applications
Tablets/Mobile Devices
Ultrabook/Notebook Computers
Docking Stations
4. Ordering information
Table 1.
Ordering information
Type number
PTN5150HX
Topside
marking
Package
Name
Description
50
X2QFN12
Plastic, super thin quad flat package; no leads; 12 terminals; SOT1355-1
body 1.6 mm 1.6 mm 0.35 mm, 0.4 mm lead pitch.
Version
4.1 Ordering options
Table 2.
Ordering options
Type number
Orderable
part number
Package
Packing method
PTN5150HX
PTN5150HXMP
X2QFN12
REEL 13" Q2/T3
10000
*STANDARD MARK
SMD DP
Tamb = 40 C to +85 C
PTN5150HX
PTN5150HXZ
X2QFN12
REEL 7" Q2/T3
500
*STANDARD MARK
SMD SMALLPQ DP
Tamb = 40 C to +85 C
PTN5150
Product data sheet
Minimum
order quantity
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Rev. 1 — 3 February 2016
Temperature
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PTN5150
NXP Semiconductors
CC logic for USB Type-C applications
5. Functional diagram
VBUS_DET
Rp
ID
CC LEVEL
DETECTION
AND INDICATION
ADR/CON_DET
VDD
CC1
Rd
ENB
Rp
VDD
CC2
ROLE
(UFP/DFP/DRP)
CONTROL
PORT
Rd
DEVICE CONTROL AND MANAGEMENT
SDA/OUT1
SCL/OUT2
INTB/OUT3
aaa-019339
Fig 1.
Functional diagram
6. Pinning information
CC1 1
9 ID
11 ENB
terminal 1
index area
10 GND
12 VDD
6.1 Pinning
8 SCL/OUT2
PTN5150
INTB/OUT3 6
VBUS_DET 4
ADR/CON_DET 5
7 SDA/OUT1
PORT 3
CC2 2
aaa-019340
Transparent top view
Fig 2.
PTN5150
Product data sheet
Pin configuration
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PTN5150
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CC logic for USB Type-C applications
6.2 Pin description
Table 3.
Pin description
Symbol
Pin
Type
Description
1
CC1
I/O
Configure Channels as defined in USB Type-C specification
Input
Trinary GPIO Input selection run from VDD
2
CC2
3
PORT
PORT= VDD: DFP mode (Rp = 80uA power default for non-I2C mode).
PORT= Mid (or floating): DRP mode
PORT=GND: UFP mode
If ADR = High or Low (I2C mode), PORT input status will be only latched during
power up. To change the mode selection, system must write I2C register bit to
override mode selection.
If ADR = Mid (no- I2C mode). PORT input can be dynamically change.
4
VBUS_DET
Input
5
ADR/CON_DET I/O
VBUS Detection Pin. (28 V Max Tolerance)
Directly tie to VBUS of the USB Type-C receptacle
Trinary GPIO Input ADR pin run from VDD
•
ADR pull up to VDD with 10 k resistor (I2C Enabled with ADDR bit 6 equal to
1, I2C Address 0x7A)
•
ADR pull down to GND with 10 k resistor. (I2C Enabled with ADDR bit 6
equal to 0, I2C Address 0x3A)
•
ADR = Mid or floating (Pin 6/7/8) configured as OUT1/2/3 in non-I2C mode
Output. This pin will automatically switch from input to CON_DET output in
"non-I2C mode or set 09H bit[0] to 0" after TINPUTLATCH
•
•
6
INTB/OUT3
O/D
output
CON_DET = High (Connection Detected)
CON_DET = Low (No Connection)
Interrupt to notify I2C status register changed
INTB: (only valid in I2C mode)
•
•
Low = Interrupt asserted
Hi-Z = Interrupt de-asserted
OUT3: (only valid in non- I2C mode)
•
•
7
8
9
SDA/OUT1
SCL/OUT2
ID
PTN5150
Product data sheet
Low = Analog Audio Detected
Hi-Z = No Detection
O/D
I2C SDA (Open Drain Input & Output)
Input
/output
OUT 2 & OUT 1 : (Open Drain Output)
0
0
= high current mode
1
0
= medium current mode
1
1
= default current mode
O/D
I2C SCL (Open Drain Input)
Input
OUT 2 & OUT 1 : (Open Drain Output)
/output
0
0
= high current mode
1
0
= medium current mode
1
1
= default current mode
O/D
output
ID (Open Drain Output)
Low = DFP mode detected valid UFP on CC1 or CC2 line. This signal is used to
enable OTG mode, requires external pull up resistor.
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Rev. 1 — 3 February 2016
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PTN5150
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CC logic for USB Type-C applications
Table 3.
Pin description …continued
Symbol
Pin
Type
Description
10
GND
Power
Ground
11
ENB
Input
Chip Enable and Disable
•
•
12
VDD
Power
Low = Chip Enable
High = Chip Disable to Hiberation mode. Note that I2C register values are lost
when ENB is HIGH.
Power supply
7. Functional description
7.1 CC detection and indication block
For USB Type-C solution, two pins on the connector, CC1 and CC2, are used to establish
and manage the DFP/UFP connection between a host port and a device port.
A hardware GPIO trinary pin, PORT, is provided to configure PTN5150 in either
DFP/DRP/UFP mode alternatively, the PORT input can be override later by override the
I2C registers. If the GPIO Trinary ADR input is mid-level or floating (non I2C), PORT input
pin can dynamically change at any time to reconfigure the DFP/DRP/UFP. The GPIO
trinary input pins should be powered by VDD.
• When PTN5150 is operating under host role, different current modes
(high/medium/default) can be configured through I2C register. During initial power up,
default current mode is being selected. In order to indicate different current modes,
three Rp current sources are being implemented.
Table 4.
Current source implementation for each DFP advertisement
DFP advertisement
Current source to VDD
Current source precision
Default USB Power
80 A
20 %
1.5 A at 5 V
180 A
8 %
3.0 A at 5 V
330 A
8 %
Internal comparators are constantly monitoring the voltage levels of CC1 and CC2 pins.
PTN5150 reports if an UFP (device) or powered cable is connected externally on the CC
pins. When no external connection is detected, cable connected bit in the I2C register will
be cleared. Any changes in the attach/detach events or Rp current source changes will
trigger INTB pin to go LOW.
Table 5.
RD implementation for each UFP advertisement
UFP advertisement
RD value
RD accuracy
UFP mode
5.1 k
10 %
Table 6.
Voltage range detection for each DFP advertisement
DFP advertisement
PTN5150
Product data sheet
UFP (VRd) voltage
range
Powered cable/adapter No connect (Vopen)
VRa voltage range
voltage range
Default USB Power
0.25 V to 1.50 V
0.00 V to 0.15 V
>1.65 V
1.5 A at 5 V
0.45 V to 1.50 V
0.00 V to 0.35 V
>1.65 V
3.0 A at 5 V
0.85 V to 2.45 V
0.00 V to 0.75 V
>2.75 V
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Rev. 1 — 3 February 2016
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PTN5150
NXP Semiconductors
CC logic for USB Type-C applications
• When PTN5150 is operating under device role (UFP), it is able to detect different
current modes indicated by external host's pull-up resistors. Internally there is a
pull-down resistor (Rd) of 5.1 k on CC1 and CC2 pins. Status of current mode
detected is reported in the I2C register. If pin 6/7/8 is configured as OUT1/2/3,
OUT1/2 reports the detected Rp pull up current source value as well.
The configuration channel (CC1 or CC2) is used to serve the following purposes in this
block
• Detect connection of USB ports, e.g. a DFP (host) or a UFP (device), and establish
host or device roles between two connected ports. When there is no power supplied
to PTN5150, device role (with internal pull-down resistor Rd active) will be the default
configuration.
• Resolve cable orientation and twist connections to establish USB data bus routing.
• Discover optional accessory modes such as audio adapter accessory and debug
accessory modes. Resistors (Ra, Rd, Rp, or Open) connected on CC1/CC2 will be
reported in the I2C registers, and host controller can configure the external interface
accordingly.
7.2 ADR/CON_DET output pin
Pin 5 is multiple purpose I/O pin. When device power up, pin 5 is input which latched the
input voltage level to configure I2C address. The I2C register offset 09H has default value
"1" to disable CON_DET output. After TINPUT_LATCH, pin 5 becomes CON_DET output.
When USB Type-C cable attached or detached in either DFP or UFP mode, CON_DET
will asserted a signal to notify the system the status. The same attached or detached
status also stored in the I2C interrupt register.
For ADR strapping resistor selection, 10 k pull up or pull down resistor is recommended.
7.3 VCONN1/VCONN2 power output control
When a USB Type-C system need to support VCONN power in DFP or UFP power
accessories mode, the system need to know the orientation to provide VCONN power.
PTN5150 provides two bits of VCONN status register 0AH and an interrupt signal to notify
system whether VCONN power is detected on VCONN1 or VCONN2 and then turn on
discrete PowerFET using via 2 x GPIO. Figure 3 shows the system level implementation
of VCONN power with PTN5150.
PTN5150
Product data sheet
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Rev. 1 — 3 February 2016
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PTN5150
NXP Semiconductors
CC logic for USB Type-C applications
2.7 V to 5 V supply
power switch
GPIO1
GPIO2
power switch
PTN5150
I2C
AP
INTB
VCONN POWER
DETECTED
I2C REGISTER
CC1 or VCONN1
CC2 or VCONN2
aaa-019349
Fig 3.
Schematic connections to turn on/off VCONN1/2 power
7.4 Off state
When PTN5150 is not powered (i.e., VDD=0V), special steps should be done to prevent
back-current issues on control pins such PORT or ADR pins when these pins' states are
not low. These pins can be controlled through two different ways.
1. pull-up/pull-down resistors - make sure these pull-up resistors' VDD is the same
power source as to power PTN5150. When power to PTN5150 is off, power to these
pull-up resistors will be off as well.
2. external processor's GPIO - if PTN5150 is turned off when the external processor's
power stays on, processor should configure these GPIOs connected to these control
pins as output low (< 0.4 V) or tri-state mode (configure GPIOs as input mode). This
will make sure no current will be flowing into PTN5150 through these control pins.
7.5 I2C-bus
PTN5150 can work with systems with or without I2C-bus. “I2C mode” is defined as ADR
pin has external 10 k pull-up or pull-down resistor during power up, and “non-I2C mode”
is defined as ADR pin is not connected to any external pull-up or pull-down resistor during
power up. When operating in I2C mode, all features of PTN5150 can be configured and
accessed through registers. OUT1, OUT2, OUT3 are not available in I2C mode. PORT
input will be a one-time latched during power up.
In non-I2C mode, a subset of features can be configured or accessed through these I/O
pins:
•
•
•
•
PTN5150
Product data sheet
PORT input: In non I2C-bus mode, PORT input can be dynamically change.
CON_DET output: attached/detached notification
OUT1/OUT2 output: detected Rp current source value
OUT3: Analog Audio Detect
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Rev. 1 — 3 February 2016
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PTN5150
NXP Semiconductors
CC logic for USB Type-C applications
7.6 I2C-bus programmability
PTN5150 has I2C-bus interface that enables system integrator to program register
settings suitable for the application needs. Table 7 describes possible settings for different
functions of the device. Although some functions of the device can be configured through
external hardware pins (such as PORT), it also allows the system integrator to override
the settings by programming the internal registers through I2C.
After power-on, the device samples the hardware pin values (as I2C is not operational yet)
and reflects the status in the I2C status registers as default condition.
Table 7.
I2C registers and descriptions
Register offset Register name
Bits
Reset value
Description
01H
Version ID
[7:3]
00001
Device version ID
Read Only
Vendor ID
[2:0]
011
Vendor ID
02H
Control
[7:5]
000
Reserved
[4:3]
00
Rp Selection (DFP mode)
Read/Write
00: 80 A Default
01: 180 A Medium
10: 330 A High
11 Reserved
[2:1]
PORT pin state Mode Selection
00: Device (UFP Mode)
01: Host (DFP Mode)
10: Dual Role (DRP Mode)
During power up, device will latch the input of PORT
input pin to configure UFP/DFP/DRP. After power up,
writing to these register bits will overwrite the PORT
Mode selection.
[0]
0
Interrupt Mask for detached/attached
0: Does not Mask Interrupts
1: Mask Interrupts for register offset 03H bit[1:0].
03H
Interrupt
[7:2]
000000
Reserved
Read
Only/Clear on
Read
Status
[1]
0
Cable Detach Interrupt
0: No Interrupt
1: Cable Detached
[0]
0
Cable Attach Interrupt
0: No Interrupt
1: Cable Attached
PTN5150
Product data sheet
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PTN5150
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CC logic for USB Type-C applications
Table 7.
I2C registers and descriptions …continued
Register offset Register name
Bits
Reset value
Description
04H
[7]
0
VBUS Detection (UFP mode after valid CC detection)
CC Status
Read Only
0: VBUS not detected
1: VBUS detected
[6:5]
00
Rp Detection (In UFP mode)
00: Standby
01: Rp = Std USB
10: Rp = 1.5A
11: Rp = 3.0A
[4:2]
000
Port Attachment Status
000: Not Connected
001: DFP attached
010: UFP attached
011: Analog Audio Accessory attached
100: Debug Accessory attached
101: Reserved
110: Reserved
111: Reserved
[1:0]
00
CC Polarity
00: Cable Not Attached
01: CC1 is connected (normal orientation)
10: CC2 is connected (reversed orientation)
11: Reserved
05H
Reserved
[7:0]
00000000
Reserved
06H
Reserved
[7:0]
00000000
Reserved
07H
Reserved
[7:0]
00000000
Reserved
08H
Reserved
[7:0]
00000000
Reserved
09H
CON_DET
configuration
register
[7:1]
0000000
Reserved
[0]
1
Disable CON_DET output bit (Read/Write)
Read/Write
0: Enable CON_DET output on pin 5
1: Disable CON_DET output on pin 5
Recommend to disable CON_DET output for system
using I2C to access PTN5150
PTN5150
Product data sheet
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PTN5150
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CC logic for USB Type-C applications
Table 7.
I2C registers and descriptions …continued
Register offset Register name
Bits
Reset value
Description
0AH
[7:2]
000000
Reserved
[1:0]
00
VCONN Detected Status (Read Only)
Read Only
VCONN Status
register
00: Standby
01: VCONN power should be applied on CC1
10: VCONN power should be applied on CC2
11: Reserved
Ra detect happens in all modes. VCONN enable
happens autonomously when as DFP (including in DRP
mode).
Prior to accessing this register, system must write
register offset 43H with value of 0xe0 to enable VCONN
detected status. If register offset 43H is not set to 0xe0,
VCONN detected status read out is always 00.
10H
Reset register
[7:1]
0000000
Reserved.
[0]
0
1: Reset system digital block
11H
Reserved
[7:0]
00001100
Reserved. Do not write any other values other than
“00001100” (power up setting) to this register
12H
Reserved
[7:0]
000000
Reserved.
13H
Reserved
[7:0]
10100001
Reserved. Do not write to this register
14H
Reserved
[7:0]
00011111
Reserved. Do not write to this register
15H
Reserved
[7:0]
11001001
Reserved. Do not write to this register
16H
Reserved
[7:0]
01010001
Reserved. Do not write to this register
17H
Reserved
[7:0]
01010000
Reserved. Do not write to this register
18H
Interrupt
[7]
0
Reserved
Read/Write
Mask register
[6]
0
Reserved
[5]
0
Reserved
[4]
1
Interrupt Mask for CC1 or CC2 Comparator Change
0: Does not Mask Interrupts
1: Mask Interrupts
[3]
1
Interrupt Mask for role Change
0: Does not Mask Interrupts
1: Mask Interrupts
[2]
1
Interrupt Mask for orientation Found
0: Does not Mask Interrupts
1: Mask Interrupts
[1]
1
Interrupt Mask for debug Accessories Found
0: Does not Mask Interrupts
1: Mask Interrupts
[0]
1
Interrupt Mask for audio Accessories Found
0: Does not Mask Interrupts
1: Mask Interrupts
PTN5150
Product data sheet
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PTN5150
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CC logic for USB Type-C applications
Table 7.
I2C registers and descriptions …continued
Register offset Register name
Bits
Reset value
Description
19H
[7]
0
Reserved
[6]
0
Reserved
Read
Only/Clear on
Read
Interrupt Register
status
[5]
0
Reserved
[4]
0
Interrupt Status for Comparator Change
0: No interrupt
1: When attached as UFP, Change of Rp current
advertisement detected. New advertisement is
reflected on register offset 04H bit[6:5].
[3]
0
Interrupt status for role change
0: No interrupt
1: Role changed detected. New role is reflected on
register offset 04H bit[4:2].
[2]
0
Interrupt status for orientation found
0: No interrupt
1: Orientation detected on attachment. New orientation
is reflected on register offset 04H bit[1:0].
[1]
0
Interrupt status for debug accessories found
0: No interrupt
1: Debug Accessory attachment detected. Register
offset 04H bit[4:2] should be updated to 3’b100.
[0]
0
Interrupt status for audio accessories found
0: No interrupt
1: Audio Accessory attachment detected. Register
offset 04H bit[4:2] should be updated to 3’b011.
7.7 I2C-bus read and write operations
PTN5150 supports programming of the internal registers through the I2C-bus interface.
I2C-bus can support up to 400 kHz data rate. 8-bit device slave address of PTN5150 is
defined in combination with ADR pin.
Table 8.
Read/write device slave address
Name
Size
(Bits)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Slave address
8
0
ADR
1
1
1
0
1
R/W
Reading/writing the internal registers must be done according to the following protocol.
The read protocol contains two phases:
• Command phase
• Data phase
The command phase is an I2C write to PTN5150 that contains a single data byte
indicating the internal register address to read out. The data phase is an I2C read
operation that contains one byte of data and STOP bit is asserted, starting from the least
significant byte.
PTN5150
Product data sheet
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PTN5150
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CC logic for USB Type-C applications
The I2C write operation contains only the command phase, which contains 8-bit internal
register address, followed by one byte of data to be written to the register, starting from
the least significant byte.
It is recommended to use single-byte write/read commands to PTN5150. Incremental
address read/write function is not supported. Figure 4 and Figure 5 illustrate the protocol
used on the I2C-bus to write and read register inside the device.
SCL
1
2
3
4
5
6
7
8
9
slave address
0 AD 1
DR
SDA S
1
1
0
1
START condition
0
R/W
A
0 1/0 0
STOP
condition
data to register
command byte
0 1/0 1/0 1/0 1/0 A
DATA 0
MSB
acknowledge
from slave
acknowledge
from slave
A
P
LSB
acknowledge
from slave
aaa-019852
Fig 4.
I2C-bus write sequences
command byte
slave address
SDA S
0 AD 1
DR
1
1
0
1
START condition
0
A
0 1/0 0
R/W
(cont.)
0 1/0 1/0 1/0 1/0 A
acknowledge
from slave
acknowledge
from slave
data from register
slave address
(cont.) S
0 AD 1
DR
1
(repeated)
START condition
1
MSB
0
1
1
A
R/W
acknowledge
from slave
LSB
DATA (first byte)
NA P
no acknowledge
from master
STOP
condition
at this moment master-transmitter becomes master-receiver
and slave-receiver becomes slave-transmitter
aaa-019853
Fig 5.
I2C-bus read sequences
PTN5150
Product data sheet
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PTN5150
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CC logic for USB Type-C applications
8. Limiting values
Table 9.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
VDD[1]
Conditions
Supply voltage
0.5
+6.0
V
VBUS_DET
VBUS Detect
0.5
+28.0
V
Control pins
PORT, ADR/CON_DET,
INTB/OUT3, CC1, CC2,
ENB, ID
0.5
VDD +0.3 V
SCL/OUT2, SDA/OUT1
0.5
VDD +0.3 V
Vesd
Max
Unit
-65
150
C
Electrostatic discharge
CC1/CC2/VBUS_DET
HBM[2]
-
7000
V
All other pins
HBM[2]
-
2000
V
All pins
CDM[3]
-
500
V
Storage temperature
Tstg
Min
[1]
All voltage values, except differential voltages, are with respect to network ground terminal.
[2]
Human Body Model: ANSI/EOS/ESD-S5.1-1994, standard for ESD sensitivity testing, Human Body Model Component level; Electrostatic Discharge Association, Rome, NY, USA.
[3]
Charged Device Model: ANSI/EOS/ESD-S5.3-1-1999, standard for ESD sensitivity testing, Charged Device
Model - Component level; Electrostatic Discharge Association, Rome, NY, USA.
9. Recommended operating conditions
Table 10.
Operating conditions
Symbol
Parameter
Conditions
Min
VDD
supply voltage
40 to +85 C
+2.7
Typ
Max
Unit
+5.5
V
TVDDramp
VDD ramp up time
Time to reach 90% of
VDD
-
10
ms
VBUS_DET
VBUS Detect
VBUS Analog Input
4.0
Vi
input voltage
CMOS inputs
0.5
5.0
21
V
-
VDD+0.3 V
0.5
-
1.98
V
40
-
85
C
-
(PORT, ADR)
I2C inputs
(SCL, SDA, ENB)
Tamb
ambient temperature
operating in free air
10. Characteristics
Table 11.
Symbol
General characteristics
Parameter
Conditions
Min
Typ
Max
Unit
Device role (UFP) Sink CC Detection
Rd
Pull down resistor
UFP mode
4.59
5.10
5.61
k
VCLAMPH
High current mode clamp
voltage
VDD=0 V
0.85
-
2.18
V
VCLAMPM
Medium current mode clamp
voltage
VDD=0 V
0.45
-
1.25
V
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Table 11.
General characteristics …continued
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VCLAMPD
Default current mode clamp
voltage
VDD=0 V
0.25
-
1.25
V
VTHH
High current mode threshold
UFP mode
1.16
1.23
1.31
V
VTHM
Medium current mode
threshold
UFP mode
0.61
0.66
0.70
V
VTHD
Default current mode threshold UFP mode
0.15
0.2
0.25
V
Host role (DFP advertisement) Current source
IPH
Current source
High current source mode (3 A)
304
330
356
A
IPM
Current source
Medium current source mode (1.5 A)
166
180
194
A
IPD
Current source
Default current source mode
64
80
96
A
No external R
2.5
3.0
3.5
V
VDD = 3.3 V; ENB = high
2
4.5
10
A
VDD = 3.3 V
65
100
130
A
5
15
35
A
5
15
35
A
5
15
35
A
5
15
35
A
VBUS Detect Threshold
VVBUSDET
VBUSDET threshold
Current Consumption
IDD_hibernation hibernation mode current
IDD_active
active supply current; cable
attached
PORT = high (DFP)
VDD = 3.3 V
PORT = low (UFP)
IDD_standby
standby/polling current; no
cable attached
VDD = 3.3 V
PORT = floating (DRP)
VDD = 3.3 V
PORT = high (DFP)
VDD = 3.3 V
PORT = low (UFP)
TCCdebounce
debounce time
time a port shall wait before it can
determine it is attached
-
120
-
ms
Tdisconnection
disconnection time
time a port shall respond when it is
disconnected
-
1.2
-
ms
TStartup
start-up time
supply voltage valid to Rp/Rd active
-
25
-
ms
When selected DFP mode, system
overwrite to UFP mode using I2C or
PORT input, the Trcfg delay is measured
from disabled Rp to enable Rd.
2
-
ms
When selected UFP mode, system
overwrite to DFP mode using I2C or
PORT input, the Trcfg delay is measured
from to disable Rd and enable Rp.
35
-
ms
Trcfg
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Table 12.
PORT control input characteristics
Symbol
Parameter
Conditions
Rpu
external pull up resistor
Rpd
external pull down resistor
VIL
Input Low Voltage
VIM
VIH
Table 13.
Min
Typ
Max
Unit
External pull-up resistor is connected to VDD
10
-
k
External pull-down
resistor is connected to
GND
10
-
k
-
-
0.4
V
Input Mid level Voltage
40%*VDD
50%*VDD
60%*VDD
V
Input High Voltage
80%*VDD
-
-
V
Min
Typ
Max
Unit
ADR/CON_DET input/output characteristics
Symbol
Parameter
Conditions
Rpu
external pull up resistor
External pull-up resistor is connected to VDD
10
-
k
Rpd
external pull down resistor
External pull-down
resistor is connected to
GND
10
-
k
VIL
Input Low Voltage
-
-
0.4
V
VIM
Input Mid level Voltage
40%*VDD
50%*VDD
60%*VDD
V
VIH
Input High Voltage
80%*VDD
-
-
V
VOH
Output High Voltage
IOH = 3 mA
80%*VDD
-
-
V
VOL
Output Low Voltage
IOL = 3 mA
-
-
20%*VDD
V
Typ
Max
Unit
[1]
CON_DET output can be enabled or disabled by accessing I2C register offset 09H bit[0]
Table 14.
ENB, SCL and SDA input characteristics
Symbol
Parameter
Conditions
Min
VIL(MAX)
maximum input voltage low level
-
+0.4
V
VIH(MIN)
minimum input voltage high level
1.05
-
-
V
0.09
-
-
V
I2C Fast mode interface pins (SCL, SDA)
VHYS
Table 15.
Hysteresis of Schmitt trigger inputs
Open-drain output buffer characteristics (OUT2, OUT1, INTB/OUT3, ID pins)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VOL
low-level output voltage
IOL= 3 mA
0
-
0.4
V
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11. Package outline
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PTN5150
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CC logic for USB Type-C applications
12. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
12.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
12.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•
•
•
•
•
•
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering
12.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
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12.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 7) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 16 and 17
Table 16.
SnPb eutectic process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
350
< 2.5
235
220
2.5
220
220
Table 17.
Lead-free process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 7.
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temperature
maximum peak temperature
= MSL limit, damage level
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 7.
Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
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13. Soldering: PCB footprints
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PCB footprint for SOT1355-1 (X2QFN12); reflow soldering
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14. Revision history
Table 18.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
PTN5150 v.1
20160203
Product data sheet
-
-
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15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
15.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
PTN5150
Product data sheet
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 3 February 2016
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Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
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17. Contents
1
2
3
4
4.1
5
6
6.1
6.2
7
7.1
7.2
7.3
7.4
7.5
7.6
7.7
8
9
10
11
12
12.1
12.2
12.3
12.4
13
14
15
15.1
15.2
15.3
15.4
16
17
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional description . . . . . . . . . . . . . . . . . . . 5
CC detection and indication block . . . . . . . . . . 5
ADR/CON_DET output pin . . . . . . . . . . . . . . . . 6
VCONN1/VCONN2 power output control . . . . . 6
Off state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
I2C-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
I2C-bus programmability . . . . . . . . . . . . . . . . . . 8
I2C-bus read and write operations . . . . . . . . . 11
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 13
Recommended operating conditions. . . . . . . 13
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 13
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16
Soldering of SMD packages . . . . . . . . . . . . . . 17
Introduction to soldering . . . . . . . . . . . . . . . . . 17
Wave and reflow soldering . . . . . . . . . . . . . . . 17
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 17
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 18
Soldering: PCB footprints. . . . . . . . . . . . . . . . 20
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 21
Legal information. . . . . . . . . . . . . . . . . . . . . . . 22
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 22
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Contact information. . . . . . . . . . . . . . . . . . . . . 23
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2016.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 3 February 2016
Document identifier: PTN5150