AND9029/D Hybrid Jig User Manual www.onsemi.com APPLICATION NOTE Introduction ON Semiconductor’s hybrid jig was designed to enable customers to evaluate new products, perform incoming QC and failure analysis on preconfigured products in a simple and convenient way, without having to wire the units. This document is intended to be a quick start guide for using the hybrid jig. The board is designed with two components: a universal hybrid board and an adapter module. The universal hybrid board is intended to provide a consistent layout for all hybrids regardless of pin−out to simplify evaluation when using multiple products. The adapter module acts as an interface with the specific hybrid and routes the various pins to the appropriate location on the universal hybrid board. NOTE: Not all hybrids will utilize all of the functionality of the universal hybrid board. For example, the RHYTHMt product (SB3229/R3910) does not bring out the VDD2X line so this pin on the universal hybrid board would not be used. Reference Documents Please refer to specific product’s user’s guide (if available). The following document can also be used as reference: • Using DSP Hybrids in High Power Applications Initial Design Tips information note (AND9028) Illustrations and Schematics An illustration of the hybrid jig for Rhythm R3110 is shown in Figure 1. NOTE: All location descriptions throughout this document are described from this orientation. Figure 1. Hybrid Jig © Semiconductor Components Industries, LLC, 2016 May, 2016 − Rev. 5 1 Publication Order Number: AND9029/D 3 2 1 1 2 3 4 5 6 7 8 9 10 11 1213 1415 www.onsemi.com 2 Figure 2. Universal Hybrid Jig Schematic F PGND C12 47u DNP A A optional dig VC − DNP B SW6 DOWN DCU 193 B F F VC A/D C17 DNP C16 DNP V_IO VB VBP IC_GND PGND J13 MISC POWER 1 2 3 4 5 6 7 8 9 10 switchable high−power circuit IC_GND IC_GND R21 0 1 2 3 R20 0 U3 3 2 1 VC A/D SW7 UP VB R11 DNP SW8 RESET Optional reset button − DNP C5 1nF R8 5K62 R6 1K5 6K81 R4 1K5 R3 Consider Keystone 635/636 9V holders. R10 681R C6 1nF 5K62 C3 1nF 1nF C2 −9V 8 4 TR16 22R TP10 VDD2X AUX OUT J16 3 2 1 R19 J24 J14 TP9 RST# TP11 EXTRA IO_VDD R7 6K81 +9V 7 Trimmer polarity corrected. TP4 IC_GND TP6 VPP TP8 IO_VDO 681R R5 HDPH_OUT U2 comp C1 DNP C10 22K 0R C9 R1 100K R2 NESS34 6 VBP F POT R16 R9 C4 1nF C13 220nF J12 5 VB F POT/SM R15 AUX OUT 220uH 220uH Y1 DNP Optional crystal circuit − DNP J1 GND TP18 BNC 1 optional local gnd−pgnd link F POT/SM R14 64 2 F POT/SM R13 24 23 22 21 20 19 18 17 16 15 14 13 F POT/SM R12 1 2 3 4 5 6 7 8 9 10 11 12 TP3 VBP TP5 PGND TP7 VREG 1 2 R22 DNP PGND TP2 VB J15 L2 L1 3 IC_GND SW DIP−5/SM 1 2 PGND J20 REC F 3 2 1 C19 DNP J19 REC M GPU0 GPU1 GPU2 GPU3 GPU4 GPU5 GPU6 GPU7 XTAL_SEL XTAL XTAL_I XTAL_O 4 6 7 5 3 IC_GND C18 DNP 5 4 3 2 1 VBP Hybrid Adapter Module OUT− OUT+ EXTRA VDD2X RST# IO_VDD D_VREG VPP PGND GND VBP VB TRIM TP MGND IN1 IN2 IN3 IN4 VREG TRIM1 TRIM2 TRIM3 TRIM4 VC DIG_VG 36 3534 33 32 3130 29 282726 25 VB SW9 C15 DNP J3 −9V C8 C7 +9V TP17 −9V 10uF 10uF TP14 +9V Instrumentation output amplifier needs external −9/0/9V supply TP1 XTAL VB 3 2 1 optional decoupling TP13 VREG U1 MICS IN TP12 MGND C14 DNP GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 SCK SDA MS2 MS1 J23 Star VREG, plane MGND under inputs SW1 MS1 PB SW3 MS1 SLIDE VB 37 38 39 40 41 42 43 44 45 46 47 48 J17 R18 DNP VB SDA LINK JS1 add CS44 drill hole SDA I2C J18 GPIO/MISC IO 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 AUX OUT J21 R17 0 SW2 MS2 PB 2 1 IO_VDD 1 2 3 4 J22 6 4 g VB CS44 DNP 5 3 1 5 3 p VB EXT MS DNP J11 4 3 2 1 SW4 MS2 SLIDE J10 CON3 J2 JMP3 AND9029/D The schematic for Wolverine universal hybrid board is shown in Figure 2. 1 2 3 2 1 2 AND9029/D OUT+ 6 OUT− MS1 MS2 SDA SCK GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 MS2 GPU0 GPU1 GPU2 GPU3 GPU4 Hybrid Adapter Module GPU5 GPU6 GPU7 XTAL_SEL XTAL XTAL_I XTAL_O VB VBP GND PGND VPP DVREG 13 14 15 16 17 18 19 20 21 22 23 24 36 35 34 33 32 31 30 29 28 27 26 25 OUT+ OUT− MS1 10 MS1 9 22 TR1 MGND IN1 IN2 IN3 IN4 VREG TRIM1 TRIM2 TRIM3 TRIM4 VC DIG_VC MS2 21 TR1 TR2 20 CLK 11 12 SCK SDA TR3 D_VIC GPIO6 MS1 MS2 SDA SCK 5 1 2 3 4 5 6 7 8 9 10 11 12 VB VBP GND PGND VPP D_VREG IO_VDD RST# VDD2X Extra OUT+ OUT− VPP VB DVREG 25 24 8 7 VBP PGND 4 1 3 GND MGND IN1 IN2 IN3 IN4 VREG TR1 TR2 TR3 TR4 VC DIG_VC VC TR2 13 OUT− TR3 DIG_VC DAI TR4 14 SA3229 / SB3229 / SB3231 19 15 VC OUT+ TIN SDA IN4 MGND 16 GPIO6 IN3 VIN1 VIN2 23 17 TR4 IN2 GPIO6 18 VREG IN1 2 U1 U2 48 47 46 45 44 43 42 41 40 39 38 37 VPP VB DVREG VBP GND PGND MGND VREG The adapter module and hybrid schematics for the different preconfigured products are shown in Figures 3−7 / Note the figure captions indicate the part number for the hybrid jig. OUT− GPIO1 / MS2 MS1 MS2 SDA SCK GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 MGND VIN1 VIN2 TIN DAI VREG TRIM1 TRIM2 TRIM3 TRIM4 VC DIG_VC GPU0 GPU1 GPU2 GPU3 GPU4 Hybrid adapter module GPU5 GPU6 GPU7 XTAL_SEL XTAL XTAL_I XTAL_O All 8 GPIOs will connect to GPIO bus − even shared ones. Note: GPIO 2 and 3 correspond to ARD1 and ARD2 for R3920 Figure 4. Rhythm R3910 / Rhythm R3920 Adapter Module − SA3400GEVB hybrid jig www.onsemi.com 3 OUT+ OUT− VB VBP GND PGND VPP DVREG MS2 GPIO1 13 14 15 16 17 18 19 20 21 22 23 24 9 GPIO5 GPIO6 GPIO0 / MS1 10 MS1 GPIO0 GPIO2 19 GPIO6 23 CLK 11 SCK SDA 12 SDA VC DIG_VC 1 2 3 4 5 6 7 8 9 10 11 12 VB VBP GND PGND VPP D_VREG IO_VDD RST# VDD2X Extra OUT+ OUT− VPP 6 MGND VIN1 VIN2 TIN DAI VREG 48 47 46 45 44 43 42 41 40 39 38 37 MS1 MS2 SDA SCK GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 VPP DVREG DVREG VB 8 24 VB VBP VBP 7 4 25 OUT+ OUT− VC DIG_VC 13 GPIO7 / DIG_VC GPIO7 PGND GND 3 GND DAI GPIO5 22 14 OUT+ 5 R3910 / R3920 GPIO4 15 VC TIN GPIO3 DAI U1 VIN2 GPIO4 21 16 PGND 17 TIN GPIO3 20 VIN2 VIN1 GPIO2 18 VREG VIN1 MGND 1 2 VREG MGND Figure 3. Rhythm SA3229 / Rhythm SB3229 / Rhythm SB3231 Adapter Module− SA3404GEVB / SA3405GEVB Hybrid Jig 36 35 34 33 32 31 30 29 28 27 26 25 AND9029/D D_VREG NRST NSDA SCK GPIO2 NSCL SDA GPIO3 BSEL MS2 GPIO4 RST# MS1 GPIO5 Hybrid Adaptor MS1 MS2 SDA SCK GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO2 48 47 46 45 44 43 42 41 40 39 38 37 u1 GPIO3 GPIO5 1 2 3 4 5 6 7 8 VREG FEMALE−3PIN ANT SA3291 GPIO4 GPIO5 GPIO4 VIN2 MGND GND DAI VB MS1 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 VIN2 VIN1 DAI VIN2 TIN VB DAI 9 10 11 12 13 14 15 16 O O O 3 2 1 VIN1 TIN VREG VC DIGVC L2 NGND L1 NVB PGND VBP OUT+ OUT− PCCLK PCSDA MS2 TIN DVREG RST_N NSCL NSDA BSEL NRST GPIO3 GPIO2 32 31 30 29 28 27 26 25 VIN1 MS1 MGND VIN1 VIN2 TIN Hybrid Adapter DAI VREG TRIM1 TRIM2 TRIM3 TRIM4 VC DIG_VC VC R1 10R VC DIG_VC BSEL NRST NSCL NSDA 13 14 15 16 17 18 19 20 21 22 23 24 SCK DIG_VC 36 35 34 33 32 31 30 29 28 27 26 25 VB VBP GND PGND VPP D_VREG IO_VDD RST# VDD2X GRAVY OUT+ OUT− VREG MS2 SDA GPU0 GPU1 GPU2 Module GPU3 GPU4 GPU5 GPU6 GPU7 XTAL_SEL XTAL XTAL_I XTAL_O VB OUT− VBP OUT+ GND VBP PGND VPP VPP GND D_VREG PGND RST# VDD2X OUT+ OUT− AGCO 14 AGC0 LC 18 LC HC 19 HC VREG 15 VREG MIC1 1 MIC1 MIC2 17 MIC2 TC−IN 16 TC−IN MGND 2 MGND MS TC−EN SDA SCK TC−EN 10 TC−EN MS 9 MS MGND MIC1 MIC2 TC−IN R3110 SCL 20 SCK SDA 11 SDA OUT+ 5 OUT+ 6 OUT− GPU0 GPU1 GPU2 GPU3 GPU4 GPU5 Hybrid Adapter Module GPU6 GPU7 XTAL_SEL XTAL XTAL_I XTAL_O VB VBP GND PGND 4 13 14 15 16 17 18 19 20 21 22 23 24 PGND MGND VIN1 VIN2 TIN DAI VREG TRIM1 TRIM2 TRIM3 TRIM4 VC DIG_VC PGND GND 3 GND OUT− VREG LC HC WG/NL AGCO VC 1 2 3 4 5 6 7 8 9 10 11 12 MS1 MS2 SDA SCK GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 U2 Figure 6. R3110 Adapter Module − R3110GEVB Hybrid Jig www.onsemi.com 4 OUT+ OUT− WG/NL TN−EN 13 TN−EN 48 47 46 45 44 43 42 41 40 39 38 37 WG/NL TN−EN 21 VB VBP GND PGND VPP D_VREG IO_VDD RST# VDD2X Extra OUT+ OUT− VC VBP 12 VB 8 U1 VC 7 VB VBP Figure 5. AYREt SA3291 Adapter Module − SA3410GEVB Hybrid Jig 36 35 34 33 32 31 30 29 28 27 26 25 8 GND VREG VC DIG_VC 48 47 46 45 44 43 42 41 40 39 38 37 MS1 MS2 SDA SCK GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 9 MGND IN1 IN2 IN3 IN4 VREG TRIM1 TRIM2 TRIM3 TRIM4 VC DIG_VC GPU0 GPU1 GPU2 GPU3 GPU4 Hybrid adapter module GPU5 GPU6 GPU7 XTAL_SEL XTAL XTAL_I XTAL_O 36 35 34 33 32 31 30 29 28 27 26 25 OUT+ OUT− GND VB 13 14 15 16 17 18 19 20 21 22 23 24 VB VBP GND PGND VPP D_VREG IO_VDD RST# VDD2X GRAVY OUT+ OUT− GND VB 7 1 2 3 4 5 6 7 8 9 10 11 12 VB CLK CLK 10 SDA SDA 11 MS1 MS1 12 14 GND2 VC MGND MGND VIN1 VIN2 OUT− OUT + 6 OUT− 5 OUT+ 4 DIG−VC MS2 DVC 3 MS2 2 VIN2 GND1 R3710 NC MGND 15 U1 VREG VC 13 VREG 16 VIN2 VIN1 1 VIN1 MS1 MS2 SDA CLK AND9029/D Figure 7. Rhythm R3710 Adapter Module − R3710GEVB hybrid jig Inserting and Extracting the Hybrid can be identified by referencing the adapter module schematic. For example, the Rhythm adapter module in Figure 3 shows that IN1 through IN4 are, respectively: MIC1, MIC2, TIN, DAI. To insert the hybrid, raise the red handled plunger in the centre of the board to gain access to the hybrid socket alignment plate. Hybrids should be inserted face down, with pin 1 in the bottom left. NOTE: Pin 1 is denoted by a dot on the underside of the hybrid in accordance with its respective datasheet. Once inserted, the hybrid I/O pads touchdown on the adapter module through a pressure sensitive conductive membrane. Finally, close the plunger which will apply pressure against the hybrid with the membrane. The plunger should only apply a small amount of pressure to the hybrid and fine adjustments can be made by adjusting the two washers on the plunger head. The amount of pressure should be similar to firmly yet gently pressing on the hybrid with a finger. To extract the hybrid, gently pull on one of the hybrid corner with ones fingers, use an electronics vacuum pen, or insert tweezers in the extraction holes of the alignment plate. Care should be taken not to puncture the membrane with tweezers. Outputs There are three possible output settings on the universal hybrid jig: receiver, headphones, and OpAmp. Using the headphones requires J15 and J16 to be jumpered on pins 2−3 as illustrated in and 1⁄8 inch headphones to be inserted in J12. To use the OpAmp, change the jumpers on J15 and J16 to short pins 1−2 and apply ±9 V on the test loops in the upper right corner of the board. To use the receiver, it is recommended to remove the jumpers from J15 and J16, to remove the LC low−pass filter effects, and to insert the receiver into either the male or female 2−pin header on J19 or J20. A summary of the configuration options is provided in Table 1. Table 1. JUMPER CONFIGURATIONS for Output Circuit on J15 and J16 Inputs The universal hybrid jig supports up to four inputs, labelled IN1−IN4, on the upper left corner of the board. The input orientation (MGND, signal, VReg) is listed on a legend in the silkscreen in the same general area. The inputs Configuration Jumper Pins Jumper Positioning OpAmp 1−2 Top of board/AMP Headphones 2−3 Bottom of board/HDPH Receiver Open N/A www.onsemi.com 5 AND9029/D Power Options Table 3. JUMPER CONFIGURATIONS for Volume Control Circuit on J14 Power is supplied from the programming box on the 6−pin mini−DIN connector, directly on J22, or through the optional CS44 socket. When powering from the 6−pin mini−DIN connector, J22 must be shorted. When powering directly from J22, remove the jumper and connect 1.3 V to pin 1. When using the optional CS44 connector, it is necessary to wire a 4−pin header or CS44 connector to OTP_CS44. The pin orientation is listed on the underside of the universal hybrid board. The universal hybrid board is setup with the high power application circuit, described in the Using DSP Hybrids in High Power Applications Initial Design Tips information note (AND9028). It can be enabled and disabled according to Table 2. NOTE: One of these jumper configurations must be selected to tie VB and VBP together; otherwise, they will have to be powered separately. Jumper Pins 1−2 Top of board/HIPWR ON High power circuit enabled 2−3 Bottom of board/HIPWR OFF Digital volume control 1−2 Bottom of board/VC DIG Analog volume control 2−3 Bottom of board/VC AN The universal hybrid jig supports both momentary and static switches on MS1 and MS2. Setting J21 will define whether the two memory selects are configured as pull−up or pull−down according to Table 4. NOTE: When using the momentary switches, leave the static switches in the off position. As well, J10 can be populated with a header to allow alternate memory selects to be incorporated and C14/C15 can be populated to reduce switch noise and de−bounce. Table 4. JUMPER CONFIGURATIONS for Memory Select Pull Options on J21 Jumper Positioning High power circuit disabled Jumper Pins Memory Select Table 2. JUMPER CONFIGURATIONS for High Power Circuit on J24 Configuration Jumper Positioning Configuration Jumper Positioning Configuration Jumper Pins Pull down 1−2 Top of board/ PULL + Pull up 2−3 Bottom of board/ PULL − Volume Control and Trimmers General Configuration Programming The volume control and four trimmers can be setup in 2−terminal or 3−terminal configurations through SW9. As listed on the silkscreen, turning a switch off or on will enable 2−terminal or 3−terminal mode, respectively, for its corresponding trimmer or volume control. NOTE: For Wolverine based products, the switch must be set to 3−terminal mode. Each trimmer and volume control has a correspondingly identified wiper and test point. Programming through SDA or I2C can be done on the 6−pin mini−DIN connector or through the optional CS44 connector. The CS44 connector needs to be populated on OPT_CS44. Reset A reset button allows for quick reset of the hybrid by pressing SW8 on the bottom right corner of the board. The hybrid will resume processing when the button is released. Test Points Volume Control The universal hybrid board contains various test points. Most notably, J13 interfaces with the power lines as noted on the silkscreen traces. For example, the leftmost pin is a test point for VB. There are also drill holes to insert optional test loops. There are also test points for trimmers and the volume control on J23 (left side of the board), and test loops for MGND, VREG, and XCLK. The volume control can be used in their analog or digital mode. This is controlled by the selection of J14 according to Table 3. The analog volume control is operated through the VC wiper, whereas the digital volume control is operated through SW7/UP and SW6/DN. NOTE: U3 can be populated with a user specific digital volume control and C16/C17 can be populated with capacitors to reduce switch noise and de−bounce. www.onsemi.com 6 AND9029/D Custom/GPIO Hybrid Jig Part Numbers Header J18 (upper right corner) allows for connections to hybrids supporting GPIOs and other custom pins that may be identified and brought out at a later date. The header is sectioned off on the silkscreen to separate the GPIO and custom pins. Each individual pin is then identified along with a ground pin, denoted as ‘G’, for each of the sections. Hybrid jig part numbers are listed in Table 5 below. Table 5. HYBRID JIG PART NUMBERS Hybrid Hybrid Jig Part Number Rhythm R3920 / Rhythm R3910 SA3400GEVB Rhythm R3710 R3710GEVB Rhythm SB3231 / Rhythm SB3229 SA3405GEVB Rhythm SA3229 SA3404GEVB External Crystal Circuit Some hybrids may support an external oscillator option and so the universal hybrid jig supports this functionality. This is contained in the XTAL_SEL section of the board. For such hybrids, the crystal and capacitors can be populated on Y1 and C9−10, respectively. Rhythm R3110 R3110GEVB Ayre SA3291 SA3410GEVB RHYTHM is a trademark of Semiconductor Components Industries, LLC. ON Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol. ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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