Ordering number : EN7332A LC75344MD CMOS LSI http://onsemi.com Two-Channel Electronic Volume Control System Overview The LC75344MD is a two-channel electronic volume control IC that is controlled by data input over a serial interface. Functions Volume control: 0 dB to –50 dB in 1 dB steps, –52 dB to –78 dB in 2 dB steps, and –, for a total of 66 positions. A balance function can be implemented by controlling the left and right channels independently. Features Built-in buffer amplifiers minimize the number of external components required. Fabricated in a silicon gate CMOS process to minimize the switching noise generated by internal switches. Built-in reference voltage generation circuit for the analog ground level. All settings are controlled by data input over a serial interface that conforms to the CCB specifications. Specifications Absolute Maximum Ratings at Ta = 25C, VSS = 0V Parameter Symbol Maximum supply voltage VDD max Input voltage VIN max Conditions Ratings VDD unit 11 CE, CL, DI V –0.3 to +11.0 LIN, RIN VSS –0.3 to VDD +0.3 VOUT1 OSC VOUT2 S1 to S87, COM1 to COM4, P1 to P8 Allowable power dissipation Pd max Ta ≤ 75°C *1: When mounted on a PCB. Operating temperature Topr –30 to +75 C Storage temperature Tstg –40 to +125 C Output voltage –0.3 to VDD +0.3 V –0.3 to VLCD +0.3 300 V mW Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. SOIC-10 NB CCB is ON Semiconductor® ’s original format. All addresses are managed by ON Semiconductor® for this format. CCB is a registered trademark of Semiconductor Components Industries, LLC. ORDERING INFORMATION See detailed ordering and shipping information on page 13 of this data sheet. Semiconductor Components Industries, LLC, 2014 May, 2014 51914HK 20120417-S00003/21004TN(OT) No.7332-1/13 LC75344MD Allowable Operating Ranges at Ta = 30 to +75C, VSS = 0V Parameter Symbol Pin Name Supply voltage VDD VDD High-level input voltage VIH CL, DI, CE Conditions Ratings min typ Unit max 4.5 10 V 2.0 10 V CL, DI, CE 7.5 ≤ VDD ≤ 10 VSS 0.8 V CL, DI, CE 4.5 ≤ VDD ≤ 7.5 VSS 0.3 V VSS VDD Low-level input voltage VIL Input voltage amplitude VIN LIN, RIN Input pulse width tøW CL 1 s s Setup time tsetup CL, DI, CE 1 Hold time thold CL, DI, CE 1 Operating frequency fopg CL Vp-p s 500 kHz Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. Electrical Characterristics at Ta = 25C, VDD = 9V, VSS = 0V Parameter Input resistance Symbol Rin Pin Name Conditions Ratings min typ LIN, RIN Unit max 50 k Overall Characteristics Parameter Symbol Conditions Ratings min typ VIN = 1 Vrms, f = 1 kHz Total harmonic distortion THD 0.002 With all settings flat overall VIN = 1 Vrms, f = 20 kHz CT VIN = 1 Vrms, f = 1 kHz, Rg = 1 k With all settings flat overall Output noise voltage VN 80 kHz L.P.F, Rg = 1 k Vomin VIN = 1 Vrms, f = 1 kHz With all settings flat overall Current drain IDD VDD – VSS = +9 V High-level input current IIH CL, DI, CE: VIN = 10 V, VDD = 10 V Low-level input current IIL CL, DI, CE: VIN = 0 V, VDD = 10 V dB 6.0 V 92 dB 12 mA 10 10 % % 90 With all settings flat overall Maximum attenuation 0.01 0.003 With all settings flat overall Crosstalk Unit max A A Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. No.7332-2/13 LC75344MD Package Dimensions unit : mm SOIC-10 NB CASE 751BQ ISSUE B 2X 0.10 C A-B D D A 2X 0.10 C A-B 10 F 6 H E 1 5 0.20 C 10X B 2X 5 TIPS L2 b 0.25 A3 L C SEATING PLANE DETAIL A M C A-B D TOP VIEW 10X 0.10 C 0.10 C h X 45 M A e A1 C NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.10mm TOTAL IN EXCESS OF ’b’ AT MAXIMUM MATERIAL CONDITION. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.15mm PER SIDE. DIMENSIONS D AND E ARE DETERMINED AT DATUM F. 5. DIMENSIONS A AND B ARE TO BE DETERMINED AT DATUM F. 6. A1 IS DEFINED AS THE VERTICAL DISTANCE FROM THE SEATING PLANE TO THE LOWEST POINT ON THE PACKAGE BODY. SEATING PLANE DETAIL A SIDE VIEW RECOMMENDED SOLDERING FOOTPRINT* END VIEW DIM A A1 A3 b D E e H h L L2 M GENERIC MARKING DIAGRAM* 10 1.00 PITCH 10X 0.58 MILLIMETERS MIN MAX 1.25 1.75 0.10 0.25 0.17 0.25 0.31 0.51 4.80 5.00 3.80 4.00 1.00 BSC 5.80 6.20 0.37 REF 0.40 0.80 0.25 BSC 0 8 XXXXX ALYWX 1 6.50 10X 1.18 1 DIMENSION: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. XXXXX A L Y W = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part No.7332-3/13 LC75344MD CE 9 Vref ROUT 10 VSS RIN Pin Arrangement 7 6 LC75344MD 5 CL 4 DI 3 VDD 2 LOUT LIN 1 Top view RVref 2.2F LOUT + 2 DI CL 3 10 RIN 1F + +- ROUT 2.2F + 9 CCB INTERFACE VDD CONTROL CIRCUIT LOGIC CIRCUIT -+ PA -+ CONTROL CIRCUIT 1F LIN + 1 +- LVref Equivalent Circuit 8 4 7 5 6 PA VSS Vref + 22F CE COM No.7332-4/13 LC75344MD Control System Timing and Data Format The LC75344MD is controlled by inputting the stipulated data serially to the CL, DI, and CE pins. The data consists of a total of 24 bits, of which 8 bits are the address and 16 bits are the data. B0 B1 B2 B3 A0 A1 A2 A3 D1 D2 D3 D4 D5 D0 D9 D10 D11 D12 D13 D14 D15 DI CE CL 1s min CE 1s min 1s min 1s min CL 1s min DI 1s ≤ TDEST Address Code (B0 to A3) The data has an 8-bit address field, and conforms to the CCB serial bus specifications. Address code (LSB) B0 B1 B2 B3 A0 A1 A2 A3 0 0 0 1 0 0 0 1 (88HEX) No.7332-5/13 LC75344MD Control Code Allocations Volume control D0 D1 D2 D3 D4 D5 D6 D7 Operation 0 0 0 0 0 0 0 0 0dB 1 0 0 0 0 0 0 0 1dB 0 1 0 0 0 0 0 0 2dB 1 1 0 0 0 0 0 0 3dB 0 0 1 0 0 0 0 0 4dB 1 0 1 0 0 0 0 0 5dB 0 1 1 0 0 0 0 0 6dB 1 1 1 0 0 0 0 0 7dB 0 0 0 1 0 0 0 0 8dB 1 0 0 1 0 0 0 0 9dB 0 1 0 1 0 0 0 0 10dB 1 1 0 1 0 0 0 0 11dB 0 0 1 1 0 0 0 0 12dB 1 0 1 1 0 0 0 0 13dB 0 1 1 1 0 0 0 0 14dB 1 1 1 1 0 0 0 0 15dB 0 0 0 0 1 0 0 0 16dB 1 0 0 0 1 0 0 0 17dB 0 1 0 0 1 0 0 0 18dB 1 1 0 0 1 0 0 0 19dB 0 0 1 0 1 0 0 0 20dB 1 0 1 0 1 0 0 0 21dB 0 1 1 0 1 0 0 0 22dB 1 1 1 0 1 0 0 0 23dB 0 0 0 1 1 0 0 0 24dB 1 0 0 1 1 0 0 0 25dB 0 1 0 1 1 0 0 0 26dB 1 1 0 1 1 0 0 0 27dB 0 0 1 1 1 0 0 0 28dB 1 0 1 1 1 0 0 0 29dB 0 1 1 1 1 0 0 0 30dB 1 1 1 1 1 0 0 0 31dB 0 0 0 0 0 1 0 0 32dB 1 0 0 0 0 1 0 0 33dB 0 1 0 0 0 1 0 0 34dB 1 1 0 0 0 1 0 0 35dB 0 0 1 0 0 1 0 0 36dB 1 0 1 0 0 1 0 0 37dB 0 1 1 0 0 1 0 0 38dB 1 1 1 0 0 1 0 0 39dB 0 0 0 1 0 1 0 0 40dB Continued on next page. No.7332-6/13 LC75344MD Continued from preceding page. Volume control D0 D1 D2 D3 D4 D5 D6 D7 Operation 1 0 0 1 0 1 0 0 41dB 0 1 0 1 0 1 0 0 42dB 1 1 0 1 0 1 0 0 43dB 0 0 1 1 0 1 0 0 44dB 1 0 1 1 0 1 0 0 45dB 0 1 1 1 0 1 0 0 46dB 1 1 1 1 0 1 0 0 47dB 0 0 0 0 1 1 0 0 48dB 1 0 0 0 1 1 0 0 49dB 0 1 0 0 1 1 0 0 50dB 0 0 1 0 1 1 0 0 52dB 0 1 1 0 1 1 0 0 54dB 0 0 0 1 1 1 0 0 56dB 0 1 0 1 1 1 0 0 58dB 0 0 1 1 1 1 0 0 60dB 0 1 1 1 1 1 0 0 62dB 0 0 0 0 0 0 1 0 64dB 0 1 0 0 0 0 1 0 66dB 0 0 1 0 0 0 1 0 68dB 0 1 1 0 0 0 1 0 70dB 0 0 0 1 0 0 1 0 72dB 0 1 0 1 0 0 1 0 74dB 0 0 1 1 0 0 1 0 76dB 0 1 1 1 0 0 1 0 78dB 0 0 0 0 1 0 1 0 D8 D9 0 0 Normally not used 1 0 RCH 0 1 LCH 1 1 Left and right channels together D10 D11 D12 D13 D14 D15 0 0 0 0 0 0 Channel selection Operation Test mode Operation These bits specify the IC test mode. They must be set to zero for normal operation. No.7332-7/13 LC75344MD Pin Functions Pin name Pin No. LIN 1 RIN 10 Function Notes Volume control inputs VDD VRIN LOUT 2 ROUT 9 Volume control outputs VDD OUT Vref 7 VDD 0.5 voltage generator block for the analog ground level. A capacitor with a value a few times 10 μF must be inserted between Vref and AVSS (VSS) to minimize power supply ripple. VDD Vref VSS 8 Ground VDD 3 Power supply CE 6 DI 4 CL 5 Chip enable The internal latch data is written and the analog switches operate at the point this pin goes from high to low. Data transfer is enabled when this pin is at the high level. VDD Serial data and clock inputs for IC control. No.7332-8/13 LC75344MD Equivalent Circuit LOUT LIN 0dB R1=5434 -1dB R28=243 R2=4845 -2dB R29=216 -3dB R30=193 R4=3850 -4dB R31=172 R5=3431 -5dB R32=153 R6=3058 -6dB R33=137 -7dB R34=122 R8=2429 -8dB R35=108 R9=2165 -9dB R36=97 R10=1930 -10dB R37=86 -11dB R38=77 R12=1533 -12dB R39=68 R13=1366 -13dB R40=61 R14=1218 -14dB R41=54 -15dB R42=48 R16=967 -16dB R43=86 R17=862 -17dB R44=77 R18=768 -18dB R45=69 -19dB R46=61 R20=610 -20dB R47=55 R21=544 -21dB R48=49 R22=485 -22dB R49=87 -23dB R50=77 R24=385 -24dB R51=130 R25=343 -25dB R26=306 -26dB R27=273 -27dB -30dB -31dB -58dB R55=104 -32dB -33dB -60dB R56=165 -34dB -35dB -62dB R57=131 -36dB -37dB -64dB R58=104 -38dB -39dB -66dB R59=165 -40dB -41dB -68dB R60=131 -42dB -43dB -70dB R61=104 -44dB -45dB -72dB R62=165 -46dB -47dB -74dB R63=131 -48dB -49dB -76dB R64=104 -50dB -78dB R65=403 -52dB R52=104 -dB -54dB R71=804 R23=432 -56dB R54=130 R70=802 R19=685 -29dB R69=800 R15=1085 R68=798 R11=1720 R67=796 R7=2726 R66=794 R3=4319 R53=164 -28dB The right channel is identical. LVref No.7332-9/13 LC75344MD Reference Voltage Generator Equivalent Circuit VDD 20k The right channel is identical. VREF 20k LVref Test Circuit Total harmonic distortion 1F 2.2F VDD 1 10 2 9 3 LC75344MD 8 4 7 5 6 1F 2.2F 22F COM THDin DISTORTION ANALYZER The right channel is identical. S.G No.7332-10/13 LC75344MD Output noise voltage 1k 1F 2.2F VDD 1 10 2 9 3 LC75344MD 8 4 7 5 6 1F 2.2F 22F COM The right channel is identical. Noise METER Crosstalk S.G 1k 1F 2.2F VDD 1 10 2 9 3 LC75344MD 8 4 7 5 6 1F 2.2F 22F COM Volt METER The right channel is identical. Usage Notes The states of the internal analog switches are undefined after power is first applied. Muting must be applied externally until the control data has been sent. When performing the initial settings after power is first applied, both the left and right channel initial settings data must be sent before releasing the external mute. Either cover the CL, DI, and CE lines with the ground pattern or use shielded lines to prevent high-frequency digital noise from entering the analog signal system from these lines. No.7332-11/13 LC75344MD THD vs. Volume Control Step Characteristics Volume Step Characteristics 0 –10 –20 Total harmonic distortion, THD — % VDD=9V VSS=0V f=1kHz VIN=0dBV Level — dB –30 –40 –50 –60 –70 –80 –90 –100 –100 –90 –80 –70 –60 –50 –40 –30 –20 0.1 7 5 3 0 2 0.01 7 5 VIN= –10dBV 0dBV 0.001 7 5 3 2 0.0001 10 2 3 Level — dB –30 5 71000 2 3 Frequency — Hz 5 710000 2 3 5 7100000 ILC05484 VDD=9V VSS=0V f=1kHz VIN=0dBV(LIN) Vin = 1 kΩ, terminated (RIN) ROUT Measured –40 –50 –60 –70 –80 –90 –100 10 10k 1kH z 0.001 7 5 3 2 –30 –20 –10 0 10 ILC05483 THD vs. Input Level Characteristics 1.0 7 5 3 2 VDD=9V VSS=0V 80kHz LPW All settings flat overall. 0.1 7 5 3 2 0.01 7 5 3 2 Hz 10k 0.001 7 5 3 2 Hz 1k 0.0001 –40 –30 –20 –10 0 10 Input level — dBV ILC05485 THD vs. Supply Voltage Characteristics 0.01 Total harmonic distortion, THD — % –20 2 3 Crosstalk Characteristics 0 –10 5 7 100 Hz 0.01 7 5 3 2 Volume Step THD vs. Frequency Characteristics 2 0.1 7 5 3 2 ILC05482 VDD=9V VSS=0V 80kHz LPW 3 VDD=9V VSS=0V 80kHz LPW All settings flat overall. 0.0001 –40 Total harmonic distortion, THD — % Total harmonic distortion, THD — % Step –10 1.0 7 5 3 2 VDD=9V VSS=0V 80kHz LPW All settings flat overall. 7 5 3 10 kH 2 z 0.001 1kHz 7 100Hz 5 3 2 3 5 7 100 2 3 5 71000 2 3 Frequency — Hz 5 710000 2 3 5 7100000 ILC05486 6 7 8 9 10 Supply voltage — V 11 12 ILC05487 No.7332-12/13 LC75344MD ORDERING INFORMATION Device LC75344MD-AH Package SOIC-10 NB (Pb-Free / Halogen Free) Shipping (Qty / Packing) 2500 / Tape & Reel ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). 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