gd25d10

http://www.elm-tech.com
GD25D10B
DATASHEET
GD25D10BxIGx Uniform sector dual and quad serial flash
http://www.elm-tech.com
- Content 1. FEATURES
Page
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2. GENERAL DESCRIPTION
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4. DEVICE OPERATION
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5. DATA PROTECTION
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6. STATUS REGISTER
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3. MEMORY ORGANIZATION
7. COMMANDS DESCRIPTION
TABLE OF ID DEFINITION
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7.1. Write enable (wren) (06H)
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7.2. Write disable (WRDI) (04H)
7.3. Read status register (WDSR) (05H)
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7.4. Write status register (WRSR) (01H)
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7.5. Read data bytes (READ) (03H)
7.6. Read data bytes at higher speed (Fast read) (0BH)
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7.7. Dual output fast read (3BH)
7.8. Page program (PP) (02H)
7.9. Fast page program (FPP) (F2H)
7.10. Sector erase (SE) (20H)
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7.11. 32KB Block erase (BE) (52H)
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7.12. 64KB Block erase (BE) (D8H)
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7.13. Chip erase (CE) (60/C7H)
7.14. Deep power-down (DP) (B9H)
7.15. Release from deep power-down / read device ID (ABH)
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7.16. Read manufacture ID / device ID (REMS) (90H)
7.17. Read identification (RDID) (9FH)
8. ELECTRICAL CHARACTERISTICS
8.1. Power-ON timing
8.2. Initial delivery state
8.3. Data retention and endurance
8.4. Latch up characteristics
8.5. Absolute maximum ratings
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8.6. Capacitance measurement conditions
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8.7. DC characteristics
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8.8. AC characteristics
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GD25D10BxIGx Uniform sector dual and quad serial flash
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9. ORDERING INFORMATION
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10. PACKAGE INFORMATION
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10.1. Package SOP8 150MIL
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10.2. Package USON8 (3x2MM)
GD25D10BxIGx Uniform sector dual and quad serial flash
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1. FEATURES
♦ 1M-bit Serial Flash
- 128K/64K-byte
- 256 bytes per programmable page
♦ Standard, Dual Output
- Standard SPI: SCLK, CS#, SI, SO, WP#
- Dual Output: SCLK, CS#, IO0, O1, WP#
♦ Clock Frequency
- 80MHz for fast read with 30PF load
- Dual Output Data transfer up to 160Mbits/s
♦ Software/Hardware Write Protection
- Write protect all/portion of memory via software
- Enable/Disable protection with WP# pin
♦ Cycling endurance
- Minimum 100,000 Program/Erase cycles
♦ Data retention
- 20-year data retention typical
♦ Program/Erase Speed
- Page Program time: 0.7ms typical
- Sector Erase time: 40ms typical
- Block Erase time: 0.2/0.4s typical
- Chip Erase time: 0.8/0.4s typical
♦ Flexible Architecture
- Sector of 4K-byte
- Block of 32/64K-byte
♦ Low Power Consumption
- 18mA maximum active current
- 5μA maximum power down current
♦ Single Power Supply Voltage
- Full voltage range: 2.7~3.6V
♦ Package option
- SOP8 150MIL
- USON8 3x2mm
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2. GENERAL DESCRIPTION
The GD25D10B (1M-bit) serial flash supports the standard serial peripheral interface (SPI), and supports the
Dual Output: Serial Clock, Chip Select, Serial Data I/O0 (SI), O1 (SO). The Dual Output data is transferred with
speed of 160Mbits/s.
Connection Diagram
8-LEAD SOP
8-LEAD USON
PIN Description
Pin Name
I/O
CS#
I
Chip Select Input
SO (O1)
WP#
VSS
O
I
Data Output ( Data Output 1 )
Write Protect Input
Ground
SI (IO0)
SCLK
NC
I/O
I
VCC
Description
Data Input ( Data Input Output 0 )
Serial Clock Input
No Connection
Power Supply
Block Diagram
Write Control
Logic
Status
Register
SCLK
CS#
SPI
Command &
Control Logic
High Voltage
Generators
Page Address
Latch/Counter
Write Protect Logic
and Row Decode
WP#
Flash
Memory
Column Decode And
256-Byte Page Buffer
SI(IO0)
SO(O1)
Byte Address
Latch/Counter
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3. MEMORY ORGANIZATION
Each device has
Each block has
Each sector has
Each page has
128K
64/32K
4K
256
bytes
512
256/128
16
-
pages
32
16/8
-
-
sectors
2/4
-
-
-
blocks
Uniform Block Sector Architecture
Block
Sector
1
31
-----
01F000H
-----
01FFFFH
-----
16
010000H
010FFFH
15
-----
00F000H
-----
00FFFFH
-----
0
000000H
000FFFH
0
Address range
4. DEVICE OPERATION
SPI Mode
Standard SPI
The GD25D10B features a serial peripheral interface on 4 signals bus: Serial Clock (SCLK), Chip Select (CS#),
Serial Data Input (SI) and Serial Data Output (SO). Both SPI bus mode 0 and 3 are supported. Input data is
latched on the rising edge of SCLK and data shifts out on the falling edge of SCLK.
Dual SPI
The GD25D10B supports Dual Output operation when using the “Dual Output Fast Read” (3BH) commands.
These commands allow data to be transferred to or from the device at two times the rate of the standard SPI.
When using the Dual Output command the SI and SO pins become bidirectional I/O pins: IO0 and O1.
5. DATA PROTECTION
The GD25D10B provides the following data protection methods:
♦ Write Enable (WREN) command: The WREN command is set the Write Enable Latch bit (WEL). The WEL
bit will reset to 0 in the following situations:
- Power-Up
- Write Disable (WRDI)
- Write Status Register (WRSR)
- Page Program (PP)
- Sector Erase (SE) / Block Erase (BE) / Chip Erase (CE)
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♦ Software Protection Mode: The Block Protect (BP2, BP1, BP0) bits define the section of the protected
memory area which is read-only and unalterable.
♦ Hardware Protection Mode: WP# going low to protected the BP0~BP2 bits and SRP bits.
♦ Deep Power-Down Mode: In Deep Power-Down Mode, all commands are ignored except the Release from
Deep Power-Down Mode command.
♦ Write Inhibit Voltage (VWI): Device would reset automatically when VCC is below a certain threshold VWI.
Table 1. GD25D10B Protected area size
Status Register Content
BP2
0
0
0
0
1
1
1
BP1
0
0
1
1
0
0
1
Memory Content
BP0
0
1
0
1
0
1
×
Blocks
NONE
Sector 0 to 29
Sector 0 to 27
Sector 0 to 23
Sector 0 to 15
All
All
Addresses
NONE
000000H-01DFFFH
000000H-01BFFFH
000000H-017FFFH
000000H-00FFFFH
000000H-01FFFFH
000000H-01FFFFH
Density
NONE
120KB
112KB
96KB
64KB
128KB
128KB
Portion
NONE
Lower 30/32
Lower 28/32
Lower 24/32
Lower 16/32
All
All
6. STATUS REGISTER
S7
S6
S5
S4
S3
S2
S1
S0
SRP
Reserved
Reserved
BP2
BP1
BP0
WEL
WIP
The status and control bits of the Status Register are as follows:
WIP bit.
The Write In Progress (WIP) bit indicates whether the memory is busy in program/erase/write status register
progress. When WIP bit is set to 1, it means the device is busy in program/erase/write status register progress.
When WIP bit is cleared to 0, it means the device is not in program/erase/write status register progress. The
default value of WIP is 0.
WEL bit.
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1 the
internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no write Status
Register, Program or Erase command is accepted. The default value of WEL is 0.
BP2, BP1, BP0 bits.
The Block Protect (BP2, BP1, BP0) bits are non-volatile. They define the size of the area to be software
protected against Program and Erase commands. These bits are written with the Write Statue Register (WRSR)
command. When the Block Protect (BP2, BP1, BP0) bits are set to 1, the relevant memory area (as defined in
Table1). Becomes protected against Page Program (PP), Sector Erase (SE) and Block Erase (BE) commands.
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The Block protect (BP2, BP1, BP0) bits can be written provided that the Hardware Protected mode has not been
set. The Chip Erase (CE) command is executed,if the Block Protect (BP2, BP1, BP0) bits are all 0.The default
value of BP2:0 are 0s.
SRP bit.
The Status Register Protect (SRP) bit operates in conjunction with the Write Protect (WP#) signal. The Status
Register Write Protect (SRP) bit and Write Protect (WP#) signal set the device to the hardware Protected mode.
When the Status Register Protect (SRP) bit is set to 1, and Write Protect (WP#) is driven Low. In this mode,
the non-volatile bits of the Status Register (SRP, BP2, BP1, BP0) become read-only bits and the Write Status
Register (WRSR) instruction is not execution. The default value of SRP is 0.
SRP
#WP
Status Register
Description
0
×
Software Protected
The Status Register can be written to after a Write Enable
command, WEL=1.(Default)
1
0
Hardware Protected
WP#=0, the Status Register locked and can not be written
to.
1
1
Hardware Unprotected
WP#=1, the Status Register is unlocked and can be
written to after a Write Enable command, WEL=1.
7. COMMANDS DESCRIPTION
All commands, addresses and data are shifted in and out of the device by the host system, with the most
significant bit first. On the first rising edge of SCLK after CS# is driven low, the one-byte command code must
be shifted into the device, with the most significant bit first on SI, each bit being latched on the rising edges of
SCLK.
See Table2, every command sequence starts with a one-byte command code. Depending on the command, this
might be followed by address bytes, or data bytes, or dummy bytes. CS# must be driven high after the last bit of
the command sequence has been shifted in.
For the command of Read, Fast Read, Read Status Register or Release from Deep Power-Down, and Read
Device ID, the shifted-in command sequence is followed by a data-out sequence. CS# can be driven high after
any bit of the data-out sequence is being shifted out.
For the command of Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Write
Enable, Write Disable or Deep Power-Down command, CS# must be driven high exactly at a byte boundary,
which means the clock pulse number should be an exact multiple of eight. Otherwise the command is rejected to
executed. Especially for Page Program command, if at any time the input end is not a completed byte, nothing
will be written into the memory array, neither would WEL bit be reset.
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Table 2. Commands
Command Name
Write Enable
Write Disable
Read Status Register
Write Status Register
Read Data
Fast Read
Dual Output Fast Read
Page Program
Fast Page Program
Sector Erase
Block Erase (32K)
Block Erase (64K)
Chip Erase
Deep Power-Down
Release From Deep
Power-Down, And
Read Device ID
Release From Deep
Power-Down
Byte 1
Byte 2
Byte 3
Byte 4
06H
04H
05H
01H
03H
0BH
3BH
02H
F2H
20H
52H
D8H
C7/60H
B9H
(S7-S0)
(S7-S0)
A23-A16
A23-A16
A23-A16
A23-A16
A23-A16
A23-A16
A23-A16
A23-A16
A15-A8
A15-A8
A15-A8
A15-A8
A15-A8
A15-A8
A15-A8
A15-A8
A7-A0
A7-A0
A7-A0
A7-A0
A7-A0
A7-A0
A7-A0
A7-A0
ABH
dummy
dummy
dummy
dummy
Byte 5
Byte 6
n-Bytes
(continuous)
(D7-D0)
dummy
dummy
(D7-D0)
(D7-D0)
(Next byte) (continuous)
(D7-D0) (continuous)
D7-D0(1) (continuous)
Next byte
Next byte
dummy
(DID7DID0)
(continuous)
00H
(MID7MID0)
ABH
Manufacturer/Device ID
90H
Read Identification
9FH
(MID7-MID0) (JDID15-JDID8) (JDID7-JDID0)
(DID7DID0)
(continuous)
(continuous)
NOTE:
(1) Dual Output data
IO0 = (D6, D4, D2, D0)
O1 = (D7, D5, D3, D1)
Table of ID Definitions :
Operation Code
M7-M0
ID15-ID8
ID7-ID0
9FH
90H
C8
C8
40
11
10
ABH
10
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7.1. Write Enable (WREN)(06H)
The Write Enable (WREN) command is for setting the Write Enable Latch (WEL) bit to 1. The Write Enable
Latch (WEL) bit must be set prior to every Page Program (PP), Sector Erase (SE), Block Erase (BE), Chip Erase
(CE) and Write Status Register (WRSR) command.
The Write Enable (WREN) command sequence: CS# goes low → sending the Write Enable command → CS#
goes high.
Figure 1. Write Enable Sequence Diagram
CS#
SCLK
0
1
2
3
4
5
6
7
Command
SI
06H
High-Z
SO
7.2. Write Disable (WRDI) (04H)
The Write Disable command is for resetting the Write Enable Latch (WEL) bit to 0. The WEL bit is reset by
following condition: Power-up and upon completion of the Write Status Register, Page Program, Sector Erase,
Block Erase and Chip Erase commands.
The Write Disable command sequence: CS# goes low → Sending the Write Disable command → CS# goes
high.
Figure 2. Write Disable Sequence Diagram
CS#
SCLK
SI
SO
0
1
2
3
4
5
6
7
Command
04H
High-Z
7.3. Read Status Register (RDSR) (05H)
The Read Status Register (RDSR) command is for reading the Status Register. The Status Register may be read
at any time, even while a Program, Erase or Write Status Register cycle is in progress.
When one of these cycles is in progress, it is recommended to check the Write in Progress (WIP) bit before
sending a new command to the device. It is also possible to read the Status Register continuously. For command
code “05H”, the SO will output Status Register bits S7~S0.
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Figure 3. Read Status Register Sequence Diagram
CS#
SCLK
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
7
6
Command
SI
05H
SO
High-Z
S7~S0 out
5 4 3 2
1
0
7
6
5
S7~S0 out
4 3 2 1
0
7
MSB
MSB
7.4. Write Status Register (WRSR) (01H)
The Write Status Register (WRSR) instruction allows new values to be written to the Status Register. A Write
Enable (WREN) instruction must be executed previously to set the Write Enable Latch (WEL) bit, before it can
be accepted.
The Write Status Register (WRSR) instruction is entered by driving Chip Select (CS#) Low, followed by the
instruction code and the data byte on Serial Data Input (DI).
The Write Status Register (WRSR) instruction has no effect on S6, S5, S1 and S0 of the Status Register. S6
and S5 are always read as 0. Chip Select (CS#) must be driven High after the eighth bit of the data byte has been
latched in. Otherwise, the Write Status Register (WRSR) instruction is not executed. As soon as Chip Select (CS#)
is driven High, the self-timed Write Status Register cycle (the duration is tw) is initiated. While the Write Status
Register cycle is in progress, reading Status Register to check the Write in Progress (WIP) bit is achievable.
The Write In Progress (WIP) bit is 1 during the self-timed Write Status Register cycle, and turn to 0 on the
completion of the Write Status Register. When the cycle is completed, the Write Enable Latch (WEL) is reset to 0.
The Write Status Register (WRSR) instruction allows the user to change the values of the Block Protect (BP2,
BP1, BP0) bits, which are utilized to define the size of the read-only area.
The Write Status Register (WRSR) instruction also allows the user to set or reset the Status Register Protect
(SRP) bit in accordance with the Write Protect (WP#) signal, by setting which the device can enter into
Hardware Protected Mode (HPM). The Write Status Register (WRSR) instruction is not executed once enter
into the Hardware Protected Mode (HPM).
Figure 4. Write Status Register Sequence Diagram
CS#
SCLK
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
7
6
Command
SI
SO
01H
Status Register in
MSB
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4
3
2
1
0
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GD25D10BxIGx Uniform sector dual and quad serial flash
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7.5. Read Data Bytes (READ) (03H)
The Read Data Bytes (READ) command is followed by a 3-byte address (A23-A0), each bit being latchedin on the rising edge of SCLK. Then the memory content, at that address, is shifted out on SO, each bit being
shifted out, at a Max frequency fR, on the falling edge of SCLK. The first byte addressed can be at any location.
The address is automatically incremented to the next higher address after each byte of data is shifted out. The
whole memory can, therefore, be read with a single Read Data Bytes (READ) command. Any Read Data Bytes
(READ) command, while an Erase, Program or Write cycle is in progress, is rejected without having any effects
on the cycle that is in progress.
Figure 5. Read Data Bytes Sequence Diagram
7.6. Read Data Bytes at Higher Speed (Fast Read) (0BH)
The Read Data Bytes at Higher Speed (Fast Read) command is for quickly reading data out. It is followed by
a 3-byte address (A23-A0) and a dummy byte, each bit being latched-in on the rising edge of SCLK. Then the
memory content, at that address, is shifted out on SO, each bit being shifted out, at a Max frequency fC, on the
falling edge of SCLK. The first byte addressed can be at any location. The address is automatically incremented
to the next higher address after each byte of data is shifted out.
Figure 6. Read Data Bytes at Higher Speed Sequence Diagram
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7.7. Dual Output Fast Read (3BH)
The Dual Output Fast Read command is followed by 3-byte address (A23-A0) and a dummy byte, each bit
being latched in on the rising edge of SCLK, then the memory contents are shifted out 2-bit per clock cycle
from SI and SO. The command sequence is shown in followed Figure7. The first byte addressed can be at any
location. The address is automatically incremented to the next higher address after each byte of data is shifted
out.
Figure 7. Dual Output Fast Read Sequence Diagram
7.8. Page Program (PP) (02H)
The Page Program (PP) command is for programming the memory. A Write Enable (WREN) command must
previously have been executed to set the Write Enable Latch (WEL) bit before sending the Page Program
command.
The Page Program (PP) command is entered by driving CS# Low, followed by the command code, three
address bytes and at least one data byte on SI.
If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data that goes beyond the end
of the current page are programmed from the start address of the same page (from the address whose 8 least
significant bits (A7-A0) are all zero). CS# must be driven low for the entire duration of the sequence.
The Page Program command sequence: CS# goes low → sending Page Program command → 3-byte address
on SI → at least 1 byte data on SI→ CS# goes high. The command sequence is shown in Figure8.
If more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes
are guaranteed to be programmed correctly within the same page. If less than 256 data bytes are sent to device,
they are correctly programmed at the requested addresses without having any effects on the other bytes of the
same page. CS# must be driven high after the eighth bit of the last data byte has been latched in; otherwise the
Page Program (PP) command is not executed.
As soon as CS# is driven high, the self-timed Page Program cycle (whose duration is tPP) is initiated. While the
Page Program cycle is in progress, the Status Register may be read to check the value of the Write in Progress
(WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is
completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
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A Page Program (PP) command is not executed when it is applied to a page protected by the Block Protect (BP2,
BP1, BP0).
Figure 8. Page Program Sequence Diagram
7.9. Fast Page Program (FPP) (F2H)
The Fast Page Program (FPP) command is for programming the memory. A Write Enable (WREN) command
must previously have been executed to set the Write Enable Latch (WEL) bit before sending the Page Program
command.
The Fast Page Program (FPP) command is entered by driving CS# Low, followed by the command code, three
address bytes and at least one data byte on SI. If the 8 least significant address bits (A7-A0) are not all zero,
all transmitted data that goes beyond the end of the current page are programmed from the start address of the
same page (from the address whose 8 least significant bits (A7-A0) are all zero). CS# must be driven low for the
entire duration of the sequence.
The Page Program command sequence: CS# goes low → sending Page Program command → 3-byte address
on SI → at least 1 byte data on SI → CS# goes high.
The command sequence is shown in Figure9. If more than 256 bytes are sent to the device, previously latched
data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page.
If less than 256 data bytes are sent to device, they are correctly programmed at the requested addresses without
having any effects on the other bytes of the same page. CS# must be driven high after the eighth bit of the last
data byte has been latched in; otherwise the Fast Page Program (FPP) command is not executed.
As soon as CS# is driven high, the self-timed Page Program cycle (whose duration is tPP) is initiated. While the
Page Program cycle is in progress, the Status Register may be read to check the value of the Write In Progress
(WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is
completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
A Fast Page Program (FPP) command is not executed when it is applied to a page protected by the Block
Protect (BP2, BP1, BP0).
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Figure 9. Fast Page Program Sequence Diagram
7.10. Sector Erase (SE) (20H)
The Sector Erase (SE) command is for erasing the all data of the specific sector. A Write Enable (WREN)
command must previously have been executed to set the Write Enable Latch (WEL) bit. The Sector Erase (SE)
command is entered by driving CS# low, followed by the command code, and 3-address byte on SI. Any address
inside the sector is a valid address for the Sector Erase (SE) command. CS# must be driven low for the entire
duration of the sequence.
The Sector Erase command sequence: CS# goes low → sending Sector Erase command → 3-byte address on
SI → CS# goes high. The command sequence is shown in Figure10. CS# must be driven high after the eighth
bit of the last address byte has been latched in; otherwise the Sector Erase (SE) command is not executed. As
soon as CS# is driven high, the self-timed Sector Erase cycle (whose duration is tSE) is initiated. While the
Sector Erase cycle is in progress, the Status Register is accessed to check the value of the Write in Progress (WIP)
bit. The Write in Progress (WIP) bit is 1 during the self-timed Sector Erase cycle, and becomes 0 when it is
completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
A Sector Erase (SE) command applied to a sector which is protected by the Block Protect (BP2, BP1, BP0) bit (see
Table1) is not executed.
Figure 10. Sector Erase Sequence Diagram
CS#
SCLK
SI
0
1
2
3
4
5
6
7
8
29 30 31
24 Bits Address
Command
20H
9
23 22
MSB
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7.11. 32KB Block Erase (BE) (52H)
The 32KB Block Erase (BE) command is for erasing the all data of the chosen block. A Write Enable (WREN)
command must previously have been executed to set the Write Enable Latch (WEL) bit. The 32KB Block Erase
(BE) command is entered by driving CS# low, followed by the command code, and three address bytes on SI.
Any address inside the block is a valid address for the 32KB Block Erase (BE) command. CS# must be driven
low for the entire duration of the sequence.
The 32KB Block Erase command sequence: CS# goes low → sending 32KB Block Erase command → 3-byte
address on SI→ CS# goes high. The command sequence is shown in Figure11. CS# must be driven high after
the eighth bit of the last address byte has been latched in; otherwise the 32KB Block Erase (BE) command is not
executed. As soon as CS# is driven high, the self-timed Block Erase cycle (whose duration is tBE) is initiated.
While the Block Erase cycle is in progress, the Status Register is accessed to check the value of the Write in
Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Block Erase cycle, and becomes
0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL)
bit is reset. A 32KB Block Erase (BE) command applied to a block which is protected by the Block Protect (BP2,
BP1, BP0) bits (see Table1) is not executed.
Figure 11. 32KB Block Erase Sequence Diagram
CS#
SCLK
0
1
SI
2
3
4
5
6
7
8
29 30 31
24 Bits Address
Command
52H
9
23 22
MSB
2
1
0
7.12. 64KB Block Erase (BE) (D8H)
The 64KB Block Erase (BE) command is for erasing the all data of the chosen block. A Write Enable (WREN)
command must previously have been executed to set the Write Enable Latch (WEL) bit. The 64KB Block Erase
(BE) command is entered by driving CS# low, followed by the command code, and three address bytes on SI.
Any address inside the block is a valid address for the 64KB Block Erase (BE) command. CS# must be driven
low for the entire duration of the sequence.
The 64KB Block Erase command sequence: CS# goes low → sending 64KB Block Erase command → 3-byte
address on SI→ CS# goes high. The command sequence is shown in Figure12. CS# must be driven high after
the eighth bit of the last address byte has been latched in; otherwise the 64KB Block Erase (BE) command is not
executed. As soon as CS# is driven high, the self-timed Block Erase cycle (whose duration is tBE) is initiated.
While the Block Erase cycle is in progress, the Status Register is accessed to check the value of the Write in
Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Block Erase cycle, and becomes
0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL)
bit is reset. A 64KB Block Erase (BE) command applied to a block which is protected by the Block Protect (BP2,
BP1, BP0) bits (see Table1) is not executed.
28 - 16
Rev.1.0
GD25D10BxIGx Uniform sector dual and quad serial flash
http://www.elm-tech.com
Figure 12. 64KB Block Erase Sequence Diagram
CS#
SCLK
1
0
2
3
4
5
6
7
8
9
24 Bits Address
Command
SI
29 30 31
23 22
MSB
D8H
2
1
0
7.13. Chip Erase (CE) (60/C7H)
The Chip Erase (CE) command is for erasing the all data of the chip. A Write Enable (WREN) command must
previously have been executed to set the Write Enable Latch (WEL) bit .The Chip Erase (CE) command is
entered by driving CS# Low, followed by the command code on Serial Data Input (SI). CS# must be driven Low
for the entire duration of the sequence.
The Chip Erase command sequence: CS# goes low → sending Chip Erase command → CS# goes high. The
command sequence is shown in Figure13. CS# must be driven high after the eighth bit of the command code
has been latched in, otherwise the Chip Erase command is not executed. As soon as CS# is driven high, the selftimed Chip Erase cycle (whose duration is tCE) is initiated. While the Chip Erase cycle is in progress, the Status
Register may be read to check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1
during the self-timed Chip Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle
is completed, the Write Enable Latch (WEL) bit is reset. The Chip Erase (CE) command is executed if the Block
Protect (BP2, BP1, BP0) bits are all 0 or all 1. The Chip Erase (CE) command is not executed if any sector is
under protection.
Figure 13. Chip Erase Sequence Diagram
CS#
SCLK
SI
0
1
2
3
4
5
6
7
Command
60H or C7H
7.14. Deep Power-Down (DP) (B9H)
Executing the Deep Power-Down (DP) command is the only way to enter the lowest consumption mode
(the Deep Power-Down Mode). Unlike deselecting the device by driving CS# high, or entering into the
Standby Mode (if there is no internal cycle currently in progress), the Deep Power-Down Mode provides an
extra software protection mechanism while the device is not in active use. The only access to this mode is by
executing the Deep power-Down (DP) command. Since in the Deep Power-Down mode, the device ignores all
Write, Program and Erase commands. Once the device is in the Deep Power-Down Mode, all commands are
ignored except the Release from Deep Power-Down and Read Device ID (RDI) command. This releases the
device from this mode. The Release from Deep Power-Down and Read Device ID (RDI) command also allows
the Device ID of the device to be output on SO.
The Deep Power-Down Mode automatically stops at Power-Down, and the device always Power-Up in
the Standby Mode. The Deep Power-Down (DP) command is entered by driving CS# low, followed by the
command code on SI. CS# must be driven low for the entire duration of the sequence.
28 - 17
Rev.1.0
GD25D10BxIGx Uniform sector dual and quad serial flash
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The Deep Power-Down command sequence: CS# goes low → sending Deep Power-Down command → CS#
goes high. The command sequence is shown in Figure14. CS# must be driven high after the eighth bit of the
command code has been latched in; otherwise the Deep Power-Down (DP) command is not executed. As soon
as CS# is driven high, it requires a delay of tDP before the supply current is reduced to ICC2 and the Deep PowerDown Mode is entered. Any Deep Power-Down (DP) command, while an Erase, Program or Write cycle is in
progress, is rejected without having any effects on the cycle that is in progress.
Figure 14. Deep Power-Down Sequence Diagram
CS#
SCLK
tDP
0 1 2 3 4 5 6 7
Command
SI
Stand-by mode Deep Power-down mode
B9H
7.15. Release from Deep Power-Down / Read Device ID (ABH)
The Release from Power-Down and Read Device ID command is a multi-purpose command, which can be used
to release the device from the Power-Down state or obtain the devices electronic identification (ID) number.
When used to release the device from the Power-Down state, the command is issued by driving the CS# pin
low, shifting the instruction code “ABH” and driving CS# high as shown in Figure15. Release from PowerDown will take the time duration of tRES1 (See AC Characteristics) before the device will resume normal
operation and other command are accepted. The CS# pin must keep high during the tRES1 time duration.
When used only to obtain the Device ID while not in the Power-Down state, the command is initiated by
driving the CS# pin low and shifting the instruction code “ABH” followed by 3-dummy byte. The Device ID
bits are then shifted out on the falling edge of SCLK with most significant bit (MSB) first as shown in Figure15.
The Device ID value for the GD25D10B is listed in Manufacturer and Device Identification table. The Device
ID can be read continuously. The command is completed by driving CS# high.
When used to release the device from the Power-Down state and obtain the Device ID, the command is the
same as previously described, and shown in Figure16, except that after CS# is driven high it must remain high
for a time duration of tRES2 (See AC Characteristics). After this time duration the device will resume normal
operation and other command will be accepted. If the Release from Power-Down and Read Device ID command
is issued while an Erase, Program or Write cycle is in process (when WIP equal 1) the command is ignored and
will not have any effects on the current cycle.
Figure 15. Release Power-Down Sequence Diagram
CS#
SCLK
SI
0
1
2
3
4
5
6
7
t RES1
Command
ABH
Deep Power-down mode
28 - 18
Stand-by mode
Rev.1.0
GD25D10BxIGx Uniform sector dual and quad serial flash
http://www.elm-tech.com
Figure 16. Release Power-Down and Read Device ID Sequence Diagram
7.16. Read Manufacture ID/Device ID (REMS) (90H)
The Read Manufacturer/Device ID command is an alternative to the Release from Power-Down/Device ID
command that provides both the JEDEC assigned Manufacturer ID and the specific Device ID.
The command is initiated by driving the CS# pin low and shifting the command code “90H” followed by a
24-bit address (A23-A0) of 000000H. After that, the Manufacturer ID and the Device ID are shifted out on
the falling edge of SCLK with most significant bit (MSB) first as shown in Figure17. If the 24-bit address is
initially set to 000001H, the Device ID will be read first.
Figure 17. Read Manufacture ID/Device ID Sequence Diagram
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GD25D10BxIGx Uniform sector dual and quad serial flash
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7.17. Read Identification (RDID) (9FH)
The Read Identification (RDID) command allows the 8-bit manufacturer identification to be read, followed by
two bytes of device identification. The device identification indicates the memory type in the first byte, and the
memory capacity of the device in the second byte. Any Read Identification (RDID) command while an Erase
or Program cycle is in progress is not decoded, and has no effect on the cycle that is in progress. The Read
Identification (RDID) command should not be issued while the device is in Deep Power-Down Mode.
The device is first selected by driving CS# to low. Then, the 8-bit command code for the command is shifted
in. This is followed by the 24-bit device identification, stored in the memory, being shifted out on Serial Data
Output, each bit being shifted out during the falling edge of Serial Clock. The command sequence is shown in
Figure18. The Read Identification (RDID) command is terminated by driving CS# to high at any time during
data output. When CS# is driven high, the device is put in the Standby Mode. Once in the Standby Mode, the
device waits to be selected, so that it can receive, decode and execute commands.
Figure 18. Read Identification ID Sequence Diagram
28 - 20
Rev.1.0
GD25D10BxIGx Uniform sector dual and quad serial flash
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8. ELECTRICAL CHARACTERISTICS
8.1. Power-ON Timing
Table 3. Power-Up Timing and Write Inhibit Threshold
Symbol
Parameter
Min
Max
Unit
tVSL
tPUW
VCC(min) To CS# Low
Time Delay From VCC(min) To Write Instruction
10
1
10
us
ms
VWI
Write Inhibit Voltage VCC(min)
1
2.5
V
8.2. Initial Delivery State
The device is delivered with the memory array erased: all bits are set to 1(each byte contains FFH). The Status
Register contains 00H (all Status Register bits are 0).
8.3. Data Retention and Endurance
Parameter
Minimum Pattern Data Retention Time
Erase / Program Endurance
Test Condition
Min
Unit
150°C
125°C
10
20
Years
Years
-40 to 85°C
100K
Cycles
8.4. Latch Up Characteristics
Parameter
Input Voltage Respect To VSS On I/O Pins
VCC Current
28 - 21
Min
Max
-1.0V
-100mA
VCC+1.0V
100mA
Rev.1.0
GD25D10BxIGx Uniform sector dual and quad serial flash
http://www.elm-tech.com
8.5. Absolute Maximum Ratings
Parameter
Ambient Operating Temperature
Storage Temperature
Output Short Circuit Current
Applied Input/Output Voltage
VCC
0.8VCC
Input timing reference level
0.7VCC
0.2VCC
0.1VCC
Value
Unit
-40 to 85
°C
-65 to 150
°C
200
-0.5 to 4.0
mA
V
-0.5 to 4.0
V
Output timing reference level
AC Measurement Level
0.5VCC
Note: Input pulse rise and fall time are <5ns
8.6. Capacitance Measurement Conditions
Symbol
CIN
COUT
CL
Parameter
Min
Typ
Max
Unit
Conditions
Input Capacitance
6
pF
VIN=0V
Output Capacitance
Load Capacitance
Input Rise And Fall time
8
VOUT=0V
5
pF
pF
ns
0.1VCC to 0.8VCC
0.2VCC to 0.7VCC
0.5VCC
V
V
V
30
Input Pulse Voltage
Input Timing Reference Voltage
Output Timing Reference Voltage
Figure 19. Input Test Waveform and Measurement Level
Maximum Negative Overshoot Waveform
20ns
Maximum Positive Overshoot Waveform
20ns
20ns
Vss
Vcc + 2.0V
Vss-2.0V
Vcc
20ns
20ns
28 - 22
20ns
Rev.1.0
GD25D10BxIGx Uniform sector dual and quad serial flash
http://www.elm-tech.com
8.7. DC Characteristics
Symbol
(T= -40°C~85°C, VCC=2.7~3.6V)
Max.
Unit.
Input Leakage Current
±2
μA
ILO
ICC1
Output Leakage Current
Standby Current
CS#=VCC, VIN=VCC or VSS
1
±2
5
μA
μA
ICC2
Deep Power-Down Current
CS#=VCC, VIN=VCC or VSS
1
5
μA
ICC3
Operating Current (Read)
CLK=0.1VCC/0.9VCC at 80MHz,
Q=Open(*1 I/O, *2 Output)
13
18
mA
ICC4
Operating Current (PP)
CS#=VCC
10
mA
ICC5
ICC6
Operating Current (WRSR) CS#=VCC
Operating Current (SE)
CS#=VCC
10
10
mA
mA
ICC7
VIL
Operating Current (BE)
Input Low Voltage
-0.5
10
0.2VCC
mA
V
VIH
Input High Voltage
0.7VCC
VCC+0.4
V
VOL
VOH
Output Low Voltage
Output High Voltage
0.4
V
V
ILI
Parameter
Test Condition
Min.
CS#=VCC
LOL=1.6mA
LOH=-100μA
28 - 23
VCC-0.2
Typ.
Rev.1.0
GD25D10BxIGx Uniform sector dual and quad serial flash
http://www.elm-tech.com
8.8. AC Characteristics
Symbol
(T= -40°C~85°C, VCC=2.7~3.6V, CL=30pf)
Parameter
Min.
Typ.
Max.
Unit.
fC
Serial Clock Frequency For: Dual Output(3BH)
DC.
80
MHz
fR
DC.
4
80
tCLH
Serial Clock Frequency For: Read(03H)
Serial Clock High Time
MHz
ns
tCLL
Serial Clock Low Time
4
ns
0.2
0.2
V/ns
V/ns
tSLCH CS# Active Setup Time
5
ns
tCHSH CS# Active Hold Time
tSHCH CS# Not Active Setup Time
5
5
ns
ns
tCHSL CS# Not Active Hold Time
tSHSL CS# High Time (Read/Write)
5
20
ns
ns
tCLCH Serial Clock Rise Time (Slew Rate)
tCHCL Serial Clock Fall Time (Slew Rate)
tSHQZ Output Disable Time
6
ns
tCLQX Output Hold Time
tDVCH Data In Setup Time
0
2
ns
ns
tCHDX Data In Hold Time
tCLQV Clock Low To Output Valid
2
ns
ns
tWHSL Write Protect Setup Time Before CS# Low
20
ns
tSHWL Write Protect Hold Time After CS# High
tDP CS# High To Deep Power-Down Mode
tRES1 CS# High To Standby Mode Without Electronic Signature Read
100
0.1
0.1
ns
μs
μs
μs
ms
ms
6
tRES2 CS# High To Standby Mode With Electronic Signature Read
tW
Write Status Register Cycle Time
tPP Page Programming Time
2
0.7
0.1
15
4.0
tFPP
tSE
Fast Page Programming Time
Sector Erase Time
0.5
40
4.0
200
ms
ms
tBE1
tBE2
tCE
Block Erase Time(32K Bytes)
Block Erase Time(64K Bytes)
Chip Erase Time(GD25D10B)
0.2
0.4
0.8
0.6
1.0
2.0
s
s
s
28 - 24
Rev.1.0
GD25D10BxIGx Uniform sector dual and quad serial flash
http://www.elm-tech.com
Figure 20. Serial Input Timing
Figure 21. Output Timing
28 - 25
Rev.1.0
GD25D10BxIGx Uniform sector dual and quad serial flash
http://www.elm-tech.com
9. ORDERING INFORMATION
GD 25 D 10 B x I G x
Packing Type
Y: Tray
R: Tape & Reel
Green Code
G: Pb Free & Halogen Free Green Package
Temperature Range
I: Industrial(-40°C to +85°C)
Package Type
T: SOP8 150mil
U: USON8 (3×2mm)
Generation
B: Version
Density
10: 1Mb
Series
D: 3V, 4KB Uniform Sector
Product Family
25: SPI Interface Flash
28 - 26
Rev.1.0
GD25D10BxIGx Uniform sector dual and quad serial flash
http://www.elm-tech.com
10. PACKAGE INFORMATION
10.1 Package SOP8 150MIL
8
θ
5
E1
E
L
1
4
L1
C
D
A2
Gauge plane
A1
b
e
A
Seating plane
0.10
Detail "A"
Dimensions
Symbol
Unit
E1
e
L
L1
θ
ɑ
ß
5.80 3.80
-
0.40
0.85
0°
6°
11°
4.90 6.00 3.90 1.27
1.06
1.75 0.25 1.55 0.51 0.25 5.03 6.20 4.00
0.90 1.27
- 0.002 0.053 0.012 0.006 0.188 - 0.149 - 0.016 0.033
8°
0°
7°
8°
6°
12°
13°
11°
Nom
- 0.016 - 0.193 0.236 0.154 0.050 0 0.042
Max 0.069 0.010 0.061 0.020 0.010 0.198 - 0.158 - 0.035 0.050
Note: Both package length and width do not include mold flash.
8°
7°
8°
12°
13°
Min
mm
Nom
Max
Min
A
A1
A2
b
-
0.05
1.35 0.31
c
D
0.15
4.77
E
Inch
28 - 27
Rev.1.0
GD25D10BxIGx Uniform sector dual and quad serial flash
http://www.elm-tech.com
10.2 Package USON8
10.2.(3x2mm)
Package USON8 (3*2mm)
D
A2
y
E
A
Top View
L
A1
Side View
D1
b
1
E1
e
Bottom View
Dimensions
Dimensions
Symbol
Unit
Symbol
Unit
A
A1
D
D1
b 0.13
D0.18
2.90
D1
0.15
E
1.90E1 1.50
2.00
1.60
0.18
0.30
3.10
0.30
2.10
1.70
0.006
0.010
0.118
Min
A1
0.50A2
0.50
0.55
0.60
mm
Min
Nom
Max
Inch
Max
Min
Nom
0.60 Max
0.05 0.024
0.18 0.0020.300.007 3.10
2.10
0.012 0.30
0.122
0.012
0.020
0.005
0.007
0.006mold0.075
Note:Both package
length and
width 0.114
do not include
flash.
0.022
0.006 0.010 0.118 0.008 0.079
Inch
Nom
Min
-
Nom
0.55
0.13
0.020
0.15
0.022
0.15
0.05
E1
b
A
mm
E
A2
0.25
3.00
0.18
2.90
0.15
0.005
0.007
0.114
0.25
3.00
0.20
Max
0.024 0.002 0.007 0.012 0.122 0.012
Note: Both package length and width do not include mold flash.
28 - 28
0.20
1.90
0.006
2.00
0.008
0.083
1.50
0.075
1.60
0.079
e
e
0.50
0.059
0.50
0.063
0.059
0.063
0.020
0.067
-
L
y0.00
0.30
L
0.35
0.05
0.020
1.70 0.067
0.083
y
0.45
0.00
0.30
0.000
0.012
0.35
0.014
0.05
0.002 0.45
0.018
0.000 0.012
0.014
0.002
0.018
Rev.1.0