FM25M64A - FIDELIX

FM25M64A
1.8V 64M-BIT
Serial Flash Memory with 4KB Sectors, Dual and Quad I/O SPI & QPI
Rev.03 (August.30.2011)
1
Documents title
64M bit Serial Flash Memory with 4KB Sectors, Dual and Quad I/O SPI &QPI
Revision History
Revision
No.
0.0
0.1
0.2
0.3
History
Initial Draft
WEL clear condition changed
Add Read SFDP(5Ah) parameter
Add VSOP
Modified some descriptions
Add Enhance Page Program(36h)
Add RESET pad
Revised ICC2, TCLH, Chip Erase time
Delete ALL FFh instruction
Revised WSON package dimension
Draft date
Remark
Feb.10.2011
preliminary
Apr.12.2011
preliminary
June.02.2011
preliminary
Aug.30.2011
Final
Rev.03 (August.30.2011)
2
Table of Contents
1.
FEATURES;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;.......6
2.
GENERAL DESCRIPTION;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;..6
3.
4.
5.
PIN / PAD CONFIGURATION;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;.7
3.1
8-Pin SOIC 208-MIL / VSOP 208-MIL;;;;;;;;;;;;;;;;;;;;..;7
3.2
8-Pad WSON 6X5-MM;;;;;;;;;;;;;;;;;;;;;;;;;;;;7
3.3
8-Pin PDIP 300-MIL;;;;;;;;;;;;;;;;;;;;;;;;;;;;;.7
3.4
16-Pin SOIC 300-MIL;;;;;;;;;;;;;;;;;;;;;;;;;;;;..8
PIN / PAD DESCRIPTION;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;...9
4.1
SOIC 208-MIL, VSOP 208-MIL, WSON 6X5-MM, PDIP 300-MIL;;;;;;;;;;9
4.2
SOIC 300-MIL;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;..9
4.3
Package Type;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;...9
SIGNAL DESCRIPTION;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;....10
5.1
Chip Select (/CS);;;;;;;;;;;;;;;;;;;;;;;;;;;;;...10
5.2
Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3);;;;;;;.....10
5.3
Write Protect (/WP);;;;;;;;;;;;;;;;;;;;;;;;;;;;;10
5.4
HOLD (/HOLD);;;;;;;;;;;;;;;;;;;;;;;;;;;;;;...10
5.5
Serial Clock (CLK);;;;;;;;;;;;;;;;;;;;;;;;;;;;;.10
5.6
RESET (/RST);;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;10
6.
BLOCK DIAGRAM;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;.;.11
7.
FUNCTIONAL DESCRIPTION;;;;;;;;;;;;;;;;;;;;;;;;;;;;;.12
8.
7.1
Standard SPI Instructions;;;;;;;;;;;;;;;;;;;;;;;;;;.12
7.2
Dual SPI Instructions;;;;;;;;;;;;;;;;;;;;;;;;;;;;.12
7.3
Quad SPI Instructions;;;;;;;;;;;;;;;;;;;;;;;;;;;...12
7.4
QPI Function;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;..13
7.5
Hold Function;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;.13
WRITE PROTECTION;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;...14
8.1
9.
Write protect Features;;;;;;;;;;;;;;;;;;;;;;;;;;;..14
STATUS REGISTER;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;..15
9.1
BUSY;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;...16
9.2
Write Enable Latch (WEL);;;;;;;;;;;;;;;;;;;;;;;;;;16
9.3
Block Protect Bits (BP2, BP1, BP0);;;;;;;;;;;;;;;;;;;;;;16
9.4
Top/Bottom Block protect (TB);;;;;;;;;;;;;;;;;;;;;;;;.16
9.5
Sector/Block Protect (SEC);;;;;;;;;;;;;;;;;;;;;;;;;..16
9.6
Status Register protect (SRP1, SRP0);;;;;;;;;;;;;;;;;;;;..17
9.7
Quad Enable (QE);;;;;;;;;;;;;;;;;;;;;;;;;;;;;.17
9.8
Complement Protect (CMP);;;;;;;;;;;;;;;;;;;;;;;;;.17
9.9
Erase/Program Suspend Status (SUS);;;;;;;;;;;;;;;;;;;.....17
9.10
Status Register Memory Protection (CMP = 0);;;;;;;;;;;;;;;;;.18
9.11
Status Register Memory Protection (CMP = 1);;;;;;;;;;;;;;;;;.19
10. INSTRUCTIONS;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;.20
10.1
Manufacturer and Device Identification;;;;;;;;;;;;;;;;;;;.....20
10.2
Instruction Set Table 1(SPI Instruction)..;;;;;;;;;;;;;;;;;;;;21
10.3
Instruction Set Table 2 (Dual SPI Instruction);;;;;;;;;;;;;;;;.......22
10.4
Instruction Set Table 3 (Quad SPI Instruction);;;;;;;;;;;;;;;;;..22
Rev.03 (August.30.2011)
3
10.5
Instruction Set Table 4 (QPI Instruction);;;;;;;;;;;;;;;;;;;;23
10.6
Write Enable (06h);;;;;;;;;;;;;;;;;;;;;;;;;;;;;.25
10.7
Write Enable for Volatile Status Register (50h);;;;;;;;;;;;;;;;....25
10.8
Write Disable (04h);;;;;;;;;;;;;;;;;;;;;;;;;;;;;26
10.9
Read Status Register-1 (05h) and Read Status Register-2 (35h);;;;;;;;;.27
10.10
Write Status Register (01h);;;;;;;;;;;;;;;;;;;;;;;;;..28
10.11
Write Status Register-2 (31h);;;;;;;;;;;;;;;;;;;;;;;;..29
10.12
Read Data (03h);;;;;;;;;;;;;;;;;;;;;;;;;;;;;;30
10.13
Fast Read (0Bh);;;;;;;;;;;;;;;;;;;;;;;;;;;;;;.30
10.14
Fast Read Dual Output (3Bh);;;;;;;;;;;;;;;;;;;;;;;;..32
10.15
Fast Read Quad Output (6Bh);;;;;;;;;;;;;;;;;;;;;;;;.33
10.16
Fast Read Dual I/O (BBh);;;;;;;;;;;;;;;;;;;;;;;;;;34
10.17
Fast Read Quad I/O (EBh);;;;;;;;;;;;;;;;;;;;;;;;;...36
10.18
Page Program (02h);;;;;;;;;;;;;;;;;;;;;;;;;;;;..39
10.19
Quad Data Input Page Program (32h)...........................................................................41
10.20
Quad Page Program (33h);;;;;;;;;;;;;;;;;;;;;;;;;...42
10.21
Enhance Page Program (EPP);;;;;;;;;;;;;;;;;;;;;;;;44
10.22
Set Enhance Page Program Enable (36h);;;;;;;;;;;;;;;;;;;45
10.23
Sector Erase (20h).........................................................................................................46
10.24
32KB Block Erase (52h);;;;;;;;;;;;;;;;;;;;;;;;;;...47
10.25
64KB Block Erase (D8h);;;;;;;;;;;;;;;;;;;;;;;;;;..48
10.26
Chip Erase (C7h / 60h);;;;;;;;;;;;;;;;;;;;;;;;;;;.49
10.27
Erase / Program Suspend (75h);;;;;;;;;;;;;;;;;;;;;;.....50
10.28
Erase / Program Resume (7Ah);;;;;;;;;;;;;;;;;;;;;;;..52
10.29
Deep Power-down (B9h);;;;;;;;;;;;;;;;;;;;;;;;;;..53
10.30
Release Deep Power-down / Device ID (ABh);;;;;;;;;;;;;;;;.....54
10.31
Read Manufacturer/ Device ID (90h);;;;;;;;;;;;;;;;;;;;;..56
10.32
Read Manufacturer / Device ID Dual I/O (92h);;;;;;;;;;;;;;;;;.57
10.33
Read Manufacturer / Device ID Quad I/O (94h);;;;;;;;;;;;;;;;...58
10.34
JEDEC ID (9Fh);;;;;;;;;;;;;;;;;;;;;;;;;;;;;;.59
10.35
Enable QPI (38h);;;;;;;;;;;;;;;;;;;;;;;;;;;;;...60
10.36
Disable QPI (FFh);;;;;;;;;;;;..;;;;;;;;..;;;;................60
10.37
Word Read Quad I/O (E7h);;;;;;;;;;;;;;;;;;;;;;;;;.61
10.38
Set Burst with Wrap (77h);;;;;;;;;;;;;;;;;;;;;;;;;;63
10.39
Burst Read with Wrap (0Ch);;;;;;;;;;;;;;;;;;;;;;;;;64
10.40
Set Read Parameters (C0h);;;;;;;;;;;;;;;;;;;;;;;;;65
10.41
Enable Reset (66h) and Reset (99h);;;;;;;;;;;;;;;;;;;;;..66
10.42
Read Serial Flash Discovery Parameter (5Ah);;;;;;;;;;;;;;;;;.67
10.43
Enter Secured OTP (B1h);;;;;;;;;;;;;;;;;;;;;;;;;;70
10.44
Exit Secured OTP (C1h);;;;;;;;;;;;;;;;;;;;;;;;;;...70
10.45
Read Security Register (2Bh);;;;;;;;;;;;;;;;;;;;;;;;..71
10.46
Write Security Register (2Fh);;;;;;;;;;;;;;;;;;;;;;;;..72
11. 4K-bit Secured OTP;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;...73
12. ELECTRICAL CHARACTERISTICS;;;;;;;;;;;;;;;;;;;;;;;;;;;74
12.1
Absolute Maximum Ratings;.;;;;;;;;;;;;;;;;;;;;;;;....74
Rev.03 (August.30.2011)
4
12.2
Operating Ranges;;;;;;;;;;;;;;;;;;;;;;;;;;;;;.74
12.3
Endurance and Data Retention;;;;;;;;;;;;;;;;;;;;;;;...74
12.4
Power-up Timing and Write Inhibit Threshold;;;;;;;;;;;;;;;;;...75
12.5
DC Electrical Characteristics;;;;;;;;;;;;;;;;;;;;;;;.......76
12.6
AC Measurement Conditions;;;;;;;;;;;;;;;;;;;;;;;;...77
12.7
AC Electrical Characteristics;;;;;;;;;;;;;;;;;;;;;;;;;78
12.8
AC Electrical Characteristics (Cont’d);;;;;;;;...;;;;;;;;;;;;.79
12.9
Input Timing ;;;;;;;.;;;;;;;;;;;;;;;;;;;;;;;;..80
12.10
Output Timing ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;80
12.11
Hold Timing;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;.80
12.12
RST Timing;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;.80
13. PACKAGE SPECIFICATION;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;81
13.1
8-Pin SOIC 208-mil;;;;;;;;;;;;;;;;;;;;;;;;;;;;;81
13.2
8-Pin VSOP 208-mil;;;;;;;;;;;;;;;;;;;;;;;;;;;;..82
13.3
8-Pin PDIP 300-mil;;;;;;;;;;;;;;;;;;;;;;;;;;;;;83
13.4
8-contact 6x5 WSON;;;;;;;;;;;;;..;;;;;;;;;;;;;;..84
13.5
8-contact 6x5 WSON(Cont’d);;.;;.;;;;;..;;;;;;;;;;;;;;..85
13.6
16-Pin SOIC 300-mil;;;;;;;;;;;;;;;;;;;;;;;;;;;;.86
14. ORDERING INFORMATION;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;.87
Rev.03 (August.30.2011)
5
1. FEATURES
■ SPI Flash Memory
－64M-bit / 8M–byte Serial Flash
－256-bytes per programmable page
－4K-bit secured OTP
■ Low Power Consumption
－Single 1.65 to 1.95V supply
－5mA active current
－<5µA Deep Power-down (typ.)
■ Standard, Dual or Quad SPI and QPI
－Standard SPI: CLK, /CS, DI, DO, /WP, /Hold
－Dual SPI: CLK, /CS, IO0, IO 1, /WP, /Hold
－Quad SPI: CLK, /CS, IO0, IO1, IO2, IO3
－QPI: CLK, /CS, IO0, IO1, IO2, IO3
■ wide Temperature Range
－-40℃ to +85℃ operating range
■ High Performance
－104MHz clock operation
－208MHz equivalent Dual SPI
－416MHz equivalent Quad SPI
－50MB/S continuous data transfer rate
－31MB/S random access (32-byte fetch)
－Comparable to X16 Parallel Flash
■ Flexible Architecture
－Uniform Sector Erase (4K-byte)
－Block Erase (32K and 64K-bytes)
－Erase/Program Suspend & Resume
■ Endurance
－100K program/ erase cycles
■ Advanced Security Features
－Software and Hardware Write-protect
－Top or Bottom, Sector or Block selection
－Lock-Down and OTP protection
－Discoverable Parameters(SFDP) Register
■ Package Options
－8-pin SOIC 208-mil
－8-pad WSON 6x5-mm
－16-pin SOIC 300-mil
－8-pin PDIP 300-mil
－8-pin VSOP 208-mil
■ Package Material
－Fidelix all product Green package
Lead-free & Halogen-free
RoHS Compliant
2. GENERAL DESCRIPTION
The FM25M64A supports the standard Serial Peripheral Interface (SPI), and Quad Peripheral
Interface (QPI): Serial Clock, Chip Select, Serial Data I/O0(DI), I/O1(DO), I/O2(/WP), and
I/O3(/HOLD).
SPI clock frequencies of up to 104MHz are supported allowing equivalent clock rates of 208MHz
for Dual Output and 416MHz for Quad Output when using the QPI and Fast Read Dual/Quad I/O
instructions.
The FM25M64A array is organized into 32.768 programmable pages of 256-bytes each. Up to 256
bytes can be programmed at a time using the Page Program instructions. Pages can be erased
Sector, 32KB Block, 64KB Block or the entire chip.
The devices operate on a single 1.65V to 1.95V power supply with current consumption as low as
5mA active and 3µA for Deep Power-down. All devices offered in space-saving packages. The
device supports JEDEC standard manufacturer and device identification with a 4K-bit Secured
OTP.
Rev.03 (August.30.2011)
6
3. PIN / PAD CONFIGURATION
3.1 8-Pin SOIC 208-MIL / VSOP 208-MIL
/ CS
1
8
VCC
DO(IO 1)
2
7
/HOLD(IO 3)
/ WP(IO 2)
3
6
CLK
GND
4
5
DI(IO0)
Figure 1a. Pin Assignments, 8-pin SOIC 208-mil / VSOP 208-mil
3.2 8-Pad WSON 6X5-MM
/CS
1
8
VCC
DO(IO1)
2
7
/HOLD(IO3 )
3
6
CLK
4
5
DI(IO0)
/WP(IO2)
GND
Figure 1b. Pad Assignments, 8-pad WSON
3.3 8-Pin PDIP 300-MIL
/CS
DO(IO1)
/WP(IO2)
GND
VCC
/HOLD(IO3)
CLK
DI(IO0)
Figure 1c. Assignments, 8-pin PDIP 300-mil
Rev.03 (August.30.2011)
7
3.4 16-Pin SOIC 300-MIL
/HOLD(IO3 )
1
16
CLK
VCC
2
15
DI(IO0 )
N/C
3
14
N/C
N/C
4
13
N/C
N/C
5
12
N/C
N/C
6
11
N/C
/CS
7
10
GND
DO(IO1 )
8
9
/WP(IO2 )
Figure 1d. Pin Assignments, 16-pin SOIC 300-mil
Rev.03 (August.30.2011)
8
4. PIN / PAD DESCRIPTION
4.1 SOIC 208-MIL, VSOP 208-MIL, WSON 6X5-MM, PDIP 300-MIL
PIN NO.
PIN NAME
I/O
FUCTION
1
/CS
I
Chip Select Input
2
DO(IO1)
I/O
Data Output (Data Input Output 1)*¹
3
/WP(IO2)
I/O
Write Protect Input (Data Input output)*²
4
GND
5
DI(IO0)
I/O
Data Input (Data Input Output 0)*¹
6
CLK
I
Serial Clock Input
7
/HOLD(IO3)
I/O
Hold Input (Data Input output 3)*²
8
VCC
Ground
Power Supply
*1 IO0 and IO1 are used for Dual and Quad instructions
*2 IO0－IO3 are used for Quad instructions
4.2 SOIC 300-MIL
PAD NO.
PAD NAME
I/O
1
/HOLD(IO3)
I/O
2
VCC
Power Supply
3
N/C
No Connect
4
N/C
No Connect
5
N/C
No Connect
6
N/C
No Connect
7
/CS
I
8
DO(IO1)
I/O
I/O
FUCTION
Hold Input(Data Input Output 3)* ²
Chip Select Input
Data output (Data Input Output 1)* ¹
9
/WP(IO2)
10
GND
Ground
Write Protection Input (Data Input Output 2)* ²
11
N/C
No Connect
12
N/C
No Connect
13
N/C
No Connect
14
N/C
No Connect
15
DI(IO0)
I/O
16
CLK
I
Data Input (Data Input Output 0)* ¹
Serial Clock Input
*1 IO0 and IO1 are used for Dual and Quad instructions
*2 IO0_IO3 are used for Quad instructions
4.3 Package Type
FM25M64A is offered in an 8-pin plastic 208-mil width VSOP, 8-pin plastic 208-mil width SOIC,
6x5-mm WSON, 8-pin PDIP and 16-pin plastic 300-mil width SOIC as shown in figure 1a, 1b,1c
and 1d respectively. Package diagrams and dimensions are illustrated at the end of this datasheet.
Rev.03 (August.30.2011)
9
5. SIGNAL DESCRIPTION
5.1 Chip Select (/CS)
When this input signal is high, the device is deselected and serial data output pins are at high
impedance. Unless an internal program, erase or write status register cycle is in progress, the
device will be in the standby power mode (this is not the deep power-down mode). Driving Chip
Select (/CS) low enables the device, placing it in the active power mode. After power-up, a falling
edge on Chip Select (/CS) is required prior to the start of any instruction.
5.2 Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3)
The FM25M64A supports standard SPI, Dual SPI, Quad SPI and QPI operation. Standard SPI
instructions use the serial DI (input) pin to write instructions, addresses or data to the device on the
rising edge of the Serial Clock (CLK) input pin. Standard SPI also uses the serial DO (output) to
read data or status from the device on the falling edge of CLK.
Dual, Quad SPI and QPI instructions use the serial IO pins to write instructions, addresses or data
to the device on the rising edge of CLK and read data or status from the device on the falling edge
of CLK. Quad SPI instructions require the non-volatile Quad Enable bit (QE) in Status Register-2 to
be set. When QE=1 the /WP pin becomes IO2 and /HOLD pin becomes IO3.
5.3 Write Protect (/WP)
The Write Protect (/WP) pin can be used to protect the Status Register against data modification.
Used in company with the Status Register’s Block Protect (SEC, TB, BP2, BP1 and BP0) bits and
Status Register Protect (SRP) bits, a portion or the entire memory array can be hardware protected.
The /WP pin is active low. When the QE bit of Status Register-2 is set for Quad I/O, the /WP pin
(Hardware Write Protect) function is not available since this pin is used for IO2. See figure 1a, 1b,
1c and 1d for the pin configuration of Quad I/O and QPI operation.
5.4 HOLD (/HOLD)
The /HOLD pin is used to pause any serial communications with the device without deselecting the
device. When /HOLD goes low, while /CS is low, the DO pin will be at high impedance and signals
on the DI and CLK pins will be ignored (don’t care). When /HOLD goes high, device operation can
resume. The /HOLD function can be useful when multiple devices are sharing the same SPI
signals. The /HOLD pin is active low. When the QE bit of Status Register-2 is set Quad I/O, the
/HOLD pin function is not available since this pin used for IO3. See figure 1a, 1b, 1c and 1d for the
pin configuration of Quad I/O and operation.
5.5 Serial Clock (CLK)
This input signal provides the timing for the serial interface. Instructions, addresses, or data
present at serial data input are latched on the rising edge of Serial Clock (CLK). Data are shifted
out on the falling edge of the Serial Clock (CLK).
5.6 RESET (/RST)
The /RST pin provides a hardware methods of the device to standby mode. When the system
drives the /RST pin to VIL for at least a period tRP, the device immediately terminates any
operation in progress and reset internal state machine to standby mode after a specified
time(tRST). This pin may be tied to the reset circuitry. This pin is available at some MCP and wafer
level only.
Rev.03 (August.30.2011)
10
6. BLOCK DIAGRAM
Block Segmentation
xxFF00h
7FFF00h
●
7F0000h
xxFFFFh
7FFFFFh
Block 127
●
(64KB)
7F00FFh
Sector 15
(4KB)
xxF000h
xxF0FFh
xxEF00h
xxEFFFh
Sector 14
(4KB)
xxE000h
xxE0FFh
xxDF00h
xxDFFFh
Sector 13
(4KB)
xxD000h
xxD0FFh
Write Protect Logic and Ro w Decode
●
●
●
xx2FFFh
xx2F00h
Sector 2
(4KB)
xx20FFh
xx2000h
xx1FFFh
xx1F00h
Sector 1
(4KB)
xx10FFh
xx1000h
xx0FFFh
xx0F00h
Sector 0
(4KB)
xx00FFh
xx0000h
40FF00h
●
400000h
Block 64
(64KB)
40FFFFh
●
4000FFh
3FFF00h
●
3F0000h
Block 63
(64KB)
3FFFFFh
●
3F00FFh
●
●
●
/WP (IO2)
Write
Control
Logic
10FF00h
●
100000h
Block 16
(64KB)
10FFFFh
●
1000FFh
0FFF00h
●
0F0000h
Block 15
(64KB)
0FFFFFh
●
0F00FFh
Status
Register
●
●
●
High
Voltage
Generators
/HOLD (IO3)
CLK
/CS
DI (IO0)
SPI Command
And Control
Logic
Page Address
Latch / Counter
00FF00h
●
000000h
Beginning
Page
Address
Block 0
(64KB)
00FFFFh
●
0000FFh
Ending
Page
Address
Column Decode
And 256Byte Page buffer
DO (IO1)
Data
/RST
Byte Address Latch /
Counter
Figure 2. Block Diagram of FM25M64A
Rev.03 (August.30.2011)
11
7. FUNCTIONAL DESCRIPTION
Figure 3. Operation Diagram of FM25M64A
7.1 Standard SPI Instructions
The FM25M64A features a serial peripheral interface on four signals: Serial Clock (CLK). Chip
Select (/CS), Serial Data Input (DI) and Serial Data Output (DO). Standard SPI instructions use the
DI input pin to serially write instructions, addresses or data to the device on the rising edge of CLK.
The DO output pin is used to read data or status from the device on the falling edge of CLK.
SPI bus operation Modes 0 (0, 0) and 3 (1, 1) are supported. The primary difference between
Mode 0 and Mode 3 concerns the normal state of the CLK signal when the SPI bus master is in
standby and data is not being transferred to the Serial Flash. For Mode 0 the CLK signal is
normally low on the falling and rising edges of /CS. For Mode 3 the CLK signal is normally high on
the falling and rising edges of /CS.
7.2 Dual SPI Instructions
The FM25M64A supports Dual SPI operation. This instruction allows data to be transferred to or
from the device at two times the rate of the standard SPI. The Dual Read instruction is ideal for
quickly downloading code to RAM upon power-up (code-shadowing) or for executing non-speedcritical code directly from the SPI bus (XIP). When using Dual SPI instructions the DI and DO pins
become bidirectional I/0 pins; IO0 and IO1.
7.3 Quad SPI Instructions
The FM25M64A supports Quad SPI operation. This instruction allows data to be transferred to or
from the device at four times the rate of the standard SPI. The Quad Read instruction offers a
significant improvement in continuous and random access transfer rates allowing fast codeshadowing to RAM or execution directly from the SPI bus (XIP). When using Quad SPI instruction
the DI and DO pins become bidirectional IO0 and IO1, and the /WP and /HOLD pins become IO2
and IO3 respectively. Quad SPI instructions require the non-volatile Quad Enable bit (QE) in Status
Register-2 to be set.
Rev.03 (August.30.2011)
12
7.4 QPI Function
The FM25M64A supports Quad Peripheral Interface (QPI) operation when the device is switched
from Standard/ Dual/ Quad SPI mode to QPI mode using the “Enable QPI (38h)” instruction. To
enable QPI mode, the non-volatile Quad Enable bit (QE) in Status Register-2 is required to be set.
When using QPI instructions, the DI and DO pins become bidirectional IO0 and IO1, and the /WP
and /HOLD pins become IO2 and IO3 respectively. See Figure 3 for the device operation modes.
The typical SPI protocol requires that the byte-long instruction code being shifted into the device
only via DI pin in eight serial clocks. The QPI mode utilizes all four IO pins to input the instruction
code, thus only two serial clocks are required. This can significantly reduce the SPI instruction
overhead and improve system performance in an XIP environment. Standard/ Dual/ Quad SPI
mode and QPI mode are exclusive. Only one mode can be active at any given time, “Enable QPI”
and “Disable QPI/ Disable QPI 2” instructions are used to switch between these two modes. Upon
power-up or after software reset using “Reset (99h) instruction, the default state of the device is
Standard/ Dual/ Quad SPI mode.
7.5 Hold Function
The /HOLD pin is used to pause a serial sequence of the SPI flash memory without resetting the
clocking sequence. To enable the /HOLD mode, the /CS must be in low state. The /HOLD mode
effects on with the falling edge of the /HOLD signal with CLK being low. The HOLD mode ends on
the rising edge of /HOLD signal with CLK being low.
In other words, /HOLD mode can’t be entered unless CLK is low at the falling edge of the /HOLD
signal. And /HOLD mode can’t be exited unless CLK is low at the rising edge of the /HOLD signal.
See Figure.4 for HOLD condition waveform.
If /CS is driven high during a HOLD condition, it resets the internal logic of the device. As long as
/HOLD signal is low, the memory remains in the HOLD condition. To re-work communication with
the device, /HOLD must go high, and /CS must go low. See 12.11 for HOLD timing.
Figure 4. Hold condition waveform (only available Standard/ Dual SPI mode)
Rev.03 (August.30.2011)
13
8. WRITE PROTECTION
To protect inadvertent writes by the possible noise, several means of protection are applied to the
Flash memory.
8.1 Write protect Features
While Power-on reset, all operations are disabled and no instruction is recognized.
An internal time delay of tPUW can protect the data against inadvertent changes while the
power supply is outside the operating specification. This includes the Write Enable, Page
program, Sector Erase, Block Erase, Chip Erase, Write Security Register and the Write Status
Register instructions.
For data changes, Write Enable instruction must be issued to set the Write Enable Latch
(WEL) bit to “0”. Power-up, Completion of Write Disable, Write Status Register, Page program,
Sector Erase, Block Erase and Chip Erase are subjected to this condition.
Using setting the Status Register protect (SRP) and Block protect (SEC, TB, BP2, BP1, and
BP0) bits a portion of memory can be configured as reading only called software protection.
Write Protect (/WP) pin can control to change the Status Register under hardware control.
The Deep Power Down mode provides extra software protection from unexpected data
changes as all instructions are ignored under this status except for Release Deep Powerdown instruction.
One time program(OTP) mode provide protection mode from program/erase operation
Rev.03 (August.30.2011)
14
9. STATUS REGISTER
The Read Status Register instruction can be used to provide status on the availability of the Flash
memory array, if the device is write enabled or disabled the state of write protection and the Quad
SPI setting. The Write Status Register instruction can be used to configure the devices writes
protection features and Quad SPI setting. Write access to the Status Register is controlled by in
some cases of the /WP pin.
S7
S6
S5
S4
S3
S2
S1
S0
SRP0
SEC
TB
BP2
BP1
BP0
WEL
BUSY
Status
Register
Protect 0
(NonVolatile)
Sector
Protect
(NonVolatile)
Top/Bott
om Write
Protect
(NonVolatile)
Block
Protect
(NonVolatile)
Block
Protect
(NonVolatile)
Block
Protect
(NonVolatile)
Write
Enable
Latch
Erase or
Write in
Progress
Figure 5a. Status Register-1
S15
S14
S13
S12
S11
S10
S9
S8
SUS
CMP
(R)
(R)
(R)
(R)
QE
SRP1
Suspend
Status
Complement
Protect
(NonVolatile)
Reserved
Quad
Enable
(NonVolatile)
Status
Register
Protect 1
(NonVolatile)
Reserved
Reserved
Reserved
Figure 5b. Status Register-2
Rev.03 (August.30.2011)
15
9.1 BUSY
BUSY is a read only bit in the status register (S0) that is set to a 1 state when the device is
executing a Page Program, Erase, Write Status Register or Write Security Register instruction.
During this time the device will ignore further instruction except for the Read Status Register and
Erase / Program Suspend instruction (see tW, tPP, tSE, tBE1, tBE2 and tCE in AC Characteristics).
When the Program, Erase, Write Status Register or Write Security Register instruction has
completed, the BUSY bit will be cleared to a 0 state indicating the device is ready for further
instructions.
9.2 Write Enable Latch (WEL)
Write Enable Latch (WEL) is a read only bit in the status register (S1) that is set to a 1 after
executing a Write Enable instruction. The WEL status bit is cleared to a 0 when device is write
disabled. A write disable state occurs upon power-up or after any of the following instructions:
Write Disable, Page Program, Erase and Write Status Register.
9.3 Block Protect Bits (BP2, BP1, BP0)
The Block Protect Bits (BP2, BP1, BP0) are non-volatile read/write bits in the status register (S4,
S3, and S2) that provide write protection control and status. Block protect bits can be set using the
Write Status Register Instruction (see tW in AC characteristics). All, none or a portion of the
memory array can be protected from Program and Erase instructions (see Status Register Memory
Protection table). The factory default setting for the Block Protection Bits is 0, none of the array
protected.
9.4 Top/Bottom Block protect (TB)
The Top/Bottom bit (TB) is non-volatile bits in the status register (S5) that controls if the Block
Protect Bits (BP2, BP1, BP0) protect from the Top (TB=0) or the Bottom (TB=1) of the array as
shown in the Status Register Memory Protection table. The factory default setting is TB=0. The TB
bit can be set with the Write Status Register Instruction depending on the state of the SRP0, SRP1
and WEL bits.
9.5 Sector/Block Protect (SEC)
The Sector protect bit (SEC) is non-volatile bits in the status register (S6) that controls if the Block
Protect Bits (BP2, BP1, BP0) protect 4KB Sectors (SEC=1)or 64KB Blocks (SEC=0) in the Top
(TB=0) or the Bottom (TB=1) of the array as shown in the Status Register Memory protection table.
The default setting is SEC=0.
Rev.03 (August.30.2011)
16
9.6 Status Register protect (SRP1, SRP0)
The Status Register Protect bits (SRP1 and SRP0) are non-volatile read/write bits in the status
register (S8 and S7). The SRP bits control the method of write protection: software protection,
hardware protection, power supply lock-down or one time programmable (OTP) protection.
SRP1
SRP0
/WP
Status
Register
Description
0
0
X
Software
Protection
/WP pin no control. The register can be written to
After a Write Enable instruction, WEL=1. [Factory Default]
0
1
0
Hardware
Protected
When /WP pin is low the Status Register locked and can not
Be written to.
0
1
1
Hardware
Unprotected
When /WP pin is high the Status register is unlocked and
can be written to after a Write Enable instruction, WEL=1
1
0
X
Power Supply
Lock-Down
Status Register is protected and cannot be written to again
(1)
until the next power-down, power-up cycle
1
1
X
One Time
Program
Status Register is permanently protected and cannot be
written to.
Note:
1. When SRP1, SRP0=(1,0), a power-down, power-up cycle will change SRP1, SRP0 to(0,0) state.
9.7 Quad Enable (QE)
The Quad Enable (QE) bit is a non-volatile read/write bit in the status register (S9) that allows
Quad operation. When the QE bit is set to a 0 state (factory default) the /WP pin and /Hold are
enabled. When the QE pin is set to a 1 the Quad IO2 and IO3 pins are enabled.
WARNING : The QE bit should never be set to a 1 during standard SPI or Dual SPI operation
if the /WP or /HOLD pins are tied directly to the power supply or ground.
9.8 Complement Protect (CMP)
The Complement Protect bit (CMP) is a non-volatile read/write bit in the status register (S14). It is
used in conjunction with SEC, TB, BP2, BP1 and BP0 bits to provide more flexibility for the array
protection. Once CMP is set to 1, previous array protection set by SEC, TB, BP2, BP1 and BP0 will
be reversed. For instance, when CMP=0, a top 4KB sector can be protected while the rest of the
array is not; when CMP=1, the top 4KB sector will become unprotected while the rest of the array
become read-only. Please refer to the Status Register Memory Protection table for details. The
default setting is CMP=0.
9.9 Erase/Program Suspend Status (SUS)
The Suspend Status bit (SUS) is a read only bit in the status register (S15) that is set to 1 after
executing an Erase/Program Suspend (75h) instruction. The SUS status bit is cleared to 0 by
Erase/Program Resume (7Ah) instruction as well as a power-down, power-up cycle.
Rev.03 (August.30.2011)
17
9.10 Status Register Memory Protection (CMP = 0)
STATUS REGISTER
MEMORY PROTECTION
SEC
TB
BP2
BP1
BP0
BLOCK(S)
ADDRESSES
DENSITY
PORTION
X
X
0
0
0
NONE
NONE
NONE
NONE
0
0
0
0
1
126 and 127
7E0000h-7FFFFFh
128KB
Upper 1/64
0
0
0
1
0
124 thru 127
7C0000h-7FFFFFh
256KB
Upper 1/32
0
0
0
1
1
120 thru 127
780000h-7FFFFFh
512KB
Upper 1/16
0
0
1
0
0
112 thru 127
700000h-7FFFFFh
1MB
Upper 1/8
0
0
1
0
1
96 thru 127
600000h-7FFFFFh
2MB
Upper 1/4
0
0
1
1
0
64 thru 127
400000h-7FFFFFh
4MB
Upper 1/2
0
1
0
0
1
0 and 1
000000h-01FFFFh
128KB
Lower 1/64
0
1
0
1
0
0 thru 3
000000h-03FFFFh
256KB
Lower 1/32
0
1
0
1
1
0 thru 7
000000h-07FFFFh
512KB
Lower 1/16
0
1
1
0
0
0 thru 15
000000h-0FFFFFh
1MB
Lower 1/8
0
1
1
0
1
0 thru 31
000000h-1FFFFFh
2MB
Lower 1/4
0
1
1
1
0
0 thru 63
000000h-3FFFFFh
4MB
Lower 1/2
X
X
1
1
1
0 thru 127
000000h-7FFFFFh
8MB
ALL
1
0
0
0
1
127
7FF000h-7FFFFFh
4KB
U – 1/2048
1
0
0
1
0
127
7FE000h-7FFFFFh
8KB
U – 1/1024
1
0
0
1
1
127
7FC000h-7FFFFFh
16KB
U – 1/512
1
0
1
0
X
127
7F8000h-7FFFFFh
32KB
U – 1/256
1
1
0
0
1
0
000000h-000FFFh
4KB
L – 1/2048
1
1
0
1
0
0
000000h-001FFFh
8KB
L – 1/1024
1
1
0
1
1
0
000000h-003FFFh
16KB
L – 1/512
1
1
1
0
X
0
000000h-007FFFh
32KB
L – 1/256
Note:
1. X = don’t care
2. L = Lower; U = Upper
3. If any Erase or Program instruction specifies a memory region that contains protected data
portion, this instruction will be ignored.
Rev.03 (August.30.2011)
18
9.11 Status Register Memory Protection (CMP = 1)
STATUS REGISTER
MEMORY PROTECTION
SEC
TB
BP2
BP1
BP0
BLOCK(S)
ADDRESSES
DENSITY
PORTION
X
X
0
0
0
0 thru 127
000000h - 7FFFFFh
8MB
ALL
0
0
0
0
1
0 thru 125
000000h – 7DFFFFh
8,064KB
Lower 63/64
0
0
0
1
0
0 and 121
000000h – 7BFFFFh
7,936KB
Lower 31/32
0
0
0
1
1
0 thru 119
000000h – 77FFFFh
7,680KB
Lower 15/16
0
0
1
0
0
0 thru 111
000000h – 6FFFFFh
7,168KB
Lower 7/8
0
0
1
0
1
0 thru 95
000000h – 5FFFFFh
6MB
Lower 3/4
0
0
1
1
0
0 thru 63
000000h – 3FFFFFh
4MB
Lower 1/2
0
1
0
0
1
2 thru 127
020000h - 7FFFFFh
8,064KB
Upper 63/64
0
1
0
1
0
4 and 127
040000h - 7FFFFFh
7,936KB
Upper 31/32
0
1
0
1
1
8 thru 127
080000h - 7FFFFFh
7,680KB
Upper 15/16
0
1
1
0
0
16 thru 127
100000h - 7FFFFFh
7,168KB
Upper 7/8
0
1
1
0
1
32 thru 127
200000h - 7FFFFFh
6MB
Upper 3/4
0
1
1
1
0
64 thru 127
400000h - 7FFFFFh
4MB
Upper 1/2
X
X
1
1
1
NONE
NONE
NONE
NONE
1
0
0
0
1
0 thru 127
000000h - 7FEFFFh
8,188KB
L – 2047/2048
1
0
0
1
0
0 thru 127
000000h - 7FDFFFh
8,184KB
L – 1023/1024
1
0
0
1
1
0 thru 127
000000h - 7FBFFFh
8,176KB
L – 511/512
1
0
1
0
X
0 thru 127
000000h - 7F7FFFh
8,160KB
L – 255/256
1
1
0
0
1
0 thru 127
001000h - 7FFFFFh
8,188KB
U – 2047/2048
1
1
0
1
0
0 thru 127
002000h - 7FFFFFh
8,184KB
U – 1023/1024
1
1
0
1
1
0 thru 127
004000h - 7FFFFFh
8,176KB
U – 511/512
1
1
1
0
X
0 thru 127
008000h - 7FFFFFh
8,160KB
U – 255/256
Note:
1. X = don’t care
2. L = Lower; U = Upper
3. If any Erase or Program instruction specifies a memory region that contains protected data
portion, this instruction will be ignored.
Rev.03 (August.30.2011)
19
10. INSTRUCTIONS
The SPI instruction set of the FM25M64A consists of thirty eight basic instructions and the QPI
instruction set of the FM25M64A consists of thirty one basic instructions that are fully controlled
through the SPI bus (see Instruction Set table). Instructions are initiated with the falling edge of
Chip Select (/CS). The first byte of data clocked into the input pins (DI or IO [3:0]) provides the
instruction code. Data on the DI input is sampled on the rising edge of clock with most significant
bit (MSB) first.
Instructions are completed with the rising edge of edge /CS. Clock relative timing diagrams for
each instruction are included in figures 6 through 44. All read instructions can be completed after
any clocked bit. However, all instructions that Write, Program or Erase must complete on a byte
(/CS driven high after a full 8-bit have been clocked) otherwise the instruction will be terminated.
This feature further protects the device from inadvertent writes. Additionally, while the memory is
being programmed or erased, or when the Status Register is being written, all instructions except
for Read Register will be ignored until the program or erase cycle has completed.
10.1 Manufacturer and Device Identification
ID code
Instruction
Manufacturer ID
Fidelix
F8h
90h, 92h, 94h, 9Fh
Device ID
FM25M64A
16h
90h, 92h, 94h, ABh
Memory Type ID
SPI / QPI
42h
9Fh
Capacity Type ID
64M
17h
9Fh
Rev.03 (August.30.2011)
20
10.2 Instruction Set Table 1 (SPI instruction)(1)
INSTRUCTION
NAME
(CLOCK NUMBER)
BYTE 1
BYTE 2
BYTE 3
BYTE 4
BYTE 5
BYTE 6
(0 – 7)
(8 - 15)
(16 - 23)
(24 - 31)
(32 - 39)
(40 - 47)
Write Enable
06h
Write Enable
For Volatile
Status Register
50h
Write Disable
04h
Read
Status Register-1
Read
Status Register-2
Write
Status Register-1
Write
Status Register-2
(2)
05h
(S7-S0)
35h
(S15-S8)(2)
01h
(S7-S0)
31h
(S15-S8)
Read Data
03h
A23-A16
A15-A8
A7-A0
(D7-D0)
Fast Read Data
0Bh
A23-A16
A15-A8
A7-A0
dummy
Page Program
02h
A23-A16
A15-A8
A7-A0
(D7-D0)
Enable QPI
38h
Sector Erase(4KB)
20h
A23-A16
A15-A8
A7-A0
Block Erase(32KB)
52h
A23-A16
A15-A8
A7-A0
Block Erase(64KB)
D8h
A23-A16
A15-A8
A7-A0
dummy
dummy
dummy
Chip Erase
Erase/Program
Suspend
Erase/Program
Resume
Deep Power-down
Release Deep power
(4)
down/ Device ID
Read Manufacturer/
Device ID(4)
(S15-S8)
(3)
60h/C7h
75h
7Ah
B9h
ABh
90h
dummy
dummy
00h or 01h
Read JEDEC ID
9Fh
(MID7-MID0)
Manufacturer
(D7-D0)
Memory Type
(D7-D0)
Capacity Type
Reset Enable
66h
Reset
99h
Enter Secured OTP
B1h
Exit Secured OTP
C1h
A15-A8
A7-A0
Read
Security Register
Write
Security Register
Read Serial Flash
Discovery Parameter
(D7-D0)
2Bh
(ID7(2)
ID0)
(MID7MID0)
(DID7-DID0)
(S7-S0)
2Fh
5Ah
A23-A16
dummy
(D7-D0)
Rev.03 (August.30.2011)
21
10.3 Instruction Set Table 2 (Dual SPI Instruction)
(CLOCK
NUMBER)
INSTRUCTION
NAME
(0 – 7)
(8 - 15)
(16 - 23)
(24 - 31)
(32 - 39)
Fast Read Dual Output
3Bh
A23-A16
A15-A7
A7-A0
dummy
Fast Read Dual I/O
BBh
A23-A8
Read Dual Manufacture/
(4)
Device ID
92h
0000h
(5)
A7-A0,
(5)
M7-M0
(00h, xxxx) or
(01h, xxxx)
(40 - 47)
(6)
(D7-D0)
(6)
(D7-D0, ;)
(MID7-MID0)
(6)
(DID7-DID0)
10.4 Instruction Set Table 3 (Quad SPI Instruction)
(CLOCK
NUMBER)
INSTRUCTION
NAME
(0 – 7)
(8 - 15)
(16 - 23)
(24 - 31)
(32 - 39)
Fast Read Quad Output
6Bh
A23-A16
A15-A8
A7-A0
dummy
Fast Read Quad I/O
EBh
A23-A0,
(7)
M7-M0
Quad Data Input
Page Program
32h
A23-A16
Quad Page Program
33h
A23-A0
(8)
(D7-D0, ;)
Read Quad
(4)
Manufacture/Device ID
94h
(00_0000h, xx)
or
(00_0001h, xx)
Word Read Quad I/O
E7h
Set Burst with Wrap
77h
A23-A0,
(7)
M7-M0
xxxxxx,
W6-W4(7)
(xxxx,
(9)
D7-D0,;)
A15-A8
(40 - 47)
(D7-D0)
(8)
(8)
(D7-D0, ;)
A7-A0
(D7-D0,
(3)
;)
(xxxx,
MID7-MID0)
(xxxx,
(9)
DID7-DID0)
(xx, D7-D0..)
(8)
(D7-D0)
Rev.03 (August.30.2011)
22
10.5 Instruction Set Table 4 (QPI instruction)
INSTRUCTION
NAME
BYTE 1
BYTE 2
BYTE 3
BYTE 4
BYTE 5
BYTE 6
BYTE 7
BYTE 8
(CLOCK NUMBER)
(0 , 1 )
(2 , 3)
(4 , 5)
(6 , 7)
(8 , 9)
(10 , 11)
(12 , 13)
(14 , 15)
Write Enable
06h
Write Enable for Volatile
Status Register
50h
Write Disable
04h
Read Status Register-1
05h
(S7-S0)
Read Status Register-2
35h
(S15-S8)
Write Status Register-1
01h
(S7-S0)
Write Status Register-2
31h
(S15-S8)
(5)
Fast Read
Data
>80MHz
(2)
(2)
(S15-S8)
A23-A16
A15-A8
A7-A0
dummy
dummy
(D7-D0)
A23-A16
A15-A8
A7-A0
dummy
dummy
dummy
0Bh
>104MHz
(3)
Page Program
02h
A23-A16
A15-A8
A7-A0
Sector Erase(4KB)
20h
A23-A16
A15-A8
A7-A0
Block Erase(32KB)
52h
A23-A16
A15-A8
A7-A0
Block Erase(64KB)
D8h
A23-A16
A15-A8
A7-A0
Chip Erase
60h/
C7h
Erase/Program Suspend
75h
Erase/Program Resume
7Ah
Deep Power-down
B9h
Release Deep power
(4)
down/ Device ID
ABh
dummy
dummy
dummy
Read Manufacturer/
(4)
Device ID
90h
00h
00h
9Fh
(MID7-MID0)
Manufacturer
(D7-D0)
Memory
Type
00h or
01h
(D7-D0)
Capacity
Type
A23-A16
A15-A8
A7-A0
(M7-M0)
dummy
A23-A16
A15-A8
A7-A0
(M7-M0)
dummy
Read JEDEC ID
(4)
Enter Security
B1h
Exit Security
C1h
Read Security Register
2Bh
Write Security Register
2Fh
Fast Read
Quad I/O
>80MHz
(D7-D0)
(D7-D0)
(ID7-ID0)
(2)
(MID7MID0)
(DID7DID0)
(ID7-ID0)
(D7-D0)
EBh
>104MHz
Reset Enable
66h
Reset
99h
Disable QPI
FFh
dummy
Rev.03 (August.30.2011)
(D7-D0)
23
Burst Read
with Wrap
>80MHz
>104MHz
Set Read Parameter
Set
Enhanced
Program mode
Quad Page Program
Notes:
1.
2.
3.
4.
5.
6.
A23-A16
A15-A8
A7-A0
dummy
dummy
(D7-D0)
A23-A16
A15-A8
A7-A0
dummy
dummy
dummy
A15-A8
A7-A0
0Ch
Page
C0h
P7-P0
36h
EP7-EP0
33h
A23-A16
(D7-D0)
(D7-D0)
Data bytes are shifted with Most Significant Bit first. Byte fields with data in parenthesis
“()” indicate data being read from the device on the IO pin.
The Status Register contents and Device ID will repeat continuously until /CS terminates
the instruction.
At least one byte of data input is required for Page Program, Quad Page Program and
Program Security Register, up to 256 bytes of data input. If more than 256 bytes of data
are sent to the device, the addressing will wrap to the beginning of the page and
overwrite previously sent data.
See Manufacturer and Device Identification table for Device ID information.
Dual Input Address
IO0 = A22, A20, A18, A16, A14, A12, A10, A8, A6, A4, A2, A0, M6, M4, M2, M0
IO1 = A23, A21, A19, A17, A15, A13, A11, A9, A7, A5, A3, A1, M7, M5, M3, M1
Dual Output data
IO0 = (D6, D4, D2, D0)
IO1 = (D7, D5, D3, D1)
7.
Quad Input Address
IO0 = A20, A16, A12, A8, A4, A0, M4, M0
IO1 = A21, A17, A13, A9, A5, A1, M5, M1
IO2 = A22, A18, A14, A10, A6, A2, M6, M2
IO3 = A23, A19, A15, A11, A7, A3, M7, M3
8.
Quad Input/ Output Data
IO0 = (D4, D0;)
IO1 = (D5, D1;)
IO2 = (D6, D2;)
IO3 = (D7, D3;)
9.
Fast Read Quad I/O Data Output
IO0 = (x, x, x, x, D4, D0;)
IO1 = (x, x, x, x, D5, D1;)
IO2 = (x, x, x, x, D6, D2;)
IO3 = (x, x, x, x, D7, D3;)
Set Burst with Wrap Input
IO0 = x, x, x, x, x, x, W4, x
IO1 = x, x, x, x, x, x, W5, x
IO2 = x, x, x, x, x, x, W6, x
IO3 = x, x, x, x, x, x, x
x
Rev.03 (August.30.2011)
24
10.6 Write Enable (06h)
Write Enable instruction is for setting the Write Enable Latch (WEL) bit in the Status Register. The
WEL bit must be set prior to every Program, Erase and Write Status Register instruction. To enter
the Write Enable instruction, /CS goes low prior to the instruction “06h” into Data Input (DI) pin on
the rising edge of CLK, and then driving /CS high.
Figure 6. Write Enable Instruction for SPI Mode (left) and QPI Mode (right)
10.7 Write Enable for Volatile Status Register (50h)
This gives more flexibility to change the system configuration and memory protection schemes
quickly without waiting for the typical non-volatile bit write cycles or affecting the endurance of the
Status Register non-volatile bits. To write the volatile values into the Status Register bits, the Write
Enable for Volatile Status Register (50h) instruction must be issued prior to a Write Status Register
(01h) instruction. Write Enable for Volatile Status Register instruction (Figure 7) will not set the
Write Enable Latch (WEL) bit. Once Write Enable for Volatile Status Register is set, a Write Enable
instruction should not have been issued prior to setting Write Status Register instruction (01h or
31h).
Figure 7. Write Enable for Volatile Status Register Instruction for SPI Mode (left) and QPI Mode (right)
Rev.03 (August.30.2011)
25
10.8 Write Disable (04h)
The Write Disable instruction is to reset the Write Enable Latch (WEL) bit in the Status Register. To
enter the Write Disable instruction, /CS goes low prior to the instruction “04h” into Data Input (DI)
pin on the rising edge of CLK, and then driving /CS high. WEL bit is automatically reset writedisable status of “0” after Power-up and upon completion of the every Program, Erase and Write
Status Register instructions.
Figure 8. Write Disable Instruction for SPI Mode (left) and QPI Mode (right)
Rev.03 (August.30.2011)
26
10.9 Read Status Register-1 (05h) and Read Status Register-2 (35h)
The Read Status Register instructions are to read the Status Register. The Read Status Register
can be read at any time (even in program/erase/write Status Register and Write Security Register
condition). It is recommended to check the BUSY bit before sending a new instruction when a
Program, Erase, Write Status Register or Write Status Register operation is in progress.
The instruction is entered by driving /CS low and sending the instruction code “05h” for Status
Register-1 or “35h” for Status Register-2 into the DI pin on the rising edge of CLK. The status
register bits are then shifted out on the DO pin at the falling edge of CLK with most significant bit
(MSB) first as shown in (figure 9). The Status Register can be read continuously. The instruction is
completed by driving /CS high.
≈
≈
≈ ≈ ≈ ≈
Figure 9a. Read Status Register Instruction (SPI Mode)
≈
≈
≈ ≈≈ ≈ ≈ ≈≈ ≈
Figure 9b. Read Status Register Instruction (QPI Mode)
Rev.03 (August.30.2011)
27
10.10 Write Status Register (01h)
The Write Status Register instruction is to write only non-volatile Status Register-1 bits (SRP0,
SEC, TB, BP2, BP1 and BP0) and Status Register-2 bits (CMP, QE and SRP1). All other Status
Register bit locations are read-only and will not be affected by the Write Status Register instruction.
A Write Enable instruction must previously have been issued prior to setting Write Status Register
Instruction (Status Register bit WEL must equal 1). Once write is enabled, the instruction is entered
by driving /CS low, sending the instruction code, and then writing the status register data byte as
illustrated in figure 10.
The /CS pin must be driven high after the eighth or sixteenth bit of data that is clocked in. If this is
not done the Write Status Register instruction will not be executed. If /CS is driven high after the
eighth clock, the QE and SRP1 bits will be cleared to 0. After /CS is driven high, the self-timed
Write Status Register cycle will commence for a time duration of tw (See AC Characteristics).
While the Write Status Register cycle is in progress, the Read Status Register instruction may still
be accessed to check the status of the BUSY bit. The BUSY bit is a 1 during the Write Status
Register cycle and a 0 when the cycle is finished and ready to accept other instructions again.
When the BUSY bit is asserted, the Write Enable Latch (WEL) bit in Status Register will be cleared
to 0.
Figure 10a. Write Status Register Instruction (SPI Mode)
Figure 10b. Write Status Register Instruction (QPI Mode)
Rev.03 (August.30.2011)
28
10.11 Write Status Register-2 (31h)
The Write Status Register-2 instruction is to write only non-volatile Status Register-2 bits (CMP, QE
and SRP1).
A Write Enable instruction must previously have been issued prior to setting Write Status Register
Instruction (Status Register bit WEL must equal 1). Once write is enabled, the instruction is entered
by driving /CS low, sending the instruction code, and then writing the status register data byte as
illustrated in figure 11.
Using Write Status Register-2 (31h) instruction, software can individually access each one-byte
status registers via different instructions.
Figure 11a. Write Status Register-2 Instruction (SPI Mode)
Figure 11b. Write Status Register-2 Instruction (QPI Mode)
Rev.03 (August.30.2011)
29
10.12 Read Data (03h)
The Read Data instruction is to read data out from the device. The instruction is initiated by driving
the /CS pin low and then sending the instruction code “03h” with following a 24-bit address (A23A0) into the DI pin. After the address is received, the data byte of the addressed memory location
will be shifted out on the DO pin at the falling edge of CLK with most significant bit (MSB) first. The
address is automatically incremented to the next higher address after byte of data is shifted out
allowing for a continuous stream of data. This means that the entire memory can be accessed with
a single instruction as long as the clock continues. The instruction is completed by driving /CS high.
The Read Data instruction sequence is shown in (figure 12). If a Read Data instruction is issued
while an Erase, Program or Write Status Register cycle is in process (BUSY=1) the instruction is
ignored and will not have any effects on the current cycle. The Read Data instruction allows clock
rates from D.C to a maximum of fR (see AC Electrical Characteristics).
≈
≈
≈ ≈ ≈≈
Figure 12. Read Data Instruction
10.13 Fast Read (0Bh)
The Fast Read instruction is high speed reading mode that it can operate at the highest possible
frequency of FR. The address is latched on the rising edge of the CLK. After the 24-bit address, this
is accomplished by adding “dummy” clocks as shown in (figure 13). The dummy clocks means the
internal circuits require time to set up the initial address. During the dummy clocks, the data value
on the DO pin is a “don’t care”. Data of each bit shifts out on the falling edge of CLK.
≈
≈
≈ ≈ ≈≈
Figure 13a. Fast Read Instruction (SPI Mode)
Fast Read in QPI Mode
Rev.03 (August.30.2011)
30
When QPI mode is enabled, the number of dummy clock is configured by the “Set Read
Parameters (C0h)” instruction to accommodate wide range applications with different needs for
either maximum Fast Read frequency or minimum data access latency. Depending on the Read
Parameter Bit P[4] setting, the number of dummy clocks can be configured as either 4, or 6. The
default number of dummy clocks upon power up or after a Reset instruction is 4. (Please refer to
figure 13b, 13c).
≈
≈
≈ ≈≈ ≈ ≈ ≈≈ ≈
Figure 13b. Fast Read instruction (QPI Mode, 80MHz)
Figure 13c. Fast Read instruction (QPI Mode, 104MHz)
10.14 Fast Read Dual Output (3Bh)
Rev.03 (August.30.2011)
31
By using two pins (IO0 and IO1, instead of just IO0), The Fast Read Dual Output instruction allows
data to be transferred from the FM25M64A at twice the rate of standard SPI devices. The Fast
Read Dual Output instruction is ideal for quickly downloading code from Flash to RAM upon
power-up or for application that cache code-segments to RAM for execution.
The Fast Read Dual Output instruction can operate at the highest possible frequency of FR (see AC
Electrical Characteristics). After the 24-bit address, this is accomplished by adding eight “dummy”
clocks as shown in (figure 14). The dummy clocks allow the internal circuits additional time for
setting up the initial address. During the dummy clocks, the data value on the DO pin is a “don’t
care”. However, the IO0 pin should be high-impedance prior to the falling edge of the first data out
clock.
≈
≈
≈≈ ≈≈
Figure14. Fast Read Dual Output instruction (SPI Mode)
Rev.03 (August.30.2011)
32
10.15 Fast Read Quad Output (6Bh)
By using four pins (IO0, IO1, IO2, and IO3), The Fast Read Quad Output instruction allows data to
be transferred from the FM25M64A at four times the rate of standard SPI devices.
A Quad enable of Status Register-2 must be executed before the device will accept the Fast Read
Quad Output instruction (Status Register bit QE must equal 1).
The Fast Read Quad Output instruction can operate at the highest possible frequency of FR (see
AC Electrical Characteristics). This is accomplished by adding eight “dummy” clocks after the 24bit address as shown in (figure 15). The dummy clocks allow the internal circuits additional time for
setting up the initial address. During the dummy clocks, the data value on the DO pin is a “don’t
care”. However, the IO0 pin should be high-impedance prior to the falling edge of the first data out
clock
/CS
Mode 3
0
1
2
4
3
5
6
7
8
9
10
28
29
30
31
CLK
Mode 0
Instruction
IO0
24 Bit Address
6Bh
23
21
38
39
3
2
1
0
41
42
43
44
MSB
High - Z
IO1
22
High - Z
IO2
High - Z
IO3
≈
/CS
32
33
34
35
36
37
40
45
47
46
≈
CLK
IO0
4
0
4
0
4
0
4
0
IO1
5
1
5
1
5
1
5
1
IO2
6
2
6
2
6
2
6
2
IO3
7
3
7
3
7
3
7
Data
Out 1
Data
Out 2
Data
Out 3
3
Data
Out 4
≈ ≈≈ ≈ ≈ ≈≈ ≈
IO0 Switches from
Input to Output
Dummy
4
5
6
7
Figure 15. Fast Read Quad Output instruction (SPI Mode)
Rev.03 (August.30.2011)
33
10.16 Fast Read Dual I/O (BBh)
The Fast Read Dual I/O instruction reduces cycle overhead through double access using two IO
pins: IO0 and IO1.
Continuous read mode
The Fast Read Dual I/O instruction can further reduce cycle overhead through setting the Mode
bits (M7-0) after the input Address bits (A23-0). The upper nibble of the Mode (M7-4) controls the
length of the next Fast Read Dual I/O instruction through the inclusion or exclusion of the first byte
instruction code. The lower nibble bits of the Mode (M3-0) are don’t care (“X”), However, the IO
pins should be high-impedance prior to the falling edge of the first data out clock.
If the Mode bits (M7-0) equal “Ax” hex, then the next Fast Dual I/O instruction (after /CS is raised
and then lowered) does not require the instruction (BBh) code, as shown in (figure 16b). This
reduces the instruction sequence by eight clocks and allows the address to be immediately
entered after /CS is asserted low. If Mode bits (M7-0) are any value other “Ax” hex, the next
instruction (after /CS is raised and then lowered) requires the first byte instruction code, thus
returning to normal operation. A Mode Bit Reset instruction can be used to reset Mode Bits (M7-0)
before issuing normal instructions.
≈
≈
≈ ≈ ≈≈
Figure 16a. Fast Read Dual I/O Instruction (initial instruction or previous M7-0≠ Axh)
Rev.03 (August.30.2011)
34
≈
≈
≈ ≈ ≈ ≈
Figure 16b. Fast Read Dual I/O Instruction (previous M7-0= Axh)
Rev.03 (August.30.2011)
35
10.17 Fast Read Quad I/O (EBh)
The Fast Read Quad I/O instruction reduces cycle overhead through quad access using four IO
pins: IO0, IO1, IO2, and IO3. The Quad Enable bit (QE) of Status Register-2 must be set to enable
the Fast read Quad I/O Instruction.
Continuous read mode
The Fast Read Quad I/O instruction can further reduce instruction overhead through setting the
Mode bits (M7-0) with following the input Address bits (A23-0), as shown in (figure 17a). The upper
nibble of the Mode (M7-4) controls the length of the next Fast Read Quad I/O instruction through
the inclusion or exclusion of the first byte instruction code. The lower nibble bits of the Mode (M3-0)
are don’t care (“X”). However, the IO pins should be high-impedance prior to the falling edge of the
first data out clock.
If the Mode bits (M7-0) equal “Ax” hex, then the next Fast Read Quad I/O instruction (after /CS is
raised and then lowered) does not require the EBh instruction code, as shown in (figure 17b). This
reduces the instruction sequence by eight clocks and allows the address to be immediately
entered after /CS is asserted low. If the Mode bits (M7-0) are any value other than “Ax” hex, the
next instruction (after /CS is raised and then lowered) requires the first byte instruction code, thus
retuning normal operation. A Mode Bit Reset can be used to reset Mode Bits (M7-0) before issuing
normal instructions.
≈
≈
≈ ≈≈ ≈ ≈ ≈≈ ≈
Figure 17a. Fast Read Quad I/O Instruction (Initial instruction or previous M7-0 ≠ Axh, SPI mode)
≈
≈
≈ ≈≈ ≈ ≈ ≈≈ ≈
Figure 17b. Fast Read Quad I/O Instruction (previous M7-0 = Axh, SPI mode)
Rev.03 (August.30.2011)
36
Wrap Around in SPI mode
The Fast Read Quad I/O instruction can also be used to access specific portion within a page by
issuing a “Set Burst with Wrap” (77h) instruction prior Fast Read Quad I/O (EBh) instruction. The
“Set Burst with Wrap” (77h) instruction can either enable or disable the “Wrap Around” feature for
the following Fast Read Quad I/O instruction.
When “Wrap Around” is enabled, the data being accessed can be limited to an 8/16/32/64-byte
section of a 256-byte page. The output data starts at the initial address specified in the instruction,
once it reaches the ending boundary of the 8/16/32/64-byte section, the output will wrap around to
the beginning boundary automatically until /CS is pulled high to terminate the instruction.
The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address
and then fill the cache afterwards within a fixed length (8/16/32/64-byte) of data without issuing
multiple read instructions. (Please refer to 10.36 Set Burst with Wrap).
Fast Read Quad I/O in QPI mode
When QPI mode in enabled, the number of dummy clocks is configured by the “Set Read
Parameters (C0h)” instruction to accommodate a wide range applications with different needs for
either maximum Fast Read frequency or minimum data access latency. Depending on the Read
Parameter Bits P [4] setting, the number of dummy clocks can be configured as either 4 or 6. The
default number of dummy clocks upon power up or after a Reset (99h) instruction is 4.
“Continuous Read Mode” feature is also available in QPI mode for Fast Read Quad I/O instruction.
In QPI mode, the “Continuous Read Mode” bits M7-0 are also considered as dummy clocks. In the
default setting, the data output will follow the Continuous Read Mode bits immediately.
“Wrap Around” feature is not available in QPI mode for Fast Read Quad I/O instruction. To perform
a read operation with fixed data length wrap around in QPI mode, a “Burst Read with Wrap” (0Ch)
instruction must be used. (Please refer to 10.37 Burst Read with Wrap).
≈
≈
≈ ≈≈ ≈ ≈ ≈≈ ≈
Figure 17c. Fast Read Quad I/O Instruction
(Initial instruction or previous M7-0 ≠ Axh, QPI mode, 80MHz)
Rev.03 (August.30.2011)
37
Figure 17d. Fast Read Quad I/O Instruction
(Initial instruction or previous M7-0 ≠ Axh, QPI mode, 104MHz)
Rev.03 (August.30.2011)
38
10.18 Page Program (02h)
The Page Program instruction is for programming the memory to be “0”. A Write Enable instruction
must be issued before the device accept the Page Program Instruction (Status Register bit WEL=
1). After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable
Latch (WEL). The instruction is entered by driving the /CS pin low and then sending the instruction
code “02h” with following a 24-bits address (A23-A0) and at least one data byte, into the DI pin.
The /CS pin must be driven low for the entire time of the instruction while data is being sent to the
device. (Please refer to figure 18).
If an entire 256 byte page is to be programmed, the last address byte (the 8 least significant
address bits) should be set to 0. If the last address byte is not zero, and the number of clocks
exceeds the remaining page length, the addressing will wrap to the beginning of the page. In some
cases, less than 256 bytes (a partial page) can be programmed without having any effect on other
bytes within the same page. One condition to perform a partial page program is that the number of
clocks cannot exceed the remaining page length. If more than 256 bytes are sent to the device the
addressing will wrap to the beginning of the page and overwrite previously sent data.
The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not
done the Page Program instruction will not be executed. After /CS is driven high, the self-timed
Page Program instruction will commence for a time duration of tPP (See AC Characteristics). While
the Page Program cycle is in progress, the Read Status Register instruction may still be accessed
for checking the status of the BUSY bit. The BUSY bit is a 1 during the Page Program cycle and
becomes a 0 when the cycle is finished and the device is ready to accept other instructions again.
When the BUSY bit is asserted, the Write Enable Latch (WEL) bit in the Status Register is cleared
to 0. The Page Program instruction will not be executed if the addressed page is protected by the
Protect (CMP, SEC, TB, BP2, BP1 and BP0) bits.
/CS
1
0
Mode 3
2
4
3
5
6
8
7
9
10
28
29
30
31
1
0
33
32
34
35
36
37
38
39
CLK
Instruction
24 Bit Address
23
22
21
3
Data Byte 1
2
MSB
6
46
47
48
49
50
51
52
53
54
55
2079
45
0
1
2078
44
2076
43
2
3
2077
42
2073
41
≈
CLK
2072
≈
40
4
5
MSB
/CS
Data Byte 2
7
MSB
6
5
4
3
Data Byte 256
Data Byte 3
2
1
0
7
MSB
6
5
4
3
2
1
0
≈
DI
7
2074
02h
DI
2075
Mode 0
7
6
5
4
3
2
1
0
MSB
Figure 18a. Page Program Instruction (SPI Mode)
Rev.03 (August.30.2011)
39
519
518
≈
≈
≈
≈
≈
≈
Figure 18b. Page Program Instruction (QPI Mode)
Rev.03 (August.30.2011)
40
10.19 Quad Data Input Page Program (32h)
The Quad Data Input Page Program instruction is to program the memory as being “0” at
previously erased memory areas. The Quad Data Input Page Program takes four pins: IO0, IO1, IO2
and IO3 as and data input, which can improve programmer performance and the effectiveness of
application of lower clock less than 5MHz. System using faster clock speed will not get more
benefit for the Quad Data Input Page Program as the required internal page program time is far
more than the time data clock-in.
To use Quad Data Input Page Program the QE bit must be set, A Write Enable instruction must be
executed before the device will accept the Quad Data Input Page Program instruction (Status
Register-1, WEL=1). The instruction is initiated by driving the /CS pin low and then sending the
instruction code “32h” with following a 24-bit address (A23-A0) and at least one data, into the IO
pins. The /CS pin must be held low for the entire length of the instruction while data is being sent to
the device. All other functions of Quad Data Input Page Program are perfectly same as standard
Page Program. (Please refer to figure 19).
/CS
1
0
Mode 3
2
4
3
5
6
7
8
9
10
28
29
30
32
31
33
34
35
CLK
Mode 0
Instruction
IO0
24 Bit Address
32h
23
IO1
22
21
3
2
1
0
High - Z
IO2
High - Z
IO3
4
0
4
0
5
1
5
1
6
2
6
2
3
7
3
MSB
High - Z
7
Data
Byte 1
44
45
543
43
542
42
541
41
40
540
39
539
38
538
37
≈
CLK
537
36
536
≈
/CS
Data
Byte 2
0
4
0
4
0
4
0
IO1
5
1
5
1
5
1
5
1
5
1
IO2
6
2
6
2
6
2
6
2
6
2
IO3
7
3
7
3
7
3
7
3
7
3
Data
Byte 3
Data
Byte 4
Data
Byte 5
Data
Byte 6
Data
Byte 7
4
0
4
0
4
0
4
0
5
1
5
1
5
1
5
1
6
2
6
2
6
2
6
2
≈
4
≈
0
≈
4
≈
IO0
7
3
7
3
7
3
7
3
Data
Byte 253
Data
Byte 254
Data
Byte 255
Data
Byte 256
Figure 19. Quad Data Input Page Program Instruction
Rev.03 (August.30.2011)
41
10.20 Quad Page Program (33h)
The Quad Page Program instruction is to program the memory as being “0” at previously erased
memory areas. The Quad Page Program takes four pins: IO0, IO1, IO2 and IO3 as address and data
input, which can improve programmer performance and the effectiveness of application of lower
clock less than 5MHz. System using faster clock speed will not get more benefit for the Quad Page
Program as the required internal page program time is far more than the time data clock-in.
To use Quad Page Program, the Quad Enable bit must be set, A Write Enable instruction must be
executed before the device will accept the Quad Page Program instruction (Status Register-1,
WEL=1). The instruction is initiated by driving the /CS pin low then sending the instruction code
“33h” with following a 24-bit address (A23-A0) and at least one data, into the IO pins. The /CS pin
must be held low for the entire length of the instruction while data is being sent to the device. All
other functions of Quad Page Program are perfectly same as standard Page Program. (Please
refer to figure 20).
/CS
1
0
Mode 3
2
4
3
5
6
7
8
9
10
12
11
13
14
16
15
17
18
19
CLK
Mode 0
Instruction
IO0
24 Bit Address
33h
High - Z
IO1
High - Z
IO2
High - Z
IO3
20
16
12
8
4
0
4
0
4
0
4
0
21
17
13
9
5
1
5
1
5
1
5
1
22
18
14
10
6
2
6
2
6
2
6
2
23
19
15
11
7
3
7
3
7
3
7
3
Data
Byte 1
MSB
Data
Byte 3
28
29
525
27
524
26
523
25
24
522
23
521
22
520
21
≈
CLK
519
20
518
≈
/CS
Data
Byte 2
0
4
0
4
0
4
0
IO1
5
1
5
1
5
1
5
1
5
1
IO2
6
2
6
2
6
2
6
2
6
2
IO3
7
3
7
3
7
3
7
3
7
3
Data
Byte 4
Data
Byte 5
Data
Byte 6
Data
Byte 7
Data
Byte 8
4
0
4
0
4
0
4
0
5
1
5
1
5
1
5
1
6
2
6
2
6
2
6
2
≈
4
≈
0
≈
4
≈
IO0
7
3
7
3
7
3
7
3
Data
Byte 253
Data
Byte 254
Data
Byte 255
Data
Byte 256
Figure 20a. Quad Page Program Instruction (SPI mode)
Rev.03 (August.30.2011)
42
519
518
≈
≈
≈
≈
≈
≈
Figure 20b. Quad Page Program Instruction (QPI mode)
Rev.03 (August.30.2011)
43
10.21 Enhance Page Program (EPP)
The Enhance Page Program instruction allows multiple bytes of data to be programmed without reissuing the instruction and next sequential address inputs. This feature decrease total
programming time when multiple bytes are to be programmed.
To start the EPP operation, A Write Enable instruction (06h) and Set Enhance Page Program
instruction (36h) must be issued before the Page Program Instruction (02h) in QPI mode.
In Enhanced Page Program, Data-in sequence can be divided into several times. Each data-in
sequence of Enhanced Page Program is initiated by driving the /CS pin low and then sending one
or more byte program data, D7-0.
Until system put the last data to be defined in the previous Set Enhanced Page Program
instruction (36h), no other instructions are available in the device, including Read Status Register
Instruction. When the last desired byte had been entered, Enhanced Page Program operation will
be started automatically. (Please refer to figure 18).
Like Page Program, the addressing will wrap to the beginning of the page to perform the page
program is if the number of data-in exceed the remaining page length.
The /CS pin must be driven high after the eighth bit of the last byte in each data-in sequence has
been latched. If this is not done the Enhanced Page Program instruction will not be executed. After
/CS is driven high in last data-in sequence, the self-timed Enhanced Page Program instruction will
commence for a time duration of tPP (See AC Characteristics). While the Enhanced Page Program
cycle is in progress, the Read Status Register instruction may still be accessed for checking the
status of the BUSY bit. The BUSY bit is a 1 during the Enhanced Page Program cycle and
becomes a 0 when the cycle is finished and the device is ready to accept other instructions again.
When the BUSY bit is asserted, the Write Enable Latch (WEL) bit in the Status Register is cleared
to 0. And when the BUSY bit is cleared, Enhanced Page Program Enable bit is cleared to 0. The
Enhanced Page Program instruction will not be executed if the addressed page is protected by the
Protect (CMP, SEC, TB, BP2, BP1 and BP0) bits.
≈
≈
≈
≈
≈
≈
≈
≈
≈
≈
≈
≈
≈
≈
≈
≈
≈
≈
≈
≈ ≈
≈
≈
≈
≈ ≈
≈ ≈ ≈
≈
Rev.03 (August.30.2011)
44
Figure 21. Enhance Page Program Instruction (QPI mode)
10.22 Set Enhance Page Program Enable (36h)
The Set Enhance Page Program enable instruction (36h) is used in conjunction with “Enhance
Page Program” instructions to set or clear Enhanced Page Program Enable mode bit of the
Enhanced Page Program and to define the number of program input data.
The Set Enhanced Page Program instruction is initiated by driving the /CS pin low and then shifting
the instruction code “36h” followed by 8 “Number bits”, EP7-0. When the number bits EP7-0 are
8’h00, Enhance Page Program Enable mode will be cleared. When the number bits EP7-0 are not
8’h00, Enhanced Page Program Enable mode is set and Enhance Page Program is started by the
next Page Program instruction (02h).
Enhance Page Program Enable mode is automatically reset Power-up and upon completion of the
Enhanced Page Program.
EP7-0
Enable mode
The Number of Input Data
= 00h
0
-
≠ 00h
1
EP7-0
Figure 22 Set Enhance Page Program enable Instruction
Rev.03 (August.30.2011)
45
10.23 Sector Erase (20h)
The Sector Erase instruction is to erase the data of the selected sector as being “1”. The
instruction is used for 4K-byte sector. Prior to the Sector Erase Instruction, the Write Enable
instruction must be issued. The instruction is initiated by driving the /CS pin low and shifting the
instruction code “20h” followed a 24-bit sector address (A23-A0). (Please refer to figure 23). The
/CS pin must go high after the eighth bit of the last byte has been latched in, otherwise, the Sector
Erase instruction will not be executed. After /CS goes high, the self-timed Sector Erase instruction
will commence for a time duration of tSE (See AC Characteristics).
While the Sector Erase cycle is in progress, the Read Status Register instruction may still be
accessed for checking the status of the BUSY bit. The BUSY bit is a 1 during the Sector Erase
cycle and becomes a 0 when the cycle is finished and the device is ready to accept other
instructions again. When the BUSY bit is asserted, the Write Enable Latch (WEL) bit in the Status
Register is cleared to 0. The sector Erase instruction will not be executed if the addressed page is
protected by the Protect (CMP, SEC, TB, BP2, BP1 and BP0) bits.
Figure 23a. Sector Erase Instruction (SPI Mode)
Figure 23b. Sector Erase Instruction (QPI Mode)
Rev.03 (August.30.2011)
46
10.24 32KB Block Erase (52h)
The Block Erase instruction is to erase the data of the selected block as being “1”. The instruction
is used for 32K-byte Block erase operation. Prior to the Block Erase Instruction, a Write Enable
instruction must be issued. The instruction is initiated by driving the /CS pin low and shifting the
instruction code “52h” followed a 24-bit block address (A23-A0). (Please refer to figure 24). The
/CS pin must go high after the eighth bit of the last byte has been latched in, otherwise, the Block
Erase instruction will not be executed. After /CS is driven high, the self-timed Block Erase
instruction will commence for a time duration of tBE1 (See AC Characteristics).
While the Block Erase cycle is in progress, the Read Status Register instruction may still be read
the status of the BUSY bit. The BUSY bit is a 1 during the Block Erase cycle and becomes a 0
when the cycle is finished and the device is ready to accept other instructions again. When the
BUSY bit is asserted, the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The
Block erase instruction will not be executed if the addressed page is protected by the Protect (CMP,
SEC, TB, BP2, BP1 and BP0) bits.
Figure 24a. 32KB Block Erase Instruction (SPI Mode)
Figure 24b. 32KB Block Erase Instruction (QPI Mode)
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47
10.25 64KB Block Erase (D8h)
The Block Erase instruction is to erase the data of the selected block as being “1”. The instruction
is used for 64K-byte Block erase operation. Prior to the Block Erase Instruction, a Write Enable
instruction must be issued. The instruction is initiated by driving the /CS pin low and shifting the
instruction code “D8h” followed a 24-bit block address (A23-A0). (Please refer to figure 25). The
/CS pin must go high after the eighth bit of the last byte has been latched in, otherwise, the Block
Erase instruction will not be executed. After /CS is driven high, the self-timed Block Erase
instruction will commence for a time duration of tBE2 (See AC Characteristics).
While the Block Erase cycle is in progress, the Read Status Register instruction may still be read
the status of the BUSY bit. The BUSY bit is a 1 during the Block Erase cycle and becomes a 0
when the cycle is finished and the device is ready to accept other instructions again. When the
BUSY bit is asserted, the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The
Block erase instruction will not be executed if the addressed page is protected by the Protect (CMP,
SEC, TB, BP2, BP1 and BP0) bits.
Figure 25a. 64KB Block Erase Instruction (SPI Mode)
Figure 25b. 64KB Block Erase Instruction (QPI Mode)
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48
10.26 Chip Erase (C7h / 60h)
The Chip Erase instruction clears all bits in the device to be FFh (all 1s). Prior to the Chip Erase
Instruction, a Write Enable instruction must be issued. The instruction is initiated by driving the /CS
pin low and shifting the instruction code “C7h” or “60h”. (Please refer to figure 26). The /CS pin
must go high after the eighth bit of the last byte has been latched in, otherwise, the Chip Erase
instruction will not be executed. After /CS is driven high, the self-timed Chip Erase instruction will
commence for a duration of tCE (See AC Characteristics).
While the Chip Erase cycle is in progress, the Read Status Register instruction may still be
accessed to check the status of the BUSY bit. The BUSY bit is a 1 during the Chip Erase cycle and
becomes a 0 when the cycle is finished and the device is ready to accept other instructions again.
When the BUSY bit is asserted, the Write Enable Latch (WEL) bit in the Status Register is cleared
to 0. The Chip erase instruction will not be executed if any page is protected by the Protect (CMP,
SEC, TB, BP2, BP1 and BP0) bits.
Figure 26. Chip Erase Instruction for SPI Mode (left) and QPI Mode (right)
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49
10.27 Erase / Program Suspend (75h)
The Erase/Program Suspend instruction allows the system to interrupt a Sector Erase, Block
Erase operation or a Page Program, Quad Data Input Page Program, Quad Page Program
operation.
Erase Suspend is valid only during the Sector or Block erase operation. The Write Status Register1(01h), Write Status Register-2 (31h) instruction and Erase instructions (20h, 52h, D8h, C7h, 60h)
are not allowed during Erase Suspend. During the Chip Erase operation, the Erase Suspend
instruction is ignored.
Program Suspend is valid only during the Page Program, Quad Data Input Page Program or Quad
Page Program operation. The Write Status Register-1(01h), Write Status Register-2 (31h)
instruction and Program instructions (02h, 32h and 33h) are not allowed during Program Suspend.
The Erase/Program Suspend instruction “75h” will be accepted by the device only if the SUS bit in
the Status Register equals to 0 and the BUSY bit equals to 1 while a Sector or Block Erase or a
Page Program operation is on-going. If the SUS bit equals to 1 or the BUSY bit equals to 0, the
Suspend instruction will be ignored by the device. A maximum of time of “tSUS” (See AC
Characteristics) is required to suspend the erase or program operation. After Erase/Program
Suspend, the SUS bit in the Status Register will be set from 0 to 1 immediately and The BUSY bit
in the Status Register will be cleared from 1 to 0 within “tSUS”. For a previously resumed
Erase/Program operation, it is also required that the Suspend instruction “75h” is not issued earlier
than a minimum of time of “tSUS” following the preceding Resume instruction “7Ah”.
Unexpected power off during the Erase/Program suspend state will reset the device and release
the suspend state. SUS bit in the Status Register will also reset to 0. The data within the page,
sector or block that was being suspended may become corrupted. It is recommended for the user
to implement system design techniques against the accidental power interruption and preserve
data integrity during erase/program suspend state. (Please refer to figure 27).
Figure 27a. Erase Suspend instruction (SPI Mode)
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50
/CS
tSUS
Mode 3
0
1
CLK
Mode 0
Instruction
75h
IO0
IO1
IO2
IO3
Accept Read or Program Instruction
Figure 27b. Erase Suspend instruction (QPI Mode)
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51
10.28 Erase / Program Resume (7Ah)
The Erase/Program Resume instruction “7Ah” is to re-work the Sector or Block Erase operation or
the Page Program operation upon an Erase/Program Suspend. The Resume instruction “7Ah” will
be accepted by the device only if the SUS bit in the Status Register equals to 1 and the BUSY bit
equals to 0. After issued, the SUS bit will be cleared from 1 to 0 immediately, the BUSY bit will be
set from 0 to 1 within 200ns and the Sector or Block will complete the erase operation or the page
will complete the program operation. If the SUS bit equals to 0 or the BUSY bit equals to 1, the
Resume instruction “7Ah” will be ignored by the device.
Resume instruction cannot be accepted if the previous Erase/Program Suspend operation was
interrupted by unexpected power off. It is also required that a subsequent Erase/Program Suspend
instruction not to be issued within a minimum of time of “tSUS” following a previous Resume
instruction. (Please refer to figure 28).
Figure 28a. Erase / Program Resume instruction (SPI Mode)
Figure 28b. Erase / Program Resume instruction (QPI Mode)
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10.29 Deep Power-down (B9h)
Executing the Deep Power-down instruction is the best way to put the device in the lowest power
consumption. The Deep Power-down instruction reduces the standby current (from ICC1 to ICC2,
as specified in AC characteristics). The instruction is entered by driving the /CS pin low with
following the instruction code “B9h”. (Please refer to figure 29).
The /CS pin must go high exactly at the byte boundary (the latest eighth bit of instruction code
been latched-in); otherwise, the Deep Power-down instruction is not executed. After /CS goes high,
it requires a delay of tDP and the Deep Power-down mode is entered. While in the Release Deep
Power-down / Device ID instruction, which restores the device to normal operation, will be
recognized. All other instructions are ignored including the Read Status Register instruction, which
is always available during normal operation. Deep Power-down Mode automatically stops at
Power-Down, and the device always Power-up in the Standby Mode.
/CS
tDP
Mode 3
0
1
2
3
4
5
6
7
CLK
Mode 0
DI
Instruction
B9h
Stand-by Current
Power-down Current
Figure 29a. Deep Power-down Instruction (SPI Mode)
Figure 29b. Deep Power-down Instruction (QPI Mode)
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53
10.30 Release Deep Power-down / Device ID (ABh)
The Release Deep Power-down / Device ID instruction is a multi-purpose instruction. It can be
used to release the device from the Deep Power-down state or obtain the device identification (ID).
The instruction is issued by driving the /CS pin low, sending the instruction code “ABh” and driving
/CS high as shown in figure 30a & 30b. Release from Deep Power-down require the time duration
of tRES1 (See AC Characteristics) for re-work a normal operation and accepting other instructions.
The /CS pin must keep high during the tRES1 time duration.
To obtain the Device ID, instruction is initiated by driving the /CS pin low and sending the
instruction code “ABh” with following 3-dummy bytes. The Device ID bits are then shifted on the
falling edge of CLK with most significant bit (MSB) first as shown in figure 30c & 30d. After /CS is
driven high it must keep high for a time duration of tRES2 (See AC Characteristics). The Device ID
can be read continuously. The instruction is completed by driving /CS high.
If the Release from Deep Power-down /Device ID instruction is issued while an Erase, Program or
Write cycle is in process (when BUSY equals 1) the instruction is ignored and will not have any
effects on the current cycle.
Figure 30a. Release power-down Instruction (SPI Mode)
Figure 30b. Release power-down Instruction (QPI Mode)
Rev.03 (August.30.2011)
54
≈
≈
≈
Figure 30c. Release power-down / Device ID Instruction (SPI Mode)
/CS
tRES2
Mode 3
0
1
2
3
4
5
6
8
7
9
CLK
Mode 0
Instruction
ABh
IOs Switches from
Input to Output
3 Dummy Bytes
IO0
4
0
IO1
5
1
IO2
6
2
IO3
7
3
Device ID
(16h)
Power-Down Current
Stand-by
Current
Figure 30d. Release power-down / Device ID Instruction (QPI Mode)
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55
10.31 Read Manufacturer/ Device ID (90h)
The Read Manufacturer/ Device ID instruction provides both the JEDEC assigned manufacturer ID
and the specific device ID.
The Read Manufacturer/ Device ID instruction is very similar to the Release from Power-down /
Device ID instruction. The instruction is initiated by driving the /CS pin low and shifting the
instruction code “90h” followed by a 24-bit address (A23-A0) of 000000h. After which, the
Manufacturer ID for FIDELIX (F8h) and the Device ID(16h) are shifted out on the falling edge of
CLK with most significant bit (MSB) first as shown in figure 31a & 31b. If the 24-bit address is
initially set to 000001h the Device ID will be read first and then followed by the Manufacturer ID.
The Manufacturer and Device ID can be read continuously, alternating from one to the other. The
instruction is completed by driving /CS high.
/CS
1
0
Mode 3
2
4
3
5
6
8
7
9
10
28
29
30
31
CLK
Mode 0
24 Bit Address
000000h or 000001h
Instruction
90h
DI
23
22
21
3
2
1
0
MSB
High - Z
DO
/CS
32
33
34
35
36
37
38
39
40
41
42
43
45
44
46
47
CLK
DI
Manufacturer ID (F8h)
DO
7
6
MSB
5
4
3
2
Device ID (16h)
1
0
7
6
5
4
3
2
1
0
MSB
Figure 31a. Read Manufacturer/ Device ID instruction (SPI Mode)
Figure 31b. Read Manufacturer/ Device ID instruction (QPI Mode)
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56
10.32 Read Manufacturer / Device ID Dual I/O (92h)
The Read Manufacturer/ Device ID Dual I/O instruction provides both the JEDEC assigned
manufacturer ID and the specific device ID.
The Read Manufacturer/ Device ID instruction is very similar to the Fast Read Dual I/O instruction.
The instruction is initiated by driving the /CS pin low and shifting the instruction code “92h” followed
by a 24-bit address (A23-A0) of 000000h. After which, the Manufacturer ID for FIDELIX (F8h) and
the Device ID(16h) are shifted out on the falling edge of CLK with most significant bit (MSB) first as
shown in figure 32. If the 24-bit address is initially set to 000001h the Device ID will be read first
and then followed by the Manufacturer ID. The Manufacturer and Device ID can be read
continuously, alternating from one to the other. The instruction is completed by driving /CS high.
≈
≈
≈≈ ≈≈
Figure 32. Read Dual Manufacturer/ Device ID Dual I/O instruction (SPI Mode)
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10.33 Read Manufacturer / Device ID Quad I/O (94h)
The Read Manufacturer/ Device ID Quad I/O instruction provides both the JEDEC assigned
manufacturer ID and the specific device ID.
The Read Manufacturer/ Device ID instruction is very similar to the Fast Read Quad I/O instruction.
The instruction is initiated by driving the /CS pin low and shifting the instruction code “94h” followed
by a 24-bit address (A23-A0) of 000000h. After which, the Manufacturer ID for FIDELIX (F8h) and
the Device ID(16h) are shifted out on the falling edge of CLK with most significant bit (MSB) first as
shown in figure 33. If the 24-bit address is initially set to 000001h the Device ID will be read first
and then followed by the Manufacturer ID. The Manufacturer and Device ID can be read
continuously, alternating from one to the other. The instruction is completed by driving /CS high.
Figure 33. Read Quad Manufacturer/ Device ID Quad I/O instruction (SPI Mode)
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58
10.34 JEDEC ID (9Fh)
For compatibility reasons, the FM25M64A provides several instructions to electronically determine
the identity of the device. The Read JEDEC ID instruction is congruous with the JEDEC standard
for SPI compatible serial flash memories that was adopted in 2003. The instruction is entered by
driving the /CS pin low with following the instruction code “9Fh”. JEDEC assigned Manufacturer ID
byte for FIDELIX (F8h) and two Device ID bytes, Memory Type (ID-15-ID8) and Capacity (ID7-ID0)
are then shifted out on the falling edge of CLK with most significant bit (MSB) first shown in figure
34. For memory type and capacity values refer to Manufacturer and Device Identification table. The
JEDEC ID can be read continuously. The instruction is terminated by driving/CS high.
/CS
1
0
Mode 3
2
4
3
5
6
8
7
9
10
11
12
13
14
15
CLK
Mode 0
Instruction
9Fh
DI
Manufacturer ID
High - Z
DO
F8h
/CS
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
CLK
DI
Memory Type ID7 - 0
DO
42h
Capacity Type ID7 - 0
17h
Figure 34a. Read JEDEC ID instruction (SPI Mode)
Figure 34b. Read JEDEC ID instruction (QPI Mode)
Rev.03 (August.30.2011)
59
10.35 Enable QPI (38h)
The FM25M64A support both Standard/Dual/Quad Serial Peripheral interface (SPI) and Quad
Peripheral Interface (QPI). However, SPI mode and QPI mode cannot be used at the same time.
Enable QPI instruction is the only way to switch the device from SPI mode to QPI mode.
In order to switch the device to QPI mode, the Quad Enable (QE) bit in Status Register 2 must be
set to 1 first, and an Enable QPI instruction must be issued. If the Quad Enable (QE) bit is 0, the
Enable QPI instruction will be ignored and the device will remain in SPI mode.
After power-up, the default state of the device is SPI mode. See the instruction Set Table 1-3 for all
the commands supported in SPI mode and the instruction Set Table 4 for all the instructions
supported in QPI mode.
When the device is switched from SPI mode to QPI mode, the existing Write Enable and
Program/Erase Suspend status, and the Wrap Length setting will remain unchanged.
Figure 35. Enable QPI instruction (SPI Mode only)
10.36 Disable QPI (FFh)
By issuing Disable QPI (FFh) instruction, the device is reset SPI mode. When the device is
switched from QPI mode to SPI mode, the existing Write Enable Latch (WEL) and Program/Erase
Suspend status, and the Wrap Length setting will remain unchanged.
Figure 36. Disable QPI instruction for QPI mode
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60
10.37 Word Read Quad I/O (E7h)
The Quad I/O dramatically reduces instruction overhead allowing faster random access for code
execution (XIP) directly from the Quad SPI. The Quad Enable bit (QE) of Status Register-2 must
be set to enable the Word Read Quad I/O instruction. The lowest Address bit (A0) must equal 0
and only two dummy clocks are required prior to the data output.
Continuous Read Mode
The Word Read Quad I/O instruction can further reduce instruction overhead through setting the
“Continuous Read Mode” bits (M7-0) after the input Address bits (A23-0), as shown in Figure 37a.
The upper nibble of the (M7-4) controls the length of the next Word Read Quad I/O instruction
through the inclusion or exclusion of the first byte instruction code. The lower nibble bits of the
(M[3:0]) are don’t care (“X”). However, the IO pins should be high-impedance prior to the falling
edge of the first data out clock.
If the “Continuous Read Mode” bits M[7-4]= Ah, then the next Fast Read Quad I/O instruction (after
/CS is raised and then lowered) does not require the E7h instruction code, as shown in Figure 37b.
This reduces the instruction sequence by eight clocks and allows the Read address to be
immediately entered after /CS is asserted low. If the “Continuous Read Mode” bits M[7:4] do not
equal to Ah(1,0,1,0) the next instruction (after /CS is raised and then lowered) requires the first
byte instruction code, thus returning to normal operation.
≈
≈
≈ ≈≈ ≈ ≈ ≈≈ ≈
Figure 37a. Word Read Quad I/O instruction (Initial instruction or previous set M7-0 ≠ Axh, SPI Mode)
≈
≈
≈ ≈≈ ≈ ≈ ≈≈ ≈
Figure 37b. Word Read Quad I/O instruction (Previous instruction set M7-0= Axh, SPI Mode)
Rev.03 (August.30.2011)
61
Wrap Around in SPI mode
The Word Read Quad I/O instruction can also be used to access a specific portion within a page
by issuing a “Set Burst with Wrap” (77h) instruction prior to E7h. The “Set Burst with Wrap” (77h)
instruction can either enable or disable the “Wrap Around” feature for the following E7h commands.
When “Wrap Around” is enabled, the output data starts at the initial address specified in the
instruction, once it reaches the ending boundary of the 8/16/32/64-byte section, the output will
wrap around to the beginning boundary automatically until /CS is pulled high to terminate the
instruction.
The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address
and then fill the cache afterwards within a fixed length (8/16/32/64-byte) of data without issuing
read instructions.
The “Set Burst with Wrap” instruction allows three “Wrap Bits”, W6-4 to be set. The W4 bit is used
to enable or disable the “Wrap Around” operation while W6-5 is used to specify the length of the
wrap around section within a page. See 10.36 for detail descriptions.
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10.38 Set Burst with Wrap (77h)
The Set Burst with Wrap (77h) instruction is used in conjunction with “Fast Read Quad I/O” and
“Word Read Quad I/O” instructions to access a fixed length of 8/16/32/64-byte section within a
256-byte page. Certain applications can benefit from this feature and improve the overall system
code execution performance. Before the device will accept the Set Burst with Wrap instruction, a
Quad enable of Status Register-2 must be executed (Status Register bit QE must equal 1).
The Set Burst with Wrap instruction is initiated by driving the /CS pin low and then shifting the
instruction code “77h” followed by 24 dummy bits and 8 “Wrap Bits”, W7-0. The instruction
sequence is shown in Set Burst with Wrap Instruction Sequence. Wrap bit W7 and W3-0 are not
used.
W4 = 0
W6, W5
W4 = 1(Default)
Wrap Around
Wrap Length
Wrap Around
Wrap Length
0
0
Yes
8-byte
No
N/A
0
1
Yes
16-byte
No
N/A
1
0
Yes
32-byte
No
N/A
1
1
Yes
64-byte
No
N/A
Once W6-4 is set by a Set Burst with Wrap instruction, all the following “Fast Read Quad I/O” and
Word Read Quad I/O instructions will use the W6-4 setting to access the 8/16/32/64-byte section
within any page. To exit the “Wrap Around” function and return to normal read operation, another
Set Burst with Wrap instruction should be issued to set W4 = 1. The default value of W4 upon
power on is 1. In the case of a system Reset while W4 = 0, it is recommended that the controller
issues a Set Burst with Wrap instruction or Reset (99h) instruction to reset W4 = 1 prior to any
normal Read instructions since FM25M64A does not have a hardware Reset Pin.
Figure 38. Set Burst with Wrap Instruction Sequence
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63
10.39 Burst Read with Wrap (0Ch)
The “Burst Read with Wrap (0Ch)” instruction provides an alternative way to perform the read
operation with “Wrap Around” in QPI mode. The instruction is similar to the “Fast Read (0Bh)”
instruction in QPI mode, except the addressing of the read operation will “Wrap Around” to the
beginning boundary of the “Wrap Length” once the ending boundary is reached.
The “Wrap Length” and the number of dummy of clocks can be configured by the “Set Read
Parameters (C0h)” instruction.
≈
≈
≈ ≈≈ ≈ ≈ ≈≈ ≈
Figure 39a. Burst Read with Wrap instruction (QPI Mode, 80MHz)
≈
≈
≈ ≈≈ ≈ ≈ ≈≈ ≈
Figure 39b. Burst Read with Wrap instruction (QPI Mode, 104MHz)
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10.40 Set Read Parameters (C0h)
In QPI mode, to accommodate a wide range of applications with different needs for either
maximum read frequency or minimum data access latency, “Set Read Parameters (C0h)”
instruction can be used to configure the number of dummy clocks for “Fast Read (0Bh)”, “Fast
Read Quad I/O (EBh)” & “Burst Raed with Wrap (0Ch)” instructions, and to configure the number
of bytes of “Wrap Length” for the “Burst Read with Wrap (0Ch)” instruction.
In Standard SPI mode, the “Set Read Parameters (C0h)” instruction is not accepted. The dummy
clocks for various Fast Read instructions in Standard/Dual/Quad SPI mode are fixed, please refer
to the instruction. Table 10.2 - 10.5 for details. The “Wrap Length” is set by W6-5 bit in the “Set
Burst with Wrap (77h)” instruction. This setting will remain unchanged when the device is switched
from Standard SPI mode to QPI mode.
The default “Wrap Length” after a power up or a Reset instruction is 8 bytes, the default number of
dummy clocks is 4.
P4
0
1
DUMMY
CLOCKS
4
6
Maximum READ
FREQ.
80MHz
104MHz
1 0
1 1
P1 – P0
0
0
0
1
WRAP
LENGTH
8-byte
16-byte
32-byte
64-byte
Figure 40. Set Read Parameters instruction (QPI Mode)
Rev.03 (August.30.2011)
65
10.41 Enable Reset (66h) and Reset (99h)
Because of the small package and the limitation on the number of pins, the FM25M64A provide a
software Reset instruction instead of a dedicated RESET pin.
Once the Reset instruction is accepted, any on-going internal operations will be terminated and the
device will return to its default power-on state and lose all the current volatile settings, such as
Volatile Status Register bits, Write Enable Latch (WEL) status, Program/Erase Suspend status,
Continuous Read Mode bit setting, Read parameter setting and Wrap bit setting.
“Enable Reset (66h)” and “Reset (99h)” instructions can be issued in either SPI mode or QPI mode.
To avoid accidental reset, both instructions must be issued in sequence. Any other instructions
other than “Reset (99h)” after the “Enable (66h)” instruction will disable the “Reset Enable” state. A
new sequence of “Enable Reset (66h)” and “Reset (99h)” is needed to reset the device. Once the
Reset instruction is accepted by the device will take approximately tRST= 30us to reset. During
this period, no instruction will be accepted.
Data corruption may happen if there is an on-going or suspended internal Erase or Program
operation when Reset instruction sequence is accepted by device. It is recommended to check the
BUSY bit and the SUS bit in Status Register before issuing the Reset instruction sequence.
Figure 41a. Enable Reset and Reset Instruction (SPI Mode)
Figure 41b. Enable Reset and Reset Instruction (QPI Mode)
Rev.03 (August.30.2011)
66
10.42 Read Serial Flash Discovery Parameter (5Ah)
The Read Serial Flash Discovery Parameter (SFDP) instruction allows reading the Serial Flash
Discovery Parameter area (SFDP). This SFDP area is composed of 2048 read-only bytes
containing operating characteristics and vendor specific information. The SFDP area is factory
programmed. If the SFDP area is blank, the device is shipped with all the SFDP bytes at FFh. If
only a portion of the SFDP area is written to, the portion not used is shipped with bytes in erased
state (FFh). The instruction sequence for the read SFDP has the same structure as that of a Fast
Read instruction. First, the device is selected by driving Chip Select (/CS) Low. Next, the 8-bit
instruction code (5Ah) and the 24-bit address are shifted in, followed by 8 dummy clock cycles. The
bytes of SFDP content are shifted out on the Serial Data Output (DO) starting from the specified
address. Each bit is shifted out during the falling edge of Serial Clock (CLK). The instruction
sequence is shown here. The Read SFDP instruction is terminated by driving Chip Select (/CS)
High at any time during data output.
≈
≈
≈ ≈ ≈≈
Figure 42. Read SFDP Register Instruction
Rev.03 (August.30.2011)
67
Read Serial Flash Discovery Parameter (SFDP)
BYTE
DATA
DESCRIPTION
COMMENT
ADDRESS
00h
53h
SFDP Signature
01h
46h
SFDP Signature
SFDP Signature
02h
44h
SFDP Signature
=50444653h
03h
50h
SFDP Signature
04h
01h
SFDP Minor Revisions
05h
01h
SFDP Major Revisions
06h
00h
Number of Parameter Header(NPH)
07h
FFh
Reserved
08h
F8h
PID(0)
09h
00h
PID(0) : Serial Flash Basics Minor Revisions
Serial Flash Basics
0Ah
01h
PID(0) : Serial Flash Basics Major Revisions
Revision 1.0
0Bh
04h
PID(0) : Serial Flash Basics Length
4 Dwords
0Ch
80h
PID(0) : Address of Parameter ID(0) Table (A7-A0)
0Dh
00h
PID(0) : Address of Parameter ID(0) Table (A15-A8)
0Eh
00h
PID(0) : Address of Parameter ID(0) Table (A23-A16)
0Fh
FFh
Reserved
10h
F8h
PID(1) : Manufacture JEDEC ID
11h
00h
PID(1) : Serial Flash Properties Minor Revisions
Serial Flash Basics
12h
01h
PID(1) : Serial Flash Properties Major Revisions
Revision 1.0
13h
00h
PID(1) : Serial Flash Properties Length
14h
90h
PID(1) : Address of Parameter ID(0) Table (A7-A0)
15h
00h
PID(1) : Address of Parameter ID(0) Table (A15-A8)
16h
00h
PID(1) : Address of Parameter ID(0) Table (A23-A16)
17h
FFh
Reserved
(1)
FFh
Reserved
80h
E5h
Bit[7:5] = 111
Reserved
Bit[4:3] = 00
Non-volatile Status Register
Bit[2] = 1
Page Programmable
Bit[1:0] = 01
Support 4KB Erase
SFDP revision 1.1
(3)
1 Parameter Header
: Manufacture JEDEC ID
F8h = Fidelix
(2)
PID(0) Table Address
= 000080h
F8h = Fidelix
00h = Unimplemented
PID(1) Table Address
= 000090h
...
Rev.03 (August.30.2011)
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Read Serial Flash Discovery Parameter (SFDP) (cont’d)
BYTE
DATA
DESCRIPTION
COMMENT
ADDRESS
81h
82h
20h
F1h
4K-Byte Erase Opcode
Bit[7] = 1
Reserved
Bit[6] = 1
Supports Single Input Quad Output
Bit[5] = 1
Supports Quad Input Quad Output
Bit[4] = 1
Supports Dual Input Dual Output
Bit[3] = 0
Dual Transfer Rate not Supported
Bit[2:1] = 00
3-Byte/24-Bit Addressing
Bit[1] = 1
Supports Single Input Dual Output
83h
FFh
Reserved
84h
FFh
Flash Size in Bits
85h
FFh
Flash Size in Bits
64 Mega Bits =
86h
FFh
Flash Size in Bits
03FFFFFFh
87h
01h
Flash Size in Bits
88h
44h
89h
EBh
8Ah
08h
8Bh
6Bh
8Ch
08h
8Dh
3Bh
8Eh
80h
Bit[7:5] = 010
8 Mode Bits are needed
Fast Read
Bit[4:0] = 00100
16 Dummy Bits are needed
Quad I/O
Bit[7:5] = 000
No Mode Bits are needed
Fast Read
Bit[4:0] = 01000
8 Dummy Bits are needed
Quad Output
Setting
Single Input Quad Output Fast Read Opcode
Bit[7:5] = 000
No Mode Bits are needed
Fast Read
Bit[4:0] = 01000
8 Dummy Bits are needed
Dual Output
Setting
Single Input Dual Output Fast Read Opcode
Bit[7:5] = 100
8 Mode Bits are needed
Bit[4:0] = 00000
No Dummy Bits are needed
8Fh
BBh
Dual Input Dual Output Fast Read Opcode
(1)
FFh
Reserved
EFh
FFh
Reserved
F0h-FFh
xxh
Reserved
...
Setting
Quad Input Quad Output Fast Read Opcode
Fast Read
Dual I/O
Setting
Notes:
1. Data stored in Byte Address 18h to 7Fh & 90h to FFh are reserved, the value is FFh.
Rev.03 (August.30.2011)
69
2. 1 Dword = 4 Bytes.
3. PID(x) = Parameter Identification Table(x)
10. 43 Enter Secured OTP (B1h)
The Enter Secured OTP instruction is for entering the additional 4K-bit secured OTP mode. The
additional 4K-bit secured OTP is independent from main array, which may be used to store unique
serial number for system identifier. After entering the Secured OTP mode, and then follow standard
read or program, procedure to read out the data or update data. The Secured OTP data cannot be
updated again once it is lock-down
Please note that Write Status Register-1, Write Status Register-2 and Write Security Register
instructions are not acceptable during the access of secure OTP region. Once security OTP is lock
down, only commands related with read are valid.
The Enter Secured OTP instruction sequence is shown in figure 43.
Figure 43. Enter Secured OTP instruction for SPI Mode (left) and QPI Mode (right)
10.44 Exit Secured OTP (C1h)
The Exit Secured OTP instruction is for exiting the additional 4K-bit secured OTP mode.
(Please refer to figure 44).
Figure 44. Exit Secured OTP instruction for SPI Mode (left) and QPI Mode (right)
Rev.03 (August.30.2011)
70
10.45 Read Security Register (2Bh)
The Read Security Register can be read the value of Security Register bits at any time (even in
program/erase/write status register-1 and write status register-2 condition) and continuously.
Secured OTP Indicator bit. The Secured OTP indicator bit shows the chip is locked by factory
before ex-factory or not. When it is “0”, it indicates non-factory lock, “1” indicates factory-lock.
Lock-down Secured OTP (LDSO) bit. By writing Write Security Register instruction, the LDSO bit
may be set to “1” for customer lock-down purpose. However, once the bit it set to “1” (Lock-down),
the LDSO bit and the 4K-bit Secured OTP area cannot be updated any more. While it is in 4K-bit
Secured OTP mode, array access is not allowed to write.
Security Register Definition
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
x
x
x
x
x
x
reserved
reserved
reserved
reserved
reserved
reserved
Volatile
bit
Volatile
bit
Volatile
bit
Volatile
bit
Volatile
bit
Volatile
bit
Bit1
LDSO
(indicate if
lockdown)
0 = not
lock-down
1 = lockdown(can
not
program/e
rase OTP)
NonVolatile bit
Bit0
Secured
OTP
indicator
bit
0 = non
factory
lock
1 = factory
lock
NonVolatile bit
≈
≈
≈ ≈ ≈ ≈
Figure 45a. Read Security Register instruction (SPI Mode)
Figure 45b. Read Security Register instruction (QPI Mode)
Rev.03 (August.30.2011)
71
10.46 Write Security Register (2Fh)
The Write Security Register instruction is for changing the values of Security Register bits. Unlike
Write Status Register, the Write Enable instruction is not required before writing Write Security
Register instruction. The Write Security Register instruction may change the value of bit1 (LDSO
bit) for customer to lock-down the 4K-bit Secured OTP area. Once the LDSO bit is set to “1”, the
Secured OTP area cannot be updated any more.
The /CS must go high exactly at the boundary; otherwise, the instruction will be rejected and not
executed.
Figure 46. Write Security Register instruction for SPI Mode (left) and QPI Mode (right)
Rev.03 (August.30.2011)
72
11. 4K-bit Secured OTP
It’s for unique identifier to provide 4K-bit one-time-program area for setting device unique serial
number which may be set by factory or system customer. Please refer to table of “4K-bit secured
OTP definition”.
- Security register bit 0 indicates whether the chip is locked by factory or not.
- To program the 4K-bit secured OTP by entering 4K-bit secured OTP mode (with ENSO
command) and going through normal program procedure, and then exiting 4K-bit secured OTP
mode by writing EXSO command
- Customer may lock-down bit1 as “1”. Please refer to “table of security register definition” for
security register bit definition and table of “4K-bit secured OTP definition” for address range
definition.
- Note. Once lock-down whatever by factory or customer, it cannot be changed any more. While
in 4K-bit secured OTP mode, array access is not allowed to write.
4K-bit secured OTP definition
Address range
Size
000000 ~ 00000F
128-bit
000010 ~ 0001FF
3968-bit
Standard
Factory Lock
ESN
(Electrical Serial Number)
Customer Lock
Determined by customer
N/A
Rev.03 (August.30.2011)
73
12. ELECTRICAL CHARACTERISTICS
12.1 Absolute Maximum Ratings (1)
PARAMETERS
SYMBOL
Supply Voltage
VCC
Voltage Applied to Any Pin
VIO
Transient Voltage on any Pin
VIOT
CONDITIONS
RANGE
UNIT
-0.6 to VCC+0.4
V
Relative to Ground
-0.6 to VCC +0.4
V
<20nS Transient
-1.0V to VCC +1.0V
V
˚C
Relative to Ground
Storage Temperature
TSTG
-65
Lead Temperature
TLEAD
See Note
˚C
Electrostatic Discharge
VESD
-2000 to +2000
V
Voltage
to +150
(2)
Human
Body Model
(3)
Notes:
1. This device has been designed and tested for the specified operation ranges. Proper operation
outside of these levels is not guaranteed. Exposure to absolute maximum ratings may affect
device reliability. Exposure beyond absolute maximum ratings may cause permanent damage.
2. Compliant with JEDEC Standard J-STD-20C for small body Sn-Pb or Pb-free (Green) assembly
and the European directive on restrictions on hazardous substances (RoHS) 2002/95/EU.
3. JEDEC Std JESD22-A114A (C1=100pF, R1=1500 ohms, R2=500 ohms).
12.2 Operating Ranges
PARAMETER
SYMBOL
Erase/Program
CONDITIONS
MIN
MAX
UNIT
1.65
1.95
V
-40
+85
˚C
FR = 104MHz (Single/Dual/Quad SPI)
VCC
Cycles
fR = 50MHz (Read Data 03h)
Temperature,Op
Tj
Industrial
erating
12.3 Endurance and Data Retention
PARAMETER
CONDITIONS
Erase/Program Cycles
4KB sector, 32/64KB block or full chip.
Data Retention
Full Temperature Range
MIN
MAX
100,000
UNIT
Cycles
20
years
Rev.03 (August.30.2011)
74
12.4 Power-up Timing and Write Inhibit Threshold
PARAMETER
SPEC
SYMBOL
MIN
VCC(min) to /CS Low
tVSL
(1)
Time Delay Before Write Instruction
tPUW
Write Inhibit Threshold Voltage
VWI
(1)
(1)
UNIT
MAX
㎲
10
1
10
㎳
1.0
1.4
V
Note:
1. These parameters are characterized only.
Figure 47. Power-up Timing and Voltage Levels
Rev.03 (August.30.2011)
75
12.5 DC Electrical Characteristics
PARAMETER
SYMBOL
SPEC
CONDITION
MIN
Input Capacitance
(1)
TYP
(2)
CIN
VIN=0V
(1)
(2)
6
㎊
8
㎊
Output Capacitance
COUT
Input Leakage
ILI
±2
㎂
I/O Leakage
ILO
±2
㎂
10
50
㎂
3
20
㎂
15
㎃
20
㎃
30
㎃
40
㎃
Standby Current
VOUT=0V
UNIT
MAX
/CS=VCC, /RST= VCC
ICC1
VIN=GND or VCC
Power-down Current
/CS=VCC, /RST= VCC
ICC2
VIN=GND or VCC
Current Read Data/
C=0.1 VCC / 0.9VCC
ICC3
(2)
Dual/Quad 1㎒
IO=Open
Current Read Data/
(2)
C=0.1 VCC / 0.9VCC
ICC3
Dual/Quad 50㎒
IO=Open
Current Read Data/
(2)
C=0.1 VCC / 0.9VCC
ICC3
Dual/Quad 80㎒
IO=Open
Current Read Data/
(2)
C=0.1 VCC / 0.9VCC
ICC3
Dual/Quad 104㎒
IO=Open
Current Write
ICC4
/CS=VCC, /RST= VCC
10
18
㎃
ICC5
/CS=VCC, /RST= VCC
20
25
㎃
ICC6
/CS=VCC, /RST= VCC
20
25
㎃
Current Chip Erase
ICC7
/CS=VCC, /RST= VCC
20
25
㎃
Input Low Voltages
VIL
-0.5
VCC x0.2
V
Input High Voltages
VIH
VCC x0.8
VCC +0.4
V
Output Low Voltages
VOL
IOL= 100㎂
0.2
V
VOH
IOH=-100㎂
Status Register
Current page
Program
Current Sector/Block
Erase
Output
VCC -0.2
V
High Voltages
Notes:
1. Tested on sample basis and specified through design and characterization data, TA = 25˚C, VCC
= 1.8V.
2. Checked Board Pattern.
Rev.03 (August.30.2011)
76
12.6 AC Measurement Conditions
PARAMETER
SPEC
SYMBOL
MIN
Load Capacitance
Input Rise and Fall Times
UNIT
MAX
CL
30
㎊
TR, TF
5
㎱
Input Pulse Voltages
VIN
0.2 VCC to 0.8 VCC
V
Input Timing Reference Voltages
IN
0.3 VCC to 0.7 VCC
V
OUT
0.5 VCC to 0.5 VCC
V
Output Timing Reference Voltages
Note:
1.
Output Hi-Z is defined as the point where data out is no longer driven.
Figure 48. AC Measurement I/O Waveform
Rev.03 (August.30.2011)
77
12.7 AC Electrical Characteristics
DESCRIPTION
SYMBOL
SPEC
ALT
MIN
TYP
UNIT
MAX
Clock frequency
For all instructions, except Read Data (03h)
D.C.
104
㎒
fR
D.C.
50
㎒
tCLH,
4.5
㎱
8
㎱
(2)
0.1
V/㎱
(2)
0.1
V/㎱
5
㎱
5
㎱
FR
fc
1.65V-1.95V VCC & Industrial Temperature
Clock freq. Read Data instruction (03h)
Clock High, Low Time except Read Data (03h)
tCLL
(1)
Clock High, Low Time for Read Data (03h)
tCRLH,
instructions
tCRLL
Clock Rise Time peak to peak
tCLCH
Clock Fall Time peak to peak
(1)
tCHCL
/CS Active Setup Time relative to CLK
tSLCH
tCSS
/CS Not Active Hold Time relative to CLK
tCHSL
Data In Setup Time
tDVCH
tDSU
2
㎱
Data In Hold Time
tCHDX
tDH
5
㎱
/CS Active Hold Time relative to CLK
tCHSH
5
㎱
/CS Not Active Setup Time relative to CLK
tSHCH
5
㎱
/CS Deselect Time (for Read instructions/ Write,
tSHSL
10/50
㎱
tCSH
Erase and Program instructions)
(2)
tDIS
7
㎱
tCLQV
tV1
7
㎱
tCLQV
tV2
8
㎱
Output Hold Time
tCLQX
tHO
/Hold Active Setup Time relative to CLK
tHLCH
Output Disable Time
tSHQZ
Clock Low to Output Valid
Clock Low to Output Valid ( Except Main Read )
(3)
0
㎱
5
㎱
Rev.03 (August.30.2011)
78
12.8 AC Electrical Characteristics (cont’d)
DESCRIPTION
SYMBOL
SPEC
ALT
MIN
TYP
UNIT
MAX
/HOLD Active Hold Time relative to CLK
tCHHH
5
㎱
/HOLD Not Active Setup Time relative to CLK
tHHCH
5
㎱
/HOLD Not Active Hold Time relative to CLK
tCHHL
5
㎱
/HOLD to Output Low-Z
/HOLD to Output High-Z
(2)
tLZ
7
㎱
(2)
tHZ
12
㎱
tHHQX
tHLQZ
(4)
20
㎱
(4)
100
㎱
500
ns
Write Protect Setup Time Before /CS Low
tWHSL
Write Protect Setup Time After /CS High
tSHWL
/RST pulse width
/CS High to Power-down Mode
/CS High to Standby Mode without Electronic
tRP
tDP
(2)
3
㎲
tRES1
(2)
3
㎲
tRES2
(2)
1.8
㎲
(2)
20
㎲
(2)
30
㎲
Signature Read
/CS High to Standby Mode with Electronic
Signature Read
/CS High to next Instruction after Suspend
CS High to next Instruction after Reset
tSUS
tRST
Write Status Register Time
tw
10
15
㎳
Byte Program Time
tBP
10
150
㎲
Page Program Time
tPP
1.5
5
㎳
Sector Erase Time(4KB)
tSE
40
300
㎳
Block Erase Time(32KB)
tBE1
200
1000
㎳
Block Erase Time(64KB)
tBE2
300
1500
㎳
Chip Erase Time
tCE
32
160
s
Notes:
1. Clock high + Clock low must be less than or equal to 1/fc.
2. Value guaranteed by design and/or characterization, not 100% tested in production.
3. Contains: Read Status Register-1,2/ Read Manufacturer/Device ID, Dual, Quad/ Read JEDEC
ID/ Read Security Register/ Read Serial Flash Discovery Parameter.
4. Only applicable as a constraint for a Write Status Register instruction when Sector Protect Bit is
set to 1.
5. Commercial temperature only applies to Fast Read (FR). Industrial temperature applies to all
other parameters.
Rev.03 (August.30.2011)
79
12.9 Input Timing
12.10 Output Timing
12.11 Hold Timing
12.12 RST Timing
Rev.03 (August.30.2011)
80
13. PACKAGE SPECIFICATION
13.1 8-Pin SOIC 208-mil
MILLIMETERS
INCHES
SYMBOL
MIN
MAX
MIN
MAX
A
1.75
2.16
0.069
0.085
A1
0.05
0.25
0.002
0.010
A2
1.70
1.91
0.067
0.075
b
0.35
0.48
0.014
0.019
C
0.19
0.25
0.007
0.010
D
5.18
5.38
0.204
0.212
E
7.70
8.10
0.303
0.319
E1
5.18
5.38
0.204
0.212
e
1.27 BSC
0.050 BSC
L
0.50
0.80
0.020
0.031
θ
0˚
8˚
0˚
8˚
y
---
0.10
---
0.004
Notes:
1. Controlling dimensions: inches, unless otherwise specified.
2. BSC = Basic lead spacing between centers.
3. Dimensions D and E1 do not include mold flash protrusions and should be measured from the
bottom of the package.
4. Formed leads shall be planar with respect to one another within. 0.004 inches at the seating
plane.
Rev.03 (August.30.2011)
81
13.2 8-Pin VSOP 208-mil
MILLIMETERS
INCHES
SYMBOL
MIN
TYP.
MAX
IN
TYP.
MAX
A
---
---
1.00
---
---
0.039
A1
0.05
0.10
0.15
0.002
0.004
0.006
A2
0.75
0.80
0.85
0.030
0.031
0.033
b
0.35
0.42
0.48
0.014
0.017
0.019
c
0.127 REF.
0.005 REF.
D
5.18
5.28
5.38
0.204
0.208
0.212
E
7.70
7.90
8.10
0.303
0.311
0.319
E1
5.18
5.28
5.38
0.204
0.208
0.212
e
---
1.27
---
---
0.050
---
L
0.50
0.65
0.80
0.020
0.026
0.031
y
---
---
0.10
---
---
0.004
θ
0˚
---
8˚
0˚
---
8˚
Notes:
1. JEDEC outline: N/A.
2. Dimension “D”, “D1” does not include mold flash, mold flash shall not exceed 0.006 [0.15mm]
per end. Dimension “E”, “E1” does not include inter lead flash. Inter lead flash shall not exceed
0.010 [0.25mm] per side.
3. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.003
[0.08mm].
Rev.03 (August.30.2011)
82
13.3 8-Pin PDIP 300-mil
Dimension in inch
Dimension in min
SYMBOL
MIN
Nom
MAX
MIN
Nom
MAX
A
---
---
0.210
---
---
5.334
A1
0.015
---
---
0.381
---
---
A2
0.125
0.130
0.135
3.18
3.30
3.43
B
0.016
0.018
0.022
0.41
0.46
0.56
B1
0.058
0.060
0.064
1.47
1.52
1.63
c
0.008
0.010
0.014
0.20
0.25
0.36
D
0.360
0.365
0.370
9.14
9.27
9.40
E
0.290
0.300
0.310
7.37
7.62
7.87
E1
0.245
0.250
0.255
6.22
6.35
6.48
e1
0.090
0.100
0.110
2.29
2.54
2.79
L
0.120
0.130
0.140
3.05
3.30
3.56
α
0
---
15
0
---
15
eA
0.335
0.355
0.375
8.51
9.02
9.53
S
---
---
0.045
---
---
1.14
Rev.03 (August.30.2011)
83
13.4 8-contact 6x5 WSON
MILLIMETERS
SYMBOL
MIN
TYP.
INCHES
MAX
TYP.
MAX
IN
A
0.70
0.75
0.80
0.0276
0.0295
0.0315
A1
0.00
0.02
0.05
0.0000
0.0008
0.0019
0.55
0.0126
2
A3
0.19
0.20
0.25
0.0075
0.0080
0.0098
b
0.36
0.40
0.48
0.0138
0.0157
0.0190
(3)
D
5.90
6.00
6.10
0.2320
0.2360
0.2400
D1
3.30
3.40
3.50
0.1299
0.1338
0.1377
E
4.90
5.00
5.10
0.1930
0.1970
0.2010
4.20
4.30
4.40
0.1653
0.1692
0.1732
E1
e
(3)
(2)
1.27 BSC
K
0.20
L
0.50
0.0500 BSC
0.0080
0.60
0.75
0.0197
0.0236
0.0295
Rev.03 (August.30.2011)
84
13.5 8-contact 6x5 WSON (cont’d)
MILLIMETERS
INCHES
SYMBOL
MIN
TYP.
MAX
MIN
TYP.
MAX
SOLDER PATTERN
M
3.40
0.1338
N
4.30
0.1692
P
6.00
0.2360
Q
0.50
0.0196
R
0.75
0.0255
Notes:
1. Advanced Packaging Information; please contact Fidelix Co., Ltd. for the latest minimum and
maximum specifications.
2. BSC = Basic lead spacing between centers.
3. Dimensions D and E1 do not include mold flash protrusions and should be measured from the bottom
of the package.
4. The metal pad area on the bottom center of the package is connected to the device ground (GND
pin). Avoid placement of exposed PCB bias under the pad.
Rev.03 (August.30.2011)
85
13.6 16-Pin SOIC 300-mil
MILLIMETERS
INCHES
SYMBOL
MIN
MAX
MIN
MAX
A
2.36
2.64
0.093
0.104
A1
0.10
0.30
0.005
0.012
b
0.33
0.51
0.013
0.020
C
0.18
0.28
0.007
0.000
10.08
10.49
0.397
0.413
10.01
10.64
0.394
0.419
7.39
7.59
0.291
0.299
(3)
D
E
E1
e
(3)
(2)
1.27BSC
0.050
L
0.39
1.27
0.015
0.050
θ
0˚
8˚
0˚
8˚
y
---
0.076
---
0.003
Notes:
1. Controlling dimensions: inches, unless otherwise specified.
2. BSC = Basic lead spacing between centers.
3. Dimensions D and E1 do not include mold flash protrusions and should be measured from the
bottom of the package.
Rev.03 (August.30.2011)
86
14. ORDERING INFORMATION
FM XXXXX X - X X X X X X
Fidelix
Memory
Packing Type
Product Family
T : Tube (Standard)
R : Tape and Reel
Y : Tray
* Package NO Marking
25 : SPI
Business Package Type
Organization
1 : 8 Pin 208 mil SOIC
S : Single
D : Dual
- 3.0V
- 3.0V
2 : 16 Pin 300 mil SOIC
Q : Quad
- 3.0V
4 : 8 Contact 6x5 WSON
Y : Single
- 1.8V
5 : 8 Pin 150 mil SOIC
E : Dual
- 1.8V
M : Quad
- 1.8V
6 : 8 Contact 8x6 WSON
7 : 8 Pin VSOP
W : Wafer
3 : 8 Pin 300 mil PDIP
Core / IO Voltage
Device Depth
04 : 4M
08 : 8M
16 : 16M
32 : 32M
64 : 64M
4A : 128M
A : 3.0V / 3.0V
B : 1.8V / 1.8V
Temperature
I (Industrial)
C (Commercial) :
Generation
Speed
A : 1st
85 : 85MHz
1A : 104MHz
B : 2nd
: -40℃~85℃
C : 3rd
Rev.03 (August.30.2011)
87
0℃~70℃