http://www.elm-tech.com GD25Q32C DATASHEET GD25Q32CxIGx 3.3V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com - Content 1. FEATURES Page ------------------------------------------------------------------------------------------------- 2. GENERAL DESCRIPTION 4 ----------------------------------------------------------------------------- 5 -------------------------------------------------------------------------- 6 4. DEVICE OPERATION ---------------------------------------------------------------------------------- 7 5. DATA PROTECTION ------------------------------------------------------------------------------------ 8 6. STATUS REGISTER ------------------------------------------------------------------------------------- 10 3. MEMORY ORGANIZATION 7. COMMANDS DESCRIPTION ------------------------------------------------------------------------- 12 7.1. Write Enable (WREN) (06H) ----------------------------------------------------------------------- 15 7.2. Write Disable (WRDI) (04H) ----------------------------------------------------------------------- 15 7.3. Write Enable for Volatile Status Register (50H) -------------------------------------------------- 15 7.4. Read Status Register (RDSR) (05H or 35H or 15H) -------------------------------------------- 16 7.5. Write Status Register (WRSR) (01H or 31H or 11H) ------------------------------------------- 16 -------------------------------------------------------------------- 17 7.6. Read Data Bytes (READ) (03H) 7.7. Read Data Bytes at Higher Speed (Fast Read) (0BH) ------------------------------------------- 17 7.8. Dual Output Fast Read (3BH) ---------------------------------------------------------------------- 18 7.9. Quad Output Fast Read (6BH) ---------------------------------------------------------------------- 19 7.10. Dual I/O Fast Read (BBH) ------------------------------------------------------------------------- 19 7.11. Quad I/O Fast Read (EBH) ------------------------------------------------------------------------- 20 7.12. Quad I/O Word Fast Read (E7H) ------------------------------------------------------------------ 22 7.13. Set Burst with Wrap (77H) -------------------------------------------------------------------------- 23 7.14. Page Program (PP) (02H) --------------------------------------------------------------------------- 24 7.15. Quad Page Program (32H) -------------------------------------------------------------------------- 25 7.16 Fast Page Program (FPP) (F2H) 7.17. Sector Erase (SE) (20H) -------------------------------------------------------------------- 26 ----------------------------------------------------------------------------- 27 7.18. 32KB Block Erase (BE) (52H) --------------------------------------------------------------------- 28 7.19. 64KB Block Erase (BE) (D8H) --------------------------------------------------------------------- 28 -------------------------------------------------------------------------- 29 --------------------------------------------------------------------- 29 7.20. Chip Erase (CE) (60/C7H) 7.21. Deep Power-Down (DP) (B9H) 7.22. Release from Deep Power-Down or High Performance Mode and Read Device ID (RDI) (ABH) 30 7.23. Read Manufacture ID/Device ID (REMS) (90H) ------------------------------------------------- 31 7.24. Dual I/O Read Manufacture ID/Device ID (92H) ------------------------------------------------ 32 7.25. Quad I/O Read Manufacture ID/Device ID (94H) ----------------------------------------------- 32 ------------------------------------------------------------------ 33 7.26. Read Identification (RDID) (9FH) 50 - 2 Rev.1.0 GD25Q32CxIGx 3.3V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com 7.27. High Performance Mode (HPM) (A3H) ----------------------------------------------------------- 34 7.28. Program/Erase Suspend (PES) (75H) -------------------------------------------------------------- 34 7.29. Program/Erase Resume (PER) (7AH) -------------------------------------------------------------- 35 ---------------------------------------------------------------------- 35 ------------------------------------------------------------------ 36 ---------------------------------------------------------------------- 37 7.30. Erase Security Registers (44H) 7.31. Program Security Registers (42H) 7.32. Read Security Registers (48H) 7.33. Enable Reset (66H) and Reset (99H) --------------------------------------------------------------- 7.34. Read Serial Flash Discoverable Parameter (5AH) ------------------------------------------------ 38 --------------------------------------------------------------- 43 ------------------------------------------------------------------------------------- 43 ---------------------------------------------------------------------------------- 43 8. ELECTRICAL CHARACTERISTICS 8.1. Power-ON timing 38 8.2. Initial delivery state 8.3. Data retention and endurance 8.4. Absolute maximum ratings ----------------------------------------------------------------------- 43 ------------------------------------------------------------------------- 44 8.5. Capacitance measurement conditions ------------------------------------------------------------- 44 8.6. DC characteristics ----------------------------------------------------------------------------------- 45 8.7. AC characteristics ----------------------------------------------------------------------------------- 45 9. ORDERING INFORMATION ------------------------------------------------------------------------- 48 10. PACKAGE INFORMATION --------------------------------------------------------------------------- 49 ----------------------------------------------------------------------------- 49 ------------------------------------------------------------------------ 50 10.1. Package SOP8 208MIL 10.2. Package WSON8 (6×5MM) 50 - 3 Rev.1.0 GD25Q32CxIGx 3.3V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com 1. FEATURES ♦ 32M-bit Serial Flash ♦ Program/Erase Speed - 4096K-byte - 256 bytes per programmable page ♦ Standard, Dual, Quad SPI - Standard SPI: SCLK, CS#, SI, SO, WP#, HOLD# - Dual SPI: SCLK, CS#, IO0, IO1, WP#, HOLD# - Quad SPI: SCLK, CS#, IO0, IO1, IO2, IO3 ♦ High Speed Clock Frequency - 120MHz for fast read with 30PF load - Dual I/O Data transfer up to 240Mbits/s - Quad I/O Data transfer up to 480Mbits/s - Continuous Read With 8/16/32/64-byte Wrap ♦ Software/Hardware Write Protection - Write protect all/portion of memory via software - Enable/Disable protection with WP# pin - Top or Bottom, Sector or Block selection ♦ Cycling endurance - Minimum 100,000 Program/Erase Cycles ♦ Data retention - Page Program time: 0.6ms typical - Sector Erase time: 50ms typical - Block Erase time: 0.15/0.25s typical - Chip Erase time: 15s typical ♦ Flexible Architecture - Sector of 4K-byte - Block of 32/64K-byte ♦ Low Power Consumption - 20mA maximum active current - 5μA maximum power down current ♦ Advanced Security Features(1) - 3×1024-Byte Security Registers With OTP Locks - Discoverable parameters(SFDP) register ♦ Single Power Supply Voltage - Full voltage range: 2.7~3.6V ♦ Package Information - SOP8 (208mil) - WSON8 (6×5mm) - 20-year data retention typical. Note: (1) Please contact ELM for details. 50 - 4 Rev.1.0 GD25Q32CxIGx 3.3V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com 2. GENERAL DESCRIPTION The GD25Q32C(32M-bit) Serial flash supports the standard Serial Peripheral Interface (SPI), and supports the Dual/Quad SPI: Serial Clock, Chip Select, Serial Data I/O0 (SI), I/O1 (SO), I/O2 (WP#) and I/O3 (HOLD#). The Dual I/O data is transferred with speed of 240Mbits/s and the Quad I/O & Quad Output data is transferred with speed of 480Mbits/s. Connection Diagram 8-LEAD SOP 8-LEAD WSON Pin Description Pin Name I/O Description CS# SO (IO1) WP# (IO2) I I/O I/O Chip Select Input Data Output (Data Input Output 1) Write Protect Input (Data Input Output 2) VSS SI (IO0) I/O Ground Data Input (Data Input Output 0) SCLK I HOLD# (IO3) VCC I/O Serial Clock Input Hold Input (Data Input Output 3) Power Supply Block Diagram Write Control Logic Status Register HOLD#(IO3) SCLK CS# SPI Command & Control Logic High Voltage Generators Page Address Latch/Counter Write Protect Logic and Row Decode WP#(IO2) Flash Memory Column Decode And 256-Byte Page Buffer SI(IO0) SO(IO1) Byte Address Latch/Counter 50 - 5 Rev.1.0 GD25Q32CxIGx 3.3V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com 3. MEMORY ORGANIZATION GD25Q32C Each device has Each block has Each sector has Each page has 4M 64/32K 4K 256 bytes 16K 256/128 16 - pages 1024 16/8 - - sectors 64/128 - - - blocks Uniform Block Sector Architecture GD25Q32C 64K Bytes Block Sector Architecture Block Sector 63 1023 ----- 3FF000H ----- 3FFFFFH ----- 1008 1007 3F0000H 3EF000H 3F0FFFH 3EFFFFH 62 ----992 ----- ----3E0000H ----- ----3E0FFFH ----- ----- ------------- ------------- ------------- ----- --------47 --------02F000H --------02FFFFH 2 ----32 ----020000H ----020FFFH 31 01F000H 01FFFFH ----16 ----010000H ----010FFFH 15 ----0 00F000H ----000000H 00FFFFH ----000FFFH 1 0 Address range 50 - 6 Rev.1.0 GD25Q32CxIGx 3.3V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com 4. DEVICE OPERATION SPI Mode Standard SPI The GD25Q32C feature a serial peripheral interface on 4 signals bus: Serial Clock (SCLK), Chip Select (CS#), Serial Data Input (SI) and Serial Data Output (SO). Both SPI bus mode 0 and 3 are supported. Input data is latched on the rising edge of SCLK and data shifts out on the falling edge of SCLK. Dual SPI The GD25Q32C supports Dual SPI operation when using the “Dual Output Fast Read” (3BH), “Dual I/O Fast Read” (BBH) and “Read Manufacture ID/Device ID Dual I/O” (92H) commands. These commands allow data to be transferred to or from the device at two times the rate of the standard SPI. When using the Dual SPI command the SI and SO pins become bidirectional I/O pins: IO0 and IO1. Quad SPI The GD25Q32C supports Quad SPI operation when using the “Quad Output Fast Read”(6BH), “Quad I/O Fast Read”(EBH), “Quad I/O Word Fast Read”(E7H), “Read Manufacture ID/Device ID Quad I/O” (94H) and“Quad Page Program” (32H) commands. These commands allow data to be transferred to or from the device at four times the rate of the standard SPI. When using the Quad SPI command the SI and SO pins become bidirectional I/O pins: IO0 and IO1, and WP# and HOLD# pins become IO2 and IO3. Quad SPI commands require the nonvolatile Quad Enable bit (QE) in Status Register to be set. Hold The HOLD# function is only available when QE=0, If QE=1, The HOLD# function is disabled, the pin acts as dedicated data I/O pin. The HOLD# signal goes low to stop any serial communications with the device, but doesn’t stop the operation of write status register, programming, or erasing in progress. The operation of HOLD, need CS# keep low, and starts on falling edge of the HOLD# signal, with SCLK signal being low (if SCLK is not being low, HOLD operation will not start until SCLK being low). The HOLD condition ends on rising edge of HOLD# signal with SCLK being low (If SCLK is not being low, HOLD operation will not end until SCLK being low). The SO is high impedance, both SI and SCLK don’t care during the HOLD operation, if CS# drives high during HOLD operation, it will reset the internal logic of the device. To re-start communication with chip, the HOLD# must be at high and then CS# must be at low. Figure 1. Hold Condition CS# SCLK HOLD# HOLD HOLD 50 - 7 Rev.1.0 GD25Q32CxIGx 3.3V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com 5. DATA PROTECTION The GD25Q32C provides the following data protection methods: ♦ Write Enable (WREN) command: The WREN command is set the Write Enable Latch bit (WEL). The WEL bit will return to reset by the following situation: - Power-Up - Write Disable (WRDI) - Write Status Register (WRSR) - Page Program (PP) - Sector Erase (SE) / Block Erase (BE) / Chip Erase (CE) ♦ Software Protection Mode: The Block Protect (BP4, BP3, BP2, BP1 and BP0) bits define the section of the memory array that can be read but not change. ♦ Hardware Protection Mode: WP# going low to protected the BP0~BP4 bits and SRP0~1 bits. ♦ Deep Power-Down Mode: In Deep Power-Down Mode, all commands are ignored except the Release from Deep Power-Down Mode command. Table1.0 GD25Q32C Protected area size (CMP=0) Status Register Content BP4 BP3 BP2 BP1 BP0 × × 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 1 0 0 1 0 1 0 1 0 0 1 0 1 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 0 × × 1 1 1 1 0 0 0 1 1 0 0 1 0 1 0 0 1 1 1 0 1 0 × 1 0 1 1 0 1 1 0 0 1 1 1 0 1 0 1 1 0 1 1 1 1 1 0 × 1 1 1 1 0 Memory Content Blocks NONE 63 62 to 63 60 to 63 56 to 63 48 to 63 32 to 63 0 0 to 1 0 to 3 0 to 7 0 to 15 0 to 31 0 to 63 63 63 63 63 63 0 0 0 0 0 Addresses NONE 3F0000H-3FFFFFH 3E0000H-3FFFFFH 3C0000H-3FFFFFH 380000H-3FFFFFH 300000H-3FFFFFH 200000H-3FFFFFH 000000H-00FFFFH 000000H-01FFFFH 000000H-03FFFFH 000000H-07FFFFH 000000H-0FFFFFH 000000H-1FFFFFH 000000H-3FFFFFH 3FF000H-3FFFFFH 3FE000H-3FFFFFH 3FC000H-3FFFFFH 3F8000H-3FFFFFH 3F8000H-3FFFFFH 000000H-000FFFH 000000H-001FFFH 000000H-003FFFH 000000H-007FFFH 000000H-007FFFH 50 - 8 Density NONE 64KB 128KB 256KB 512KB 1MB 2MB 64KB 128KB 256KB 512KB 1MB 2MB 4MB 4KB 8KB 16KB 32KB 32KB 4KB 8KB 16KB 32KB 32KB Portion NONE Upper 1/64 Upper 1/32 Upper 1/16 Upper 1/8 Upper 1/4 Upper 1/2 Lower 1/64 Lower 1/32 Lower 1/16 Lower 1/8 Lower 1/4 Lower 1/2 ALL Top Block Top Block Top Block Top Block Top Block Bottom Block Bottom Block Bottom Block Bottom Block Bottom Block Rev.1.0 GD25Q32CxIGx 3.3V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com Table1.1. GD25Q32C Protected area size (CMP=1) Status Register Content BP4 BP3 BP2 BP1 BP0 × × 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 1 0 0 1 0 1 0 1 0 0 1 0 1 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 0 × × 1 1 1 1 0 0 0 1 1 0 0 1 0 1 0 0 1 1 1 0 1 0 × 1 0 1 1 0 1 1 0 0 1 1 1 0 1 0 1 1 0 1 1 1 1 1 0 × 1 1 1 1 0 Memory Content Blocks ALL 0 to 62 0 to 61 0 to 59 0 to 55 0 to 47 0 to 31 1 to 63 2 to 63 4 to 63 8 to 63 16 to 63 32 to 63 NONE 0 to 63 0 to 63 0 to 63 0 to 63 0 to 63 0 to 63 0 to 63 0 to 63 0 to 63 0 to 63 Addresses 000000H-3FFFFFH 000000H-3EFFFFH 000000H-3DFFFFH 000000H-3BFFFFH 000000H-37FFFFH 000000H-2FFFFFH 000000H-1FFFFFH 010000H-3FFFFFH 020000H-3FFFFFH 040000H-3FFFFFH 080000H-3FFFFFH 100000H-3FFFFFH 200000H-3FFFFFH NONE 000000H-3FEFFFH 000000H-3FDFFFH 000000H-3FBFFFH 000000H-3F7FFFH 000000H-3F7FFFH 001000H-3FFFFFH 002000H-3FFFFFH 004000H-3FFFFFH 008000H-3FFFFFH 008000H-3FFFFFH 50 - 9 Density 4MB 4032KB 3968KB 3840KB 3584KB 3MB 2MB 4032KB 3968KB 3840KB 3584KB 3MB 2MB NONE 4092KB 4088KB 4080KB 4064KB 4064KB 4092KB 4088KB 4080KB 4064KB 4064KB Portion ALL Lower 63/64 Lower 31/32 Lower 15/16 Lower 7/8 Lower 3/4 Lower 1/2 Upper 63/64 Upper 31/32 Upper 15/16 Upper 7/8 Upper 3/4 Upper 1/2 NONE L-1023/1024 L-511/512 L-255/256 L-127/128 L-127/128 U-1023/1024 U-511/512 U-255/256 U-127/128 U-127/128 Rev.1.0 GD25Q32CxIGx 3.3V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com 6. STATUS REGISTER S23 Reserved S22 DRV1 S21 DRV0 S20 HPF S19 Reserved S18 Reserved S17 Reserved S16 Reserved S15 S14 S13 S12 S11 S10 S9 S8 SUS1 CMP LB3 LB2 LB1 SUS2 QE SRP1 S7 S6 S5 S4 S3 S2 S1 S0 SRP0 BP4 BP3 BP2 BP1 BP0 WEL WIP The status and control bits of the Status Register are as follows: WIP bit. The Write in Progress (WIP) bit indicates whether the memory is busy in program/erase/write status register progress. When WIP bit sets to 1, means the device is busy in program/erase/write status register progress, when WIP bit sets 0, means the device is not in program/erase/write status register progress. WEL bit. The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Write Status Register, Program or Erase command is accepted. BP4, BP3, BP2, BP1, BP0 bits. The Block Protect (BP4, BP3, BP2, BP1 and BP0) bits are non-volatile. They define the size of the area to be software protected against Program and Erase commands. These bits are written with the Write Status Register (WRSR) command. When the Block Protect (BP4, BP3, BP2, BP1 and BP0) bits are set to 1, the relevant memory area (as defined in Table1). becomes protected against Page Program (PP), Sector Erase (SE) and Block Erase (BE) commands. The Block Protect (BP4, BP3, BP2, BP1 and BP0) bits can be written provided that the Hardware Protected mode has not been set. The Chip Erase (CE) command is executed, only if the Block Protect (BP2, BP1 and BP0) bits are 0 and CMP=0. SRP1, SRP0 bits. The Status Register Protect (SRP1 and SRP0) bits are non-volatile Read/Write bits in the status register. The SRP bits control the method of write protection: software protection, hardware protection, power supply lockdown or one time programmable protection. SRP1 SRP0 #WP Status Register 0 0 × Software Protected 0 1 0 Hardware Protected 0 1 1 1 0 × 1 1 × Description The Status Register can be written to after a Write Enable command, WEL=1.(Default) WP#=0, the Status Register locked and can not be written to. WP#=1, the Status Register is unlocked and can be written to Hardware Unprotected after a Write Enable command, WEL=1. Power Supply Status Register is protected and can not be written to again until the next Power-Down, Power-Up cycle. Lock-Down(1) One Time Program(2) Status Register is permanently protected and can not be written to. 50 - 10 Rev.1.0 GD25Q32CxIGx 3.3V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com NOTE: (1). When SRP1, SRP0= (1, 0), a Power-Down, Power-Up cycle will change SRP1, SRP0 to (0, 0) state. (2). This feature is available on special order. (GD25Q32CxxSx)Please contact ELM for details. QE bit. The Quad Enable (QE) bit is a non-volatile Read/Write bit in the Status Register that allows Quad operation. When the QE bit is set to 0 (Default) the WP# pin and HOLD# pin are enable. When the QE pin is set to 1, the Quad IO2 and IO3 pins are enabled. (The QE bit should never be set to 1 during standard SPI or Dual SPI operation if the WP# or HOLD# pins are tied directly to the power supply or ground). LB3, LB2, LB1 bits. The LB3, LB2, LB1 bits are non-volatile One Time Program (OTP) bits in Status Register (S13-S11) that provide the write protect control and status to the Security Registers. The default state of LB3-LB1 are 0, the security registers are unlocked. The LB3-LB1 bits can be set to 1 individually using the Write Register instruction. The LB3-LB1 bits are One Time Programmable, once its set to 1, the Security Registers will become read-only permanently. CMP bit. The CMP bit is a non-volatile Read/Write bit in the Status Register (S14). It is used in conjunction the BP4BP0 bits to provide more flexibility for the array protection. Please see the Status registers Memory Protection table for details. The default setting is CMP=0. SUS1, SUS2 bits. The SUS1 and SUS2 bits are read only bit in the status register (S15 and S10) that are set to 1 after executing an Program/Erase Suspend (75H) command (The Erase Suspend will set the SUS1 to 1, and the Program Suspend will set the SUS2 to 1) . The SUS1 and SUS2 bits are cleared to 0 by Program/Erase Resume (7AH) command as well as a power-down, power-up cycle. HPF bit. The High Performance Flag (HPF) bit indicates the status of High Performance Mode (HPM). When HPF bit sets to 1, it means the device is in High Performance Mode, when HPF bit sets 0 (default), it means the device is not in High Performance Mode. DRV1/DRV0. The DRV1 & DRV0 bits are used to determine the output driver strength for the Read operations. DRV1, DRV0 00 01 10 11 Driver Strength 100% 75% (default) 50% 25% 50 - 11 Rev.1.0 GD25Q32CxIGx 3.3V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com 7. COMMANDS DESCRIPTION All commands, addresses and data are shifted in and out of the device, beginning with the most significant bit on the first rising edge of SCLK after CS# is driven low. Then, the one-byte command code must be shifted in to the device, most significant bit first on SI, each bit being latched on the rising edges of SCLK. See Table2, every command sequence starts with a one-byte command code. Depending on the command, this might be followed by address bytes, or by data bytes, or by both or none. CS# must be driven high after the last bit of the command sequence has been shifted in. For the command of Read, Fast Read, Read Status Register or Release from Deep Power-Down, and Read Device ID, the shifted-in command sequence is followed by a dataout sequence. CS# can be driven high after any bit of the data-out sequence is being shifted out. For the command of Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Write Enable, Write Disable or Deep Power-Down command, CS# must be driven high exactly at a byte boundary, otherwise the command is rejected, and is not executed. That means CS# must be driven high when the number of clock pulses after CS# being driven low is an exact multiple of eight. For Page Program, if CS# is driven high at any time the input byte is not a full byte, nothing will happen and WEL will not be reset. Table2. Commands (Standard/Dual/Quad SPI) Command Name Byte 1 Byte 2 Write Enable Write Disable Volatile SR Write Enable Read Status Register-1 Read Status Register-2 Read Status Register-3 Write Status Register-1 Write Status Register-2 Write Status Register-3 Read Data Fast Read Dual Output Fast Read 06H 04H 50H 05H 35H 15H 01H 31H 11H 03H 0BH 3BH (S7-S0) (S15-S8) (S23-S16) S7-S0 S15-S8 S23-S16 A23-A16 A23-A16 A23-A16 Dual I/O Fast Read BBH A23-A8 (2) Quad Output Fast Read 6BH Quad I/O Fast Read EBH A23-A16 A23-A0 M7-M0 (4) A23-A0 M7-M0 (4) A23-A16 A23-A16 A23-A16 A23-A16 A23-A16 A23-A16 Quad I/O Word Fast Read (7) Page Program Quad Page Program Fast Page Program Sector Erase Block Erase (32K) Block Erase (64K) Chip Erase Enable Reset Reset E7H 02H 32H F2H 20H 52H D8H C7/60H 66H 99H Byte 3 Byte 4 Byte 5 Byte 6 n-Bytes (continuous) (continuous) (continuous) A15-A8 A15-A8 A15-A8 A7-A0 M7-M0 (2) A15-A8 A7-A0 A7-A0 A7-A0 (D7-D0) (1) A7-A0 dummy (5) (D7-D0) (3) dummy (6) (D7-D0) (3) A15-A8 A15-A8 A15-A8 A15-A8 A15-A8 A15-A8 A7-A0 A7-A0 A7-A0 A7-A0 A7-A0 A7-A0 50 - 12 (D7-D0) dummy dummy (Next byte) dummy (Next byte) (Next byte) D7-D0 D7-D0 (3) D7-D0 (Next byte) (continuous) (D7-D0) (continuous) D7-D0 (1) (continuous) (Next byte) (continuous) (D7-D0) (3) (continuous) (Next byte) (continuous) (Next byte) (continuous) Next byte Next byte Next byte continuous continuous continuous Rev.1.0 GD25Q32CxIGx 3.3V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com Command Name Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Set Burst with Wrap 77H dummy (9) W7-W0 Program/Erase Suspend Program/Erase Resume Release From Deep Power-Down, And Read Device ID 75H 7AH dummy dummy dummy (DID7DID0) 90H dummy dummy 00H (MID7MID0) 92H A23-A8 Manufacturer/ Device ID by Quad I/O 94H A23-A0, M7-M0 Read Identification 9FH High Performance Mode Read Serial Flash Discoverable Parameter Erase Security Registers (8) Program Security Registers (8) Read Security Registers (8) A3H (MID7MID0) dummy 5AH A23-A16 A15-A8 A7-A0 44H A23-A16 A15-A8 A7-A0 42H A23-A16 A15-A8 48H A23-A16 A15-A8 Release From Deep Power-Down Deep Power-Down Manufacturer/ Device ID Manufacturer/ Device ID by Dual I/O ABH Byte 6 n-Bytes (continuous) ABH B9H (DID7DID0) A7-A0, (MID7-MID0) M7-M0 (DID7-DID0) (10) dummy (MID7- MID0) (DID7-DID0) (JDID15(JDID7JDID8) JDID0) dummy dummy (continuous) (continuous) (continuous) (continuous) dummy (D7-D0) (continuous) A7-A0 D7-D0 D7-D0 continuous A7-A0 dummy (D7-D0) (continuous) NOTE: (1) Dual Output data IO0 = (D6, D4, D2, D0) IO1 = (D7, D5, D3, D1) (2) Dual Input Address IO0 = A22, A20, A18, A16, A14, A12, A10, A8 IO1 = A23, A21, A19, A17, A15, A13, A11, A9 A6, A4, A2, A0, M6, M4, M2, M0 A7, A5, A3, A1, M7, M5, M3, M1 (3) Quad Output Data IO0 = (D4, D0, …..) IO1 = (D5, D1, …..) IO2 = (D6, D2, …..) IO3 = (D7, D3, …..) 50 - 13 Rev.1.0 GD25Q32CxIGx 3.3V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com (4) Quad Input Address IO0 = A20, A16, A12, A8, A4, A0, M4, M0 IO1 = A21, A17, A13, A9, A5, A1, M5, M1 IO2 = A22, A18, A14, A10, A6, A2, M6, M2 IO3 = A23, A19, A15, A11, A7, A3, M7, M3 (5) Fast Read Quad I/O Data IO0 = (x, x, x, x, D4, D0,…) IO1 = (x, x, x, x, D5, D1,…) IO2 = (x, x, x, x, D6, D2,…) IO3 = (x, x, x, x, D7, D3,…) (6) Fast Word Read Quad I/O Data IO0 = (x, x, D4, D0,…) IO1 = (x, x, D5, D1,…) IO2 = (x, x, D6, D2,…) IO3 = (x, x, D7, D3,…) (7) Fast Word Read Quad I/O Data: the lowest address bit must be 0. (8) Security Registers Address: Security Register1: A23-A16=00H, A15-A10=000100b, A9-A0=Byte Address; Security Register2: A23-A16=00H, A15-A10=001000b, A9-A0=Byte Address; Security Register3: A23-A16=00H, A15-A10=001100b, A9-A0=Byte Address. (9) Dummy bits and Wrap Bits IO0 = (x, x, x, x, x, x, W4, x) IO1 = (x, x, x, x, x, x, W5, x) IO2 = (x, x, x, x, x, x, W6, x) IO3 = (x, x, x, x, x, x, W7, x) (10) Address, Continuous Read Mode bits, Dummy bits, Manufacture ID and Device ID IO0 = (A20, A16, A12, A8, A4, A0, M4, M0, x, x, x, x, MID4, MID0, DID4, DID0, …) IO1 = (A21, A17, A13, A9, A5, A1, M5, M1, x, x, x, x, MID5, MID1, DID5, DID1, …) IO2 = (A22, A18, A14, A10, A6, A2, M6, M2, x, x, x, x, MID6, MID2, DID6, DID2, …) IO3 = (A23, A19, A15, A11, A7, A3, M7, M3, x, x, x, x, MID7, MID3, DID7, DID3, …) Table Of ID Definitions: GD25Q32C Operation Code MID7-MID0 ID15-ID8 ID7-ID0 9FH 90H/92H/94H C8 C8 40 16 15 ABH 15 50 - 14 Rev.1.0 GD25Q32CxIGx 3.3V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com 7.1. Write Enable (WREN)(06H) The Write Enable (WREN) command is for setting the Write Enable Latch (WEL) bit. The Write Enable Latch (WEL) bit must be set prior to every Page Program (PP), Sector Erase (SE), Block Erase (BE), Chip Erase (CE), Write Status Register (WRSR) and Erase/Program Security Register command. The Write Enable (WREN) command sequence: CS# goes low → sending the Write Enable command → CS# goes high. Figure 2. Write Enable Sequence Diagram CS# SCLK 0 1 2 3 4 5 6 7 Command SI 06H High-Z SO 7.2. Write Disable (WRDI) (04H) The Write Disable command is for resetting the Write Enable Latch (WEL) bit. The Write Disable command sequence: CS# goes low → Sending the Write Disable command → CS# goes high. The WEL bit is reset by following condition: Power-up and upon completion of the Write Status Register, Page Program, Sector Erase, Block Erase, Chip Erase, Erase/Program Security Register and Reset commands. Figure 3. Write Disable Sequence Diagram CS# SCLK 0 1 2 3 4 5 6 7 Command SI 04H High-Z SO 7.3. Write Enable for Volatile Status Register (50H) The non-volatile Status Register bits can also be written to as volatile bits. This gives more flexibility to change the system configuration and memory protection schemes quickly without waiting for the typical nonvolatile bit write cycles or affecting the endurance of the Status Register non-volatile bits. The Write Enable for Volatile Status Register command must be issued prior to a Write Status Register command. The Write Enable for Volatile Status Register command will not set the Write Enable Latch bit, it is only valid for the Write Status Register command to change the volatile Status Register bit values. 50 - 15 Rev.1.0 GD25Q32CxIGx 3.3V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com Figure 4. Write Enable for Volatile Status Register Sequence Diagram CS# SCLK 0 1 2 3 4 5 6 7 Command(50H) SI SO High-Z 7.4. Read Status Register (RDSR) (05H or 35H or 15H) The Read Status Register (RDSR) command is for reading the Status Register. The Status Register may be read at any time, even while a Program, Erase or Write Status Register cycle is in progress. When one of these cycles is in progress, it is recommended to check the Write In Progress (WIP) bit before sending a new command to the device. It is also possible to read the Status Register continuously. For command code “05H”“35H”“15H”, the SO will output Status Register bits S7~S0 / S15~S8 / S16~S23. Figure 5. Read Status Register Sequence Diagram 7.5. Write Status Register (WRSR) (01H or 31H or 11H) The Write Status Register (WRSR) command allows new values to be written to the Status Register. Before it can be accepted, a Write Enable (WREN) command must previously have been executed. After the Write Enable (WREN) command has been decoded and executed, the device sets the Write Enable Latch (WEL). The Write Status Register (WRSR) command has no effect on S23, S20, S19, S18, S17, S16, S15, S10, S1 and S0 of the Status Register. CS# must be driven high after the eighth of the data byte has been latched in. If not, the Write Status Register (WRSR) command is not executed. As soon as CS# is driven high, the selftimed Write Status Register cycle (whose duration is tW) is initiated. While the Write Status Register cycle is in progress, the Status Register may still be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed. When the cycle is completed, the Write Enable Latch (WEL) is reset. The Write Status Register (WRSR) command allows the user to change the values of the Block Protect (BP4, BP3, BP2, BP1 and BP0) bits, to define the size of the area that is to be treated as read-only, as defined in Table1. The Write Status Register (WRSR) command also allows the user to set or reset the Status Register 50 - 16 Rev.1.0 GD25Q32CxIGx 3.3V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com Protect (SRP1 and SRP0) bits in accordance with the Write Protect (WP#) signal. The Status Register Protect (SRP1 and SRP0) bits and Write Protect (WP#) signal allow the device to be put in the Hardware Protected Mode. The Write Status Register (WRSR) command is not executed once the Hardware Protected Mode is entered. Figure 6. Write Status Register Sequence Diagram 7.6. Read Data Bytes (READ) (03H) The Read Data Bytes (READ) command is followed by a 3-byte address (A23-A0), each bit being latched-in during the rising edge of SCLK. Then the memory content, at that address, is shifted out on SO, each bit being shifted out, at a Max frequency fR, during the falling edge of SCLK. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read with a single Read Data Bytes (READ) command. Any Read Data Bytes (READ) command, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure 7. Read Data Bytes Sequence Diagram CS# SCLK SI SO 0 1 2 3 4 5 6 7 8 Command 03H High-Z 9 10 28 29 30 31 32 33 34 35 36 37 38 39 24-bit address 23 22 21 3 2 1 0 MSB MSB 7 6 5 Data Out1 4 3 2 1 Data Out2 0 7.7. Read Data Bytes at Higher Speed (Fast Read) (0BH) The Read Data Bytes at Higher Speed (Fast Read) command is for quickly reading data out. It is followed by a 3-byte address (A23-A0) and a dummy byte, each bit being latched-in during the rising edge of SCLK. Then the memory content, at that address, is shifted out on SO, each bit being shifted out, at a Max frequency fC, during the falling edge of SCLK. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. 50 - 17 Rev.1.0 GD25Q32CxIGx 3.3V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com Figure 8. Read Data Bytes at Higher Speed Sequence Diagram 7.8. Dual Output Fast Read (3BH) The Dual Output Fast Read command is followed by 3-byte address (A23-A0) and a dummy byte, each bit being latched in during the rising edge of SCLK, then the memory contents are shifted out 2-bit per clock cycle from SI and SO. The command sequence is shown in followed Figure9. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. Figure 9. Dual Output Fast Read Sequence Diagram 50 - 18 Rev.1.0 GD25Q32CxIGx 3.3V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com 7.9. Quad Output Fast Read (6BH) The Quad Output Fast Read command is followed by 3-byte address (A23-A0) and a dummy byte, each bit being latched in during the rising edge of SCLK, then the memory contents are shifted out 4-bit per clock cycle from IO3, IO2, IO1 and IO0. The command sequence is shown in followed Figure10. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. Figure 10. Quad Output Fast Read Sequence Diagram CS# 0 SCLK 1 2 3 4 5 6 7 8 9 10 Command SI(IO0) 24-bit address 6BH High-Z WP#(IO2) High-Z HOLD#(IO3) High-Z SCLK 3 23 22 21 SO(IO1) CS# 28 29 30 31 2 1 0 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 Dummy Clocks SI(IO0) 4 0 4 0 4 0 4 0 4 SO(IO1) 5 1 5 1 5 1 5 1 5 WP#(IO2) 6 2 6 2 6 2 6 2 6 HOLD#(IO3) 7 3 7 3 7 3 7 3 7 Byte1 Byte2 Byte3 Byte4 7.10. Dual I/O Fast Read (BBH) The Dual I/O Fast Read command is similar to the Dual Output Fast Read command but with the capability to input the 3-byte address (A23-0) and a “Continuous Read Mode” byte 2-bit per clock by SI and SO, each bit being latched in during the rising edge of SCLK, then the memory contents are shifted out 2-bit per clock cycle from SI and SO. The command sequence is shown in followed Figure11. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. Dual I/O Fast Read with “Continuous Read Mode” The Dual I/O Fast Read command can further reduce command overhead through setting the “Continuous Read Mode” bits (M7-4) after the input 3-byte address (A23-A0). If the “Continuous Read Mode” bits (M5-4) =(1, 0), then the next Dual I/O Fast Read command (after CS# is raised and then lowered) does not require the BBH command code. The command sequence is shown in followed Figure12. If the “Continuous Read Mode” bits (M5-4) do not equal (1, 0), the next command requires the first BBH command code, thus returning to normal operation. A “Continuous Read Mode” Reset command can be used to reset (M5-4) before issuing normal command. 50 - 19 Rev.1.0 GD25Q32CxIGx 3.3V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com Figure 11. Dual I/O Fast Read Sequence Diagram (M5-4 ≠ (1, 0)) Figure 11. Dual I/O Fast Read Sequence Diagram (M5-4� (1, 0)) Figure 12. Dual I/O Fast Read Sequence Diagram (M5-4 = (1, 0)) Figure 12. Dual I/O Fast Read Sequence Diagram (M5-4= (1, 0)) 7.11. Quad I/O Fast Read (EBH) The Quad I/O Fast Read command is similar to the Dual I/O Fast Read command but with the capability to input the 3-byte address (A23-0) and a “Continuous Read Mode” byte and 4-dummy clock 4-bit per clock by IO0, IO1, IO2, IO3, each bit being latched in during the rising edge of SCLK, then the memory contents are shifted out 4-bit per clock cycle from IO0, IO1, IO2, IO3. The command sequence is shown in followed Figure13. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The Quad Enable bit (QE) of Status Register (S9) must be set to enable for the Quad I/O Fast read command. 50 - 20 Rev.1.0 GD25Q32CxIGx 3.3V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com Quad I/O Fast Read with “Continuous Read Mode” The Quad I/O Fast Read command can further reduce command overhead through setting the “Continuous Read Mode” bits (M7-0) after the input 3-byte address (A23-A0). If the “Continuous Read Mode” bits (M5-4) =(1, 0), then the next Quad I/O Fast Read command (after CS# is raised and then lowered) does not require the EBH command code. The command sequence is shown in followed Figure14. If the “Continuous Read Mode” bits (M5-4) do not equal to (1, 0), the next command requires the first EBH command code, thus returning to normal operation. A “Continuous Read Mode” Reset command can be used to reset (M5-4) before issuing normal command. Figure 13. Quad I/O Fast Read Sequence Diagram (M5-4 ≠ (1, 0)) CS# 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 4 0 4 0 4 0 4 0 4 0 4 0 4 SO(IO1) 5 1 5 1 5 1 5 1 5 1 5 1 5 WP#(IO2) 6 2 6 2 6 2 6 2 6 2 6 2 6 HOLD#(IO3) 7 3 7 3 7 3 7 3 7 3 7 3 7 0 SCLK 1 2 3 4 5 6 7 Command SI(IO0) EBH A23-16 A15-8 A7-0 M7-0 Dummy Byte1 Byte2 Figure 14. Quad I/O Fast Read Sequence Diagram (M5-4 = (1, 0)) CS# 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 SI(IO0) 4 0 4 0 4 0 4 0 4 0 4 0 4 SO(IO1) 5 1 5 1 5 1 5 1 5 1 5 1 5 WP#(IO2) 6 2 6 2 6 2 6 2 6 2 6 2 6 HOLD#(IO3) 7 3 7 3 7 3 7 3 7 3 7 3 7 SCLK A23-16 A15-8 A7-0 M7-0 Dummy Byte1 Byte2 Quad I/O Fast Read with “8/16/32/64-Byte Wrap Around” in Standard SPI mode The Quad I/O Fast Read command can be used to access a specific portion within a page by issuing “Set Burst with Wrap” (77H) commands prior to EBH. The “Set Burst with Wrap” (77H) command can either enable or disable the “Wrap Around” feature for the following EBH commands. When “Wrap Around” is enabled, the data being accessed can be limited to either an 8/16/32/64-byte section of a 256-byte page. The output data starts at the initial address specified in the command, once it reaches the ending boundary of the 8/16/32/64-byte section, the output will wrap around the beginning boundary automatically until CS# is pulled high to terminate the command. 50 - 21 Rev.1.0 GD25Q32CxIGx 3.3V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then fill the cache afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read commands. The “Set Burst with Wrap” command allows three “Wrap Bits” W6-W4 to be set. The W4 bit is used to enable or disable the “Wrap Around” operation while W6-W5 is used to specify the length of the wrap around section within a page. 7.12. Quad I/O Word Fast Read (E7H) The Quad I/O Word Fast Read command is similar to the Quad I/O Fast Read command except that the lowest address bit (A0) must equal 0 and only 2-dummy clock. The command sequence is shown in followed Figure15. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The Quad Enable bit (QE) of Status Register (S9) must be set to enable for the Quad I/O Word Fast read command. Quad I/O Word Fast Read with “Continuous Read Mode” The Quad I/O Word Fast Read command can further reduce command overhead through setting the “Continuous Read Mode” bits (M7-0) after the input 3-byte address (A23-A0). If the “Continuous Read Mode” bits (M5-4) =(1, 0), then the next Quad I/O Word Fast Read command (after CS# is raised and then lowered) does not require the E7H command code. The command sequence is shown in followed Figure16. If the “Continuous Read Mode” bits (M5-4) do not equal to (1, 0), the next command requires the first E7H command code, thus returning to normal operation. A “Continuous Read Mode” Reset command can be used to reset (M5-4) before issuing normal command. Figure 15. Quad I/O Word Fast Read Sequence Diagram (M5-4 ≠ (1, 0)) CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 SO(IO1) 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 WP#(IO2) 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 HOLD#(IO3) 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 SCLK Command SI(IO0) E7H A23-16 A15-8 A7-0 M7-0 Dummy Byte1 Byte2 Byte3 50 - 22 Rev.1.0 GD25Q32CxIGx 3.3V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com Figure 16. Quad I/O Word Fast Read Sequence Diagram (M5-4 = (1, 0)) CS# 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 SI(IO0) 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 SO(IO1) 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 WP#(IO2) 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 HOLD#(IO3) 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 SCLK A23-16 A15-8 A7-0 M7-0 Dummy Byte1 Byte2 Byte3 Quad I/O Word Fast Read with “8/16/32/64-Byte Wrap Around” in Standard SPI mode The Quad I/O Word Fast Read command can be used to access a specific portion within a page by issuing “Set Burst with Wrap” (77H) commands prior to E7H. The “Set Burst with Wrap” (77H) command can either enable or disable the “Wrap Around” feature for the following E7H commands. When “Wrap Around” is enabled, the data being accessed can be limited to either an 8/16/32/64-byte section of a 256-byte page. The output data starts at the initial address specified in the command, once it reaches the ending boundary of the 8/16/32/64-byte section, the output will wrap around the beginning boundary automatically until CS# is pulled high to terminate the command. The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then fill the cache afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read commands. The “Set Burst with Wrap” command allows three “Wrap Bits” W6-W4 to be set. The W4 bit is used to enable or disable the “Wrap Around” operation while W6-W5 is used to specify the length of the wrap around section within a page. 7.13. Set Burst with Wrap (77H) The Set Burst with Wrap command is used in conjunction with “Quad I/O Fast Read” and “Quad I/O Word Fast Read” command to access a fixed length of 8/16/32/64-byte section within a 256-byte page, in standard SPI mode. The Set Burst with Wrap command sequence: CS# goes low → Send Set Burst with Wrap command → Send 24 dummy bits → Send 8 bits “Wrap bits” → CS# goes high. W6, W5 W4=0 W4=1 (default) Wrap Around Wrap Length Wrap Around Wrap Length 0, 0 0, 1 Yes Yes 8-byte 16-byte No No N/A N/A 1, 0 1, 1 Yes Yes 32-byte 64-byte No No N/A N/A If the W6-W4 bits are set by the Set Burst with Wrap command, all the following “Quad I/O Fast Read” and “Quad I/O Word Fast Read” command will use the W6-W4 setting to access the 8/16/32/64-byte section within any page. To exit the “Wrap Around” function and return to normal read operation, another Set Burst with Wrap command should be issued to set W4=1. 50 - 23 Rev.1.0 GD25Q32CxIGx 3.3V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com Figure 17. Set Burst with Wrap Sequence Diagram CS# 8 9 10 11 12 13 14 15 x x x x x x 4 x SO(IO1) x x x x x x 5 x WP#(IO2) x x x x x x 6 x HOLD#(IO3) x x x x x x x x SCLK 0 1 2 3 4 5 6 7 Command SI(IO0) 77H W6-W4 7.14. Page Program (PP) (02H) The Page Program (PP) command is for programming the memory. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit before sending the Page Program command. The Page Program (PP) command is entered by driving CS# Low, followed by the command code, three address bytes and at least one data byte on SI. If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data that goes beyond the end of the current page are programmed from the start address of the same page (from the address whose 8 least significant bits (A7-A0) are all zero). CS# must be driven low for the entire duration of the sequence. The Page Program command sequence: CS# goes low → sending Page Program command → 3-byte address on SI → at least 1 byte data on SI → CS# goes high. The command sequence is shown in Figure18. If more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. If less than 256 data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes of the same page. CS# must be driven high after the eighth bit of the last data byte has been latched in; otherwise the Page Program (PP) command is not executed. As soon as CS# is driven high, the self-timed Page Program cycle (whose duration is tPP) is initiated. While the Page Program cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A Page Program (PP) command applied to a page which is protected by the Block Protect (BP4, BP3, BP2, BP1 and BP0) is not executed. 50 - 24 Rev.1.0 GD25Q32CxIGx 3.3V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com Figure 18. Page Program Sequence Diagram 7.15. Quad Page Program (32H) The Quad Page Program command is for programming the memory using four pins: IO0, IO1, IO2 and IO3. To use Quad Page Program the Quad enable in status register Bit9 must be set (QE=1). A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit before sending the Page Program command. The quad Page Program command is entered by driving CS# Low, followed by the command code (32H), three address bytes and at least one data byte on IO pins. The command sequence is shown in Figure19. If more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. If less than 256 data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes of the same page. CS# must be driven high after the eighth bit of the last data byte has been latched in; otherwise the Quad Page Program (PP) command is not executed. As soon as CS# is driven high, the self-timed Quad Page Program cycle (whose duration is tPP) is initiated. While the Quad Page Program cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Quad Page Program cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A Quad Page Program command applied to a page which is protected by the Block Protect (BP4, BP3, BP2, BP1 and BP0) is not executed. 50 - 25 Rev.1.0 GD25Q32CxIGx 3.3V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com Figure 19. Quad Page Program Sequence Diagram CS# 0 SCLK 1 2 3 4 5 6 8 7 24-bit address Command 0 4 0 4 0 4 0 5 1 5 1 5 1 5 1 WP#(IO2) 6 2 6 2 6 2 6 2 HOLD#(IO3) 7 3 7 3 7 3 7 3 537 542 543 Byte1 Byte2 0 4 538 SI(IO0) 28 29 30 31 32 33 34 35 36 37 38 39 9 10 23 22 21 32H 2 3 1 MSB SO(IO1) 540 541 SI(IO0) 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 SO(IO1) 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 WP#(IO2) 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 HOLD#(IO3) 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 SCLK 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 Byte11 Byte12 536 539 CS# Byte256 Byte253 7.16. Fast Page Program (FPP) (F2H) The Fast Page Program (FPP) command is used to program the memory. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit before sending the Page Program command. The Fast Page Program (FPP) command is entered by driving CS# Low, followed by the command code, three address bytes and at least one data byte on SI. If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data that goes beyond the end of the current page are programmed from the start address of the same page (from the address whose 8 least significant bits (A7-A0) are all zero). CS# must be driven low for the entire duration of the sequence. The Page Program command sequence: CS# goes low → sending Page Program command → 3-byte address on SI → at least 1 byte data on SI → CS# goes high. The command sequence is shown in Figure20. If more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. If less than 256 data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes of the same page. CS# must be driven high after the eighth bit of the last data byte has been latched in; otherwise the Fast Page Program (FPP) command is not executed. As soon as CS# is driven high, the self-timed Page Program cycle (whose duration is tPP) is initiated. While the 50 - 26 Rev.1.0 GD25Q32CxIGx 3.3V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com Page Program cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A Fast Page Program (FPP) command is not executed when it is applied to a page protected by the Block Protect (BP4, BP3, BP2, BP1, BP0). Figure 20. Fast Page Program Sequence Diagram 7.17. Sector Erase (SE) (20H) The Sector Erase (SE) command is used to erase all the data of the chosen sector. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit. The Sector Erase (SE) command is entered by driving CS# low, followed by the command code, and 3-address byte on SI. Any address inside the sector is a valid address for the Sector Erase (SE) command. CS# must be driven low for the entire duration of the sequence. The Sector Erase command sequence: CS# goes low → sending Sector Erase command → 3-byte address on SI → CS# goes high. The command sequence is shown in Figure21. CS# must be driven high after the eighth bit of the last address byte has been latched in; otherwise the Sector Erase (SE) command is not executed. As soon as CS# is driven high, the self-timed Sector Erase cycle (whose duration is tSE) is initiated. While the Sector Erase cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Sector Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A Sector Erase (SE) command applied to a sector which is protected by the Block Protect (BP4, BP3, BP2, BP1 and BP0) bit (see Table1 & Table1.1.) is not executed. Figure 21. Sector Erase Sequence Diagram CS# SCLK SI 0 1 2 3 4 5 6 7 8 29 30 31 24 Bits Address Command 20H 9 23 22 MSB 50 - 27 2 1 0 Rev.1.0 GD25Q32CxIGx 3.3V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com 7.18. 32KB Block Erase (BE) (52H) The 32KB Block Erase (BE) command is used to erase all the data of the chosen block. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit. The 32KB Block Erase (BE) command is entered by driving CS# low, followed by the command code, and three address bytes on SI. Any address inside the block is a valid address for the 32KB Block Erase (BE) command. CS# must be driven low for the entire duration of the sequence. The 32KB Block Erase command sequence: CS# goes low → sending 32KB Block Erase command → 3-byte address on SI→ CS# goes high. The command sequence is shown in Figure22. CS# must be driven high after the eighth bit of the last address byte has been latched in; otherwise the 32KB Block Erase (BE) command is not executed. As soon as CS# is driven high, the self-timed Block Erase cycle (whose duration is tBE) is initiated. While the Block Erase cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Block Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A 32KB Block Erase (BE) command applied to a block which is protected by the Block Protect (BP4, BP3, BP2, BP1 and BP0) bits (see Table1. & Table1.1.) is not executed. Figure 22. 32KB Block Erase Sequence Diagram CS# SCLK 0 1 SI 2 3 4 5 6 7 8 29 30 31 24 Bits Address Command 52H 9 23 22 MSB 2 1 0 7.19. 64KB Block Erase (BE) (D8H) The 64KB Block Erase (BE) command is used to erase all the data of the chosen block. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit. The 64KB Block Erase (BE) command is entered by driving CS# low, followed by the command code, and three address bytes on SI. Any address inside the block is a valid address for the 64KB Block Erase (BE) command. CS# must be driven low for the entire duration of the sequence. The 64KB Block Erase command sequence: CS# goes low → sending 64KB Block Erase command → 3-byte address on SI → CS# goes high. The command sequence is shown in Figure23. CS# must be driven high after the eighth bit of the last address byte has been latched in; otherwise the 64KB Block Erase (BE) command is not executed. As soon as CS# is driven high, the self-timed Block Erase cycle (whose duration is tBE) is initiated. While the Block Erase cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Block Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A 64KB Block Erase (BE) command applied to a block which is protected by the Block Protect (BP4, BP3, BP2, BP1 and BP0) bits (see Table1. & Table1.1.) is not executed. 50 - 28 Rev.1.0 GD25Q32CxIGx 3.3V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com Figure 23. 64KB Block Erase Sequence Diagram CS# SCLK 1 0 2 3 4 5 6 7 8 9 24 Bits Address Command SI 29 30 31 23 22 MSB D8H 2 1 0 7.20. Chip Erase (CE) (60/C7H) The Chip Erase (CE) command is used to erase all the data of the chip. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit. The Chip Erase (CE) command is entered by driving CS# Low, followed by the command code on Serial Data Input (SI). CS# must be driven Low for the entire duration of the sequence. The Chip Erase command sequence: CS# goes low → sending Chip Erase command → CS# goes high. The command sequence is shown in Figure24. CS# must be driven high after the eighth bit of the command code has been latched in; otherwise the Chip Erase command is not executed. As soon as CS# is driven high, the selftimed Chip Erase cycle (whose duration is tCE) is initiated. While the Chip Erase cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Chip Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. The Chip Erase (CE) command is executed only if all Block Protect (BP2, BP1 and BP0) bits are 0. The Chip Erase (CE) command is ignored if one or more sectors are protected. Figure 24. Chip Erase Sequence Diagram CS# SCLK SI 0 1 2 3 4 5 6 7 Command 60H or C7H 7.21. Deep Power-Down (DP) (B9H) Executing the Deep Power-Down (DP) command is the only way to put the device in the lowest consumption mode (the Deep Power-Down Mode). It can also be used as an extra software protection mechanism, while the device is not in active use, since in this mode, the device ignores all Write, Program and Erase commands. Driving CS# high deselects the device, and puts the device in the Standby Mode (if there is no internal cycle currently in progress). But this mode is not the Deep Power-Down Mode. The Deep Power-Down Mode can only be entered by executing the Deep Power-Down (DP) command. Once the device has entered the Deep Power-Down Mode, all commands are ignored except the Release from Deep Power-Down and Read Device ID (RDI) command. This releases the device from this mode. The Release from Deep Power-Down and Read Device ID (RDI) command also allows the Device ID of the device to be output on SO. The Deep Power-Down Mode automatically stops at Power-Down, and the device always Power-Up in the Standby Mode. The Deep Power-Down (DP) command is entered by driving CS# low, followed by the command 50 - 29 Rev.1.0 GD25Q32CxIGx 3.3V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com code on SI. CS# must be driven low for the entire duration of the sequence. The Deep Power-Down command sequence: CS# goes low → sending Deep Power-Down command → CS# goes high. The command sequence is shown in Figure25. CS# must be driven high after the eighth bit of the command code has been latched in; otherwise the Deep Power-Down (DP) command is not executed. As soon as CS# is driven high, it requires a delay of tDP before the supply current is reduced to ICC2 and the Deep PowerDown Mode is entered. Any Deep Power-Down (DP) command, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure 25. Deep Power-Down Sequence Diagram CS# SCLK tDP 0 1 2 3 4 5 6 7 Command SI Stand-by mode Deep Power-down mode B9H 7.22. Release from Deep Power-Down or High Performance Mode and Read Device ID (RDI) (ABH) The Release from Power-Down or High Performance Mode/Device ID command is a multi-purpose command. It can be used to release the device from the Power-Down state or High Performance Mode or obtain the devices electronic identification (ID) number. To release the device from the Power-Down state or High Performance Mode, the command is issued by driving the CS# pin low, shifting the instruction code “ABH” and driving CS# high as shown in Figure26. Release from Power-Down will take the time duration of tRES1 (See AC Characteristics) before the device will resume normal operation and other command are accepted. The CS# pin must remain high during the tRES1 time duration. When used only to obtain the Device ID while not in the Power-Down state, the command is initiated by driving the CS# pin low and shifting the instruction code “ABH” followed by 3-dummy byte. The Device ID bits are then shifted out on the falling edge of SCLK with most significant bit (MSB) first as shown in Figure27. The Device ID value for the GD25Q32C is listed in Manufacturer and Device Identification table. The Device ID can be read continuously. The command is completed by driving CS# high. When used to release the device from the Power-Down state and obtain the Device ID, the command is the same as previously described, and shown in Figure27, except that after CS# is driven high it must remain high for a time duration of tRES2 (See AC Characteristics). After this time duration the device will resume normal operation and other command will be accepted. If the Release from Power-Down/Device ID command is issued while an Erase, Program or Write cycle is in process (when WIP equal 1) the command is ignored and will not have any effects on the current cycle. Figure 26. Release Power-Down Sequence or High Performance Mode Sequence Diagram CS# SCLK SI 0 1 2 3 4 5 6 7 t RES1 Command ABH Deep Power-down mode 50 - 30 Stand-by mode Rev.1.0 GD25Q32CxIGx 3.3V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com Figure 27. Release Power-Down and Read Device ID Sequence Diagram 7.23. Read Manufacture ID/Device ID (REMS) (90H) The Read Manufacturer/Device ID command is an alternative to the Release from Power-Down/Device ID command that provides both the JEDEC assigned Manufacturer ID and the specific Device ID. The command is initiated by driving the CS# pin low and shifting the command code “90H” followed by a 24-bit address (A23-A0) of 000000H. After which, the Manufacturer ID and the Device ID are shifted out on the falling edge of SCLK with most significant bit (MSB) first as shown in Figure28. If the 24-bit address is initially set to 000001H, the Device ID will be read first. Figure 28. Read Manufacture ID/Device ID Sequence Diagram 50 - 31 Rev.1.0 GD25Q32CxIGx 3.3V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com 7.24. Dual I/O Read Manufacture ID/Device ID (92H) The Dual I/O Read Manufacturer/Device ID command is an alternative to the Release from Power-Down/ Device ID command that provides both the JEDEC assigned Manufacturer ID and the specific Device ID by dual I/O. The command is initiated by driving the CS# pin low and shifting the command code “92H” followed by a 24-bit address (A23-A0) of 000000H. After which, the Manufacturer ID and the Device ID are shifted out on the falling edge of SCLK with most significant bit (MSB) first as shown in Figure29. If the 24-bit address is initially set to 000001H, the Device ID will be read first. Figure 29. Read Manufacture ID/Device ID Dual I/O Sequence Diagram CS# 0 SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 6 4 2 0 6 5 3 1 7 Command SI(IO0) 92H SO(IO1) 7 A23-16 4 2 0 6 5 3 1 7 A15-8 4 2 0 6 5 3 1 7 A7-0 4 2 0 5 3 1 M7-0 CS# SCLK 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SI(IO0) 6 SO(IO1) 7 4 2 0 6 4 2 0 6 5 3 1 7 5 3 1 7 MFR ID Device ID 4 2 0 6 4 2 0 6 5 3 1 7 5 3 1 7 MFR ID (Repeat) Device ID (Repeat) 4 2 0 6 4 2 0 5 3 1 7 5 3 1 MFR ID (Repeat) Device ID (Repeat) 7.25. Quad I/O Read Manufacture ID/Device ID (94H) The Quad I/O Read Manufacturer/Device ID command is an alternative to the Release from Power-Down/ Device ID command that provides both the JEDEC assigned Manufacturer ID and the specific Device ID by quad I/O. The command is initiated by driving the CS# pin low and shifting the command code “94H” followed by a 24-bit address (A23-A0) of 000000H. and 4 dummy clocks. After which, the Manufacturer ID and the Device ID are shifted out on the falling edge of SCLK with most significant bit (MSB) first as shown in Figure30. If the 24-bit address is initially set to 000001H, the Device ID will be read first. 50 - 32 Rev.1.0 GD25Q32CxIGx 3.3V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com Figure 30. Read Manufacture ID/Device ID Quad I/O Sequence Diagram CS# 0 SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 4 0 4 0 4 0 4 0 4 0 4 0 5 1 5 1 5 1 5 1 5 1 5 1 6 2 6 2 6 2 6 2 6 2 6 2 7 3 7 3 7 3 7 3 7 3 7 3 Command SI(IO0) 94H SO(IO1) WP#(IO2) HOLD#(IO3) A23-16 A15-8 A7-0 M7-0 Dummy MFR ID DID CS# SCLK 24 25 26 27 28 29 30 31 SI(IO0) 4 0 SO(IO1) 5 1 5 1 5 1 5 1 WP#(IO2) 6 2 6 2 6 2 6 2 HOLD#(IO3) 7 4 0 4 0 4 0 3 7 3 7 3 7 3 MFR ID DID MFR ID DID (Repeat)(Repeat)(Repeat)(Repeat) 7.26. Read Identification (RDID) (9FH) The Read Identification (RDID) command allows the 8-bit manufacturer identification to be read, followed by two bytes of device identification. The device identification indicates the memory type in the first byte, and the memory capacity of the device in the second byte. The Read Identification (RDID) command while an Erase or Program cycle is in progress is not decoded, and has no effect on the cycle that is in progress. The Read Identification (RDID) command should not be issued while the device is in Deep Power-Down Mode. The device is first selected by driving CS# to low. Then, the 8-bit command code for the command is shifted in. This is followed by the 24-bit device identification, stored in the memory, being shifted out on Serial Data Output, each bit being shifted out during the falling edge of Serial Clock. The command sequence is shown in Figure31. The Read Identification (RDID) command is terminated by driving CS# to high at any time during data output. When CS# is driven high, the device is put in the Standby Mode. Once in the Standby Mode, the device waits to be selected, so that it can receive, decode and execute commands. 50 - 33 Rev.1.0 GD25Q32CxIGx 3.3V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com Figure 31. Read Identification ID Sequence Diagram 7.27. High Performance Mode (HPM) (A3H) The High Performance Mode (HPM) command must be executed prior to Dual or Quad I/O commands when operating at high frequencies (see fR and fC1 in AC Electrical Characteristics). This command allows precharging of internal charge pumps so the voltages required for accessing the flash memory array are readily available. The command sequence: CS# goes low → Sending A3H command → Sending 3-dummy byte → CS# goes high. See Figure32. After the HPM command is executed, the device will maintain a slightly higher standby current (Icc8) than standard SPI operation. The Release from Power-Down or HPM command (ABH) can be used to return to standard SPI standby current (Icc1). In addition, Power-Down command (B9H) will also release the device from HPM mode back to standard SPI standby state. Figure 32. High Performance Mode Sequence Diagram CS# SCLK SI 0 1 2 3 4 5 Command A3H 6 7 8 9 29 30 31 t HPM 3 Dummy Bytes 23 22 MSB 2 1 0 SO High Performance Mode 7.28. Program/Erase Suspend (PES) (75H) The Program/Erase Suspend command “75H”, allows the system to interrupt a page program or sector/ block erase operation and then read data from any other sector or block. The Write Status Register command (01H/31H/11H) and Erase/Program Security Registers command (44H, 42H) and Erase commands (20H, 52H, D8H, C7H, 60H) and Page Program command (02H/32H) are not allowed during Program/Erase suspend. Program/Erase Suspend is valid only during the page program or sector/block erase operation. A maximum of 50 - 34 Rev.1.0 GD25Q32CxIGx 3.3V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com time of “tsus” (See AC Characteristics) is required to suspend the program/erase operation. The Program/Erase Suspend command will be accepted by the device only if the SUS2/SUS1 bit in the Status Register equal to 0 and WIP bit equal to 1 while a Page Program or a Sector or Block Erase operation is ongoing. If the SUS2/SUS1 bit equal to 1 or WIP bit equal to 0, the Suspend command will be ignored by the device. The WIP bit will be cleared from 1 to 0 within “tsus” and the SUS2/SUS1 bit will be set from 0 to 1 immediately after Program/Erase Suspend. A power-off during the suspend period will reset the device and release the suspend state. The command sequence is show below. Figure 33. Program/Erase Suspend Sequence Diagram CS# SCLK 0 1 2 3 4 5 6 tSUS 7 Command SI 75H High-Z SO Accept read command 7.29. Program/Erase Resume (PER) (7AH) The Program/Erase Resume command must be written to resume the program or sector/block erase operation after a Program/Erase Suspend command. The Program/Erase command will be accepted by the device only if the SUS2/SUS1 bit equal to 1 and the WIP bit equal to 0. After issued the SUS2/SUS1 bit in the status register will be cleared from 1 to 0 immediately, the WIP bit will be set from 0 to 1 within 200ns and the Sector or Block will complete the erase operation or the page will complete the program operation. The Program/Erase Resume command will be ignored unless a Program/Erase Suspend is active. The command sequence is show in Figure34. Figure 34. Program/Erase Resume Sequence Diagram CS# SCLK SI 0 1 2 3 4 5 6 7 Command 7AH SO Resume Erase/Program 7.30. Erase Security Registers (44H) The GD25Q32C provides three 1024-byte Security Registers which can be erased and programmed individually. These registers may be used by the system manufacturers to store security and other important information separately from the main memory array. The Erase Security Registers command is similar to Sector/Block Erase command. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit. The Erase Security Registers command sequence: CS# goes low → sending Erase Security Registers command 50 - 35 Rev.1.0 GD25Q32CxIGx 3.3V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com → CS# goes high. The command sequence is shown in Figure35. CS# must be driven high after the eighth bit of the command code has been latched in; otherwise the Erase Security Registers command is not executed. As soon as CS# is driven high, the self-timed Erase Security Registers cycle (whose duration is tSE) is initiated. While the Erase Security Registers cycle is in progress, the Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Erase Security Registers cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. The Security Registers Lock Bit (LB3-1) in the Status Register can be used to OTP protect the security registers. Once the LB bit is set to 1, the Security Registers will be permanently locked; the Erase Security Registers command will be ignored. Address A23-A16 A15-A12 A11-A10 A9-A0 Security Register #1 00H 0001 00 Byte Address Security Register #2 Security Register #3 00H 00H 0010 0011 00 00 Byte Address Byte Address Figure 35. Erase Security Registers command Sequence Diagram CS# SCLK 0 1 2 3 4 5 6 7 8 9 24 Bits Address Command SI 44H 29 30 31 23 22 MSB 2 1 0 7.31. Program Security Registers (42H) The Program Security Registers command is similar to the Page Program command. It allows from 1 to 1024 bytes Security Registers data to be programmed. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit before sending the Program Security Registers command. The Program Security Registers command is entered by driving CS# Low, followed by the command code (42H), three address bytes and at least one data byte on SI. As soon as CS# is driven high, the self-timed Program Security Registers cycle (whose duration is tPP) is initiated. While the Program Security Registers cycle is in progress, the Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Program Security Registers cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. If the Security Registers Lock Bit (LB3-1) is set to 1, the Security Registers will be permanently locked. Program Security Registers command will be ignored. Address A23-A16 A15-A12 A11-A10 A9-A0 Security Register #1 Security Register #2 00H 00H 0001 0010 00 00 Byte Address Byte Address Security Register #3 00H 0011 00 Byte Address 50 - 36 Rev.1.0 GD25Q32CxIGx 3.3V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com Figure 36. Program Security Registers command Sequence Diagram CS# 5 6 7 8 24-bit address 3 23 22 21 2 Data Byte 1 0 7 1 MSB 6 5 4 3 2 1 2078 42H 2079 Command SI 28 29 30 31 32 33 34 35 36 37 38 39 9 10 2076 4 2077 3 2075 2 1 0 0 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 2072 MSB CS# 2073 1 2074 0 SCLK SCLK Data Byte 3 Data Byte 2 SI 7 6 5 4 3 2 1 0 7 6 5 4 3 Data Byte 256 2 1 0 7 MSB MSB 6 5 4 3 2 MSB 7.32. Read Security Registers (48H) The Read Security Registers command is similar to Fast Read command. The command is followed by a 3-byte address (A23-A0) and a dummy byte, each bit being latched-in during the rising edge of SCLK. Then the memory content, at that address, is shifted out on SO, each bit being shifted out, at a Max frequency fC, during the falling edge of SCLK. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. Once the A9-A0 address reaches the last byte of the register (Byte 3FFH), it will reset to 000H, the command is completed by driving CS# high. Address A23-A16 A15-A12 A11-A10 A9-A0 Security Register #1 00H 0001 00 Byte Address Security Register #2 Security Register #3 00H 00H 0010 0011 00 00 Byte Address Byte Address Figure 37. Read Security Registers command Sequence Diagram CS# 0 SCLK 1 2 3 4 5 6 8 7 28 29 30 31 24-bit address Command SI 9 10 48H 23 22 21 3 2 1 0 High-Z SO CS# 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCLK SI SO Dummy Byte 7 6 5 4 3 2 1 0 7 6 MSB 50 - 37 Data Out1 5 4 3 2 1 0 Data Out2 7 6 5 MSB Rev.1.0 GD25Q32CxIGx 3.3V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com 7.33. Enable Reset (66H) and Reset (99H) If the Reset command is accepted, any on-going internal operation will be terminated and the device will return to its default power-on state and lose all the current volatile settings, such as Volatile Status Register bits, Write Enable Latch status (WEL), Program/Erase Suspend status, Read Parameter setting (P7-P0), Continuous Read Mode bit setting (M7-M0) and Wrap Bit Setting (W6-W4). The “Reset (99H)” command sequence as follow: CS# goes low → Sending Enable Reset command → CS# goes high → CS# goes low → Sending Reset command → CS# goes high. Once the Reset command is accepted by the device, the device will take approximately tRST=60µs to reset. During this period, no command will be accepted. Data corruption may happen if there is an on-going or suspended internal Erase or Program operation when Reset command sequence is accepted by the device. It is recommended to check the BUSY bit and the SUS bit in Status Register before issuing the Reset command sequence. Figure 38.38. Enable commandSequence Sequence Diagram Figure EnableReset Resetand and Reset Reset command Diagram 7.34. Read Serial Flash Discoverable Parameter (5AH) 7.34. Read Serial Flash Discoverable Parameter (5AH) The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing the functional and feature capabilities of serial flash devices in a standard set of internal parameter tables. These parameter tables can be interrogated by host system software to enable adjustments needed to accommodate divergent features from multiple vendors. The concept is similar to the one found in the Introduction of JEDEC Standard, JESD68 on CFI. SFDP is a standard of JEDEC Standard No.216. FigureFigure 39. Read Serial Flash Discoverable Parameter command Sequence Diagram 39. Read Serial Flash Discoverable Parameter command Sequence Diagram 50 - 38 Rev.1.0 GD25Q32CxIGx 3.3V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com Table3. Signature and Parameter Identification Data Values Description Comment 53H 46H 44H 50H 00H 01H 01H 53H 46H 44H 50H 00H 01H 01H 07H 31:24 FFH FFH 08H 07:00 00H 00H Start from 0×00H 09H 15:08 00H 00H Start from 0×01H 0AH 23:16 01H 01H How many DWORDs in the Parameter Table 0BH 31:24 09H 09H 0CH 0DH 0EH 07:00 15:08 23:16 30H 00H 00H 30H 00H 00H 0FH 31:24 FFH FFH 10H 07:00 C8H C8H Start from 0×00H 11H 15:08 00H 00H Start from 0×01H 12H 23:16 01H 01H How many DWORDs in the Parameter Table 13H 31:24 03H 03H 14H 15H 16H 07:00 15:08 23:16 60H 00H 00H 60H 00H 00H 17H 31:24 FFH FFH SFDF Minor Revision Number SFDF Major Revision Number Number of Parameters Headers Start from 00H Start from 01H Start from 00H Contains 0×FFH and can never be changed 00H: It indicates a JEDEC specified header Parameter Table Minor Revision Number Parameter Table Major Revision Number Parameter Table Length (in double word) Parameter Table Pointer (PTP) Unused ID Number (ELM Manufacturer ID) Parameter Table Minor Revision Number Parameter Table Major Revision Number Parameter Table Length (in double word) Data 07:00 15:08 23:16 31:24 07:00 15:08 23:16 Fixed:50444653H ID number (JEDEC) Data 00H 01H 02H 03H 04H 05H 06H SFDP Signature Unused Add(H) DW Add (Byte) (Bit) Fist address of JEDEC Flash Parameter Table Contains 0×FFH and can never be changed It is indicates ELM manufacturer ID Parameter Table Pointer (PTP) Fist address of ELM Flash Parameter Table Unused Contains 0×FFH and can never be changed 50 - 39 Rev.1.0 GD25Q32CxIGx 3.3V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com Table4. Parameter Table (0): JEDEC Flash Parameter Tables Description Comment 00: Reserved; 01: 4KB erase; Block/Sector Erase Size 10: Reserved; 11: not support 4KB erase Write Granularity 0: 1Byte, 1: 64Byte or larger 0: Nonvolatile status bit Write Enable Instruction Requested for Writing to Volatile 1: Volatile status bit (BP status register bit) Status Registers Add(H) DW Add (Byte) (Bit) 30H 0: Use 50H Opcode, Write Enable Opcode Select for 1: Use 06H Opcode, Writing to Volatile Status Note: If target flash status Registers register is Nonvolatile, then bits 3 and 4 must be set to 00b. Unused 4KB Erase Opcode (1-1-2) Fast Read Address Bytes Number used in addressing flash array Double Transfer Rate (DTR) clocking (1-2-2) Fast Read (1-4-4) Fast Read (1-1-4) Fast Read Unused Unused Flash Memory Density (1-4-4) Fast Read Number of Wait states (1-4-4) Fast Read Number of Mode Bits (1-4-4) Fast Read Opcode (1-1-4) Fast Read Number of Wait states (1-1-4) Fast Read Number of Mode Bits (1-1-4) Fast Read Opcode (1-1-2) Fast Read Number of Wait states (1-1-2) Fast Read Number of Mode Bits (1-1-2) Fast Read Opcode Contains 111b and can never be changed 0=Not support, 1=Support 00: 3Byte only, 01: 3 or 4Byte, 10: 4Byte only, 11: Reserved 0=Not support, 1=Support 0=Not support, 1=Support 0=Not support, 1=Support 0=Not support, 1=Support 00000b: Wait states (Dummy Clocks) not support 000b: Mode Bits not support 00000b: Wait states (Dummy Clocks) not support 000b: Mode Bits not support 00000b: Wait states (Dummy Clocks) not support 000b: Mode Bits not support 31H 32H 33H 37H:34H 38H 39H 3AH 3BH 3CH 3DH 50 - 40 Data 01:00 01b 02 1b 03 0b 04 0b 07:05 111b 15:08 16 20H 1b 18:17 00b 19 0b 20 21 22 23 31:24 31:00 Data E5H 20H F1H 1b 1b 1b 1b FFH FFH 01FFFFFFH 04:00 00100b 07:05 010b 15:08 EBH 20:16 01000b 23:21 000b 31:24 6BH 04:00 01000b 07:05 000b 15:08 3BH 44H EBH 08H 6BH 08H 3BH Rev.1.0 GD25Q32CxIGx 3.3V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com Description (1-2-2) Fast Read Number of Wait states (1-2-2) Fast Read Number of Mode Bits (1-2-2) Fast Read Opcode (2-2-2) Fast Read Unused (4-4-4) Fast Read Unused Unused Unused (2-2-2) Fast Read Number of Wait states (2-2-2) Fast Read Number of Mode Bits (2-2-2) Fast Read Opcode Unused (4-4-4) Fast Read Number of Wait states (4-4-4) Fast Read Number of Mode Bits (4-4-4) Fast Read Opcode Sector Type 1 Size Sector Type 1 erase Opcode Sector Type 2 Size Sector Type 2 erase Opcode Sector Type 3 Size Sector Type 3 erase Opcode Sector Type 4 Size Sector Type 4 erase Opcode Comment 00000b: Wait states (Dummy Clocks) not support 000b: Mode Bits not support 0=not support; 1=support 0=not support; 1=support 00000b: Wait states (Dummy Clocks) not support 000b: Mode Bits not support 00000b: Wait states (Dummy Clocks) not support 000b: Mode Bits not support Sector/block size=2^N bytes 0×00b: this sector type don’t exist Sector/block size=2^N bytes 0×00b: this sector type don’t exist Sector/block size=2^N bytes 0×00b: this sector type don’t exist Sector/block size=2^N bytes 0×00b: this sector type don’t exist 50 - 41 Add(H) DW Add (Byte) (Bit) Data Data 20:16 00010b 23:21 010b 31:24 00 03:01 04 07:05 31:08 15:00 BBH 0b 111b 0b 111b 0×FFH 0×FFH 20:16 00000b 23:21 000b 31:24 15:00 FFH 0×FFH 20:16 00000b 23:21 000b 4BH 31:24 FFH FFH 4CH 07:00 0CH 0CH 4DH 15:08 20H 20H 4EH 23:16 0FH 0FH 4FH 31:24 52H 52H 50H 07:00 10H 10H 51H 15:08 D8H D8H 52H 23:16 00H 00H 53H 31:24 FFH FFH 3EH 3FH 40H 43H:41H 45H:44H 46H 47H 49H:48H 4AH 42H BBH EEH 0×FFH 0×FFH 00H FFH 0×FFH 00H Rev.1.0 GD25Q32CxIGx 3.3V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com Table5. Parameter Table (1): ELM Flash Parameter Tables Description Vcc Supply Maximum Voltage Vcc Supply Minimum Voltage HW Reset# pin HW Hold# pin Deep Power Down Mode SW Reset SW Reset Opcode Program Suspend/Resume Erase Suspend/Resume Unused Wrap-Around Read mode Wrap-Around Read mode Opcode Comment 2000H=2.000V 2700H=2.700V 3600H=3.600V 1650H=1.650V 2250H=2.250V 2350H=2.350V 2700H=2.700V 0=not support; 1=support 0=not support; 1=support 0=not support; 1=support 0=not support; 1=support Should be issue Reset Enable(66H) before Reset cmd. 0=not support; 1=support 0=not support; 1=support Add(H) (Byte) DW Add (Bit) Data Data 61H:60H 15:00 3600H 3600H 63H:62H 31:16 2700H 2700H 00 01 02 03 65H:64H 12 13 14 15 0=not support; 1=support 08H: support 8B wrap-around read Wrap-Around Read data length 16H: 8B & 16B 32H: 8B & 16B & 32B 64H: 8B & 16B & 32B & 64B Individual block lock 0=not support; 1=support Individual block lock bit 0=Volatile; 1=Nonvolatile (Volatile/Nonvolatile) Individual block lock Opcode Individual block lock Volatile 0=protect; 1=unprotect protect bit default protect status Secured OTP 0=not support; 1=support Read Lock 0=not support; 1=support Permanent Lock 0=not support; 1=support Unused Unused 50 - 42 11:04 0b 1b 1b 1b 1001 1001b F99EH (99H) 1b 1b 1b 1b 66H 23:16 77H 77H 67H 31:24 64H 64H 00 0b 01 0b 09:02 FFH 10 0b EBFCH 11 12 13 15:14 31:16 1b 0b 1b 11b FFFFH FFFFH 6BH:68H Rev.1.0 GD25Q32CxIGx 3.3V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com 8. ELECTRICAL CHARACTERISTICS 8.1. Power-On Timing Figure 40. Power-on Timing Sequence Diagram Table6. Power-Up Timing and Write Inhibit Threshold Symbol Parameter Min tVSL VCC(min) To CS# Low 10 tPUW VWI Time Delay From VCC(min) To Write Instruction Write Inhibit Voltage VCC(min) 1 1 Max Unit us 10 2.5 ms V 8.2. Initial Delivery State The device is delivered with the memory array erased: all bits are set to 1(each byte contains FFH).The Status Register bits are set to 0, except DRV0 bit (S21) is set to 1. 8.3. Data Retention And Endurance Parameter Minimum Pattern Data Retention Time Erase/Program Endurance 50 - 43 Test Condition Min Unit 150°C 125°C -40 to 85°C 10 20 100K Years Years Cycles Rev.1.0 GD25Q32CxIGx 3.3V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com 8.4. Absolute Maximum Ratings Parameter Ambient Operating Temperature Storage Temperature Value Unit -40 to 85 °C -65 to 150 °C 200 mA V Output Short Circuit Current Applied Input/Output Voltage Transient Input/Output Voltage(note: overshoot) -0.6 to VCC+4.0 -2.0 to VCC+2.0 VCC -0.6 to VCC+4.0 V V Figure 41. Maximum Negative/positive Overshoot Diagram Maximum Negative Overshoot Waveform 20ns Maximum Positive Overshoot Waveform 20ns 20ns Vss Vcc + 2.0V Vss-2.0V Vcc 20ns 20ns 20ns 8.5. Capacitance Measurement Conditions Symbol CIN COUT CL Parameter Min Typ Max Unit Conditions 6 8 pF pF VIN=0V VOUT=0V 5 0.1VCC to 0.8VCC pF ns V 0.2VCC to 0.7VCC 0.5VCC V V Input Capacitance Output Capacitance Load Capacitance Input Rise And Fall time Input Pulse Voltage Input Timing Reference Voltage 30 Output Timing Reference Voltage Figure 42. Input Test Waveform and Measurement Level Diagram 0.8VCC 0.1VCC Input timing reference level 0.7VCC 0.2VCC Output timing reference level AC Measurement Level 0.5VCC Note: Input pulse rise and fall time are <5ns 50 - 44 Rev.1.0 GD25Q32CxIGx 3.3V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com 8.6. DC Characteristics Symbol (T= -40°C~85°C, VCC=2.7~3.6V) Max. Unit. Input Leakage Current ±2 μA ILO ICC1 Output Leakage Current Standby Current CS#=VCC, VIN=VCC or VSS 1 ±2 5 μA μA ICC2 Deep Power-Down Current CS#=VCC, VIN=VCC or VSS 1 5 μA CLK=0.1VCC/0.9VCC at 120MHz, Q=Open(*1,*2,*4 I/O) 15 20 mA CLK=0.1VCC/0.9VCC at 80MHz, Q=Open(*1,*2,*4 I/O) 13 18 mA ILI ICC3 Parameter Operating Current (Read) Test Condition Min. Typ. ICC4 Operating Current (PP) CS#=VCC 20 mA ICC5 ICC6 Operating Current (WRSR) CS#=VCC Operating Current (SE) CS#=VCC 20 20 mA mA ICC7 Operating Current (BE) CS#=VCC 20 mA ICC8 ICC9 Operating Current (CE) High Performance Current CS#=VCC 20 800 mA μA VIL VIH Input Low Voltage Input High Voltage 0.2VCC VCC+0.4 V V VOL Output Low Voltage IOL=100μA 0.2 V VOH Output High Voltage IOH=-100μA 400 -0.5 0.7VCC VCC-0.2 8.7. AC Characteristics Symbol fC fC1 fC2 fR tCLH tCLL V (T= -40°C~85°C, VCC=2.7~3.6V, CL=30pf) Parameter Min. Serial Clock Frequency For: Dual I/O(BBH), Quad I/O(EBH), Quad Output(6BH) (Dual I/O & Quad I/O Without High Performance Mode), on 3.0V-3.6V power supply Serial Clock Frequency For: Dual I/O(BBH), Quad I/O(EBH), Quad Output(6BH) (Dual I/O & Quad I/O Without High Performance Mode), on 2.7V-3.0V power supply Serial Clock Frequency For: Dual I/O(BBH), Quad I/O(EBH), Quad Output(6BH) (Dual I/O & Quad I/O With High Performance Mode), on 2.7V-3.6V power supply Serial Clock Frequency For: Read (03H) Serial Clock High Time Serial Clock Low Time Typ. Max. Unit. DC. 104 MHz DC. 80 MHz DC. 120 MHz DC. 80 MHz 4 4 ns ns tCLCH Serial Clock Rise Time (Slew Rate) 0.2 V/ns tCHCL Serial Clock Fall Time (Slew Rate) tSLCH CS# Active Setup Time 0.2 5 V/ns ns 5 ns tCHSH CS# Active Hold Time 50 - 45 Rev.1.0 GD25Q32CxIGx 3.3V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com Symbol Parameter Min. Typ. Max. Unit. tSHCH CS# Not Active Setup Time 5 ns tCHSL CS# Not Active Hold Time 5 ns tSHSL CS# High Time (Read/Write) 20 ns tSHQZ Output Disable Time tCLQX Output Hold Time 6 1.2 ns ns tDVCH Data In Setup Time 2 ns tCHDX Data In Hold Time tHLCH Hold# Low Setup Time (Relative to Clock) 2 5 ns ns tHHCH Hold# High Setup Time (Relative to Clock) 5 ns tCHHL Hold# High Hold Time (Relative to Clock) tCHHH Hold# Low Hold Time (Relative to Clock) tHLQZ Hold# Low To High-Z Output 5 5 6 ns ns ns tHHQX Hold# High To Low-Z Output 6 ns tCLQV Clock Low To Output Valid tWHSL Write Protect Setup Time Before CS# Low 7 ns ns 20 tSHWL Write Protect Hold Time After CS# High tDP CS# High To Deep Power-Down Mode 100 20 ns μs tRES1 CS# High To Standby Mode Without Electronic Signature Read tRES2 CS# High To Standby Mode With Electronic Signature Read tSUS CS# High To Next Command After Suspend 20 20 20 μs μs μs tRST tW tBP1 CS# High To Next Command After Reset Write Status Register Cycle Time Byte Program Time (First Byte) 5 30 20 30 50 μs ms μs tBP2 tPP Additional Byte Program Time (After First Byte) Page Programming Time 2.5 0.6 12 2.4 μs ms tSE Sector Erase Time (4K Bytes) 50 200/300(1) ms tBE1 tBE2 tCE Block Erase Time (32K Bytes) Block Erase Time (64K Bytes) Chip Erase Time (GD25Q32C) 0.15 0.25 15 0.8/1.6(2) 1.2/2.0(3) 30 s s s Note: (1). Max Value 4KB tSE with<50K cycles is 200ms and >50K & <100k cycles is 300ms. (2). Max Value 32KB tBE with<50K cycles is 0.8s and >50K & <100k cycles is 1.6s. (3). Max Value 64KB tBE with<50K cycles is 1.2s and >50K & <100k cycles is 2.0s. 50 - 46 Rev.1.0 GD25Q32CxIGx 3.3V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com Figure43. Serial Input Timing Diagram tSHSL CS# tCHSL SCLK tSLCH tDVCH tCHSH MSB SO High-Z tCHCL tCLCH tCHDX SI tSHCH LSB Figure44. Output Timing Diagram CS# tCLH SCLK tCLQV tCLQX tCLQV tSHQZ tCLL tCLQX LSB SO SI Least significant address bit (LIB) in Figure45. Hold Timing Diagram CS# SCLK SO tCHHL tHLCH tCHHH tHLQZ tHHCH tHHQX HOLD# SI do not care during HOLD operation. 50 - 47 Rev.1.0 GD25Q32CxIGx 3.3V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com 9. ORDERING INFORMATION GD 25 Q 32 C x I G x Packing Type Y: Tray R: Tape & Reel Green Code G: Pb Free & Halogen Free Green Package S: Pb Free & Halogen Free Green Package SRP1 available Temperature Range I: Industrial(-40°C to +85°C) Package Type S: SOP8 208mil W: WSON8 (6×5mm) Generation C: Version Density 32: 32Mb Series Q: 3V, 4KB Uniform Sector Product Family 25: SPI Interface Flash 50 - 48 Rev.1.0 GD25Q32CxIGx 3.3V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com 10. PACKAGE INFORMATION 10.1 Package SOP8 208MIL 8 � 5 E1 E L 1 L1 4 C D A2 Dimensions Symbol Unit A1 b e A A A1 A2 b c D E E1 e L L1 θ - 0.05 1.70 0.31 0.18 5.13 7.70 5.18 - 0.50 1.21 0° 2.16 - 0.15 0.25 0.002 1.80 0.41 1.91 0.51 0.067 0.012 1.27BSC - 0.67 0.85 0.020 1.31 1.41 0.048 5° 8° 0° Inch Nom 0.006 0.071 0.016 0.008 0.206 0.311 0.208 0.050BSC 0.026 Max 0.085 0.010 0.075 0.020 0.010 0.210 0.319 0.212 0.033 Note: Both package length and width do not include mold flash. 0.052 0.056 5° 8° Min mm Nom Max Min 0.21 5.23 0.25 5.33 0.007 0.202 50 - 49 7.90 5.28 8.10 5.38 0.303 0.204 Rev.1.0 GD25Q32CxIGx 3.3V Uniform Sector Dual and Quad Serial Flash http://www.elm-tech.com 10.2 Package WSON8 (6×5mm) D A2 y E A Top View L A1 Side View D1 b 1 E1 e Bottom View Dimensions Symbol Unit A A1 A2 b D D1 E E1 e y L mm Min Nom 0.70 0.75 - 0.19 0.22 0.35 0.42 5.90 6.00 3.25 3.37 4.90 5.00 3.85 3.97 1.27 BSC 0.00 0.04 0.50 0.60 Inch Max Min Nom 0.80 0.028 0.030 0.05 - 0.25 0.007 0.009 0.48 0.014 0.016 6.10 0.232 0.236 3.50 0.128 0.133 5.10 0.193 0.197 4.10 0.151 0.156 0.05 BSC 0.08 0.000 0.001 0.75 0.020 0.024 Max 0.032 0.002 0.010 0.019 0.240 0.138 0.201 0.161 - 0.003 0.030 Note: 1. Both package length and width do not include mold flash. 2. The exposed metal pad area on the bottom of the package is connected to device ground (GND pin), so both Floating and connecting GND of exposed pad are also available. 50 - 50 Rev.1.0