TH71112 868/915MHz FSK/ASK Receiver Features Double-conversion superhet architecture for high degree of image rejection FSK demodulation with phase-coincidence demodulator Low current consumption in active mode and very low standby current Switchable LNA gain for improved dynamic range RSSI allows signal strength indication and ASK detection 32-pin Low profile Quad Flat Package (LQFP) Ordering Information Part No. Temperature Code Package Code Part Number Temperature Code Package Code Delivery Form TH71112 E (-40 °C to 85 °C) C (-10 °C to 70 °C) NE (LQFP32) 250 pc/tray 2000 pc/T&R General digital data transmission Tire Pressure Monitoring Systems (TPMS) Remote Keyless Entry (RKE) Wireless access control Alarm and security systems Garage door openers Remote Controls Home and building automation Low-power telemetry systems Pin Description OUTP VEE_BIAS RSSI OAP OAN OUT_OA VCC_BIAS Application Examples 24 VEE_RO RO VCC_PLL ENRX LF VEE_LNA IN_LNA VCC_LNA 17 25 16 OUT_IFA VCC_IF FBC2 FBC1 IN_IFA VEE_IF OUT_MIX2 TH71112 32 9 8 VEE_LNAC GAIN_LNA OUT_LNA IN_MIX1 VEE_MIX IF_1P IF_1N VCC_MIX 1 General Description The TH71112 FSK/ASK double-conversion superheterodyne receiver IC is designed for applications in the European 868 MHz industrial-scientific-medical (ISM) band, according to the EN 300 220 telecommunications standard. It can also be used for any other system with carrier frequencies ranging from 750 MHz to 990 MHz (e.g. for applications according to FCC part 15). 39010 71112 Rev. 015 Page 1 of 20 Data Sheet Jan/09 TH71112 868/915MHz FSK/ASK Receiver Document Content 1 Theory of Operation ...................................................................................................3 1.1 General ............................................................................................................................. 3 1.2 Technical Data Overview.................................................................................................. 3 1.3 Block Diagram .................................................................................................................. 4 1.4 Mode Configurations ........................................................................................................ 4 1.5 LNA GAIN Control ............................................................................................................ 4 1.6 Frequency Planning.......................................................................................................... 4 1.6.1 1.6.2 Selected Frequency Plans........................................................................................................... 5 Maximum Frequency Coverage................................................................................................... 5 2 Pin Definitions and Descriptions ..............................................................................6 3 Technical Data............................................................................................................9 4 3.1 Absolute Maximum Ratings .............................................................................................. 9 3.2 Normal Operating Conditions ........................................................................................... 9 3.3 Crystal Parameters ........................................................................................................... 9 3.4 DC Characteristics.......................................................................................................... 10 3.5 AC System Characteristics ............................................................................................. 11 Test Circuits .............................................................................................................12 4.1 Standard FSK Reception ................................................................................................ 12 4.1.1 4.1.2 4.2 Standard FSK Application Circuit .............................................................................................. 12 Standard FSK Component List .................................................................................................. 13 Narrow Band FSK Reception.......................................................................................... 14 4.2.1 4.2.2 4.3 Narrow Band FSK Application Circuit ........................................................................................ 14 Narrow Band FSK Component List............................................................................................ 15 ASK Reception ............................................................................................................... 16 4.3.1 4.3.2 5 ASK Application Circuit .............................................................................................................. 16 ASK Component List.................................................................................................................. 17 Package Description ................................................................................................18 5.1 Soldering Information ..................................................................................................... 18 6 Reliability Information .............................................................................................19 7 ESD Precautions ......................................................................................................19 8 Disclaimer .................................................................................................................20 39010 71112 Rev. 015 Page 2 of 20 Data Sheet Jan/09 TH71112 868/915MHz FSK/ASK Receiver 1 Theory of Operation 1.1 General With the TH71112 receiver chip, various circuit configurations can be arranged in order to meet a number of different customer requirements. For FSK reception the IF tank used in the phase coincidence demodulator can be constituted by an external ceramic discriminator. In ASK configuration, the RSSI signal is fed to an ASK detector, which is constituted by the operational amplifier. The superheterodyne configuration is double conversion where MIX1 and MIX2 are driven by the internal local oscillator signals LO1 and LO2, respectively. This allows a high degree of image rejection, achieved in conjunction with an RF front-end filter. Efficient RF front-end filtering is realized by using a SAW, ceramic or helix filter in front of the LNA and by adding an LC filter at the LNA output. A single-conversion variant, called TH71111, is also available. Both Receiver ICs have the same die. At the TH71111 the second mixer MIX2 operates as an amplifier. The TH71112 receiver IC consists of the following building blocks: 1.2 PLL synthesizer (PLL SYNTH) for generation of the first and second local oscillator signals LO1 and LO2, parts of the PLL SYNTH are: the high-frequency VCO1, the feedback dividers DIV_16 and DIV_2, a phase-frequency detector (PFD) with charge pump (CP) and a crystal-based reference oscillator (RO) Low-noise amplifier (LNA) for high-sensitivity RF signal reception First mixer (MIX1) for down-conversion of the RF signal to the first IF (IF1) Second mixer (MIX2) for down-conversion of the IF1 to the second IF (IF2) IF amplifier (IFA) to amplify and limit the IF2 signal and for RSSI generation Phase coincidence demodulator (DEMOD) with third mixer (MIX3) to demodulate the IF signal Operational amplifier (OA) for data slicing, filtering and ASK detection Bias circuitry for bandgap biasing and circuit shutdown Technical Data Overview Input frequency range: 750 MHz to 990 MHz Power supply range: 2.3 V to 5.5 V @ ASK Temperature range: -40 °C to +85 °C Standby current: 50 nA Operating current: 7.5 mA @ low gain mode 9.2 mA @ high gain mode Sensitivity: -112 dBm @ ASK 1) -106 dBm @ FSK 2) Maximum data rate: 260 kbps NRZ @ ASK 180 kbps NRZ @ FSK Range of IF1: 10 MHz to 80 MHz Range of IF2: 400 kHz to 22 MHz Maximum input level: -10 dBm @ ASK 0 dBm @ FSK Image rejection: > 60 dB (e.g. with 868.3 MHz SAW front-end filter and at 10.7 MHz IF2) Spurious emission: < -70 dBm Input frequency acceptance range: up to ±100 kHz RSSI range: 70 dB FSK deviation range: ±2.5 kHz to ±80 kHz 1) at 4 kbps NRZ, BER = 3⋅10-3, 180 kHz IF filter BW, without SAW front-end-filter loss 2) at 4 kbps NRZ, BER = 3⋅10-3, ± 20 kHz FSK deviation, 180 kHz IF filter BW, without SAW front-end-filter loss 39010 71112 Rev. 015 Page 3 of 20 Data Sheet Jan/09 TH71112 868/915MHz FSK/ASK Receiver IN_LNA 31 MIX1 21 14 15 16 MIX2 OUTP MIX3 IF2 IF1 LNA IN_DEM 13 OUT_IFA 12 RSSI 11 FBC1 10 IN_IFA 9 VEE_IF 8 OUT_MIX2 7 VCC_MIX 6 IF1N 5 IF1P 4 VEE_MIX 3 IN_MIX1 2 OUT_LNA 1 GAIN_LNA Block Diagram VEE_LNAC 1.3 23 IFA OUTN 24 LO2 LO1 OAP OA 19 PFD OUT_OA RO 25 27 28 ENRX 26 RO VCC_PLL 29 LF VEE_RO 30 18 CP VEE_LNA VCC_LNA VCO1 BIAS 22 17 VCC_BIAS DIV2 VEE_BIAS DIV16 32 20 OAN Fig. 1: TH71112 block diagram 1.4 Mode Configurations ENRX Mode Description 0 RX standby RX disabled 1 RX active RX enable Note: ENRX are pulled down internally 1.5 LNA GAIN Control VGAIN_LNA Mode Description < 0.8 V HIGH GAIN LNA set to high gain > 1.4 V LOW GAIN LNA set to low gain Note: hysteresis between gain modes to ensure stability 1.6 Frequency Planning Frequency planning is straightforward for single-conversion applications because there is only one IF that can be chosen, and then the only possible choice is low-side or high-side injection of the LO signal (which is now the one and only LO signal in the receiver). The receiver’s double-conversion architecture requires careful frequency planning. Besides the desired RF input signal, there are a number of spurious signals that may cause an undesired response at the output. Among them are the image of the RF signal (that must be suppressed by the RF front-end filter), spurious signals injected to the first IF (IF1) and their images which could be mixed down to the same second IF (IF2) as the desired RF signal (they must be suppressed by the LC filter at IF1 and/or by low-crosstalk design). 39010 71112 Rev. 015 Page 4 of 20 Data Sheet Jan/09 TH71112 868/915MHz FSK/ASK Receiver By configuring the TH71112 for double conversion and using its internal PLL synthesizer with fixed feedback divider ratios of N1 = 16 (DIV_16) and N2 = 2 (DIV_2), four types of down-conversion are possible: low-side injection of LO1 and LO2 (low-low), LO1 low-side and LO2 high-side (low-high), LO1 high-side and LO2 low-side (high-low) or LO1 and LO2 high-side (high-high). The following table summarizes some equations that are useful to calculate the crystal reference frequency (REF), the first IF (IF1) and the VCO1 or first LO frequency (LO1), respectively, for a given RF and second IF (IF2). Injection type high-high low-low high-low low-high REF (RF – IF2)/30 (RF – IF2)/34 (RF + IF2)/30 (RF + IF2)/34 LO1 32•REF 32•REF 32•REF 32•REF IF1 LO1 – RF RF – LO1 LO1 – RF RF – LO1 LO2 2•REF 2•REF 2•REF 2•REF IF2 LO2 – IF1 IF1 – LO2 IF1 – LO2 LO2 – IF1 1.6.1 Selected Frequency Plans The following table depicts crystal, LO and image signals considering the examples of 868.3 MHz and 915 MHz RF reception at IF2 = 10.7 MHz. The columns in bold depict the selected frequency plans to receive at 868.3 MHz and 915 MHz, respectively. Signal type RF = 868.3 MHz Injection type high-high RF = 868.3 MHz RF = 868.3 MHz RF = 868.3 MHz RF = 915 MHz RF = 915 MHz RF = 915 MHz RF = 915 MHz low-low high-low low-high high-high low-low high-low low-high REF / MHz 28.58667 25.22353 29.3 25.85294 30.14333 26.59706 30.85667 27.22647 LO1 / MHz 914.77333 807.15294 937.6 827.29412 964.58667 851.10588 987.41333 871.24706 IF1 / MHz 46.47333 61.14706 69.3 41.00588 49.58667 63.89412 72.41333 43.75294 LO2 / MHz 57.17333 50.44706 58.6 51.70588 60.28667 53.19412 61.71333 54.45294 RF image/MHz 961.24667 746.00588 1006.9 786.28824 1014.17 787.21176 1059.83 827.49412 IF1 image/MHz 39.74706 47.9 62.40588 70.98667 42.49412 51.01333 65.15294 1.6.2 67.87333 Maximum Frequency Coverage Parameter fmin fmax Injection type high-low low-low RF / MHz 739.3 998.825 REF / MHz 25.0 29.0625 LO1 / MHz 800 930 IF1 / MHz 60.7 68.825 LO2 / MHz 50.0 58.125 IF2/ MHz 10.7 10.7 39010 71112 Rev. 015 The selection of the reference crystal frequency is based on some assumptions. As for example: the first IF and the image frequencies should not be in a radio band where strong interfering signals might occur (because they could represent parasitic receiving signals), the LO1 signal should be in the range of 800 MHz to 930 MHz (because this is the optimum frequency range of the VCO1). Furthermore the first IF should be as high as possible to achieve highest RF image rejection. Page 5 of 20 Data Sheet Jan/09 TH71112 868/915MHz FSK/ASK Receiver 2 Pin Definitions and Descriptions Pin No. 3 Name OUT_LNA I/O Type Functional Schematic analog output Description LNA open-collector output, to be connected to external LC tank that resonates at RF OUT_LNA 3 31 IN_LNA analog input 1 VEE_LNAC ground 2 GAIN_LNA analog input 5k IN_LNA VEE_LNAC 31 ground of LNA core (cascode) 1 LNA gain control (input with hysteresis) GAIN_LNA 400Ω RX standby: no pull-up RX active: pull-up 2 4 IN_MIX1 LNA input, approx. 26Ω single-ended analog input MIX1 input, approx. 33Ω single-ended 13Ω IN_MIX1 4 13Ω 500µA 5 VEE_MIX ground 6 IF1P analog I/O ground of MIX1 and MIX2 VCC 20p IF1P IF1N 20p 7 6 7 IF1N analog I/O open-collector output, to be connected to external LC tank that resonates at first IF 2x500µA VEE VEE 8 VCC_MIX supply 9 OUT_MIX2 analog output open-collector output, to be connected to external LC tank that resonates at first IF positive supply of MIX1 and MIX2 6.8k OUT_MIX2 MIX2 output, approx. 330Ω output impedance 130Ω 9 230µA 10 VEE_IF 39010 71112 Rev. 015 ground ground of IFA and DEMOD Page 6 of 20 Data Sheet Jan/09 TH71112 868/915MHz FSK/ASK Receiver Pin No. 11 12 Name IN_IFA FBC1 I/O Type Functional Schematic analog input analog I/O IN_IFA FBC1 11 12 2.2k analog I/O FBC2 to be connected to external IFA feedback capacitor 2.2k 200µA FBC2 IFA input, approx. 2.2kΩ input impedance VCC VCC VEE VCC 13 Description VEE VEE to be connected to external IFA feedback capacitor 13 VEE 14 VCC_IF supply positive supply of IFA and DEMOD 15 OUT_IFA analog I/O IFA output and MIX3 input (of DEMOD) OUT_IFA 15 40µA 16 IN_DEM analog input DEMOD input, to MIX3 core 47k IN_DEM 16 17 VCC_BIAS supply positive supply of general bias system and OA 18 OUT_OA analog output OA output, 40uA current drive capability OUT_OA 50Ω 18 19 OAN analog input negative OA input 20µA OAN 20 OAP 39010 71112 Rev. 015 analog input 50Ω 50Ω OAP positive OA input 20 19 Page 7 of 20 Data Sheet Jan/09 TH71112 868/915MHz FSK/ASK Receiver Pin No. 21 Name RSSI I/O Type Functional Schematic analog output 50Ω RSSI Description RSSI output, for RSSI and ASK detection, approx. 36kΩ output impedance I (Pi) 21 36k 22 VEE_BIAS ground ground of general bias system and OA 23 OUTP analog output FSK positive output, output impedance of 100kΩ to 300kΩ 24 OUTN analog output OUTP OUTN 50Ω 23 24 20µA 20µA FSK negative output, output impedance of 100kΩ to 300kΩ 25 VEE_RO ground ground of DIV, PFD, RO and charge pump 26 RO analog input RO input, Colpitts type oscillator with internal feedback capacitors 50k RO 26 30p 30p 27 VCC_PLL supply positive supply of DIV, PFD, RO and charge pump 28 ENRX digital input mode control input, CMOS-compatible with internal pull-down circuit ENRX 1.5k 28 29 LF analog I/O charge pump output and VCO1 control input LF 200Ω 29 400Ω 4p 30 VEE_LNA ground ground of LNA biasing 32 VCC_LNA supply positive supply of LNA biasing 39010 71112 Rev. 015 Page 8 of 20 Data Sheet Jan/09 TH71112 868/915MHz FSK/ASK Receiver 3 Technical Data 3.1 Absolute Maximum Ratings Parameter Supply voltage Input voltage Input RF level Storage temperature Junction temperature Thermal Resistance Power dissipation Electrostatic discharge Symbol VCC VIN PiRF TSTG TJ RthJA Pdiss VESD1 VESD2 Condition / Note Min Max Unit 0 - 0.3 V V dBm °C °C K/W W -1.0 -0.75 7.0 Vcc+0.3 10 +125 +150 60 0.1 +1.0 +0.75 Min Max Unit 2.5 2.6 2.7 2.3 -40 -10 5.5 5.5 5.5 5.5 +85 +70 0.3*VCC @ LNA input -40 human body model, 3) human body model, 4) kV 3) all pins except OUT_LNA, IF1P and IF1N 4) pin OUT_LNA, IF1P and IF1N 3.2 Normal Operating Conditions Parameter Symbol VCC, FSK Supply voltage Operating temperature Input low voltage (CMOS) Input high voltage (CMOS) Input frequency range First IF range Second IF range XOSC frequency VCO frequency Frequency deviation FSK data rate ASK data rate VCC, ASK TA VIL VIH fi fIF1 fIF2 fref fLO Δf RFSK RASK Condition 0 °C to 85 °C -20 °C to 85 °C -40 °C to 85 °C -40 °C to 85 °C TH71112 E TH71112 C ENRX pin ENRX pin set by the crystal fLO = 16 • fref 0.7*VCC 739.3 10 0.4 25 800 ±2.5 998.8 80 22 29.063 930 V ºC V V MHz MHz MHz MHz MHz ±80 180 260 kbps kbps Min Max Unit 25 10 29.063 15 7 50 MHz pF pF NRZ, C15 = NIP, 5) NRZ, C16 = NIP, 5) kHz 5) BIF = 400 kHz, PIN = -90 dBm 3.3 Crystal Parameters Parameter Crystal frequency Load capacitance Static capacitance Series resistance 39010 71112 Rev. 015 Symbol f0 CL C0 R1 Condition fundamental mode, AT Page 9 of 20 Ω Data Sheet Jan/09 TH71112 868/915MHz FSK/ASK Receiver 3.4 DC Characteristics all parameters under normal operating conditions, unless otherwise stated; typical values at TA= 23 °C and VCC = 3 V Parameter Symbol Condition ISBY ICC, low ENRX=0 ENRX=1, GAIN_LNA=1, TH71112 E ENRX=1, GAIN_LNA=1, TH71112 C ENRX=1, GAIN_LNA=0, TH71112 E ENRX=1, GAIN_LNA=0, TH71112 C Min Typ Max Unit 4.5 50 7.5 100 12.0 nA mA Operating Currents Standby current Supply current at low gain Supply current at high gain ICC, high 11.6 5.0 9.2 mA 14.0 13.5 Digital Pin Characteristics Input low voltage CMOS Input high voltage CMOS Pull down current ENRX pin Low level input current ENRX pin VIL VIH IPDEN ENRX pin ENRX pin ENRX=1 -0.3 0.7*VCC 0.1 IINLEN ENRX=0 0.05 µA IINHGAIN GAIN_LNA=1 0.05 µA IPUGAINa GAIN_LNA=0 ENRX=1 GAIN_LNA=0 ENRX=0 ENRX=1 ENRX=1 0.3 µA 0.05 µA 0.7 V V 35 50 150 mV nA nA 2 0.3*Vcc VCC+0.3 10 V V µA Analog Pin Characteristics High level input current GAIN_LNA pin Pull up current GAIN_LNA pin active Pull up current GAIN_LNA pin standby IPUGAINs High gain input voltage Low gain input voltage VIHGAIN VILGAIN 0.08 0.15 1.5 Opamp Characteristics Opamp input offset voltage Opamp input offset current Opamp input bias current Voffs Ioffs Ibias IOAP – IOAN 0.5 * (IOAP + IOAN) -35 -50 -150 RSSI Characteristics RSSI voltage at low input level VRSSI, low RSSI voltage at high input level VRSSI, high 39010 71112 Rev. 015 Pi = -65 dBm, GAIN_LNA=1 Pi = -35 dBm, GAIN_LNA=1 Page 10 of 20 0.5 1.0 1.5 V 1.2 1.9 2.5 V Data Sheet Jan/09 TH71112 868/915MHz FSK/ASK Receiver 3.5 AC System Characteristics all parameters under normal operating conditions, unless otherwise stated; typical values at TA = 23 °C and VCC = 3 V, RF at 868.3 MHz; SAW frond-end filter loss and IF at 10.7 MHz; all parameters based on test circuits as shown in Fig. 2, Fig.3 and Fig. 5 Parameter Symbol Condition Min Typ Max Unit Receive Characteristics BIF = 180kHz, Δf = ±20kHz, 4kbps NRZ, BER ≤ 3⋅10-3, 6) BIF = 30kHz, Δf = ±5kHz, 4kbps NRZ, BER ≤ 3⋅10-3, 6) BIF = 180kHz, 4kbps NRZ, BER ≤ 3⋅10-3, 6) -103 dBm -105 dBm -109 dBm BER ≤ 3⋅10-3 GAIN_LNA = 1 0 dBm -10 dBm Input sensitivity – FSK (standard) Pmin, ST Input sensitivity – FSK (narrow band) Pmin, NB Input sensitivity – ASK Pmin, ASK Maximum input signal – FSK Pmax, FSK Maximum input signal – ASK Pmax, ASK BER ≤ 3⋅10-3 GAIN_LNA = 1 Pspur Spurious emission Image rejection ΔPimag -70 dBm dB 0.9 ms 60 Start-up Parameters Crystal start-up time Receiver start-up time TXTL TRX ENRX from 0 to 1 ENRX from 0 to 1, depends on data slicer time constant, valid data at output TXTL + R4 · C17 PLL Parameters VCO gain Charge pump current KVCO ICP 350 60 MHz/V µA 6) incl. 3 dB loss of front-end SAW filter 39010 71112 Rev. 015 Page 11 of 20 Data Sheet Jan/09 TH71112 868/915MHz FSK/ASK Receiver 4 Test Circuits 4.1 Standard FSK Reception 4.1.1 Standard FSK Application Circuit OUTP RSSI C15 C16 R5 R4 FSK output C17 VCC C3 3 C10 VCC 17 OAN 19 OUT_OA 18 OAP 20 VEE GAIN_LNA OUT_LNA IN_MIX1 VEE IF1P IF1N VCC VEE 10 1 2 3 4 5 6 7 8 CERFIL C8 C7 SAWFIL L1 C4 L5 1 R2 OUT_MIX2 9 L4 4 C11 FBC1 12 IN_IFA 11 32 VCC VCC C9 30 VEE VCC C12 FBC2 13 TH71112 29 LF 31 IN_LNA 6 16 VCC 14 28 ENRX R1 CERDIS OUT_IFA 15 26 RO 27 VCC ENRX C5 RSSI 21 25 VEE C1 L2 VEE 22 24 XTAL OUTP 23 VCC L3 CB* VCC 50 RF input * each Vcc pin with blocking cap of 330pF * one global Vcc blocking cap of 33nF Fig. 2: Test circuit for FSK reception Circuit Features • Tolerates input frequency variations • Well-suited for NRZ, Manchester and similar codes 39010 71112 Rev. 015 Page 12 of 20 Data Sheet Jan/09 TH71112 868/915MHz FSK/ASK Receiver 4.1.2 Standard FSK Component List Part Size Value @ 868.3 MHz C1 0805 22 pF ±5% C3 0603 1 nF ±10% loop filter capacitor C4 0603 4.7 pF ±5% capacitor to match SAW filter input C5 0603 2.7 pF ±5% capacitor to match SAW filter output C7 0603 1.0 pF ±5% MIX1 input matching capacitor C8 0603 22 pF ±5% IF1 tank capacitor C9 0603 33 nF ±10% IFA feedback capacitor C10 0603 1 nF ±10% IFA feedback capacitor C11 0603 1 nF ±10% IFA feedback capacitor C12 0805 10 pF ±5% DEMOD phase-shift capacitor C15 0805 100 pF ±5% demodulator output low-pass capacitor, this value for data rates < 20 kbps NRZ C16 0805 1.5 nF ±10% RSSI output low-pass capacitor C17 0805 10 nF ±10% data slicer capacitor, this value for data rates > 0.8 kbps NRZ R1 0603 10 kΩ ±5% loop filter resistor R2 0603 330 Ω ±5% optional CERFIL output matching resistor R4 0805 330 kΩ ±5% data slicer resistor R5 0805 220 kΩ ±5% loading resistor L1 0603 22 nH ±5% L2 0603 22 nH ±5% SAW filter matching inductor from Würth-Elektronik (WE-KI series), or equivalent part L3 0603 10 nH ±5% LNA output tank inductor from Würth-Elektronik (WE-KI series), or equivalent part L4 0805 100 nH ±5% L5 0805 100 nH ±5% IF1 tank inductor from Würth-Elektronik (WE-KI series) or equivalent part XTAL SMD 6x3.5 25.22353 MHz @ RF = 868.3 MHz ±25ppm cal. ±30ppm temp. SAWFIL SMD 3x3 SAFCC868MSL0X00 (f0 =868.3 MHz) B3dB = 2 MHz CERFIL SMD 3.45x3.1 SFECF10M7HA00 B3dB = 180 kHz CERDIS SMD 4.5x2 CDSCB10M7GA135 Tolerance Description crystal series capacitor fundamental-mode crystal from Telcona/Horizon or equivalent par low-loss SAW filter from Murata, or equivalent part ceramic filter from Murata, or equivalent part ceramic discriminator from Murata, or equivalent part • For component values for other frequencies, please refer to the EVB descriptions 39010 71112 Rev. 015 Page 13 of 20 Data Sheet Jan/09 TH71112 868/915MHz FSK/ASK Receiver 4.2 4.2.1 Narrow Band FSK Reception Narrow Band FSK Application Circuit OUTP RSSI C16 C15 FSK output C17 R4 VCC VCC C3 OAN 19 OUT_OA 18 VCC 17 R2 C10 VEE GAIN_LNA OUT_LNA IN_MIX1 VEE IF1P IF1N VCC VEE 10 1 2 3 4 5 6 7 8 OUT_MIX2 9 CERFIL C8 C7 L1 L5 SAWFIL L4 4 3 C11 FBC1 12 IN_IFA 11 32 VCC CERDIS VCC C9 30 VEE VCC C12 FBC2 13 TH71112 29 LF 31 IN_LNA 6 OAP 20 VCC 14 28 ENRX R1 1 16 OUT_IFA 15 26 RO 27 VCC ENRX C5 RSSI 21 25 VEE C1 L2 VEE 22 24 XTAL OUTP 23 CP L3 C4 CB* VCC 50 RF input * each Vcc pin with blocking cap of 330pF * one global Vcc blocking cap of 33nF Fig. 3: Test circuit for FSK reception (narrow band) Circuit Features • Applicable for narrow band FSK 39010 71112 Rev. 015 Page 14 of 20 Data Sheet Jan/09 TH71112 868/915MHz FSK/ASK Receiver 4.2.2 Narrow Band FSK Component List Part Size Value @ 868.3 MHz C1 0805 22 pF ±5% C3 0603 1 nF ±10% loop filter capacitor C4 0603 4.7 pF ±5% capacitor to match SAW filter input C5 0603 2.7 pF ±5% capacitor to match SAW filter output C7 0603 1.0 pF ±5% MIX1 input matching capacitor C8 0603 22 pF ±5% IF1 tank capacitor C9 0603 33 nF ±10% IFA feedback capacitor C10 0603 1 nF ±10% IFA feedback capacitor C11 0603 1 nF ±10% IFA feedback capacitor C12 0805 1.5 pF ±5% DEMOD phase-shift capacitor C15 0805 220 pF ±5% demodulator output low-pass capacitor, this value for data rates < 10 kbps NRZ C16 0805 1.5 nF ±10% RSSI output low-pass capacitor C17 0805 10 nF ±10% data slicer capacitor, this value for data rates > 0.8 kbps NRZ CP 0603 6.8 - 8.2 pF ±5% ceramic resonator loading capacitor R1 0603 10 kΩ ±5% loop filter resistor R2 0603 330 Ω ±5% optional CERFIL output matching resistor R4 0805 330 kΩ ±5% data slicer resistor, this value for 0.4 to 10 kbps NRZ L1 0603 22 nH ±5% L2 0603 22 nH ±5% SAW filter matching inductor from Würth-Elektronik (WE-KI series), or equivalent part L3 0603 10 nH ±5% LNA output tank inductor from Würth-Elektronik (WE-KI series), or equivalent part L4 0805 100 nH ±5% L5 0805 100 nH ±5% IF1 tank inductor from Würth-Elektronik (WE-KI series) or equivalent part XTAL SMD 6x3.5 25.22353 MHz @ RF = 868.3 MHz ±25ppm cal. ±30ppm temp. SAWFIL SMD 3x3 SAFCC868MSL0X00 (f0 =868.3 MHz) B3dB = 2 MHz low-loss SAW filter from Murata, or equivalent part Leaded type SFKLA10M7NL00 B3dB = 30 kHz ceramic filter from Murata, or equivalent part SFVLA10M7LF00 B3dB = 80 kHz optional, ceramic filter from Murata, or equivalent part SMD 4.5x2 CDSCB10M7GA135 CERFIL CERDIS Tolerance Description crystal series capacitor fundamental-mode crystal from Telcona/Horizon or equivalent par ceramic discriminator from Murata, or equivalent part • For component values for other frequencies, please refer to the EVB descriptions 39010 71112 Rev. 015 Page 15 of 20 Data Sheet Jan/09 TH71112 868/915MHz FSK/ASK Receiver 4.3 4.3.1 ASK Reception ASK Application Circuit RSSI C16 ASK output C17 VCC VCC C3 OAN 19 OUT_OA 18 VCC 17 R2 C10 VEE GAIN_LNA OUT_LNA IN_MIX1 VEE IF1P IF1N VCC VEE 10 1 2 3 4 5 6 7 8 OUT_MIX2 9 CERFIL C8 C7 L1 C4 L5 SAWFIL L4 4 3 FBC1 12 IN_IFA 11 32 VCC C11 C9 30 VEE VCC VCC FBC2 13 TH71112 29 LF 31 IN_LNA 6 OAP 20 VCC 14 28 ENRX R1 1 16 OUT_IFA 15 26 RO 27 VCC ENRX C5 RSSI 21 25 VEE C1 L2 VEE 22 24 XTAL OUTP 23 R4 L3 CB* VCC 50 RF input * each Vcc pin with blocking cap of 330pF * one global Vcc blocking cap of 33nF Fig. 4: Test circuit for ASK reception 39010 71112 Rev. 015 Page 16 of 20 Data Sheet Jan/09 TH71112 868/915MHz FSK/ASK Receiver 4.3.2 ASK Component List Part Size Value @ 868.3 MHz C1 0805 22 pF ±5% C3 0603 1 nF ±10% loop filter capacitor C4 0603 4.7 pF ±5% capacitor to match SAW filter input C5 0603 2.7 pF ±5% capacitor to match SAW filter output C7 0603 1.0 pF ±5% MIX1 input matching capacitor C8 0603 22 pF ±5% IF1 tank capacitor C9 0603 33 nF ±10% IFA feedback capacitor C10 0603 1 nF ±10% IFA feedback capacitor C11 0603 1 nF ±10% IFA feedback capacitor C16 0805 1.5 nF ±10% RSSI output low-pass capacitor, this value for data rates < 10 kbps NRZ, for higher data rates decrease the value C17 0805 10 nF ±10% data slicer capacitor, this value for data rates > 0.8 kbps NRZ, for lower data rates increase the value Tolerance Description crystal series capacitor R1 0603 10 kΩ ±5% loop filter resistor R2 0603 330 Ω ±5% optional CERFIL output matching resistor R4 0805 330 kΩ ±5% data slicer resistor L1 0603 22 nH ±5% L2 0603 22 nH ±5% SAW filter matching inductor from Würth-Elektronik (WE-KI series), or equivalent part L3 0603 10 nH ±5% LNA output tank inductor from Würth-Elektronik (WE-KI series), or equivalent part L4 0805 100 nH ±5% L5 0805 100 nH ±5% IF1 tank inductor from Würth-Elektronik (WE-KI series) or equivalent part XTAL SMD 6x3.5 25.22353 MHz @ RF = 868.3 MHz ±25ppm cal. ±30ppm temp. SAWFIL SMD 3x3 SAFCC868MSL0X00 (f0 =868.3 MHz) B3dB = 2 MHz SMD 3.45x3.1 SFECF10M7HA00 B3dB = 180 kHz ceramic filter from Murata, or equivalent part Leaded type SFVLA10M7LF00 B3dB = 80 kHz optional, ceramic filter from Murata, or equivalent part CERFIL fundamental-mode crystal from Telcona/Horizon or equivalent par low-loss SAW filter from Murata, or equivalent part • For component values for other frequencies, please refer to the EVB descriptions 39010 71112 Rev. 015 Page 17 of 20 Data Sheet Jan/09 TH71112 868/915MHz FSK/ASK Receiver 5 Package Description The device TH71112 is RoHS compliant. D D1 A 24 17 16 25 b E e E1 32 9 1 8 A2 A1 12° +1° 0.25 (0.0098) c 12° +1° L .10 (.004) Fig. 6: LQFP32 (Low profile Quad Flat Package) All Dimension in mm, coplanaríty < 0.1mm min max E1, D1 E, D A A1 A2 e b c L α 7.00 9.00 1.40 1.60 0.05 0.15 1.35 1.45 0.8 0.30 0.45 0.09 0.20 0.45 0.75 0° 7° 0.053 0.057 0.031 0.012 0.018 0.0035 0.0079 0.018 0.030 0° 7° All Dimension in inch, coplanaríty < 0.004” min max 5.1 0.276 0.354 0.055 0.063 0.002 0.006 Soldering Information • 39010 71112 Rev. 015 The device TH71112 is qualified for MSL3 with soldering peak temperature 260 deg C according to JEDEC J-STD-20 Page 18 of 20 Data Sheet Jan/09 TH71112 868/915MHz FSK/ASK Receiver 6 Reliability Information This Melexis device is classified and qualified regarding soldering technology, solderability and moisture sensitivity level, as defined in this specification, according to following test methods: Reflow Soldering SMD’s (Surface Mount Devices) • IPC/JEDEC J-STD-020 “Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices (classification reflow profiles according to table 5-2)” Wave Soldering SMD’s (Surface Mount Devices) • EN60749-20 “Resistance of plastic- encapsulated SMD’s to combined effect of moisture and soldering heat” Solderability SMD’s (Surface Mount Devices) • EIA/JEDEC JESD22-B102 “Solderability” For all soldering technologies deviating from above mentioned standard conditions (regarding peak temperature, temperature gradient, temperature profile etc) additional classification and qualification tests have to be agreed upon with Melexis. The application of Wave Soldering for SMD’s is allowed only after consulting Melexis regarding assurance of adhesive strength between device and board. 7 ESD Precautions Electronic semiconductor products are sensitive to Electro Static Discharge (ESD). Always observe Electro Static Discharge control procedures whenever handling semiconductor products. 39010 71112 Rev. 015 Page 19 of 20 Data Sheet Jan/09 TH71112 868/915MHz FSK/ASK Receiver 8 Disclaimer 1) The information included in this documentation is subject to Melexis intellectual and other property rights. Reproduction of information is permissible only if the information will not be altered and is accompanied by all associated conditions, limitations and notices. 2) Any use of the documentation without the prior written consent of Melexis other than the one set forth in clause 1 is an unfair and deceptive business practice. Melexis is not responsible or liable for such altered documentation. 3) The information furnished by Melexis in this documentation is provided ’as is’. Except as expressly warranted in any other applicable license agreement, Melexis disclaims all warranties either express, implied, statutory or otherwise including but not limited to the merchantability, fitness for a particular purpose, title and non-infringement with regard to the content of this documentation. 4) Notwithstanding the fact that Melexis endeavors to take care of the concept and content of this documentation, it may include technical or factual inaccuracies or typographical errors. Melexis disclaims any responsibility in connection herewith. 5) Melexis reserves the right to change the documentation, the specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with Melexis for current information. 6) Melexis shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interrupt of business or indirect, special incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the information in this documentation. 7) The product described in this documentation is intended for use in normal commercial applications. Applications requiring operation beyond ranges specified in this documentation, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by Melexis for each application. 8) Any supply of products by Melexis will be governed by the Melexis Terms of Sale, published on www.melexis.com. © Melexis NV. All rights reserved. For the latest version of this document, go to our website at: www.melexis.com Or for additional information contact Melexis Direct: Europe, Africa: Americas: Asia: Phone: +32 1367 0495 E-mail: [email protected] Phone: +1 603 223 2362 E-mail: [email protected] Phone: +32 1367 0495 E-mail: [email protected] ISO/TS 16949 and ISO14001 Certified 39010 71112 Rev. 015 Page 20 of 20 Data Sheet Jan/09