C8051F30x Mixed-Signal ISP Flash MCU Family

C8051F300/1/2/3/4/5
Mixed Signal ISP Flash MCU Family
Analog Peripherals
- 8-Bit ADC ('F300/2 only)
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•
•
•
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High Speed 8051 µc Core
- Pipelined instruction architecture; executes 70% of
Up to 500 ksps
Up to 8 external inputs
Programmable amplifier gains of 4, 2, 1, & 0.5
VREF from external pin or VDD
Built-in temperature sensor
External conversion start input
instructions in 1 or 2 system clocks
- Up to 25 MIPS throughput with 25 MHz clock
- Expanded interrupt handler
Memory
- 256 bytes internal data RAM
- Up to 8 kB (‘F300/1/2/3), 4 kB (‘F304), or 2 kB
Comparator
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Programmable hysteresis and response time
Configurable as interrupt or reset source
Low current (<0.5 µA)
(‘F305) Flash; 512 bytes are reserved in the 8 kB
devices
On-chip Debug
- On-chip debug circuitry facilitates full speed,
-
non-intrusive in-system debug (no emulator
required)
Provides breakpoints, single stepping,
inspect/modify memory and registers
Superior performance to emulation systems using
ICE-chips, target pods, and sockets
Complete development kit
Supply Voltage 2.7 to 3.6 V
- Typical operating current: 6.6 mA @ 25 MHz;
-
Digital Peripherals
- 8 Port I/O; All 5 V tolerant with high sink current
- Hardware enhanced UART and SMBus™ serial
-
ports
Three general-purpose 16-bit counter/timers
16-bit programmable counter array (PCA) with three
capture/compare modules
Real time clock mode using PCA or timer and
external clock source
Clock Sources
- Internal oscillator: 24.5 MHz with ±2% accuracy
14 µA @ 32 kHz
Typical stop mode current: 0.1 µA
Temperature range: –40 to +85 °C
-
supports UART operation
External oscillator: Crystal, RC, C, or clock (1 or 2
pin modes)
Can switch between clock sources on-the-fly; Useful
in power saving modes
11-Pin QFN or 14-Pin SOIC Package
- QFN Size = 3x3 mm
PGA
8-bit
500 ksps
ADC
C8051F300/2 only
+
TEMP
SENSOR
-
VOLTAGE COMPARATOR
UART
SMBus
PCA
Timer 0
Timer 1
I/O Port
A
M
U
X
DIGITAL I/O
CROSSBAR
ANALOG
PERIPHERALS
Timer 2
PROGRAMMABLE PRECISION INTERNAL
OSCILLATOR
HIGH-SPEED CONTROLLER CORE
8/4/2 kBytes
ISP Flash
12
INTERRUPTS
Rev. 2.9 7/08
8051 CPU
(25MIPS)
DEBUG
CIRCUITRY
256 B SRAM
POR
Copyright © 2008 by Silicon Laboratories
WDT
C8051F300/1/2/3/4/5
C8051F300/1/2/3/4/5
NOTES:
2
Rev. 2.9
C8051F300/1/2/3/4/5
Table of Contents
1. System Overview.................................................................................................... 13
1.1. CIP-51™ Microcontroller Core.......................................................................... 16
1.1.1. Fully 8051 Compatible.............................................................................. 16
1.1.2. Improved Throughput ............................................................................... 16
1.1.3. Additional Features .................................................................................. 17
1.2. On-Chip Memory............................................................................................... 18
1.3. On-Chip Debug Circuitry................................................................................... 19
1.4. Programmable Digital I/O and Crossbar ........................................................... 19
1.5. Serial Ports ....................................................................................................... 20
1.6. Programmable Counter Array ........................................................................... 21
1.7. 8-Bit Analog to Digital Converter (C8051F300/2 Only) ..................................... 22
1.8. Comparator ....................................................................................................... 23
2. Absolute Maximum Ratings .................................................................................. 24
3. Global Electrical Characteristics .......................................................................... 25
4. Pinout and Package Definitions............................................................................ 27
5. ADC0 (8-Bit ADC, C8051F300/2)............................................................................ 35
5.1. Analog Multiplexer and PGA............................................................................. 36
5.2. Temperature Sensor ......................................................................................... 36
5.3. Modes of Operation .......................................................................................... 39
5.3.1. Starting a Conversion............................................................................... 39
5.3.2. Tracking Modes........................................................................................ 40
5.3.3. Settling Time Requirements ..................................................................... 41
5.4. Programmable Window Detector ...................................................................... 45
5.4.1. Window Detector In Single-Ended Mode ................................................. 45
5.4.2. Window Detector In Differential Mode...................................................... 46
6. Voltage Reference (C8051F300/2) ......................................................................... 49
7. Comparator0 ........................................................................................................... 51
8. CIP-51 Microcontroller ........................................................................................... 57
8.1. Instruction Set ................................................................................................... 58
8.1.1. Instruction and CPU Timing ..................................................................... 58
8.1.2. MOVX Instruction and Program Memory ................................................. 59
8.2. Memory Organization........................................................................................ 63
8.2.1. Program Memory...................................................................................... 63
8.2.2. Data Memory............................................................................................ 64
8.2.3. General Purpose Registers ...................................................................... 64
8.2.4. Bit Addressable Locations........................................................................ 65
8.2.5. Stack ....................................................................................................... 65
8.2.6. Special Function Registers....................................................................... 65
8.2.7. Register Descriptions ............................................................................... 68
8.3. Interrupt Handler ............................................................................................... 72
8.3.1. MCU Interrupt Sources and Vectors ........................................................ 72
8.3.2. External Interrupts .................................................................................... 73
8.3.3. Interrupt Priorities ..................................................................................... 73
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C8051F300/1/2/3/4/5
8.3.4. Interrupt Latency ...................................................................................... 73
8.3.5. Interrupt Register Descriptions................................................................. 75
8.4. Power Management Modes .............................................................................. 80
8.4.1. Idle Mode.................................................................................................. 80
8.4.2. Stop Mode ................................................................................................ 81
9. Reset Sources......................................................................................................... 83
9.1. Power-On Reset ............................................................................................... 84
9.2. Power-Fail Reset/VDD Monitor......................................................................... 84
9.3. External Reset .................................................................................................. 85
9.4. Missing Clock Detector Reset........................................................................... 85
9.5. Comparator0 Reset........................................................................................... 85
9.6. PCA Watchdog Timer Reset............................................................................. 85
9.7. Flash Error Reset.............................................................................................. 86
9.8. Software Reset ................................................................................................. 86
10. Flash Memory ......................................................................................................... 89
10.1.Programming The Flash Memory ..................................................................... 89
10.1.1.Flash Lock and Key Functions ................................................................. 89
10.1.2.Flash Erase Procedure ............................................................................ 89
10.1.3.Flash Write Procedure ............................................................................. 90
10.2.Non-Volatile Data Storage................................................................................ 90
10.3.Security Options ............................................................................................... 90
10.4.Flash Write and Erase Guidelines .................................................................... 94
10.4.1.VDD Maintenance and the VDD monitor ................................................... 94
10.4.2.PSWE Maintenance ................................................................................. 94
10.4.3.System Clock ........................................................................................... 95
11. Oscillators ............................................................................................................... 97
11.1.Programmable Internal Oscillator ..................................................................... 97
11.2.External Oscillator Drive Circuit........................................................................ 99
11.3.System Clock Selection.................................................................................... 99
11.4.External Crystal Example ............................................................................... 101
11.5.External RC Example ..................................................................................... 102
11.6.External Capacitor Example ........................................................................... 102
12. Port Input/Output.................................................................................................. 103
12.1.Priority Crossbar Decoder .............................................................................. 104
12.2.Port I/O Initialization ....................................................................................... 106
12.3.General Purpose Port I/O ............................................................................... 108
13. SMBus ................................................................................................................... 111
13.1.Supporting Documents ................................................................................... 112
13.2.SMBus Configuration...................................................................................... 112
13.3.SMBus Operation ........................................................................................... 112
13.3.1.Arbitration............................................................................................... 113
13.3.2.Clock Low Extension.............................................................................. 114
13.3.3.SCL Low Timeout................................................................................... 114
13.3.4.SCL High (SMBus Free) Timeout .......................................................... 114
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13.4.Using the SMBus............................................................................................ 115
13.4.1.SMBus Configuration Register............................................................... 116
13.4.2.SMB0CN Control Register ..................................................................... 119
13.4.3.Data Register ......................................................................................... 122
13.5.SMBus Transfer Modes.................................................................................. 123
13.5.1.Master Transmitter Mode ....................................................................... 123
13.5.2.Master Receiver Mode ........................................................................... 124
13.5.3.Slave Receiver Mode ............................................................................. 125
13.5.4.Slave Transmitter Mode ......................................................................... 126
13.6.SMBus Status Decoding................................................................................. 127
14. UART0.................................................................................................................... 131
14.1.Enhanced Baud Rate Generation................................................................... 132
14.2.Operational Modes ......................................................................................... 133
14.2.1.8-Bit UART ............................................................................................. 133
14.2.2.9-Bit UART ............................................................................................. 134
14.3.Multiprocessor Communications .................................................................... 135
15. Timers.................................................................................................................... 143
15.1.Timer 0 and Timer 1 ....................................................................................... 143
15.1.1.Mode 0: 13-bit Counter/Timer ................................................................ 143
15.1.2.Mode 1: 16-bit Counter/Timer ................................................................ 145
15.1.3.Mode 2: 8-bit Counter/Timer with Auto-Reload...................................... 145
15.1.4.Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)................................. 146
15.2.Timer 2 .......................................................................................................... 151
15.2.1.16-bit Timer with Auto-Reload................................................................ 151
15.2.2.8-bit Timers with Auto-Reload................................................................ 152
16. Programmable Counter Array ............................................................................. 155
16.1.PCA Counter/Timer ........................................................................................ 156
16.2.Capture/Compare Modules ............................................................................ 157
16.2.1.Edge-triggered Capture Mode................................................................ 158
16.2.2.Software Timer (Compare) Mode........................................................... 159
16.2.3.High Speed Output Mode....................................................................... 160
16.2.4.Frequency Output Mode ........................................................................ 161
16.2.5.8-Bit Pulse Width Modulator Mode......................................................... 162
16.2.6.16-Bit Pulse Width Modulator Mode....................................................... 163
16.3.Watchdog Timer Mode ................................................................................... 164
16.3.1.Watchdog Timer Operation .................................................................... 164
16.3.2.Watchdog Timer Usage ......................................................................... 165
16.4.Register Descriptions for PCA........................................................................ 167
17. C2 Interface ........................................................................................................... 173
17.1.C2 Interface Registers.................................................................................... 173
17.2.C2 Pin Sharing ............................................................................................... 175
Document Change List............................................................................................. 176
Contact Information.................................................................................................. 178
Rev. 2.9
5
C8051F300/1/2/3/4/5
NOTES:
6
Rev. 2.9
C8051F300/1/2/3/4/5
List of Figures
1. System Overview
Figure 1.1. C8051F300/2 Block Diagram ................................................................. 15
Figure 1.2. C8051F301/3/4/5 Block Diagram ........................................................... 15
Figure 1.3. Comparison of Peak MCU Execution Speeds ....................................... 16
Figure 1.4. On-Chip Clock and Reset ...................................................................... 17
Figure 1.5. On-chip Memory Map (C8051F300/1/2/3 Shown) ................................. 18
Figure 1.6. Development/In-System Debug Diagram............................................... 19
Figure 1.7. Digital Crossbar Diagram ....................................................................... 20
Figure 1.8. PCA Block Diagram ............................................................................... 21
Figure 1.9. PCA Block Diagram ............................................................................... 21
Figure 1.10. 8-Bit ADC Block Diagram ..................................................................... 22
Figure 1.11. Comparator Block Diagram .................................................................. 23
2. Absolute Maximum Ratings
3. Global Electrical Characteristics
4. Pinout and Package Definitions
Figure 4.1. QFN-11 Pinout Diagram (Top View) ...................................................... 28
Figure 4.2. QFN-11 Package Drawing ..................................................................... 29
Figure 4.3. Typical QFN-11 Solder Paste Mask....................................................... 30
Figure 4.4. Typical QFN-11 Landing Diagram.......................................................... 31
Figure 4.5. SOIC-14 Pinout Diagram (Top View) ..................................................... 32
Figure 4.6. SOIC-14 Package Drawing .................................................................... 33
Figure 4.7. SOIC-14 PCB Land Pattern ................................................................... 34
5. ADC0 (8-Bit ADC, C8051F300/2)
Figure 5.1. ADC0 Functional Block Diagram............................................................ 35
Figure 5.2. Typical Temperature Sensor Transfer Function..................................... 37
Figure 5.3. Temperature Sensor Error with 1-Point Calibration (VREF = 2.40 V).... 38
Figure 5.4. 8-Bit ADC Track and Conversion Example Timing ................................ 40
Figure 5.5. ADC0 Equivalent Input Circuits.............................................................. 41
Figure 5.6. ADC Window Compare Examples, Single-Ended Mode........................ 45
Figure 5.7. ADC Window Compare Examples, Differential Mode ............................ 46
6. Voltage Reference (C8051F300/2)
Figure 6.1. Voltage Reference Functional Block Diagram ....................................... 49
7. Comparator0
Figure 7.1. Comparator0 Functional Block Diagram ................................................ 51
Figure 7.2. Comparator Hysteresis Plot ................................................................... 52
8. CIP-51 Microcontroller
Figure 8.1. CIP-51 Block Diagram............................................................................ 57
Figure 8.2. Program Memory Maps.......................................................................... 63
Figure 8.3. Data Memory Map.................................................................................. 64
9. Reset Sources
Figure 9.1. Reset Sources........................................................................................ 83
Figure 9.2. Power-On and VDD Monitor Reset Timing ............................................ 84
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7
C8051F300/1/2/3/4/5
10. Flash Memory
Figure 10.1. Flash Program Memory Map................................................................ 91
11. Oscillators
Figure 11.1. Oscillator Diagram................................................................................ 97
Figure 11.2. 32.768 kHz External Crystal Example................................................ 101
12. Port Input/Output
Figure 12.1. Port I/O Functional Block Diagram ..................................................... 103
Figure 12.2. Port I/O Cell Block Diagram ............................................................... 103
Figure 12.3. Crossbar Priority Decoder with XBR0 = 0x00 .................................... 104
Figure 12.4. Crossbar Priority Decoder with XBR0 = 0x44 .................................... 105
13. SMBus
Figure 13.1. SMBus Block Diagram ....................................................................... 111
Figure 13.2. Typical SMBus Configuration ............................................................. 112
Figure 13.3. SMBus Transaction ............................................................................ 113
Figure 13.4. Typical SMBus SCL Generation......................................................... 117
Figure 13.5. Typical Master Transmitter Sequence................................................ 123
Figure 13.6. Typical Master Receiver Sequence.................................................... 124
Figure 13.7. Typical Slave Receiver Sequence...................................................... 125
Figure 13.8. Typical Slave Transmitter Sequence.................................................. 126
14. UART0
Figure 14.1. UART0 Block Diagram ....................................................................... 131
Figure 14.2. UART0 Baud Rate Logic .................................................................... 132
Figure 14.3. UART Interconnect Diagram .............................................................. 133
Figure 14.4. 8-Bit UART Timing Diagram............................................................... 133
Figure 14.5. 9-Bit UART Timing Diagram............................................................... 134
Figure 14.6. UART Multi-Processor Mode Interconnect Diagram .......................... 135
15. Timers
Figure 15.1. T0 Mode 0 Block Diagram.................................................................. 144
Figure 15.2. T0 Mode 2 Block Diagram.................................................................. 145
Figure 15.3. T0 Mode 3 Block Diagram.................................................................. 146
Figure 15.4. Timer 2 16-Bit Mode Block Diagram .................................................. 151
Figure 15.5. Timer 2 8-Bit Mode Block Diagram .................................................... 152
16. Programmable Counter Array
Figure 16.1. PCA Block Diagram............................................................................ 155
Figure 16.2. PCA Counter/Timer Block Diagram.................................................... 156
Figure 16.3. PCA Interrupt Block Diagram ............................................................. 157
Figure 16.4. PCA Capture Mode Diagram.............................................................. 158
Figure 16.5. PCA Software Timer Mode Diagram .................................................. 159
Figure 16.6. PCA High Speed Output Mode Diagram............................................ 160
Figure 16.7. PCA Frequency Output Mode ............................................................ 161
Figure 16.8. PCA 8-Bit PWM Mode Diagram ......................................................... 162
Figure 16.9. PCA 16-Bit PWM Mode...................................................................... 163
Figure 16.10. PCA Module 2 with Watchdog Timer Enabled ................................. 164
17. C2 Interface
Figure 17.1. Typical C2 Pin Sharing....................................................................... 175
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Rev. 2.9
C8051F300/1/2/3/4/5
List of Tables
1. System Overview
Table 1.1. Product Selection Guide ......................................................................... 14
2. Absolute Maximum Ratings
Table 2.1. Absolute Maximum Ratings .................................................................... 24
3. Global Electrical Characteristics
Table 3.1. Global Electrical Characteristics ............................................................. 25
4. Pinout and Package Definitions
Table 4.1. Pin Definitions for the C8051F300/1/2/3/4/5 ........................................... 27
Table 4.2. QFN-11 Package Dimensions ................................................................ 29
Table 4.3. QFN-11 Landing Diagram Dimensions ................................................... 31
Table 4.4. SOIC-14 Package Dimensions ............................................................... 33
Table 4.5. SOIC-14 PCB Land Pattern Dimensions ................................................ 34
5. ADC0 (8-Bit ADC, C8051F300/2)
Table 5.1. ADC0 Electrical Characteristics .............................................................. 47
6. Voltage Reference (C8051F300/2)
Table 6.1. External Voltage Reference Circuit Electrical Characteristics ................ 50
7. Comparator0
Table 7.1. Comparator0 Electrical Characteristics .................................................. 55
8. CIP-51 Microcontroller
Table 8.1. CIP-51 Instruction Set Summary ............................................................ 59
Table 8.2. Special Function Register (SFR) Memory Map ...................................... 66
Table 8.3. Special Function Registers ..................................................................... 66
Table 8.4. Interrupt Summary .................................................................................. 74
9. Reset Sources
Table 9.1. User Code Space Address Limits ........................................................... 86
Table 9.2. Reset Electrical Characteristics .............................................................. 86
10. Flash Memory
Table 10.1. Flash Electrical Characteristics ............................................................ 90
Table 10.2. Security Byte Decoding ........................................................................ 91
11. Oscillators
Table 11.1. Internal Oscillator Electrical Characteristics ......................................... 99
12. Port Input/Output
Table 12.1. Port I/O DC Electrical Characteristics ................................................. 110
13. SMBus
Table 13.1. SMBus Clock Source Selection .......................................................... 116
Table 13.2. Minimum SDA Setup and Hold Times ................................................ 117
Table 13.3. Sources for Hardware Changes to SMB0CN ..................................... 121
Table 13.4. SMBus Status Decoding ..................................................................... 127
14. UART0
Table 14.1. Timer Settings for Standard Baud Rates
Using The Internal 24.5 MHz Oscillator .............................................. 138
Table 14.2. Timer Settings for Standard Baud Rates
Using an External 25 MHz Oscillator .................................................. 138
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9
C8051F300/1/2/3/4/5
Table 14.3. Timer Settings for Standard Baud Rates
Using an External 22.1184 MHz Oscillator ......................................... 139
Table 14.4. Timer Settings for Standard Baud Rates
Using an External 18.432 MHz Oscillator ........................................... 140
Table 14.5. Timer Settings for Standard Baud Rates
Using an External 11.0592 MHz Oscillator ......................................... 141
Table 14.6. Timer Settings for Standard Baud Rates
Using an External 3.6864 MHZ Oscillator .......................................... 142
15. Timers
16. Programmable Counter Array
Table 16.1. PCA Timebase Input Options ............................................................. 156
Table 16.2. PCA0CPM Register Settings for PCA Capture/Compare Modules .... 157
Table 16.3. Watchdog Timer Timeout Intervals ..................................................... 166
17. C2 Interface
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List of Registers
SFR Definition 5.1. AMX0SL: AMUX0 Channel Select (C8051F300/2) . . . . . . . . . . . . 42
SFR Definition 5.2. ADC0CF: ADC0 Configuration (C8051F300/2) . . . . . . . . . . . . . . . 43
SFR Definition 5.3. ADC0: ADC0 Data Word (C8051F300/2) . . . . . . . . . . . . . . . . . . . 43
SFR Definition 5.4. ADC0CN: ADC0 Control (C8051F300/2) . . . . . . . . . . . . . . . . . . . . 44
SFR Definition 5.5. ADC0GT: ADC0 Greater-Than Data Byte (C8051F300/2) . . . . . . 46
SFR Definition 5.6. ADC0LT: ADC0 Less-Than Data Byte (C8051F300/2) . . . . . . . . . 46
SFR Definition 6.1. REF0CN: Reference Control Register . . . . . . . . . . . . . . . . . . . . . . 50
SFR Definition 7.1. CPT0CN: Comparator0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
SFR Definition 7.2. CPT0MX: Comparator0 MUX Selection . . . . . . . . . . . . . . . . . . . . 54
SFR Definition 7.3. CPT0MD: Comparator0 Mode Selection . . . . . . . . . . . . . . . . . . . . 54
SFR Definition 8.1. DPL: Data Pointer Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
SFR Definition 8.2. DPH: Data Pointer High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
SFR Definition 8.3. SP: Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
SFR Definition 8.4. PSW: Program Status Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
SFR Definition 8.5. ACC: Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
SFR Definition 8.6. B: B Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
SFR Definition 8.7. IE: Interrupt Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
SFR Definition 8.8. IP: Interrupt Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
SFR Definition 8.9. EIE1: Extended Interrupt Enable 1 . . . . . . . . . . . . . . . . . . . . . . . . 77
SFR Definition 8.10. EIP1: Extended Interrupt Priority 1 . . . . . . . . . . . . . . . . . . . . . . . 78
SFR Definition 8.11. IT01CF: INT0/INT1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . 79
SFR Definition 8.12. PCON: Power Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
SFR Definition 9.1. RSTSRC: Reset Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
SFR Definition 10.1. PSCTL: Program Store R/W Control . . . . . . . . . . . . . . . . . . . . . . 92
SFR Definition 10.2. FLKEY: Flash Lock and Key . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
SFR Definition 10.3. FLSCL: Flash Scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
SFR Definition 11.1. OSCICL: Internal Oscillator Calibration . . . . . . . . . . . . . . . . . . . . 98
SFR Definition 11.2. OSCICN: Internal Oscillator Control . . . . . . . . . . . . . . . . . . . . . . 98
SFR Definition 11.3. OSCXCN: External Oscillator Control . . . . . . . . . . . . . . . . . . . . 100
SFR Definition 12.1. XBR0: Port I/O Crossbar Register 0 . . . . . . . . . . . . . . . . . . . . . 107
SFR Definition 12.2. XBR1: Port I/O Crossbar Register 1 . . . . . . . . . . . . . . . . . . . . . 107
SFR Definition 12.3. XBR2: Port I/O Crossbar Register 2 . . . . . . . . . . . . . . . . . . . . . 108
SFR Definition 12.4. P0: Port0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
SFR Definition 12.5. P0MDIN: Port0 Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
SFR Definition 12.6. P0MDOUT: Port0 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . 110
SFR Definition 13.1. SMB0CF: SMBus Clock/Configuration . . . . . . . . . . . . . . . . . . . 118
SFR Definition 13.2. SMB0CN: SMBus Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
SFR Definition 13.3. SMB0DAT: SMBus Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
SFR Definition 14.1. SCON0: Serial Port 0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . 136
SFR Definition 14.2. SBUF0: Serial (UART0) Port Data Buffer . . . . . . . . . . . . . . . . . 137
SFR Definition 15.1. TCON: Timer Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
SFR Definition 15.2. TMOD: Timer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
SFR Definition 15.3. CKCON: Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
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C8051F300/1/2/3/4/5
SFR Definition 15.4. TL0: Timer 0 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
SFR Definition 15.5. TL1: Timer 1 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
SFR Definition 15.6. TH0: Timer 0 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
SFR Definition 15.7. TH1: Timer 1 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
SFR Definition 15.8. TMR2CN: Timer 2 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
SFR Definition 15.9. TMR2RLL: Timer 2 Reload Register Low Byte . . . . . . . . . . . . . 154
SFR Definition 15.10. TMR2RLH: Timer 2 Reload Register High Byte . . . . . . . . . . . 154
SFR Definition 15.11. TMR2L: Timer 2 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
SFR Definition 15.12. TMR2H Timer 2 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
SFR Definition 16.1. PCA0CN: PCA Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
SFR Definition 16.2. PCA0MD: PCA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
SFR Definition 16.3. PCA0CPMn: PCA Capture/Compare Mode . . . . . . . . . . . . . . . 169
SFR Definition 16.4. PCA0L: PCA Counter/Timer Low Byte . . . . . . . . . . . . . . . . . . . 170
SFR Definition 16.5. PCA0H: PCA Counter/Timer High Byte . . . . . . . . . . . . . . . . . . 170
SFR Definition 16.6. PCA0CPLn: PCA Capture Module Low Byte . . . . . . . . . . . . . . . 171
SFR Definition 16.7. PCA0CPHn: PCA Capture Module High Byte . . . . . . . . . . . . . . 171
C2 Register Definition 17.1. C2ADD: C2 Address . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
C2 Register Definition 17.2. DEVICEID: C2 Device ID . . . . . . . . . . . . . . . . . . . . . . . . 173
C2 Register Definition 17.3. REVID: C2 Revision ID . . . . . . . . . . . . . . . . . . . . . . . . . 174
C2 Register Definition 17.4. FPCTL: C2 Flash Programming Control . . . . . . . . . . . . 174
C2 Register Definition 17.5. FPDAT: C2 Flash Programming Data . . . . . . . . . . . . . . 174
12
Rev. 2.9
C8051F300/1/2/3/4/5
1.
System Overview
C8051F300/1/2/3/4/5 devices are fully integrated mixed-signal system-on-a-chip MCUs. Highlighted features are listed below. Refer to Table 1.1 on page 14 for specific product feature selection.
•
•
•
•
•
•
•
•
•
•
•
•
High-speed pipelined 8051-compatible microcontroller core (up to 25 MIPS)
In-system, full-speed, non-intrusive debug interface (on-chip)
True 8-bit 500 ksps 11-channel ADC with programmable gain pre-amplifier and analog multiplexer
(C8051F300/2 only)
Precision programmable 25 MHz internal oscillator
Up to 8 kB of on-chip Flash memory
256 bytes of on-chip RAM
SMBus/I2C and Enhanced UART serial interfaces implemented in hardware
Three general-purpose 16-bit timers
Programmable counter/timer array (PCA) with three capture/compare modules and watchdog timer
function
On-chip power-on reset, VDD monitor, and temperature sensor
On-chip voltage comparator
Byte-wide I/O port (5 V tolerant)
With on-chip Power-On Reset, VDD monitor, Watchdog Timer, and clock oscillator, the
C8051F300/1/2/3/4/5 devices are truly stand-alone System-on-a-Chip solutions. The Flash memory can
be reprogrammed even in-circuit, providing non-volatile data storage, and also allowing field upgrades of
the 8051 firmware. User software has complete control of all peripherals, and may individually shut down
any or all peripherals for power savings.
The on-chip Silicon Laboratories 2-Wire (C2) Development Interface allows non-intrusive (uses no on-chip
resources), full speed, in-circuit debugging using the production MCU installed in the final application. This
debug logic supports inspection and modification of memory and registers, setting breakpoints, single
stepping, run and halt commands. All analog and digital peripherals are fully functional while debugging
using C2. The two C2 interface pins can be shared with user functions, allowing in-system debugging without occupying package pins.
Each device is specified for 2.7 to 3.6 V operation over the industrial temperature range (–45 to +85 °C).
The Port I/O and RST pins are tolerant of input signals up to 5 V. The C8051F300/1/2/3/4/5 are available in
3 x 3 mm 11-pin QFN or 14-pin SOIC packaging.
Rev. 2.9
13
C8051F300/1/2/3/4/5
Ordering Part Number
MIPS (Peak)
Flash Memory
RAM
Calibrated Internal Oscillator
SMBus/I2C
UART
Timers (16-bit)
Programmable Counter Array
Digital Port I/Os
8-bit 500ksps ADC
Temperature Sensor
Analog Comparators
Lead-free (RoHS compliant)
Package
Table 1.1. Product Selection Guide
C8051F300-GM
25
8k
256



3

8


1

QFN-11
C8051F300-GS
25
8k
256



3

8


1

SOIC-14
C8051F301-GM
25
8k
256



3

8
—
—
1

QFN-11
C8051F301-GS
25
8k
256



3

8
—
—
1

SOIC-14
C8051F302-GM
25
8k
256
—


3

8


1

QFN-11
C8051F302-GS
25
8k
256
—


3

8


1

SOIC-14
C8051F303-GM
25
8k
256
—


3

8
—
—
1

QFN-11
C8051F303-GS
25
8k
256
—


3

8
—
—
1

SOIC-14
C8051F304-GM
25
4k
256
—


3

8
—
—
1

QFN-11
C8051F304-GS
25
4k
256
—


3

8
—
—
1

SOIC-14
C8051F305-GM
25
2k
256
—


3

8
—
—
1

QFN-11
C8051F305-GS
25
2k
256
—


3

8
—
—
1

SOIC-14
14
Rev. 2.9
C8051F300/1/2/3/4/5
Analog/Digital
Power
VDD
Port I/O Mode
& Config.
GND
C2D
Debug HW
Reset
/RST/C2CK
BrownOut
POR
External
Oscillator
Circuit
XTAL1
XTAL2
System Clock
Precision
Internal
Oscillator
8
0
5
1
Port 0
Latch
8kbyte
FLASH
P0.0/VREF
PCA/
WDT
C
o SFR Bus
r
e
P
0
X
B
A
R
Timer 0, 1
256 byte
SRAM
x4
P0.3/XTAL2
D
r
v
P0.4/TX
P0.5/RX
P0.6/CNVSTR
x2
SMBus
CP0
P0.7/C2D
XBAR
Control
C2D
CP0
Clock & Reset
Configuration
P0.1
P0.2/XTAL1
x2
UART
ADC
Config. &
Control
VDD
+
-
VREF
Temp
8-bit
500ksps
ADC
PGA
CNVSTR
A
M
U
X
AIN0-AIN7
VDD
Figure 1.1. C8051F300/2 Block Diagram
VDD
Analog/Digital
Power
Port I/O Mode
& Config.
GND
C2D
Debug HW
Reset
/RST/C2CK
POR
XTAL1
XTAL2
External
Oscillator
Circuit
Precision
Internal
Oscillator
BrownOut
System Clock
8
0
5
1
Port 0
Latch
8k/4k/2k
byte
FLASH
UART
Timer 0, 1
256 byte
SRAM
PCA/
WDT
C
o SFR Bus
r
e
SMBus
P0.0/VREF
P0.1
x2
x4
P
0
X
B
A
R
D
r
v
x2
CP0
XBAR
Control
P0.2/XTAL1
P0.3/XTAL2
P0.4/TX
P0.5/RX
P0.6
P0.7/C2D
C2D
CP0
+
-
Clock & Reset
Configuration
Figure 1.2. C8051F301/3/4/5 Block Diagram
Rev. 2.9
15
C8051F300/1/2/3/4/5
1.1.
CIP-51™ Microcontroller Core
1.1.1. Fully 8051 Compatible
The C8051F300/1/2/3/4/5 family utilizes Silicon Labs' proprietary CIP-51 microcontroller core. The CIP-51
is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can
be used to develop software. The CIP-51 core offers all the peripherals included with a standard 8052,
including two standard 16-bit counter/timers, one enhanced 16-bit counter/timer with external oscillator
input, a full-duplex UART with extended baud rate configuration, 256 bytes of internal RAM, 128 byte Special Function Register (SFR) address space, and a byte-wide I/O Port.
1.1.2. Improved Throughput
The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system
clock cycles to execute with a maximum system clock of 12 to 24 MHz. By contrast, the CIP-51 core executes 70% of its instructions in one or two system clock cycles, with only four instructions taking more than
four system clock cycles.
The CIP-51 has a total of 109 instructions. The table below shows the total number of instructions that
require each execution time.
Clocks to Execute
1
2
2/3
3
3/4
4
4/5
5
8
Number of Instructions
26
50
5
14
7
3
1
2
1
With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS. Figure 1.3
shows a comparison of peak throughputs for various 8-bit microcontroller cores with their maximum system clocks.
25
MIPS
20
15
10
5
Silicon Labs
CIP-51
(25 MHz clk)
Microchip
PIC17C75x
(33 MHz clk)
Philips
80C51
(33 MHz clk)
ADuC812
8051
(16 MHz clk)
Figure 1.3. Comparison of Peak MCU Execution Speeds
16
Rev. 2.9
C8051F300/1/2/3/4/5
1.1.3. Additional Features
The C8051F300/1/2/3/4/5 SoC family includes several key enhancements to the CIP-51 core and peripherals to improve performance and ease of use in end applications.
The extended interrupt handler provides 12 interrupt sources into the CIP-51 (as opposed to 7 for the standard 8051), allowing numerous analog and digital peripherals to interrupt the controller. An interrupt driven
system requires less intervention by the MCU, giving it more effective throughput. The extra interrupt
sources are very useful when building multitasking, real-time systems.
Eight reset sources are available: power-on reset circuitry (POR), an on-chip VDD monitor (forces reset
when power supply voltage drops below 2.7 V), a Watchdog Timer, a Missing Clock Detector, a voltage
level detection from Comparator0, a forced software reset, an external reset pin, and an illegal Flash
read/write protection circuit. Each reset source except for the POR, Reset Input Pin, or Flash protection
may be disabled by the user in software. The WDT may be permanently enabled in software after a poweron reset during MCU initialization.
The internal oscillator is available as a factory calibrated 24.5 MHz ±2% (C8051F300/1 devices); an uncalibrated version is available on C8051F302/3/4/5 devices. On all C8051F300/1/2/3/4/5 devices, the internal
oscillator period may be user programmed in ~0.5% increments. An external oscillator drive circuit is also
included, allowing an external crystal, ceramic resonator, capacitor, RC, or CMOS clock source to generate
the system clock. If desired, the system clock source may be switched on-the-fly to the external oscillator
circuit. An external oscillator can be extremely useful in low power applications, allowing the MCU to run
from a slow (power saving) external crystal source, while periodically switching to the fast (up to 25 MHz)
internal oscillator as needed.
VDD
Supply
Monitor
+
-
Enable
Power On
Reset
Comparator 0
P0.x
'0'
(wired-OR)
/RST
+
-
P0.y
C0RSEF
Missing
Clock
Detector
(oneshot)
EN
Reset
Funnel
PCA
WDT
(Software Reset)
SWRSF
Illegal
FLASH
Operation
Internal
Oscillator
XTAL1
XTAL2
External
Oscillator
Drive
System
Clock
Clock Select
WDT
Enable
MCD
Enable
EN
CIP-51
Microcontroller
Core
System Reset
Extended Interrupt
Handler
Figure 1.4. On-Chip Clock and Reset
Rev. 2.9
17
C8051F300/1/2/3/4/5
1.2.
On-Chip Memory
The CIP-51 has a standard 8051 program and data address configuration. It includes 256 bytes of data
RAM, with the upper 128 bytes dual-mapped. Indirect addressing accesses the upper 128 bytes of general
purpose RAM, and direct addressing accesses the 128 byte SFR address space. The lower 128 bytes of
RAM are accessible via direct and indirect addressing. The first 32 bytes are addressable as four banks of
general purpose registers, and the next 16 bytes can be byte addressable or bit addressable.
The C8051F300/1/2/3 includes 8k bytes of Flash program memory (the C8051F304 includes 4k bytes; the
C8051F305 includes 2k bytes). This memory may be reprogrammed in-system in 512 byte sectors, and
requires no special off-chip programming voltage. See Figure 1.5 for the C8051F300/1/2/3 system memory
map.
PROGRAM MEMORY
DATA MEMORY
INTERNAL DATA ADDRESS SPACE
0xFF
0x1E00
RESERVED
0x1DFF
0x80
0x7F
(Direct and Indirect
Addressing)
8k bytes
FLASH
(In-System
Programmable in 512
Byte Sectors)
Upper 128 RAM
(Indirect Addressing
Only)
0x30
0x2F
0x20
0x1F
0x00
Bit Addressable
Special Function
Register's
(Direct Addressing Only)
Lower 128 RAM
(Direct and Indirect
Addressing)
General Purpose
Registers
0x0000
Figure 1.5. On-chip Memory Map (C8051F300/1/2/3 Shown)
18
Rev. 2.9
C8051F300/1/2/3/4/5
1.3.
On-Chip Debug Circuitry
The C8051F300/1/2/3/4/5 devices include on-chip Silicon Labs 2-Wire (C2) debug circuitry that provides
non-intrusive, full-speed, in-circuit debugging of the production part installed in the end application.
Silicon Labs' debugging system supports inspection and modification of memory and registers, breakpoints, and single stepping. No additional target RAM, program memory, timers, or communications channels are required. All the digital and analog peripherals are functional and work correctly while debugging.
All the peripherals (except for the ADC and SMBus) are stalled when the MCU is halted, during single
stepping, or at a breakpoint in order to keep them synchronized.
The C8051F300DK development kit provides all the hardware and software necessary to develop application code and perform in-circuit debugging with the C8051F300/1/2/3/4/5 MCUs. The kit includes software
with a developer's studio and debugger, an integrated 8051 assembler, and a C2 debug adapter. It also
has a target application board with the associated MCU installed and large prototyping area, plus the necessary communication cables and wall-mount power supply. The Development Kit requires a computer
with Windows® 98 SE or later. The Silicon Labs IDE interface is a vastly superior developing and debugging configuration, compared to standard MCU emulators that use onboard "ICE Chips" and require the
MCU in the application board to be socketed. Silicon Labs' debug paradigm increases ease of use and
preserves the performance of the precision analog peripherals.
Silicon Labs Integrated
Development Environment
WINDOWS 98 SE or Later
RS-232
Debug
Adapter
C2 (x2), VDD, GND
VDD
TARGET PCB
GND
C8051F300
Figure 1.6. Development/In-System Debug Diagram
1.4.
Programmable Digital I/O and Crossbar
C8051F300/1/2/3/4/5 devices include a byte-wide I/O Port that behaves like a typical 8051 Port with a few
enhancements. Each Port pin may be configured as an analog input or a digital I/O pin. Pins selected as
digital I/Os may additionally be configured for push-pull or open-drain output. The “weak pull-ups” that are
fixed on typical 8051 devices may be globally disabled, providing power savings capabilities.
Rev. 2.9
19
C8051F300/1/2/3/4/5
Perhaps the most unique Port I/O enhancement is the Digital Crossbar. This is essentially a digital switching network that allows mapping of internal digital system resources to Port I/O pins (See Figure 1.7). Onchip counter/timers, serial buses, HW interrupts, comparator output, and other digital signals in the controller can be configured to appear on the Port I/O pins specified in the Crossbar Control registers. This allows
the user to select the exact mix of general purpose Port I/O and digital resources needed for the particular
application.
XBR0, XBR1,
XBR2 Registers
P0MDOUT,
P0MDIN Registers
Priority
Decoder
Highest
Priority
UART
(Internal Digital Signals)
SMBus
CP0
Outputs
2
2
Digital
Crossbar
2
8
SYSCLK
PCA
T0, T1
P0
I/O
Cells
P0.0
P0.7
4
2
8
Lowest
Priority
Port Latch
P0
(P0.0-P0.7)
Figure 1.7. Digital Crossbar Diagram
1.5.
Serial Ports
The C8051F300/1/2/3/4/5 Family includes an SMBus/I2C interface and a full-duplex UART with enhanced
baud rate configuration. Each of the serial buses is fully implemented in hardware and makes extensive
use of the CIP-51's interrupts, thus requiring very little CPU intervention.
20
Rev. 2.9
C8051F300/1/2/3/4/5
1.6.
Programmable Counter Array
An on-chip Programmable Counter/Timer Array (PCA) is included in addition to the three 16-bit general
purpose counter/timers. The PCA consists of a dedicated 16-bit counter/timer time base with three programmable capture/compare modules. The PCA clock is derived from one of six sources: the system clock
divided by 12, the system clock divided by 4, Timer 0 overflows, an External Clock Input (ECI), the system
clock, or the external oscillator clock source divided by 8. The external clock source selection is useful for
real-time clock functionality, where the PCA is clocked by an external source while the internal oscillator
drives the system clock.
Each capture/compare module can be configured to operate in one of six modes: Edge-Triggered Capture,
Software Timer, High Speed Output, 8- or 16-bit Pulse Width Modulator, or Frequency Output. Additionally,
Capture/Compare Module 2 offers watchdog timer (WDT) capabilities. Following a system reset, Module 2
is configured and enabled in WDT mode. The PCA Capture/Compare Module I/O and External Clock Input
may be routed to Port I/O via the Digital Crossbar.
SYSCLK/12
SYSCLK/4
Timer 0 Overflow
ECI
PCA
CLOCK
MUX
16-Bit Counter/Timer
SYSCLK
External Clock/8
Capture/Compare
Module 0
Capture/Compare
Module 1
Capture/Compare
Module 2
CEX2
CEX1
CEX0
ECI
Digital Crossbar
Port I/O
Figure 1.9. PCA Block Diagram
Rev. 2.9
21
C8051F300/1/2/3/4/5
1.7.
8-Bit Analog to Digital Converter (C8051F300/2 Only)
The C8051F300/2 includes an on-chip 8-bit SAR ADC with a 10-channel differential input multiplexer and
programmable gain amplifier. With a maximum throughput of 500 ksps, the ADC offers true 8-bit accuracy
with an INL of ±1LSB. The ADC system includes a configurable analog multiplexer that selects both positive and negative ADC inputs. Each Port pin is available as an ADC input; additionally, the on-chip Temperature Sensor output and the power supply voltage (VDD) are available as ADC inputs. User firmware
may shut down the ADC to save power.
The integrated programmable gain amplifier (PGA) amplifies the ADC input by 0.5, 1, 2, or 4 as defined by
user software. The gain stage is especially useful when different ADC input channels have widely varied
input voltage signals, or when it is necessary to "zoom in" on a signal with a large DC offset.
Conversions can be started in five ways: a software command, an overflow of Timer 0, 1, or 2, or an external convert start signal. This flexibility allows the start of conversion to be triggered by software events, a
periodic signal (timer overflows), or external HW signals. Conversion completions are indicated by a status
bit and an interrupt (if enabled). The resulting 8-bit data word is latched into an SFR upon completion of a
conversion.
Window compare registers for the ADC data can be configured to interrupt the controller when ADC data is
either within or outside of a specified range. The ADC can monitor a key voltage continuously in background mode, but not interrupt the controller unless the converted data is within/outside the specified
range.
Analog Multiplexer
P0.0
P0.1
P0.2
Configuration, Control, and Data Registers
P0.3
P0.4
P0.5
10-to-1
AMUX
Software Write
T0 Overflow
Start
Conversion
P0.6
TMR2 Overflow
P0.7
Temp
Sensor
Programmable Gain
Amplifier
VDD
VDD
X
+
-
P0.0
T1 Overflow
8-Bit
SAR
ADC
External
Convert Start
8
ADC Data
Register
P0.1
P0.2
P0.3
P0.4
End of
Conversion
Interrupt
9-to-1
AMUX
P0.5
P0.6
P0.7
DGND
Figure 1.10. 8-Bit ADC Block Diagram
22
Rev. 2.9
Window Compare
Logic
Window
Compare
Interrupt
C8051F300/1/2/3/4/5
1.8.
Comparator
C8051F300/1/2/3/4/5 devices include an on-chip voltage comparator that is enabled/disabled and configured via user software. All Port I/O pins may be configurated as comparator inputs. Two comparator outputs may be routed to a Port pin if desired: a latched output and/or an unlatched (asynchronous) output.
Comparator response time is programmable, allowing the user to select between high-speed and lowpower modes. Positive and negative hysteresis is also configurable.
Comparator interrupts may be generated on rising, falling, or both edges. When in IDLE mode, these interrupts may be used as a “wake-up” source. The comparator may also be configured as a reset source.
P0.0
P0.2
P0.4
CP0 +
Interrupt
Handler
VDD
P0.6
+
D
-
CLR
P0.5
P0.7
Q
Q
D
SET
CLR
Q
Q
Crossbar
P0.1
P0.3
SET
(SYNCHRONIZER)
CP0 -
GND
Reset
Decision
Tree
Figure 1.11. Comparator Block Diagram
Rev. 2.9
23
C8051F300/1/2/3/4/5
2.
Absolute Maximum Ratings
Table 2.1. Absolute Maximum Ratings*
Parameter
Conditions
Min
Typ
Max
Units
Ambient temperature under bias
–55
—
125
°C
Storage Temperature
–65
—
150
°C
Voltage on any Port I/O Pin or RST with respect to
GND
–0.3
—
5.8
V
Voltage on VDD with respect to GND
–0.3
—
4.2
V
Maximum Total current through VDD and GND
—
—
500
mA
Maximum output current sunk by RST or any Port pin
—
—
100
mA
*Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the devices at those or any other conditions above
those indicated in the operation listings of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
24
Rev. 2.9
C8051F300/1/2/3/4/5
3.
Global Electrical Characteristics
Table 3.1. Global Electrical Characteristics
–40 to +85 °C, 25 MHz system clock unless otherwise specified.
Parameter
Conditions
Min
Typ
Max
Units
VRST1
3.0
3.6
V
Digital Supply RAM Data
Retention Voltage
—
1.5
—
V
SYSCLK (System Clock)
(Note 2)
0
—
25
MHz
TSYSH (SYSCLK High Time)
18
—
—
ns
TSYSL (SYSCLK Low Time)
18
—
—
ns
Specified Operating
Temperature Range
–40
—
+85
°C
Digital Supply Voltage
Digital Supply Current—CPU Active (Normal Mode, fetching instructions from Flash)
IDD (Note 3)
IDD Supply Sensitivity (Note 3)
IDD Frequency Sensitivity
(Note 3, Note 4)
VDD = 3.6 V, F = 25 MHz
—
9.4
10.2
mA
VDD = 3.0 V, F = 25 MHz
—
6.6
7.2
mA
VDD = 3.0 V, F = 1 MHz
—
0.45
—
mA
VDD = 3.0 V, F = 80 kHz
—
36
—
µA
F = 25 MHz
—
69
—
%/V
F = 1 MHz
—
51
—
%/V
VDD = 3.0 V, F <= 15 MHz, T = 25 °C
—
0.45
—
mA/MHz
VDD = 3.0 V, F > 15 MHz, T = 25 °C
—
0.16
—
mA/MHz
VDD = 3.6 V, F <= 15 MHz, T = 25 °C
—
0.69
—
mA/MHz
VDD = 3.6 V, F > 15 MHz, T = 25 °C
—
0.20
—
mA/MHz
Digital Supply Current—CPU Inactive (Idle Mode, not fetching instructions from Flash)
IDD (Note 3)
VDD = 3.6 V, F = 25 MHz
—
3.3
4.0
mA
VDD = 3.0 V, F = 25 MHz
—
2.5
3.2
mA
VDD = 3.0 V, F = 1 MHz
—
0.10
—
mA
VDD = 3.0 V, F = 80 kHz
—
8
—
µA
Rev. 2.9
25
C8051F300/1/2/3/4/5
Table 3.1. Global Electrical Characteristics (Continued)
–40 to +85 °C, 25 MHz system clock unless otherwise specified.
Parameter
IDD Supply Sensitivity (Note 3)
IDD Frequency Sensitivity
(Note 3, Note 5)
Digital Supply Current
(Stop Mode, shutdown)
Conditions
Min
Typ
Max
Units
F = 25 MHz
—
47
—
%/V
F = 1 MHz
—
59
—
%/V
VDD = 3.0 V, F <= 1 MHz, T = 25 °C
—
0.27
—
mA/MHz
VDD = 3.0 V, F > 1 MHz, T = 25 °C
—
0.10
—
mA/MHz
VDD = 3.6 V, F <= 1 MHz, T = 25 °C
—
0.35
—
mA/MHz
VDD = 3.6 V, F > 1 MHz, T = 25 °C
—
0.12
—
mA/MHz
Oscillator not running,
VDD Monitor Disabled
—
< 0.1
—
µA
Notes:
1. Given in Table 9.2 on page 86.
2. SYSCLK must be at least 32 kHz to enable debugging.
3. Based on device characterization data; Not production tested.
4. Normal IDD can be estimated for frequencies <= 15 MHz by simply multiplying the frequency of interest by
the frequency sensitivity number for that range. When using these numbers to estimate IDD for >15 MHz, the
estimate should be the current at 25 MHz minus the difference in current indicated by the frequency sensitivity
number.
For example: VDD = 3.0 V; F = 20 MHz, IDD = 6.6 mA – (25 MHz – 20 MHz) x 0.16 mA/MHz = 5.8 mA.
5. Idle IDD can be estimated for frequencies <= 1 MHz by simply multiplying the frequency of interest by the
frequency sensitivity number for that range. When using these numbers to estimate Idle IDD for >1 MHz, the
estimate should be the current at 25 MHz minus the difference in current indicated by the frequency sensitivity
number.
For example: VDD = 3.0 V; F = 5 MHz, Idle IDD = 3.3 mA – (25 MHz – 5 MHz) x 0.10 mA/MHz = 1.3 mA.
26
Rev. 2.9
C8051F300/1/2/3/4/5
4.
Pinout and Package Definitions
Table 4.1. Pin Definitions for the C8051F300/1/2/3/4/5
Name
VREF /
Pin
Pin
F300/1/2/3/4/5 F300/1/2/3/4/5
GM
GP
1
5
P0.0
A In
Description
External Voltage Reference Input.
D I/O or Port 0.0. See Section 12 for complete description.
A In
P0.1
2
6
VDD
3
7
XTAL1 /
4
8
P0.2
XTAL2 /
Type
D I/O or Port 0.1. See Section 12 for complete description.
A In
Power Supply Voltage.
A In
Crystal Input. This pin is the external oscillator circuit return for a crystal or ceramic resonator. See
Section 11.2.
D I/O or
A In
Port 0.2. See Section 12 for complete description.
5
10
P0.3
A Out
Crystal Input/Output. For an external crystal or resonator, this pin is the excitation driver. This pin is
the external clock input for CMOS, capacitor, or RC
network configurations. See Section 11.2.
D I/O
Port 0.3. See Section 12 for complete description.
P0.4
6
12
D I/O or Port 0.4. See Section 12 for complete description.
A In
P0.5
7
13
D I/O or Port 0.5. See Section 12 for complete description.
A In
C2CK /
8
14
RST
P0.6 /
9
1
CNVSTR
C2D /
10
2
Clock signal for the C2 Development Interface.
D I/O
Device Reset. Open-drain output of internal POR or
VDD monitor. An external source can initiate a system reset by driving this pin low for at least 10 µs.
D I/O or Port 0.6. See Section 12 for complete description.
A In
D I/O
ADC External Convert Start Input Strobe.
D I/O
Data signal for the C2 Development Interface.
D I/O or Port 0.7. See Section 12 for complete description.
A In
P0.7
GND
D I/O
11
3
Ground.
N.C. pins for F30x GP packages: 4, 9, 11
Rev. 2.9
27
C8051F300/1/2/3/4/5
VREF /
P0.0
C2D /
P0.7
P0.1
P0.6 /
CNVSTR
VDD
GND
XTAL1 /
P0.2
P0.5
XTAL2 /
P0.3
P0.4
Figure 4.1. QFN-11 Pinout Diagram (Top View)
28
C2CK /
/RST
Rev. 2.9
C8051F300/1/2/3/4/5
Figure 4.2. QFN-11 Package Drawing
Table 4.2. QFN-11 Package Dimensions
Dimension
Min
Nom
Max
Dimension
A
0.80
0.90
1.00
E
A1
0.03
0.07
0.11
E2
2.20
2.25
2.30
L
.45
.55
.65
aaa
--
--
0.15
bbb
--
--
0.15
ddd
--
--
0.05
eee
--
--
0.08
A3
b
0.25 REF
0.18
D
D2
e
0.25
0.30
3.00 BSC.
1.30
1.35
0.50 BSC.
1.40
Min
Nom
Max
3.00 BSC.
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC outline MO-243, variation VEED except for custom features D2, E2, and L
which are toleranced per supplier designation.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body
Components.
Rev. 2.9
29
C8051F300/1/2/3/4/5
0.10 mm
b
0.10 mm
LT
0.50 mm
D4
0.35 mm
0.50 mm
0.30 mm
0.35 mm
0.20 mm
L
0.30 mm
D
b
D2
0.20 mm
E2
0.70 mm
e
0.60 mm
0.20 mm
0.30 mm
D4
LB
k
e
E
Figure 4.3. Typical QFN-11 Solder Paste Mask
30
Rev. 2.9
C8051F300/1/2/3/4/5
.
Figure 4.4. Typical QFN-11 Landing Diagram
Table 4.3. QFN-11 Landing Diagram Dimensions
Dimension
C1
C2
E
X1
X2
Y1
Y2
MIN
2.75
2.75
MAX
2.85
2.85
0.50 BSC
0.20
1.40
0.65
2.30
0.30
1.50
0.75
2.40
Notes: General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This land pattern design is based on the IPC-7351 guidelines.
Notes: Solder Mask Design
1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder
mask and the metal pad is to be 60 µm minimum, all the way around the pad.
Notes: Stencil Design
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to
assure good solder paste release.
2. The stencil thickness should be 0.125 mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
4. A 3 x 1 array of 1.30 x 0.60 mm openings on 0.80 mm pitch should be used for the center
ground pad.
Notes: Card Assembly
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for
Small Body Components.
Rev. 2.9
31
C8051F300/1/2/3/4/5
TOP VIEW
P0.6
1
14
C2CK/RST
C2D/P0.7
2
13
P0.5
GND
3
12
P0.4
N/C
4
11
N/C
P0.0
5
10
P0.3
P0.1
6
9
N/C
VDD
7
8
P0.2
Figure 4.5. SOIC-14 Pinout Diagram (Top View)
32
Rev. 2.9
C8051F300/1/2/3/4/5
Figure 4.6. SOIC-14 Package Drawing
Table 4.4. SOIC-14 Package Dimensions
Dimension
Min
Max
Dimension
Min
Max
A
---
1.75
L
0.40
1.27
A1
0.10
0.25
L2
b
0.33
0.51
Q
c
0.17
0.25
aaa
0.10
0.25 BSC
0°
8°
D
8.65 BSC
bbb
0.20
E
6.00 BSC
ccc
0.10
E1
3.90 BSC
ddd
0.25
e
1.27 BSC
Notes:
1. All dimensions shown are in millimeters (mm).
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC outline MS012, variation AB.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for
Small Body Components.
Rev. 2.9
33
C8051F300/1/2/3/4/5
Figure 4.7. SOIC-14 PCB Land Pattern
Table 4.5. SOIC-14 PCB Land Pattern Dimensions
Dimension
Min
Max
C1
5.30
5.40
E
34
1.27 BSC
X1
0.50
0.60
Y1
1.45
1.55
Rev. 2.9
C8051F300/1/2/3/4/5
5.
ADC0 (8-Bit ADC, C8051F300/2)
The ADC0 subsystem for the C8051F300/2 consists of two analog multiplexers (referred to collectively as
AMUX0) with 11 total input selections, a differential programmable gain amplifier (PGA), and a 500 ksps, 8bit successive-approximation-register ADC with integrated track-and-hold and programmable window
detector (see block diagram in Figure 5.1). The AMUX0, PGA, data conversion modes, and window detector are all configurable under software control via the Special Function Registers shown in Figure 5.1.
ADC0 operates in both Single-ended and Differential modes, and may be configured to measure any Port
pin, the Temperature Sensor output, or VDD with respect to any Port pin or GND. The ADC0 subsystem is
enabled only when the AD0EN bit in the ADC0 Control register (ADC0CN) is set to logic 1. The ADC0 subsystem is in low power shutdown when this bit is logic 0.
AMUX0
P0.0
ADC0CN
AD0EN
AD0TM
AD0INT
AD0BUSY
AD0WINT
AD0CM2
AD0CM1
AD0CM0
P0.1
AMX0N2
AMX0N1
AMX0N0
AMX0P3
AMX0P2
AMX0P1
AMX0P0
AMX0N3
AMX0SL
P0.2
P0.3
P0.4
P0.5
10-to-1
AMUX
VDD
Start
Conversion
P0.6
P0.7
X
+
-
ADC0
8-Bit
SAR
VDD
ADC
P0.0
AD0BUSY (W)
001
Timer 0 Overflow
010
Timer 2 Overflow
011
Timer 1 Overflow
1xx
CNVSTR Input
8
SYSCLK
REF
P0.1
P0.2
P0.3
P0.5
P0.6
P0.7
ADC0CF
AMP0GN1
AMP0GN0
P0.4
AD0WINT
9-to-1
AMUX
AD0SC4
AD0SC3
AD0SC2
AD0SC1
AD0SC0
Temp
Sensor
VDD
000
16
Comb.
Logic
ADC0LT
ADC0GT
GND
Figure 5.1. ADC0 Functional Block Diagram
Rev. 2.9
35
C8051F300/1/2/3/4/5
5.1.
Analog Multiplexer and PGA
The analog multiplexers (AMUX0) select the positive and negative inputs to the PGA, allowing any Port pin
to be measured relative to any other Port pin or GND. Additionally, the on-chip temperature sensor or the
positive power supply (VDD) may be selected as the positive PGA input. When GND is selected as the
negative input, ADC0 operates in Single-ended Mode; all other times, ADC0 operates in Differential
Mode. The ADC0 input channels are selected in the AMX0SL register as described in SFR Definition 5.1.
The conversion code format differs in Single-ended versus Differential modes, as shown below. When in
Single-ended Mode (negative input is selected GND), conversion codes are represented as 8-bit unsigned
integers. Inputs are measured from ‘0’ to VREF x 255/256. Example codes are shown below.
Input Voltage
ADC0 Output (Conversion Code)
VREF x 255/256
0xFF
VREF x 128/256
0x80
VREF x 64/256
0x40
0
0x00
When in Differential Mode (negative input is not selected as GND), conversion codes are represented as
8-bit signed 2s complement numbers. Inputs are measured from –VREF to VREF x 127/128. Example
codes are shown below.
Input Voltage
ADC0 Output (Conversion Code)
VREF x 127/128
0x7F
VREF x 64/128
0x40
0
0x00
–VREF x 64/128
0xC0
–VREF
0x80
Important Note About ADC0 Input Configuration: Port pins selected as ADC0 inputs should be configured as analog inputs and should be skipped by the Digital Crossbar. To configure a Port pin for analog
input, set to ‘0’ the corresponding bit in register P0MDIN. To force the Crossbar to skip a Port pin, set to ‘1’
the corresponding bit in register XBR0. See Section “12. Port Input/Output” on page 103 for more Port
I/O configuration details.
The PGA amplifies the AMUX0 output signal as defined by the AMP0GN1-0 bits in the ADC0 Configuration
register (SFR Definition 5.2). The PGA is software-programmable for gains of 0.5, 1, 2, or 4. The gain
defaults to 0.5 on reset.
5.2.
Temperature Sensor
The typical temperature sensor transfer function is shown in Figure 5.2. The output voltage (VTEMP) is the
positive PGA input when the temperature sensor is selected by bits AMX0P2-0 in register AMX0SL; this
voltage will be amplified by the PGA according to the user-programmed PGA settings.
36
Rev. 2.9
C8051F300/1/2/3/4/5
(mV)
1200
1100
1000
900
VTEMP = 3.35*(TEMPC) + 897 mV
800
700
-50
0
50
100
(Celsius)
Figure 5.2. Typical Temperature Sensor Transfer Function
The uncalibrated temperature sensor output is extremely linear and suitable for relative temperature measurements (see Table 5.1 for linearity specifications). For absolute temperature measurements, gain and/
or offset calibration is recommended. Typically a 1-point calibration includes the following steps:
Step 1. Control/measure the ambient temperature (this temperature must be known).
Step 2. Power the device, and delay for a few seconds to allow for self-heating.
Step 3. Perform an ADC conversion with the temperature sensor selected as the positive input
and GND selected as the negative input.
Step 4. Calculate the offset and/or gain characteristics, and store these values in non-volatile
memory for use with subsequent temperature sensor measurements.
Figure 5.3 shows the typical temperature sensor error assuming a 1-point calibration at 25 °C. Note that
parameters which affect ADC measurement, in particular the voltage reference value, will also
affect temperature measurement.
Rev. 2.9
37
Error (degrees C)
C8051F300/1/2/3/4/5
5.00
5.00
4.00
4.00
3.00
3.00
2.00
2.00
1.00
1.00
0.00
-40.00
-20.00
40.00
0.00
20.00
60.00
0.00
80.00
-1.00
-1.00
-2.00
-2.00
-3.00
-3.00
-4.00
-4.00
-5.00
-5.00
Temperature (degrees C)
Figure 5.3. Temperature Sensor Error with 1-Point Calibration (VREF = 2.40 V)
38
Rev. 2.9
C8051F300/1/2/3/4/5
5.3.
Modes of Operation
ADC0 has a maximum conversion speed of 500 ksps. The ADC0 conversion clock is a divided version of
the system clock, determined by the AD0SC bits in the ADC0CF register (system clock divided by
(AD0SC + 1) for 0 ≤ AD0SC ≤ 31).
5.3.1. Starting a Conversion
A conversion can be initiated in one of five ways, depending on the programmed states of the ADC0 Start
of Conversion Mode bits (AD0CM2–0) in register ADC0CN. Conversions may be initiated by one of the following:
1.
2.
3.
4.
5.
Writing a ‘1’ to the AD0BUSY bit of register ADC0CN
A Timer 0 overflow (i.e. timed continuous conversions)
A Timer 2 overflow
A Timer 1 overflow
A rising edge on the CNVSTR input signal (pin P0.6)
Writing a ‘1’ to AD0BUSY provides software control of ADC0 whereby conversions are performed "ondemand". During conversion, the AD0BUSY bit is set to logic 1 and reset to logic 0 when the conversion is
complete. The falling edge of AD0BUSY triggers an interrupt (when enabled) and sets the ADC0 interrupt
flag (AD0INT). Note: When polling for ADC conversion completions, the ADC0 interrupt flag (AD0INT)
should be used. Converted data is available in the ADC0 data register, ADC0, when bit AD0INT is logic 1.
Note that when Timer 2 overflows are used as the conversion source, Timer 2 Low Byte overflows are
used if Timer 2 is in 8-bit mode; Timer 2 High byte overflows are used if Timer 2 is in 16-bit mode. See Section “15. Timers” on page 143 for timer configuration.
Important Note About Using CNVSTR: The CNVSTR input pin also functions as Port pin P0.6. When the
CNVSTR input is used as the ADC0 conversion source, Port pin P0.6 should be skipped by the Digital
Crossbar. To configure the Crossbar to skip P0.6, set to ‘1’ Bit6 in register XBR0. See Section “12. Port
Input/Output” on page 103 for details on Port I/O configuration.
Rev. 2.9
39
C8051F300/1/2/3/4/5
5.3.2. Tracking Modes
According to Table 5.1 on page 47, each ADC0 conversion must be preceded by a minimum tracking time
for the converted result to be accurate. The AD0TM bit in register ADC0CN controls the ADC0 track-andhold mode. In its default state, the ADC0 input is continuously tracked except when a conversion is in progress. When the AD0TM bit is logic 1, ADC0 operates in low-power track-and-hold mode. In this mode,
each conversion is preceded by a tracking period of 3 SAR clocks (after the start-of-conversion signal).
When the CNVSTR signal is used to initiate conversions in low-power tracking mode, ADC0 tracks only
when CNVSTR is low; conversion begins on the rising edge of CNVSTR (see Figure 5.4). Tracking can
also be disabled (shutdown) when the device is in low power standby or sleep modes. Low-power trackand-hold mode is also useful when AMUX or PGA settings are frequently changed, due to the settling time
requirements described in Section “5.3.3. Settling Time Requirements” on page 41.
A. ADC Timing for External Trigger Source
CNVSTR
(AD0CM[2:0]=1xx)
1
2
3
4
5
6
7
8
9
10
11 12
SAR Clocks
AD0TM=1
AD0TM=0
Low Power
or Convert
Track
Track or Convert
Convert
Low Power
Mode
Convert
Track
B. ADC Timing for Internal Trigger Source
Write '1' to AD0BUSY,
Timer 0, Timer 2, Timer 1 Overflow
(AD0CM[2:0]=000, 001, 010, 011)
1
2
3
4
5
6
7
8
9
10
11 12 13
SAR
Clocks
AD0TM=1
Low Power
or Convert
Track
1
2
3
14 15
Low Power
Mode
Convert
4
5
6
7
8
9
10
11 12
SAR
Clocks
AD0TM=0
Track or
Convert
Convert
Track
Figure 5.4. 8-Bit ADC Track and Conversion Example Timing
40
Rev. 2.9
C8051F300/1/2/3/4/5
5.3.3. Settling Time Requirements
When the ADC0 input configuration is changed (i.e., a different AMUX0 or PGA selection is made), a minimum tracking time is required before an accurate conversion can be performed. This tracking time is determined by the AMUX0 resistance, the ADC0 sampling capacitance, any external source resistance, and the
accuracy required for the conversion. Note that in low-power tracking mode, three SAR clocks are used for
tracking at the start of every conversion. For most applications, these three SAR clocks will meet the minimum tracking time requirements.
Figure 5.5 shows the equivalent ADC0 input circuits for both Differential and Single-ended modes. Notice
that the equivalent time constant for both input circuits is the same. The required ADC0 settling time for a
given settling accuracy (SA) may be approximated by Equation 5.1. When measuring the Temperature
Sensor output or VDD with respect to GND, RTOTAL reduces to RMUX. See Table 5.1 for ADC0 minimum
settling time (track/hold time) requirements.
n
2
t = ln  ------- × R TOTAL C SAMPLE
 SA
Equation 5.1. ADC0 Settling Time Requirements
Where:
SA is the settling accuracy, given as a fraction of an LSB (for example, 0.25 to settle within 1/4 LSB)
t is the required settling time in seconds
RTOTAL is the sum of the AMUX0 resistance and any external source resistance.
n is the ADC resolution in bits (8).
Differential Mode
Single-Ended Mode
MUX Select
MUX Select
P0.x
P0.x
RMUX = 5k
RMUX = 5k
CSAMPLE = 5pF
CSAMPLE = 5pF
RCInput= RMUX * CSAMPLE
RCInput= RMUX * CSAMPLE
CSAMPLE = 5pF
P0.y
RMUX = 5k
MUX Select
Note: When the PGA gain is set to 0.5, CSAMPLE = 3pF
Figure 5.5. ADC0 Equivalent Input Circuits
Rev. 2.9
41
C8051F300/1/2/3/4/5
SFR Definition 5.1. AMX0SL: AMUX0 Channel Select (C8051F300/2)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
AMX0N3
AMX0N2
AMX0N1
AMX0N0
AMX0P3
AMX0P2
AMX0P1
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
R/W
Reset Value
AMX0P0 00000000
Bit0
SFR Address:
0xBB
Bits7–4: AMX0N3–0: AMUX0 Negative Input Selection.
Note that when GND is selected as the Negative Input, ADC0 operates in Single-ended
mode. For all other Negative Input selections, ADC0 operates in Differential mode.
0000–1000b: ADC0 Negative Input selected per the chart below.
AMX0N3–0
0000
0001
0010
0011
0100
0101
0110
0111
1xxx
ADC0 Negative Input
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
GND (ADC in Single-Ended Mode)
Bits3–0: AMX0P3–0: AMUX0 Positive Input Selection.
0000–1001b: ADC0 Positive Input selected per the chart below.
1010–1111b: RESERVED.
AMX0P3–0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
42
ADC0 Positive Input
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
Temperature Sensor
VDD
Rev. 2.9
C8051F300/1/2/3/4/5
SFR Definition 5.2. ADC0CF: ADC0 Configuration (C8051F300/2)
R/W
R/W
R/W
R/W
R/W
R/W
AD0SC4
AD0SC3
AD0SC2
AD0SC1
AD0SC0
—
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
R/W
R/W
Reset Value
AMP0GN1 AMP0GN0 11111000
Bit1
Bit0
SFR Address:
0xBC
Bits7–3: AD0SC4–0: ADC0 SAR Conversion Clock Period Bits.
SAR Conversion clock is derived from system clock by the following equation, where
AD0SC refers to the 5-bit value held in bits AD0SC4-0. SAR Conversion clock requirements
are given in Table 5.1.
SYSCLK
AD0SC = ---------------------- – 1
CLK SAR
Bit2:
UNUSED. Read = 0b; Write = don’t care.
Bits1–0: AMP0GN1–0: ADC0 Internal Amplifier Gain (PGA).
00: Gain = 0.5
01: Gain = 1
10: Gain = 2
11: Gain = 4
SFR Definition 5.3. ADC0: ADC0 Data Word (C8051F300/2)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0xBE
Bits7–0: ADC0 Data Word.
ADC0 holds the output data byte from the last ADC0 conversion. When in Single-ended
mode, ADC0 holds an 8-bit unsigned integer. When in Differential mode, ADC0 holds a 2’s
complement signed 8-bit integer.
Rev. 2.9
43
C8051F300/1/2/3/4/5
SFR Definition 5.4. ADC0CN: ADC0 Control (C8051F300/2)
R/W
R/W
AD0EN
AD0TM
Bit7
Bit6
R/W
R/W
R/W
R/W
R/W
R/W
AD0INT AD0BUSY AD0WINT AD0CM2 AD0CM1
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
(bit addressable)
Bit7:
Reset Value
AD0CM0 00000000
SFR Address:
0xE8
AD0EN: ADC0 Enable Bit.
0: ADC0 Disabled. ADC0 is in low-power shutdown.
1: ADC0 Enabled. ADC0 is active and ready for data conversions.
Bit6:
AD0TM: ADC0 Track Mode Bit.
0: Normal Track Mode: When ADC0 is enabled, tracking is continuous unless a conversion
is in progress.
1: Low-power Track Mode: Tracking Defined by AD0CM2-0 bits (see below).
Bit5:
AD0INT: ADC0 Conversion Complete Interrupt Flag.
0: ADC0 has not completed a data conversion since the last time AD0INT was cleared.
1: ADC0 has completed a data conversion.
Bit4:
AD0BUSY: ADC0 Busy Bit.
Read: Unused.
Write:
0: No Effect.
1: Initiates ADC0 Conversion if AD0CM2-0 = 000b
Bit3:
AD0WINT: ADC0 Window Compare Interrupt Flag.
0: ADC0 Window Comparison Data match has not occurred since this flag was last cleared.
1: ADC0 Window Comparison Data match has occurred.
Bits2–0: AD0CM2-0: ADC0 Start of Conversion Mode Select.
When AD0TM = 0:
000: ADC0 conversion initiated on every write of ‘1’ to AD0BUSY.
001: ADC0 conversion initiated on overflow of Timer 0.
010: ADC0 conversion initiated on overflow of Timer 2.
011: ADC0 conversion initiated on overflow of Timer 1.
1xx: ADC0 conversion initiated on rising edge of external CNVSTR.
When AD0TM = 1:
000: Tracking initiated on write of ‘1’ to AD0BUSY and lasts 3 SAR clocks, followed by conversion.
001: Tracking initiated on overflow of Timer 0 and lasts 3 SAR clocks, followed by conversion.
010: Tracking initiated on overflow of Timer 2 and lasts 3 SAR clocks, followed by conversion.
011: Tracking initiated on overflow of Timer 1 and lasts 3 SAR clocks, followed by conversion.
1xx: ADC0 tracks only when CNVSTR input is logic low; conversion starts on rising
CNVSTR edge.
44
Rev. 2.9
C8051F300/1/2/3/4/5
5.4.
Programmable Window Detector
The ADC Programmable Window Detector continuously compares the ADC0 output to user-programmed
limits, and notifies the system when a desired condition is detected. This is especially effective in an interrupt-driven system, saving code space and CPU bandwidth while delivering faster system response times.
The window detector interrupt flag (AD0WINT in register ADC0CN) can also be used in polled mode. The
ADC0 Greater-Than (ADC0GT) and Less-Than (ADC0LT) registers hold the comparison values. Example
comparisons for Single-ended and Differential modes are shown in Figure 5.6 and Figure 5.7, respectively.
Notice that the window detector flag can be programmed to indicate when measured data is inside or outside of the user-programmed limits depending on the contents of the ADC0LT and ADC0GT registers.
5.4.1. Window Detector In Single-Ended Mode
Figure 5.6 shows two example window comparisons for Single-ended mode, with ADC0LT = 0x20 and
ADC0GT = 0x10. Notice that in Single-ended mode, the codes vary from 0 to VREF x (255/256) and are
represented as 8-bit unsigned integers. In the left example, an AD0WINT interrupt will be generated if the
ADC0 conversion word (ADC0) is within the range defined by ADC0GT and ADC0LT
(if 0x10 < ADC0 < 0x20). In the right example, and AD0WINT interrupt will be generated if ADC0 is outside
of the range defined by ADC0GT and ADC0LT (if ADC0 < 0x10 or ADC0 > 0x20).
ADC0
ADC0
Input Voltage
(P0.x - GND)
REF x (255/256)
Input Voltage
(P0.x - GND)
REF x (255/256)
0xFF
0xFF
AD0WINT
not affected
AD0WINT=1
0x21
REF x (32/256)
0x20
0x21
ADC0LT
REF x (32/256)
0x1F
0x20
0x1F
AD0WINT=1
REF x (16/256)
0x11
0x10
ADC0GT
REF x (16/256)
0x0F
0x11
0x10
0x00
ADC0LT
0x0F
AD0WINT=1
AD0WINT
not affected
0
ADC0GT
AD0WINT
not affected
0
0x00
Figure 5.6. ADC Window Compare Examples, Single-Ended Mode
Rev. 2.9
45
C8051F300/1/2/3/4/5
5.4.2. Window Detector In Differential Mode
Figure 5.7 shows two example window comparisons for differential mode, with ADC0LT = 0x10 (+16d) and
ADC0GT = 0xFF (–1d). Notice that in Differential mode, the codes vary from –VREF to VREF x (127/128)
and are represented as 8-bit 2’s complement signed integers. In the left example, an AD0WINT interrupt
will be generated if the ADC0 conversion word (ADC0L) is within the range defined by ADC0GT and
ADC0LT (if 0xFF (–1d) < ADC0 < 0x10 (16d)). In the right example, an AD0WINT interrupt will be generated if ADC0 is outside of the range defined by ADC0GT and ADC0LT (if ADC0 < 0xFF (–1d) or ADC0 >
0x10 (+16d)).
ADC0
ADC0
Input Voltage
(P0.x - P0.y)
REF x (127/128)
Input Voltage
(P0.x - P0.y)
0x7F (127d)
REF x (127/128)
0x7F (127d)
AD0WINT
not affected
AD0WINT=1
0x11 (17d)
REF x (16/128)
0x11 (17d)
0x10 (16d)
ADC0LT
REF x (16/128)
0x0F (15d)
0x10 (16d)
0x0F (15d)
AD0WINT=1
0x00 (0d)
REF x (-1/256)
0x00 (0d)
0xFF (-1d)
ADC0GT
REF x (-1/256)
0xFE (-2d)
0xFF (-1d)
ADC0GT
AD0WINT
not affected
ADC0LT
0xFE (-2d)
AD0WINT=1
AD0WINT
not affected
-REF
0x80 (-128d)
0x80 (-128d)
-REF
Figure 5.7. ADC Window Compare Examples, Differential Mode
SFR Definition 5.5. ADC0GT: ADC0 Greater-Than Data Byte (C8051F300/2)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
11111111
0xC4
Bits7–0: ADC0 Greater-Than Data Word.
SFR Definition 5.6. ADC0LT: ADC0 Less-Than Data Byte (C8051F300/2)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0xC6
Bits7–0: ADC0 Less-Than Data Word.
46
Rev. 2.9
C8051F300/1/2/3/4/5
Table 5.1. ADC0 Electrical Characteristics
VDD = 3.0 V, VREF = 2.40 V (REFSL = 0), PGA Gain = 1, –40 to +85 °C unless otherwise specified.
Parameter
Conditions
Min
Typ
Max
Units
DC Accuracy
Resolution
8
Integral Nonlinearity
Differential Nonlinearity
Guaranteed Monotonic
Offset Error
Full Scale Error
Differential mode
bits
—
±0.5
±1
LSB
—
±0.5
±1
LSB
–5.0
0.5
5.0
LSB
–5.0
–1
5.0
LSB
Dynamic Performance (10 kHz Sine-wave Differential Input, 1 dB below Full Scale, 500 ksps)
Signal-to-Noise Plus Distortion
45
48
—
dB
—
–56
—
dB
—
58
—
dB
SAR Conversion Clock
—
—
6
MHz
Conversion Time in SAR Clocks
11
—
—
clocks
300
—
—
ns
—
—
500
ksps
Input Voltage Range
0
—
VREF
V
Input Capacitance
—
5
—
pF
Temperature Sensor
—
—
—
Linearity1,2,3
—
±0.5
—
°C
—
3350
±110
—
µV / °C
—
897±31
—
mV
—
400
900
µA
—
±0.3
—
mV/V
Total Harmonic Distortion
th
Up to the 5 harmonic
Spurious-Free Dynamic Range
Conversion Rate
Track/Hold Acquisition Time
Throughput Rate
Analog Inputs
Gain1,2,3
Offset1,2,3
(Temp = 0 °C)
Power Specifications
Power Supply Current
(VDD supplied to ADC0)
Operating Mode, 500 ksps
Power Supply Rejection
Notes:
1. Represents one standard deviation from the mean.
2. Measured with PGA Gain = 2.
3. Includes ADC offset, gain, and linearity variations.
Rev. 2.9
47
C8051F300/1/2/3/4/5
NOTES:
48
Rev. 2.9
C8051F300/1/2/3/4/5
6.
Voltage Reference (C8051F300/2)
The voltage reference MUX on C8051F300/2 devices is configurable to use an externally connected voltage reference or the power supply voltage, VDD (see Figure 6.1). The REFSL bit in the Reference Control
register (REF0CN) selects the reference source. For an external source, REFSL should be set to ‘0’; For
VDD as the reference source, REFSL should be set to ‘1’.
The BIASE bit enables the internal voltage bias generator, which is used by the ADC, Temperature Sensor,
and Internal Oscillator. This bit is forced to logic 1 when any of the aforementioned peripherals is enabled.
The bias generator may be enabled manually by writing a ‘1’ to the BIASE bit in register REF0CN; see
SFR Definition 6.1 for REF0CN register details. The electrical specifications for the voltage reference circuit are given in Table 6.1.
Important Note About the VREF Input: Port pin P0.0 is used as the external VREF input. When using an
external voltage reference, P0.0 should be configured as analog input and skipped by the Digital Crossbar.
To configure P0.0 as analog input, set to ‘1’ Bit0 in register P0MDIN. To configure the Crossbar to skip
P0.0, set to ‘1’ Bit0 in register XBR0. Refer to Section “12. Port Input/Output” on page 103 for complete
Port I/O configuration details. The external reference voltage must be within the range 0 ≤ VREF ≤ VDD.
On C8051F300/2 devices, the temperature sensor connects to the highest order input of the ADC0 positive
input multiplexer (see Section “5.1. Analog Multiplexer and PGA” on page 36 for details). The TEMPE
bit in register REF0CN enables/disables the temperature sensor. While disabled, the temperature sensor
defaults to a high impedance state and any ADC0 measurements performed on the sensor result in meaningless data.
BIASE
REFSL
TEMPE
REF0CN
EN
Bias Generator
To ADC, Internal
Oscillator,
Temperature Sensor
IOSCEN
VDD
R1
External
Voltage
Reference
Circuit
EN
VREF
Temp Sensor
To Analog Mux
0
Internal
VREF
(to ADC)
GND
VDD
1
Figure 6.1. Voltage Reference Functional Block Diagram
Rev. 2.9
49
C8051F300/1/2/3/4/5
SFR Definition 6.1. REF0CN: Reference Control Register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
—
—
—
—
REFSL
TEMPE
BIASE
—
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0xD1
Bits7–3: UNUSED. Read = 00000b; Write = don’t care.
Bit3:
REFSL: Voltage Reference Select.
This bit selects the source for the internal voltage reference.
0: VREF input pin used as voltage reference.
1: VDD used as voltage reference.
Bit2:
TEMPE: Temperature Sensor Enable Bit.
0: Internal Temperature Sensor off.
1: Internal Temperature Sensor on.
Bit1:
BIASE: Internal Analog Bias Generator Enable Bit. (Must be ‘1’ if using ADC).
0: Internal Bias Generator off.
1: Internal Bias Generator on.
Bit0:
UNUSED. Read = 0b. Write = don’t care.
Table 6.1. External Voltage Reference Circuit Electrical Characteristics
VDD = 3.0 V; –40 to +85°C unless otherwise specified.
Parameter
Conditions
Input Voltage Range
Input Current
50
Sample Rate = 500 ksps;
VREF = 3.0 V
Rev. 2.9
Min
Typ
Max
Units
0
—
VDD
V
—
12
—
µA
C8051F300/1/2/3/4/5
7.
Comparator0
C8051F300/1/2/3/4/5 devices include an on-chip programmable voltage comparator, which is shown in
Figure 7.1. Comparator0 offers programmable response time and hysteresis, an analog input multiplexer,
and two outputs that are optionally available at the Port pins: a synchronous “latched” output (CP0), or an
asynchronous “raw” output (CP0A). The asynchronous CP0A signal is available even when the system
clock is not active. This allows Comparator0 to operate and generate an output with the device in STOP
mode. When assigned to a Port pin, the Comparator0 output may be configured as open drain or push-pull
(see Section “12.2. Port I/O Initialization” on page 106). Comparator0 may also be used as a reset
source (see Section “9.5. Comparator0 Reset” on page 85).
The inputs for Comparator0 are selected in the CPT0MX register (SFR Definition 7.2). The CMX0P1-CMX0P0 bits select the Comparator0 positive input; the CMX0N1-CMX0N0 bits select the Comparator0 negative input.
Important Note About Comparator Inputs: The Port pins selected as comparator inputs should be configured as analog inputs in their associated Port configuration register, and configured to be skipped by the
Crossbar (for details on Port configuration, see Section “12.3. General Purpose Port I/O” on page 108).
CP0EN
CPT0CN
CMX0N1
CMX0N0
CP0RIF
VDD
CP0FIF
CP0HYP1
CP0HYP0
CP0HYN1
CP0HYN0
CMX0P1
CP0
Rising-edge
Interrupt Flag
CMX0P0
P0.0
CP0
Falling-edge
Interrupt Flag
P0.2
P0.4
CP0 +
Interrupt
Logic
P0.6
CP0
+
D
-
CLR
Q
Q
D
SET
CLR
Q
Q
Crossbar
P0.1
P0.3
SET
(SYNCHRONIZER)
CP0 -
GND
P0.5
CP0A
Reset
Decision
Tree
P0.7
CPT0MD
CPT0MX
CP0OUT
CP0MD1
CP0MD0
Figure 7.1. Comparator0 Functional Block Diagram
Rev. 2.9
51
C8051F300/1/2/3/4/5
The output of Comparator0 can be polled in software, used as an interrupt source, and/or routed to a Port
pin. When routed to a Port pin, the Comparator0 output is available asynchronous or synchronous to the
system clock; the asynchronous output is available even in STOP mode (with no system clock active).
When disabled, the Comparator0 output (if assigned to a Port I/O pin via the Crossbar) defaults to the logic
low state, and its supply current falls to less than 100 nA. See Section “12.1. Priority Crossbar
Decoder” on page 104 for details on configuring the Comparator0 output via the digital Crossbar. Comparator0 inputs can be externally driven from –0.25 to (VDD) + 0.25 V without damage or upset. The complete electrical specifications for Comparator0 are given in Table 7.1.
The Comparator0 response time may be configured in software via the CP0MD1-0 bits in register
CPT0MD (see SFR Definition 7.3). Selecting a longer response time reduces the amount of power consumed by Comparator0. See Table 7.1 for complete timing and power consumption specifications.
VIN+
VIN-
CP0+
CP0-
+
CP0
_
OUT
CIRCUIT CONFIGURATION
Positive Hysteresis Voltage
(Programmed with CP0HYP Bits)
VIN-
INPUTS
Negative Hysteresis Voltage
(Programmed by CP0HYN Bits)
VIN+
VOH
OUTPUT
VOL
Negative Hysteresis
Disabled
Positive Hysteresis
Disabled
Maximum
Negative Hysteresis
Maximum
Positive Hysteresis
Figure 7.2. Comparator Hysteresis Plot
The hysteresis of Comparator0 is software-programmable via its Comparator0 Control register (CPT0CN).
The user can program both the amount of hysteresis voltage (referred to the input voltage) and the positive
and negative-going symmetry of this hysteresis around the threshold voltage.
The Comparator0 hysteresis is programmed using Bits3–0 in the Comparator0 Control Register CPT0CN
(shown in SFR Definition 7.1). The amount of negative hysteresis voltage is determined by the settings of
the CP0HYN bits. As shown in Figure 7.2, settings of 20, 10 or 5 mV of negative hysteresis can be programmed, or negative hysteresis can be disabled. In a similar way, the amount of positive hysteresis is
determined by the setting the CP0HYP bits.
52
Rev. 2.9
C8051F300/1/2/3/4/5
Comparator0 interrupts can be generated on both rising-edge and falling-edge output transitions. (For
Interrupt enable and priority control, see Section “8.3. Interrupt Handler” on page 72). The CP0FIF flag
is set to logic 1 upon a Comparator0 falling-edge interrupt, and the CP0RIF flag is set to logic 1 upon the
Comparator0 rising-edge interrupt. Once set, these bits remain set until cleared by software. The output
state of Comparator0 can be obtained at any time by reading the CP0OUT bit. Comparator0 is enabled by
setting the CP0EN bit to logic 1, and is disabled by clearing this bit to logic 0.
SFR Definition 7.1. CPT0CN: Comparator0 Control
R/W
R
R/W
R/W
CP0EN
CP0OUT
CP0RIF
CP0FIF
Bit7
Bit6
Bit5
Bit4
R/W
R/W
R/W
R/W
Reset Value
CP0HYP1 CP0HYP0 CP0HYN1 CP0HYN0 00000000
Bit3
Bit2
Bit1
Bit0
(bit addressable)
SFR Address:
0xF8
Bit7:
CP0EN: Comparator0 Enable Bit.
0: Comparator0 Disabled.
1: Comparator0 Enabled.
Bit6:
CP0OUT: Comparator0 Output State Flag.
0: Voltage on CP0+ < CP0–.
1: Voltage on CP0+ > CP0–.
Bit5:
CP0RIF: Comparator0 Rising-Edge Interrupt Flag.
0: No Comparator0 Rising Edge Interrupt has occurred since this flag was last cleared.
1: Comparator0 Rising Edge Interrupt has occurred.
Bit4:
CP0FIF: Comparator0 Falling-Edge Interrupt Flag.
0: No Comparator0 Falling-Edge Interrupt has occurred since this flag was last cleared.
1: Comparator0 Falling-Edge Interrupt has occurred.
Bits3–2: CP0HYP1–0: Comparator0 Positive Hysteresis Control Bits.
00: Positive Hysteresis Disabled.
01: Positive Hysteresis = 5 mV.
10: Positive Hysteresis = 10 mV.
11: Positive Hysteresis = 20 mV.
Bits1–0: CP0HYN1–0: Comparator0 Negative Hysteresis Control Bits.
00: Negative Hysteresis Disabled.
01: Negative Hysteresis = 5 mV.
10: Negative Hysteresis = 10 mV.
11: Negative Hysteresis = 20 mV.
Rev. 2.9
53
C8051F300/1/2/3/4/5
SFR Definition 7.2. CPT0MX: Comparator0 MUX Selection
R/W
R/W
—
—
Bit7
Bit6
R/W
R/W
CMX0N1 CMX0N0
Bit5
Bit4
R/W
R/W
—
—
Bit3
Bit2
R/W
R/W
Reset Value
CMX0P1 CMX0P0 00000000
Bit1
Bit0
SFR Address:
0x9F
Bits7–6: UNUSED. Read = 00b, Write = don’t care.
Bits6–4: CMX0N1–CMX0N0: Comparator0 Negative Input MUX Select.
These bits select which Port pin is used as the Comparator0 negative input.
CMX0N1 CMX0N0
0
0
0
1
1
0
1
1
Negative Input
P0.1
P0.3
P0.5
P0.7
Bits3–2: UNUSED. Read = 00b, Write = don’t care.
Bits1–0: CMX0P1–CMX0P0: Comparator0 Positive Input MUX Select.
These bits select which Port pin is used as the Comparator0 positive input.
CMX0P1 CMX0P0
0
0
0
1
1
0
1
1
Positive Input
P0.0
P0.2
P0.4
P0.6
SFR Definition 7.3. CPT0MD: Comparator0 Mode Selection
R/W
R/W
R/W
R/W
R/W
R/W
—
—
—
—
—
—
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
R/W
R/W
Reset Value
CP0MD1 CP0MD0 00000010
Bit1
Bit0
SFR Address:
0x9D
Bits7–2: UNUSED. Read = 000000b, Write = don’t care.
Bits1–0: CP0MD1–CP0MD0: Comparator0 Mode Select.
These bits select the response time for Comparator0.
54
Mode
CP0MD1
CP0MD0
CP0 Response Time (TYP)
0
0
0
Fastest Response Time
1
0
1
—
2
1
0
—
3
1
1
Lowest Power Consumption
Rev. 2.9
C8051F300/1/2/3/4/5
Table 7.1. Comparator0 Electrical Characteristics
VDD = 3.0 V, –40 to +85 °C unless otherwise specified.
Parameter
Response Time:
Mode 0, Vcm* = 1.5 V
Response Time:
Mode 1, Vcm* = 1.5 V
Response Time:
Mode 2, Vcm* = 1.5 V
Response Time:
Mode 3, Vcm* = 1.5 V
Conditions
Min
Typ
Max
Units
CP0+ – CP0– = 100 mV
—
100
—
ns
CP0+ – CP0– = –100 mV
—
250
—
ns
CP0+ – CP0– = 100 mV
—
175
—
ns
CP0+ – CP0– = –100 mV
—
500
—
ns
CP0+ – CP0– = 100 mV
—
320
—
ns
CP0+ – CP0– = –100 mV
—
1100
—
ns
CP0+ – CP0– = 100 mV
—
1050
—
ns
CP0+ – CP0– = –100 mV
—
5200
—
ns
—
1.5
4
mV/V
Common-Mode Rejection
Ratio
Positive Hysteresis 1
CP0HYP1–0 = 00
—
0
1
mV
Positive Hysteresis 2
CP0HYP1–0 = 01
3
5
7
mV
Positive Hysteresis 3
CP0HYP1–0 = 10
7
10
15
mV
Positive Hysteresis 4
CP0HYP1–0 = 11
15
20
25
mV
Negative Hysteresis 1
CP0HYN1–0 = 00
—
0
1
mV
Negative Hysteresis 2
CP0HYN1–0 = 01
3
5
7
mV
Negative Hysteresis 3
CP0HYN1–0 = 10
7
10
15
mV
Negative Hysteresis 4
CP0HYN1–0 = 11
15
20
25
mV
–0.25
—
VDD +
0.25
V
Input Capacitance
—
7
—
pF
Input Bias Current
–5
0.001
+5
nA
Input Offset Voltage
–5
—
+5
mV
Power Supply Rejection
—
0.1
1
mV/V
Power-up Time
—
10
—
µs
Mode 0
—
7.6
—
µA
Mode 1
—
3.2
—
µA
Mode 2
—
1.3
—
µA
Mode 3
—
0.4
—
µA
Inverting or Non-Inverting
Input Voltage Range
Power Supply
Supply Current at DC
*Note: Vcm is the common-mode voltage on CP0+ and CP0–.
Rev. 2.9
55
C8051F300/1/2/3/4/5
NOTES:
56
Rev. 2.9
C8051F300/1/2/3/4/5
8.
CIP-51 Microcontroller
The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the
MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop software. The MCU family has a superset of all the peripherals included with a standard 8051. Included are
three 16-bit counter/timers (see description in Section 15), an enhanced full-duplex UART (see description
in Section 14), 256 bytes of internal RAM, 128 byte Special Function Register (SFR) address space (Section 8.2.6), and one byte-wide I/O Port (see description in Section 12). The CIP-51 also includes on-chip
debug hardware (see description in Section 17), and interfaces directly with the analog and digital subsystems providing a complete data acquisition or control-system solution in a single integrated circuit.
The CIP-51 Microcontroller core implements the standard 8051 organization and peripherals as well as
additional custom peripherals and functions to extend its capability (see Figure 8.1 for a block diagram).
The CIP-51 includes the following features:
Fully Compatible with MCS-51 Instruction Set
25 MIPS Peak Throughput with 25 MHz Clock
0 to 25 MHz Clock Frequency
256 Bytes of Internal RAM
Byte-Wide I/O Port
-
Extended Interrupt Handler
Reset Input
Power Management Modes
On-chip Debug Logic
Program and Data Memory Security
D8
D8
B REGISTER
STACK POINTER
D8
D8
D8
DATA BUS
ACCUMULATOR
TMP1
TMP2
SRAM
ADDRESS
REGISTER
PSW
D8
D8
D8
ALU
SRAM
(256 X 8)
D8
DATA BUS
DATA BUS
SFR_ADDRESS
BUFFER
D8
DATA POINTER
D8
D8
SFR
BUS
INTERFACE
SFR_CONTROL
SFR_WRITE_DATA
SFR_READ_DATA
PC INCREMENTER
DATA BUS
-
PROGRAM COUNTER (PC)
PRGM. ADDRESS REG.
MEM_ADDRESS
D8
MEM_CONTROL
A16
MEMORY
INTERFACE
MEM_WRITE_DATA
MEM_READ_DATA
PIPELINE
RESET
D8
CONTROL
LOGIC
SYSTEM_IRQs
CLOCK
D8
STOP
IDLE
POWER CONTROL
REGISTER
INTERRUPT
INTERFACE
EMULATION_IRQ
D8
Figure 8.1. CIP-51 Block Diagram
Rev. 2.9
57
C8051F300/1/2/3/4/5
Performance
The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system
clock cycles to execute, and usually have a maximum system clock of 12 MHz. By contrast, the CIP-51
core executes 70% of its instructions in one or two system clock cycles, with no instructions taking more
than eight system clock cycles.
With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS. The CIP-51 has
a total of 109 instructions. The table below shows the total number of instructions that require each execution time.
Clocks to Execute
1
2
2/3
3
3/4
4
4/5
5
8
Number of Instructions
26
50
5
14
7
3
1
2
1
Programming and Debugging Support
In-system programming of the Flash program memory and communication with on-chip debug support
logic is accomplished via the Silicon Labs 2-Wire Development Interface (C2). Note that the re-programmable Flash can also be read and changed a single byte at a time by the application software using the
MOVC and MOVX instructions. This feature allows program memory to be used for non-volatile data storage as well as updating program code under software control.
The on-chip debug support logic facilitates full speed in-circuit debugging, allowing the setting of hardware
breakpoints, starting, stopping and single stepping through program execution (including interrupt service
routines), examination of the program's call stack, and reading/writing the contents of registers and memory. This method of on-chip debugging is completely non-intrusive, requiring no RAM, Stack, timers, or
other on-chip resources. C2 details can be found in Section “17. C2 Interface” on page 173.
The CIP-51 is supported by development tools from Silicon Labs and third party vendors. Silicon Labs provides an integrated development environment (IDE) including editor, macro assembler, debugger and programmer. The IDE's debugger and programmer interface to the CIP-51 via the C2 interface to provide fast
and efficient in-system device programming and debugging. Third party macro assemblers and C compilers are also available.
8.1.
Instruction Set
The instruction set of the CIP-51 System Controller is fully compatible with the standard MCS-51™ instruction set. Standard 8051 development tools can be used to develop software for the CIP-51. All CIP-51
instructions are the binary and functional equivalent of their MCS-51™ counterparts, including opcodes,
addressing modes and effect on PSW flags. However, instruction timing is different than that of the standard 8051.
8.1.1. Instruction and CPU Timing
In many 8051 implementations, a distinction is made between machine cycles and clock cycles, with
machine cycles varying from 2 to 12 clock cycles in length. However, the CIP-51 implementation is based
solely on clock cycle timing. All instruction timings are specified in terms of clock cycles.
Due to the pipelined architecture of the CIP-51, most instructions execute in the same number of clock
cycles as there are program bytes in the instruction. Conditional branch instructions take one less clock
cycle to complete when the branch is not taken as opposed to when the branch is taken. Table 8.1 is the
58
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C8051F300/1/2/3/4/5
CIP-51 Instruction Set Summary, which includes the mnemonic, number of bytes, and number of clock
cycles for each instruction.
8.1.2. MOVX Instruction and Program Memory
The MOVX instruction is typically used to access external data memory (Note: the C8051F300/1/2/3/4/5
does not support external data or program memory). In the CIP-51, the MOVX instruction accesses the onchip program memory space implemented as re-programmable Flash memory. This feature provides a
mechanism for the CIP-51 to update program code and use the program memory space for non-volatile
data storage. Refer to Section “10. Flash Memory” on page 89 for further details.
Table 8.1. CIP-51 Instruction Set Summary
Mnemonic
Description
Bytes
Clock
Cycles
1
1
Arithmetic Operations
ADD A, Rn
Add register to A
ADD A, direct
Add direct byte to A
2
2
ADD A, @Ri
Add indirect RAM to A
1
2
ADD A, #data
Add immediate to A
2
2
ADDC A, Rn
Add register to A with carry
1
1
ADDC A, direct
Add direct byte to A with carry
2
2
ADDC A, @Ri
Add indirect RAM to A with carry
1
2
ADDC A, #data
Add immediate to A with carry
2
2
SUBB A, Rn
Subtract register from A with borrow
1
1
SUBB A, direct
Subtract direct byte from A with borrow
2
2
SUBB A, @Ri
Subtract indirect RAM from A with borrow
1
2
SUBB A, #data
Subtract immediate from A with borrow
2
2
INC A
Increment A
1
1
INC Rn
Increment register
1
1
INC direct
Increment direct byte
2
2
INC @Ri
Increment indirect RAM
1
2
DEC A
Decrement A
1
1
DEC Rn
Decrement register
1
1
DEC direct
Decrement direct byte
2
2
DEC @Ri
Decrement indirect RAM
1
2
INC DPTR
Increment Data Pointer
1
1
MUL AB
Multiply A and B
1
4
DIV AB
Divide A by B
1
8
DA A
Decimal adjust A
1
1
Logical Operations
ANL A, Rn
AND Register to A
1
1
ANL A, direct
AND direct byte to A
2
2
ANL A, @Ri
AND indirect RAM to A
1
2
ANL A, #data
AND immediate to A
2
2
Rev. 2.9
59
C8051F300/1/2/3/4/5
Table 8.1. CIP-51 Instruction Set Summary (Continued)
Mnemonic
Description
Bytes
Clock
Cycles
ANL direct, A
AND A to direct byte
2
2
ANL direct, #data
AND immediate to direct byte
3
3
ORL A, Rn
OR Register to A
1
1
ORL A, direct
OR direct byte to A
2
2
ORL A, @Ri
OR indirect RAM to A
1
2
ORL A, #data
OR immediate to A
2
2
ORL direct, A
OR A to direct byte
2
2
ORL direct, #data
OR immediate to direct byte
3
3
XRL A, Rn
Exclusive-OR Register to A
1
1
XRL A, direct
Exclusive-OR direct byte to A
2
2
XRL A, @Ri
Exclusive-OR indirect RAM to A
1
2
XRL A, #data
Exclusive-OR immediate to A
2
2
XRL direct, A
Exclusive-OR A to direct byte
2
2
XRL direct, #data
Exclusive-OR immediate to direct byte
3
3
CLR A
Clear A
1
1
CPL A
Complement A
1
1
RL A
Rotate A left
1
1
RLC A
Rotate A left through Carry
1
1
RR A
Rotate A right
1
1
RRC A
Rotate A right through Carry
1
1
SWAP A
Swap nibbles of A
1
1
Data Transfer
MOV A, Rn
Move Register to A
1
1
MOV A, direct
Move direct byte to A
2
2
MOV A, @Ri
Move indirect RAM to A
1
2
MOV A, #data
Move immediate to A
2
2
MOV Rn, A
Move A to Register
1
1
MOV Rn, direct
Move direct byte to Register
2
2
MOV Rn, #data
Move immediate to Register
2
2
MOV direct, A
Move A to direct byte
2
2
MOV direct, Rn
Move Register to direct byte
2
2
MOV direct, direct
Move direct byte to direct byte
3
3
MOV direct, @Ri
Move indirect RAM to direct byte
2
2
MOV direct, #data
Move immediate to direct byte
3
3
MOV @Ri, A
Move A to indirect RAM
1
2
MOV @Ri, direct
Move direct byte to indirect RAM
2
2
MOV @Ri, #data
Move immediate to indirect RAM
2
2
MOV DPTR, #data16
Load DPTR with 16-bit constant
3
3
MOVC A, @A+DPTR
Move code byte relative DPTR to A
1
3
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C8051F300/1/2/3/4/5
Table 8.1. CIP-51 Instruction Set Summary (Continued)
Mnemonic
Description
Bytes
Clock
Cycles
MOVC A, @A+PC
Move code byte relative PC to A
1
3
MOVX A, @Ri
Move external data (8-bit address) to A
1
3
MOVX @Ri, A
Move A to external data (8-bit address)
1
3
MOVX A, @DPTR
Move external data (16-bit address) to A
1
3
MOVX @DPTR, A
Move A to external data (16-bit address)
1
3
PUSH direct
Push direct byte onto stack
2
2
POP direct
Pop direct byte from stack
2
2
XCH A, Rn
Exchange Register with A
1
1
XCH A, direct
Exchange direct byte with A
2
2
XCH A, @Ri
Exchange indirect RAM with A
1
2
XCHD A, @Ri
Exchange low nibble of indirect RAM with A
1
2
Boolean Manipulation
CLR C
Clear Carry
1
1
CLR bit
Clear direct bit
2
2
SETB C
Set Carry
1
1
SETB bit
Set direct bit
2
2
CPL C
Complement Carry
1
1
CPL bit
Complement direct bit
2
2
ANL C, bit
AND direct bit to Carry
2
2
ANL C, /bit
AND complement of direct bit to Carry
2
2
ORL C, bit
OR direct bit to carry
2
2
ORL C, /bit
OR complement of direct bit to Carry
2
2
MOV C, bit
Move direct bit to Carry
2
2
MOV bit, C
Move Carry to direct bit
2
2
JC rel
Jump if Carry is set
2
2/3
JNC rel
Jump if Carry is not set
2
2/3
JB bit, rel
Jump if direct bit is set
3
3/4
JNB bit, rel
Jump if direct bit is not set
3
3/4
JBC bit, rel
Jump if direct bit is set and clear bit
3
3/4
Program Branching
ACALL addr11
Absolute subroutine call
2
3
LCALL addr16
Long subroutine call
3
4
RET
Return from subroutine
1
5
RETI
Return from interrupt
1
5
AJMP addr11
Absolute jump
2
3
LJMP addr16
Long jump
3
4
SJMP rel
Short jump (relative address)
2
3
JMP @A+DPTR
Jump indirect relative to DPTR
1
3
JZ rel
Jump if A equals zero
2
2/3
Rev. 2.9
61
C8051F300/1/2/3/4/5
Table 8.1. CIP-51 Instruction Set Summary (Continued)
Mnemonic
Description
Bytes
Clock
Cycles
JNZ rel
Jump if A does not equal zero
2
2/3
CJNE A, direct, rel
Compare direct byte to A and jump if not equal
3
3/4
CJNE A, #data, rel
Compare immediate to A and jump if not equal
3
3/4
CJNE Rn, #data, rel
Compare immediate to Register and jump if not
equal
3
3/4
CJNE @Ri, #data, rel
Compare immediate to indirect and jump if not
equal
3
4/5
DJNZ Rn, rel
Decrement Register and jump if not zero
2
2/3
DJNZ direct, rel
Decrement direct byte and jump if not zero
3
3/4
NOP
No operation
1
1
Notes on Registers, Operands and Addressing Modes:
Rn - Register R0-R7 of the currently selected register bank.
@Ri - Data RAM location addressed indirectly through R0 or R1.
rel - 8-bit, signed (two’s complement) offset relative to the first byte of the following instruction. Used by
SJMP and all conditional jumps.
direct - 8-bit internal data location’s address. This could be a direct-access Data RAM location (0x000x7F) or an SFR (0x80-0xFF).
#data - 8-bit constant
#data16 - 16-bit constant
bit - Direct-accessed bit in Data RAM or SFR
addr11 - 11-bit destination address used by ACALL and AJMP. The destination must be within the same
2K-byte page of program memory as the first byte of the following instruction.
addr16 - 16-bit destination address used by LCALL and LJMP. The destination may be anywhere within
the 8K-byte program memory space.
There is one unused opcode (0xA5) that performs the same function as NOP.
All mnemonics copyrighted © Intel Corporation 1980.
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8.2.
Memory Organization
The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are
two separate memory spaces: program memory and data memory. Program and data memory share the
same address space but are accessed via different instruction types. The CIP-51 memory organization is
shown in Figure 8.2 and Figure 8.3.
8.2.1. Program Memory
The CIP-51 core has a 64k-byte program memory space. The C8051F300/1/2/3 implements 8192 bytes of
this program memory space as in-system, reprogrammable Flash memory, organized in a contiguous
block from addresses 0x0000 to 0x1FFF. Note: 512 bytes (0x1E00 - 0x1FFF) of this memory are reserved
for factory use and are not available for user program storage. The C8051F304 implements 4096 bytes of
reprogrammable Flash program memory space; the C8051F305 implements 2048 bytes of reprogrammable Flash program memory space. Figure 8.2 shows the program memory maps for C8051F300/1/2/3/4/5
devices.
C8051F300/1/2/3
(8k FLASH)
0x1E00
0x1DFF
C8051F304
(4k FLASH)
RESERVED
FLASH
0x1000
0x0FFF
FLASH
(In-System
Programmable in 512
Byte Sectors)
0x0000
C8051F305
(2k FLASH)
RESERVED
0x0800
0x07FF
(In-System
Programmable in 512
Byte Sectors)
0x0000
0x0000
RESERVED
FLASH
(In-System
Programmable in 512
Byte Sectors)
Figure 8.2. Program Memory Maps
Program memory is normally assumed to be read-only. However, the CIP-51 can write to program memory
by setting the Program Store Write Enable bit (PSCTL.0) and using the MOVX instruction. This feature provides a mechanism for the CIP-51 to update program code and use the program memory space for nonvolatile data storage. Refer to Section “10. Flash Memory” on page 89 for further details.
Rev. 2.9
63
C8051F300/1/2/3/4/5
8.2.2. Data Memory
The CIP-51 includes 256 bytes of internal RAM mapped into the data memory space from 0x00 through
0xFF. The lower 128 bytes of data memory are used for general purpose registers and scratch pad memory. Either direct or indirect addressing may be used to access the lower 128 bytes of data memory. Locations 0x00 through 0x1F are addressable as four banks of general purpose registers, each bank consisting
of eight byte-wide registers. The next 16 bytes, locations 0x20 through 0x2F, may either be addressed as
bytes or as 128 bit locations accessible with the direct addressing mode.
The upper 128 bytes of data memory are accessible only by indirect addressing. This region occupies the
same address space as the Special Function Registers (SFR) but is physically separate from the SFR
space. The addressing mode used by an instruction when accessing locations above 0x7F determines
whether the CPU accesses the upper 128 bytes of data memory space or the SFRs. Instructions that use
direct addressing will access the SFR space. Instructions using indirect addressing above 0x7F access the
upper 128 bytes of data memory. Figure 8.3 illustrates the data memory organization of the CIP-51.
INTERNAL DATA ADDRESS SPACE
0xFF
0x80
0x7F
Upper 128 RAM
(Indirect Addressing
Only)
(Direct and Indirect
Addressing)
0x30
0x2F
0x20
0x1F
0x00
Bit Addressable
Special Function
Register's
(Direct Addressing Only)
Lower 128 RAM
(Direct and Indirect
Addressing)
General Purpose
Registers
Figure 8.3. Data Memory Map
8.2.3. General Purpose Registers
The lower 32 bytes of data memory, locations 0x00 through 0x1F, may be addressed as four banks of general-purpose registers. Each bank consists of eight byte-wide registers designated R0 through R7. Only
one of these banks may be enabled at a time. Two bits in the program status word, RS0 (PSW.3) and RS1
(PSW.4), select the active register bank (see description of the PSW in SFR Definition 8.4). This allows
fast context switching when entering subroutines and interrupt service routines. Indirect addressing modes
use registers R0 and R1 as index registers.
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8.2.4. Bit Addressable Locations
In addition to direct access to data memory organized as bytes, the sixteen data memory locations at 0x20
through 0x2F are also accessible as 128 individually addressable bits. Each bit has a bit address from
0x00 to 0x7F. Bit 0 of the byte at 0x20 has bit address 0x00 while bit 7 of the byte at 0x20 has bit address
0x07. Bit 7 of the byte at 0x2F has bit address 0x7F. A bit access is distinguished from a full byte access by
the type of instruction used (bit source or destination operands as opposed to a byte source or destination).
The MCS-51™ assembly language allows an alternate notation for bit addressing of the form XX.B where
XX is the byte address and B is the bit position within the byte. For example, the instruction:
MOV
C, 22.3h
moves the Boolean value at 0x13 (bit 3 of the byte at location 0x22) into the Carry flag.
8.2.5. Stack
A programmer's stack can be located anywhere in the 256-byte data memory. The stack area is designated using the Stack Pointer (SP, 0x81) SFR. The SP will point to the last location used. The next value
pushed on the stack is placed at SP+1 and then SP is incremented. A reset initializes the stack pointer to
location 0x07. Therefore, the first value pushed on the stack is placed at location 0x08, which is also the
first register (R0) of register bank 1. Thus, if more than one register bank is to be used, the SP should be
initialized to a location in the data memory not being used for data storage. The stack depth can extend up
to 256 bytes.
8.2.6. Special Function Registers
The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers
(SFRs). The SFRs provide control and data exchange with the CIP-51's resources and peripherals. The
CIP-51 duplicates the SFRs found in a typical 8051 implementation as well as implementing additional
SFRs used to configure and access the subsystems unique to the MCU. This allows the addition of new
functionality while retaining compatibility with the MCS-51™ instruction set. Table 8.2 lists the SFRs implemented in the CIP-51 System Controller.
The SFR registers are accessed anytime the direct addressing mode is used to access memory locations
from 0x80 to 0xFF. SFRs with addresses ending in 0x0 or 0x8 (e.g. P0, TCON, SCON0, IE, etc.) are bitaddressable as well as byte-addressable. All other SFRs are byte-addressable only. Unoccupied
addresses in the SFR space are reserved for future use. Accessing these areas will have an indeterminate
effect and should be avoided. Refer to the corresponding pages of the datasheet, as indicated in Table 8.3,
for a detailed description of each register.
Rev. 2.9
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C8051F300/1/2/3/4/5
Table 8.2. Special Function Register (SFR) Memory Map
F8
F0
E8
E0
D8
D0
C8
C0
B8
B0
A8
A0
98
90
88
80
CPT0CN
B
ADC0CN
ACC
PCA0CN
PSW
TMR2CN
SMB0CN
IP
PCA0L
PCA0H PCA0CPL0 PCA0CPH0
P0MDIN
PCA0CPL1 PCA0CPH1 PCA0CPL2 PCA0CPH2
XBR0
XBR1
XBR2
IT01CF
PCA0MD PCA0CPM0 PCA0CPM1 PCA0CPM2
REF0CN
TMR2RLL TMR2RLH
TMR2L
TMR2H
SMB0CF SMB0DAT
ADC0GT
AMX0SL
ADC0CF
OSCXCN OSCICN
OSCICL
EIP1
RSTSRC
EIE1
ADC0LT
ADC0
FLSCL
FLKEY
IE
P0MDOUT
SCON0
SBUF0
TCON
P0
0(8)
(bit addressable)
TMOD
SP
1(9)
CPT0MD
TL0
DPL
2(A)
TL1
DPH
3(B)
CPT0MX
TH0
TH1
CKCON
4(C)
5(D)
6(E)
PSCTL
PCON
7(F)
Table 8.3. Special Function Registers*
Register
Address
Description
Page
No.
ACC
0xE0
Accumulator
71
ADC0CF
0xBC
ADC0 Configuration
43
ADC0CN
0xE8
ADC0 Control
44
ADC0GT
0xC4
ADC0 Greater-Than Compare Word
46
ADC0LT
0xC6
ADC0 Less-Than Compare Word
46
ADC0
0xBE
ADC0 Data Word
43
AMX0SL
0xBB
ADC0 Multiplexer Channel Select
42
B
0xF0
B Register
71
CKCON
0x8E
Clock Control
149
CPT0CN
0xF8
Comparator0 Control
53
CPT0MD
0x9D
Comparator0 Mode Selection
54
CPT0MX
0x9F
Comparator0 MUX Selection
54
DPH
0x83
Data Pointer High
69
DPL
0x82
Data Pointer Low
68
EIE1
0xE6
Extended Interrupt Enable 1
77
EIP1
0xF6
External Interrupt Priority 1
78
FLKEY
0xB7
Flash Lock and Key
93
*Note: SFRs are listed in alphabetical order. All undefined SFR locations are reserved
66
Rev. 2.9
C8051F300/1/2/3/4/5
Table 8.3. Special Function Registers* (Continued)
Register
Address
Description
Page
No.
FLSCL
0xB6
Flash Scale
93
IE
0xA8
Interrupt Enable
75
IP
0xB8
Interrupt Priority
76
IT01CF
0xE4
INT0/INT1 Configuration Register
79
OSCICL
0xB3
Internal Oscillator Calibration
98
OSCICN
0xB2
Internal Oscillator Control
98
OSCXCN
0xB1
External Oscillator Control
100
P0
0x80
Port 0 Latch
109
P0MDIN
0xF1
Port 0 Input Mode Configuration
109
P0MDOUT
0xA4
Port 0 Output Mode Configuration
110
PCA0CN
0xD8
PCA Control
167
PCA0MD
0xD9
PCA Mode
168
PCA0CPH0
0xFC
PCA Capture 0 High
171
PCA0CPH1
0xEA
PCA Capture 1 High
171
PCA0CPH2
0xEC
PCA Capture 2 High
171
PCA0CPL0
0xFB
PCA Capture 0 Low
171
PCA0CPL1
0xE9
PCA Capture 1 Low
171
PCA0CPL2
0xEB
PCA Capture 2 Low
171
PCA0CPM0
0xDA
PCA Module 0 Mode Register
169
PCA0CPM1
0xDB
PCA Module 1 Mode Register
169
PCA0CPM2
0xDC
PCA Module 2 Mode Register
169
PCA0H
0xFA
PCA Counter High
170
PCA0L
0xF9
PCA Counter Low
170
PCON
0x87
Power Control
81
PSCTL
0x8F
Program Store R/W Control
92
PSW
0xD0
Program Status Word
70
REF0CN
0xD1
Voltage Reference Control
49
RSTSRC
0xEF
Reset Source Configuration/Status
87
SBUF0
0x99
UART 0 Data Buffer
137
SCON0
0x98
UART 0 Control
136
SMB0CF
0xC1
SMBus Configuration
118
SMB0CN
0xC0
SMBus Control
120
SMB0DAT
0xC2
SMBus Data
122
SP
0x81
Stack Pointer
69
TMR2CN
0xC8
Timer/Counter 2 Control
154
TCON
0x88
Timer/Counter Control
147
TH0
0x8C
Timer/Counter 0 High
150
*Note: SFRs are listed in alphabetical order. All undefined SFR locations are reserved
Rev. 2.9
67
C8051F300/1/2/3/4/5
Table 8.3. Special Function Registers* (Continued)
Register
Address
Description
Page
No.
TH1
0x8D
Timer/Counter 1 High
150
TL0
0x8A
Timer/Counter 0 Low
150
TL1
0x8B
Timer/Counter 1 Low
150
TMOD
0x89
Timer/Counter Mode
148
TMR2RLH
0xCB
Timer/Counter 2 Reload High
154
TMR2RLL
0xCA
Timer/Counter 2 Reload Low
154
TMR2H
0xCD
Timer/Counter 2 High
154
TMR2L
0xCC
Timer/Counter 2 Low
154
XBR0
0xE1
Port I/O Crossbar Control 0
107
XBR1
0xE2
Port I/O Crossbar Control 1
107
XBR2
0xE3
Port I/O Crossbar Control 2
108
0x97, 0xAE, 0xAF, 0xB4,
0xB6, 0xBF, 0xCE, 0xD2,
0xD3, 0xD4, 0xD5, 0xD6,
0xD7, 0xDD, 0xDE, 0xDF,
0xF5
Reserved
*Note: SFRs are listed in alphabetical order. All undefined SFR locations are reserved
8.2.7. Register Descriptions
Following are descriptions of SFRs related to the operation of the CIP-51 System Controller. Reserved bits
should not be set to logic l. Future product versions may use these bits to implement new features in which
case the reset value of the bit will be logic 0, selecting the feature's default state. Detailed descriptions of
the remaining SFRs are included in the sections of the datasheet associated with their corresponding system function.
SFR Definition 8.1. DPL: Data Pointer Low Byte
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0x82
Bits7–0: DPL: Data Pointer Low.
The DPL register is the low byte of the 16-bit DPTR. DPTR is used to access indirectly
addressed Flash memory.
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SFR Definition 8.2. DPH: Data Pointer High Byte
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0x83
Bits7–0: DPH: Data Pointer High.
The DPH register is the high byte of the 16-bit DPTR. DPTR is used to access indirectly
addressed Flash memory.
SFR Definition 8.3. SP: Stack Pointer
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000111
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0x81
Bits7–0: SP: Stack Pointer.
The Stack Pointer holds the location of the top of the stack. The stack pointer is incremented
before every PUSH operation. The SP register defaults to 0x07 after reset.
Rev. 2.9
69
C8051F300/1/2/3/4/5
SFR Definition 8.4. PSW: Program Status Word
R/W
R/W
R/W
R/W
R/W
R/W
CY
Bit7
R/W
R
AC
F0
RS1
RS0
Bit6
Bit5
Bit4
Bit3
OV
F1
PARITY
00000000
Bit2
Bit1
Bit0
SFR Address:
(bit addressable)
Reset Value
0xD0
Bit7:
CY: Carry Flag.
This bit is set when the last arithmetic operation resulted in a carry (addition) or a borrow
(subtraction). It is cleared to logic 0 by all other arithmetic operations.
Bit6:
AC: Auxiliary Carry Flag
This bit is set when the last arithmetic operation resulted in a carry into (addition) or a borrow
from (subtraction) the high order nibble. It is cleared to logic 0 by all other arithmetic operations.
Bit5:
F0: User Flag 0.
This is a bit-addressable, general purpose flag for use under software control.
Bits4–3: RS1-RS0: Register Bank Select.
These bits select which register bank is used during register accesses.
Bit2:
Bit1:
Bit0:
70
RS1
RS0
Register Bank
Address
0
0
0
0x00–0x07
0
1
1
0x08–0x0F
1
0
2
0x10–0x17
1
1
3
0x18–0x1F
OV: Overflow Flag.
This bit is set to 1 under the following circumstances:
• An ADD, ADDC, or SUBB instruction causes a sign-change overflow.
• A MUL instruction results in an overflow (result is greater than 255).
• A DIV instruction causes a divide-by-zero condition.
The OV bit is cleared to 0 by the ADD, ADDC, SUBB, MUL, and DIV instructions in all other
cases.
F1: User Flag 1.
This is a bit-addressable, general purpose flag for use under software control.
PARITY: Parity Flag.
This bit is set to logic 1 if the sum of the eight bits in the accumulator is odd and cleared if the
sum is even.
Rev. 2.9
C8051F300/1/2/3/4/5
SFR Definition 8.5. ACC: Accumulator
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
ACC.7
ACC.6
ACC.5
ACC.4
ACC.3
ACC.2
ACC.1
ACC.0
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
(bit addressable)
0xE0
Bits7–0: ACC: Accumulator.
This register is the accumulator for arithmetic operations.
SFR Definition 8.6. B: B Register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
B.7
B.6
B.5
B.4
B.3
B.2
B.1
B.0
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
(bit addressable)
Reset Value
0xF0
Bits7–0: B: B Register.
This register serves as a second accumulator for certain arithmetic operations.
Rev. 2.9
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C8051F300/1/2/3/4/5
8.3.
Interrupt Handler
The CIP-51 includes an extended interrupt system supporting a total of 12 interrupt sources with two priority levels. The allocation of interrupt sources between on-chip peripherals and external inputs pins varies
according to the specific version of the device. Each interrupt source has one or more associated interruptpending flag(s) located in an SFR. When a peripheral or external source meets a valid interrupt condition,
the associated interrupt-pending flag is set to logic 1.
If interrupts are enabled for the source, an interrupt request is generated when the interrupt-pending flag is
set. As soon as execution of the current instruction is complete, the CPU generates an LCALL to a predetermined address to begin execution of an interrupt service routine (ISR). Each ISR must end with an RETI
instruction, which returns program execution to the next instruction that would have been executed if the
interrupt request had not occurred. If interrupts are not enabled, the interrupt-pending flag is ignored by the
hardware and program execution continues as normal. (The interrupt-pending flag is set to logic 1 regardless of the interrupt's enable/disable state.)
Each interrupt source can be individually enabled or disabled through the use of an associated interrupt
enable bit in an SFR (IE-EIE1). However, interrupts must first be globally enabled by setting the EA bit
(IE.7) to logic 1 before the individual interrupt enables are recognized. Setting the EA bit to logic 0 disables
all interrupt sources regardless of the individual interrupt-enable settings.
Note: Any instruction that clears the EA bit should be immediately followed by an instruction that
has two or more opcode bytes. For example:
// in 'C':
EA = 0;
// clear EA bit
EA = 0;
// ... followed by another 2-byte opcode
; in assembly:
CLR EA
; clear EA bit
CLR EA
; ... followed by another 2-byte opcode
If an interrupt is posted during the execution phase of a "CLR EA" opcode (or any instruction which clears
the EA bit), and the instruction is followed by a single-cycle instruction, the interrupt may be taken. However, a read of the EA bit will return a '0' inside the interrupt service routine. When the "CLR EA" opcode is
followed by a multi-cycle instruction, the interrupt will not be taken.
Some interrupt-pending flags are automatically cleared by the hardware when the CPU vectors to the ISR.
However, most are not cleared by the hardware and must be cleared by software before returning from the
ISR. If an interrupt-pending flag remains set after the CPU completes the return-from-interrupt (RETI)
instruction, a new interrupt request will be generated immediately and the CPU will reenter the ISR after
the completion of the next instruction.
8.3.1. MCU Interrupt Sources and Vectors
The MCUs support 12 interrupt sources. Software can simulate an interrupt by setting any interrupt-pending flag to logic 1. If interrupts are enabled for the flag, an interrupt request will be generated and the CPU
will vector to the ISR address associated with the interrupt-pending flag. MCU interrupt sources, associated vector addresses, priority order and control bits are summarized in Table 8.4 on page 74. Refer to the
datasheet section associated with a particular on-chip peripheral for information regarding valid interrupt
conditions for the peripheral and the behavior of its interrupt-pending flag(s).
72
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8.3.2. External Interrupts
The /INT0 and /INT1 external interrupt sources are configurable as active high or low, edge or level sensitive. The IN0PL (/INT0 Polarity) and IN1PL (/INT1 Polarity) bits in the IT01CF register select active high or
active low; the IT0 and IT1 bits in TCON (Section “15.1. Timer 0 and Timer 1” on page 143) select level
or edge sensitive. The table below lists the possible configurations.
IT0
IN0PL
1
0
1
1
/INT0 Interrupt
IT1
IN1PL
Active low, edge sensitive
1
0
Active low, edge sensitive
Active high, edge sensitive
1
1
Active high, edge sensitive
0
Active low, level sensitive
1
Active high, level sensitive
0
0
Active low, level sensitive
0
0
1
Active high, level sensitive
0
/INT1 Interrupt
/INT0 and /INT1 are assigned to Port pins as defined in the IT01CF register (see SFR Definition 8.11).
Note that /INT0 and /INT0 Port pin assignments are independent of any Crossbar assignments. /INT0 and
/INT1 will monitor their assigned Port pins without disturbing the peripheral that was assigned the Port pin
via the Crossbar. To assign a Port pin only to /INT0 and/or /INT1, configure the Crossbar to skip the
selected pin(s). This is accomplished by setting the associated bit in register XBR0 (see Section
“12.1. Priority Crossbar Decoder” on page 104 for complete details on configuring the Crossbar).
IE0 (TCON.1) and IE1 (TCON.3) serve as the interrupt-pending flags for the /INT0 and /INT1 external
interrupts, respectively. If an /INT0 or /INT1 external interrupt is configured as edge-sensitive, the corresponding interrupt-pending flag is automatically cleared by the hardware when the CPU vectors to the ISR.
When configured as level sensitive, the interrupt-pending flag remains logic 1 while the input is active as
defined by the corresponding polarity bit (IN0PL or IN1PL); the flag remains logic 0 while the input is inactive. The external interrupt source must hold the input active until the interrupt request is recognized. It
must then deactivate the interrupt request before execution of the ISR completes or another interrupt
request will be generated.
8.3.3. Interrupt Priorities
Each interrupt source can be individually programmed to one of two priority levels: low or high. A low priority interrupt service routine can be preempted by a high priority interrupt. A high priority interrupt cannot be
preempted. Each interrupt has an associated interrupt priority bit in an SFR (IP or EIP1) used to configure
its priority level. Low priority is the default. If two interrupts are recognized simultaneously, the interrupt with
the higher priority is serviced first. If both interrupts have the same priority level, a fixed priority order is
used to arbitrate, given in Table 8.4.
8.3.4. Interrupt Latency
Interrupt response time depends on the state of the CPU when the interrupt occurs. Pending interrupts are
sampled and priority decoded each system clock cycle. Therefore, the fastest possible response time is 5
system clock cycles: 1 clock cycle to detect the interrupt and 4 clock cycles to complete the LCALL to the
ISR. If an interrupt is pending when a RETI is executed, a single instruction is executed before an LCALL
is made to service the pending interrupt. Therefore, the maximum response time for an interrupt (when no
other interrupt is currently being serviced or the new interrupt is of greater priority) occurs when the CPU is
performing an RETI instruction followed by a DIV as the next instruction. In this case, the response time is
18 system clock cycles: 1 clock cycle to detect the interrupt, 5 clock cycles to execute the RETI, 8 clock
cycles to complete the DIV instruction and 4 clock cycles to execute the LCALL to the ISR. If the CPU is
executing an ISR for an interrupt with equal or higher priority, the new interrupt will not be serviced until the
current ISR completes, including the RETI and following instruction.
Rev. 2.9
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Cleared by HW?
Bit addressable?
Table 8.4. Interrupt Summary
Interrupt
Vector
Priority
Order
Reset
0x0000
Top
External Interrupt 0 (/INT0)
0x0003
0
IE0 (TCON.1)
Y
Timer 0 Overflow
0x000B
1
TF0 (TCON.5)
Y
Y
ET0 (IE.1) PT0 (IP.1)
External Interrupt 1 (/INT1)
0x0013
2
IE1 (TCON.3)
Y
Y
EX1 (IE.2) PX1 (IP.2)
Timer 1 Overflow
0x001B
3
TF1 (TCON.7)
Y
Y
ET1 (IE.3) PT1 (IP.3)
UART0
0x0023
4
RI0 (SCON0.0)
TI0 (SCON0.1)
Y
N
ES0 (IE.4) PS0 (IP.4)
Timer 2 Overflow
0x002B
5
TF2H
(TMR2CN.7)
TF2L
(TMR2CN.6)
Y
N
ET2 (IE.5) PT2 (IP.5)
SMBus Interface
0x0033
6
SI (SMB0CN.0)
Y
N
ESMB0
(EIE1.0)
PSMB0
(EIP1.0)
ADC0 Window Compare
0x003B
7
AD0WINT
(ADC0CN.3)
Y
N
EWADC0
(EIE1.1)
PWADC0
(EIP1.1)
ADC0 Conversion Complete
0x0043
8
AD0INT
(ADC0CN.5)
Y
N
EADC0C
(EIE1.2)
PADC0C
(EIP1.2)
Programmable Counter
Array
0x004B
9
CF (PCA0CN.7)
CCFn
(PCA0CN.n)
Y
N
EPCA0
(EIE1.3)
PPCA0
(EIP1.3)
Comparator0 Falling Edge
0x0053
10
CP0FIF
(CPT0CN.4)
N
N
ECP0F
(EIE1.4)
PCP0F
(EIP1.4)
Comparator0 Rising Edge
0x005B
11
CP0RIF
(CPT0CN.5)
N
N
ECP0R
(EIE1.5)
PCP0R
(EIP1.5)
Interrupt Source
74
Pending Flag
None
Rev. 2.9
N/A
Enable
Flag
Priority
Control
N/A Always
Always
Enabled
Highest
Y EX0 (IE.0) PX0 (IP.0)
C8051F300/1/2/3/4/5
8.3.5. Interrupt Register Descriptions
The SFRs used to enable the interrupt sources and set their priority level are described below. Refer to the
datasheet section associated with a particular on-chip peripheral for information regarding valid interrupt
conditions for the peripheral and the behavior of its interrupt-pending flag(s).
SFR Definition 8.7. IE: Interrupt Enable
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
EA
IEGF0
ET2
ES0
ET1
EX1
ET0
EX0
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
(bit addressable)
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
0xA8
EA: Enable All Interrupts.
This bit globally enables/disables all interrupts. It overrides the individual interrupt mask settings.
0: Disable all interrupt sources.
1: Enable each interrupt according to its individual mask setting.
IEGF0: General Purpose Flag 0.
This is a general purpose flag for use under software control.
ET2: Enable Timer 2 Interrupt.
This bit sets the masking of the Timer 2 interrupt.
0: Disable Timer 2 interrupt.
1: Enable interrupt requests generated by the TF2L or TF2H flags.
ES0: Enable UART0 Interrupt.
This bit sets the masking of the UART0 interrupt.
0: Disable UART0 interrupt.
1: Enable UART0 interrupt.
ET1: Enable Timer 1 Interrupt.
This bit sets the masking of the Timer 1 interrupt.
0: Disable all Timer 1 interrupt.
1: Enable interrupt requests generated by the TF1 flag.
EX1: Enable External Interrupt 1.
This bit sets the masking of external interrupt 1.
0: Disable external interrupt 1.
1: Enable interrupt requests generated by the /INT1 input.
ET0: Enable Timer 0 Interrupt.
This bit sets the masking of the Timer 0 interrupt.
0: Disable all Timer 0 interrupt.
1: Enable interrupt requests generated by the TF0 flag.
EX0: Enable External Interrupt 0.
This bit sets the masking of external interrupt 0.
0: Disable external interrupt 0.
1: Enable interrupt requests generated by the /INT0 input.
Rev. 2.9
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SFR Definition 8.8. IP: Interrupt Priority
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
—
—
PT2
PS0
PT1
PX1
PT0
PX0
11000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
(bit addressable)
Bits7–6: UNUSED. Read = 11b, Write = don't care.
Bit5:
PT2: Timer 2 Interrupt Priority Control.
This bit sets the priority of the Timer 2 interrupt.
0: Timer 2 interrupts set to low priority level.
1: Timer 2 interrupts set to high priority level.
Bit4:
PS0: UART0 Interrupt Priority Control.
This bit sets the priority of the UART0 interrupt.
0: UART0 interrupts set to low priority level.
1: UART0 interrupts set to high priority level.
Bit3:
PT1: Timer 1 Interrupt Priority Control.
This bit sets the priority of the Timer 1 interrupt.
0: Timer 1 interrupts set to low priority level.
1: Timer 1 interrupts set to high priority level.
Bit2:
PX1: External Interrupt 1 Priority Control.
This bit sets the priority of the External Interrupt 1 interrupt.
0: External Interrupt 1 set to low priority level.
1: External Interrupt 1 set to high priority level.
Bit1:
PT0: Timer 0 Interrupt Priority Control.
This bit sets the priority of the Timer 0 interrupt.
0: Timer 0 interrupts set to low priority level.
1: Timer 0 interrupts set to high priority level.
Bit0:
PX0: External Interrupt 0 Priority Control.
This bit sets the priority of the External Interrupt 0 interrupt.
0: External Interrupt 0 set to low priority level.
1: External Interrupt 0 set to high priority level.
76
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C8051F300/1/2/3/4/5
SFR Definition 8.9. EIE1: Extended Interrupt Enable 1
R/W
R/W
R/W
R/W
R/W
—
—
ECP0R
ECP0F
EPCA0
Bit7
Bit6
Bit5
Bit4
Bit3
R/W
R/W
EADC0C EWADC0
Bit2
R/W
Reset Value
ESMB0
00000000
Bit0
SFR Address:
Bit1
0xE6
Bits7–6: UNUSED. Read = 00b. Write = don’t care.
Bit5:
ECP0R: Enable Comparator0 (CP0) Rising Edge Interrupt.
This bit sets the masking of the CP0 Rising Edge interrupt.
0: Disable CP0 Rising Edge interrupt.
1: Enable interrupt requests generated by the CP0RIF flag.
Bit4:
ECP0F: Enable Comparator0 (CP0) Falling Edge Interrupt.
This bit sets the masking of the CP0 Falling Edge interrupt.
0: Disable CP0 Falling Edge interrupt.
1: Enable interrupt requests generated by the CP0FIF flag.
Bit3:
EPCA0: Enable Programmable Counter Array (PCA0) Interrupt.
This bit sets the masking of the PCA0 interrupts.
0: Disable all PCA0 interrupts.
1: Enable interrupt requests generated by PCA0.
Bit2:
EADC0C: Enable ADC0 Conversion Complete Interrupt.
This bit sets the masking of the ADC0 Conversion Complete interrupt.
0: Disable ADC0 Conversion Complete interrupt.
1: Enable interrupt requests generated by the AD0INT flag.
Bit1:
EWADC0: Enable Window Comparison ADC0 Interrupt.
This bit sets the masking of ADC0 Window Comparison interrupt.
0: Disable ADC0 Window Comparison interrupt.
1: Enable interrupt requests generated by ADC0 Window Compare flag.
Bit0:
ESMB0: Enable SMBus Interrupt.
This bit sets the masking of the SMBus interrupt.
0: Disable all SMBus interrupts.
1: Enable interrupt requests generated by the SI flag.
Rev. 2.9
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C8051F300/1/2/3/4/5
SFR Definition 8.10. EIP1: Extended Interrupt Priority 1
R/W
R/W
R/W
R/W
R/W
—
—
PCP0R
PCP0F
PPCA0
Bit7
Bit6
Bit5
Bit4
Bit3
R/W
R/W
PADC0C PWADC0
Bit2
Bit1
R/W
Reset Value
PSMB0
11000000
Bit0
SFR Address:
0xF6
Bits7–6: UNUSED. Read = 11b. Write = don’t care.
Bit5:
PCP0R: Comparator0 (CP0) Rising Interrupt Priority Control.
This bit sets the priority of the CP0 rising-edge interrupt.
0: CP0 rising interrupt set to low priority level.
1: CP0 rising interrupt set to high priority level.
Bit4:
PCP0F: Comparator0 (CP0) Falling Interrupt Priority Control.
This bit sets the priority of the CP0 falling-edge interrupt.
0: CP0 falling interrupt set to low priority level.
1: CP0 falling interrupt set to high priority level.
Bit3:
PPCA0: Programmable Counter Array (PCA0) Interrupt Priority Control.
This bit sets the priority of the PCA0 interrupt.
0: PCA0 interrupt set to low priority level.
1: PCA0 interrupt set to high priority level.
Bit2:
PADC0C ADC0 Conversion Complete Interrupt Priority Control
This bit sets the priority of the ADC0 Conversion Complete interrupt.
0: ADC0 Conversion Complete interrupt set to low priority level.
1: ADC0 Conversion Complete interrupt set to high priority level.
Bit1:
PWADC0: ADC0 Window Comparator Interrupt Priority Control.
This bit sets the priority of the ADC0 Window interrupt.
0: ADC0 Window interrupt set to low priority level.
1: ADC0 Window interrupt set to high priority level.
Bit0:
PSMB0: SMBus Interrupt Priority Control.
This bit sets the priority of the SMBus interrupt.
0: SMBus interrupt set to low priority level.
1: SMBus interrupt set to high priority level.
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SFR Definition 8.11. IT01CF: INT0/INT1 Configuration
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
IN1PL
IN1SL2
IN1SL1
IN1SL0
IN0PL
IN0SL2
IN0SL1
IN0SL0
00000001
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0xE4
Note: Refer to SFR Definition 15.1 for INT0/1 edge- or level-sensitive interrupt selection.
Bit7:
IN1PL: /INT1 Polarity
0: /INT1 input is active low.
1: /INT1 input is active high.
Bits6–4: IN1SL2–0: /INT1 Port Pin Selection Bits
These bits select which Port pin is assigned to /INT1. Note that this pin assignment is independent of the Crossbar; /INT1 will monitor the assigned Port pin without disturbing the
peripheral that has been assigned the Port pin via the Crossbar. The Crossbar will not
assign the Port pin to a peripheral if it is configured to skip the selected pin (accomplished by
setting to ‘1’ the corresponding bit in register XBR0).
IN1SL2–0
000
001
010
011
100
101
110
111
/INT1 Port Pin
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
Bit3:
IN0PL: /INT0 Polarity
0: /INT0 interrupt is active low.
1: /INT0 interrupt is active high.
Bits2–0: INT0SL2–0: /INT0 Port Pin Selection Bits
These bits select which Port pin is assigned to /INT0. Note that this pin assignment is independent of the Crossbar. /INT0 will monitor the assigned Port pin without disturbing the
peripheral that has been assigned the Port pin via the Crossbar. The Crossbar will not
assign the Port pin to a peripheral if it is configured to skip the selected pin (accomplished by
setting to ‘1’ the corresponding bit in register XBR0).
IN0SL2–0
000
001
010
011
100
101
110
111
/INT0 Port Pin
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
Rev. 2.9
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8.4.
Power Management Modes
The CIP-51 core has two software programmable power management modes: Idle and Stop. Idle mode
halts the CPU while leaving the peripherals and clocks active. In Stop mode, the CPU is halted, all interrupts and timers (except the Missing Clock Detector) are inactive, and the system clock is stopped (analog
peripherals remain in their selected states). Since clocks are running in Idle mode, power consumption is
dependent upon the system clock frequency and the number of peripherals left in active mode before
entering Idle. Stop mode consumes the least power. SFR Definition 8.12 describes the Power Control Register (PCON) used to control the CIP-51's power management modes.
Although the CIP-51 has Idle and Stop modes built in (as with any standard 8051 architecture), power
management of the entire MCU is better accomplished by enabling/disabling individual peripherals as
needed. Each analog peripheral can be disabled when not in use and placed in low power mode. Digital
peripherals, such as timers or serial buses, draw little power when they are not in use. Turning off the oscillators lowers power consumption considerably; however a reset is required to restart the MCU.
8.4.1. Idle Mode
Setting the Idle Mode Select bit (PCON.0) causes the CIP-51 to halt the CPU and enter Idle mode as soon
as the instruction that sets the bit completes execution. All internal registers and memory maintain their
original data. All analog and digital peripherals can remain active during Idle mode.
Idle mode is terminated when an enabled interrupt is asserted or a reset occurs. The assertion of an
enabled interrupt will cause the Idle Mode Selection bit (PCON.0) to be cleared and the CPU to resume
operation. The pending interrupt will be serviced and the next instruction to be executed after the return
from interrupt (RETI) will be the instruction immediately following the one that set the Idle Mode Select bit.
If Idle mode is terminated by an internal or external reset, the CIP-51 performs a normal reset sequence
and begins program execution at address 0x0000.
If enabled, the Watchdog Timer (WDT) will eventually cause an internal watchdog reset and thereby terminate the Idle mode. This feature protects the system from an unintended permanent shutdown in the event
of an inadvertent write to the PCON register. If this behavior is not desired, the WDT may be disabled by
software prior to entering the Idle mode if the WDT was initially configured to allow this operation. This provides the opportunity for additional power savings, allowing the system to remain in the Idle mode indefinitely, waiting for an external stimulus to wake up the system. Refer to Section “16.3. Watchdog Timer
Mode” on page 164 for more information on the use and configuration of the WDT.
Note: Any instruction that sets the IDLE bit should be immediately followed by an instruction that
has 2 or more opcode bytes. For example:
// in 'C':
PCON |= 0x01;
PCON = PCON;
// set IDLE bit
// ... followed by a 3-cycle dummy instruction
; in assembly:
ORL PCON, #01h
MOV PCON, PCON
; set IDLE bit
; ... followed by a 3-cycle dummy instruction
If the instruction following the write of the IDLE bit is a single-byte instruction and an interrupt occurs during
the execution phase of the instruction that sets the IDLE bit, the CPU may not wake from IDLE mode when
a future interrupt occurs.
80
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8.4.2. Stop Mode
Setting the Stop Mode Select bit (PCON.1) causes the CIP-51 to enter Stop mode as soon as the instruction that sets the bit completes execution. In Stop mode the internal oscillator, CPU, and all digital peripherals are stopped; the state of the external oscillator circuit is not affected. Each analog peripheral
(including the external oscillator circuit) may be shut down individually prior to entering Stop Mode. Stop
mode can only be terminated by an internal or external reset. On reset, the CIP-51 performs the normal
reset sequence and begins program execution at address 0x0000.
If enabled, the Missing Clock Detector will cause an internal reset and thereby terminate the Stop mode.
The Missing Clock Detector should be disabled if the CPU is to be put to in STOP mode for longer than the
MCD timeout of 100 µsec.
SFR Definition 8.12. PCON: Power Control
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
GF5
GF4
GF3
GF2
GF1
GF0
STOP
IDLE
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0x87
Bits7–2: GF5–GF0: General Purpose Flags 5-0.
These are general purpose flags for use under software control.
Bit1:
STOP: Stop Mode Select.
Setting this bit will place the CIP-51 in Stop mode. This bit will always be read as 0.
1: CPU goes into Stop mode (turns off internal oscillator).
Bit0:
IDLE: Idle Mode Select.
Setting this bit will place the CIP-51 in Idle mode. This bit will always be read as 0.
1: CPU goes into Idle mode (shuts off clock to CPU, but clock to Timers, Interrupts, Serial
Ports, and Analog Peripherals are still active).
Rev. 2.9
81
C8051F300/1/2/3/4/5
NOTES:
82
Rev. 2.9
C8051F300/1/2/3/4/5
9.
Reset Sources
Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this
reset state, the following occur:
•
•
•
•
CIP-51 halts program execution
Special Function Registers (SFRs) are initialized to their defined reset values
External Port pins are forced to a known state
Interrupts and timers are disabled.
All SFRs are reset to the predefined values noted in the SFR detailed descriptions. The contents of internal
data memory are unaffected during a reset; any previously stored data is preserved. However, since the
stack pointer SFR is reset, the stack is effectively lost even though the data on the stack is not altered.
The Port I/O latches are reset to 0xFF (all logic ones) in open-drain mode. Weak pullups are enabled
during and after the reset. For VDD Monitor and power-on resets, the RST pin is driven low until the device
exits the reset state.
On exit from the reset state, the program counter (PC) is reset, and the system clock defaults to the internal oscillator. Refer to Section “11. Oscillators” on page 97 for information on selecting and configuring
the system clock source. The Watchdog Timer is enabled with the system clock divided by 12 as its clock
source (Section “16.3. Watchdog Timer Mode” on page 164 details the use of the Watchdog Timer).
Once the system clock source is stable, program execution begins at location 0x0000.
VDD
Supply
Monitor
+
-
Enable
Power On
Reset
Comparator 0
P0.x
'0'
(wired-OR)
/RST
+
-
P0.y
C0RSEF
Missing
Clock
Detector
(oneshot)
EN
Reset
Funnel
PCA
WDT
(Software Reset)
SWRSF
Illegal
FLASH
Operation
Internal
Oscillator
XTAL1
XTAL2
External
Oscillator
Drive
System
Clock
Clock Select
WDT
Enable
MCD
Enable
EN
CIP-51
Microcontroller
Core
System Reset
Extended Interrupt
Handler
Figure 9.1. Reset Sources
Rev. 2.9
83
C8051F300/1/2/3/4/5
9.1.
Power-On Reset
During powerup, the device is held in a reset state and the RST pin is driven low until VDD settles above
VRST. An additional delay occurs before the device is released from reset; the delay decreases as the VDD
ramp time increases (VDD ramp time is defined as how fast VDD ramps from 0 V to VRST). For valid ramp
times (less than 1 ms), the power-on reset delay (TPORDelay) is typically less than 0.3 ms.
Note: The maximum VDD ramp time is 1 ms; slower ramp times may cause the device to be
released from reset before VDD reaches the VRST level.
volts
On exit from a power-on reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1. When PORSF is
set, all of the other reset flags in the RSTSRC Register are indeterminate (PORSF is cleared by all other
resets). Since all resets cause program execution to begin at the same location (0x0000) software can
read the PORSF flag to determine if a powerup was the cause of reset. The content of internal data memory should be assumed to be undefined after a power-on reset. The VDD monitor is disabled following a
power-on reset.
VDD
2.70
2.55
VRST
VD
D
2.0
1.0
t
Logic HIGH
Logic LOW
/RST
TPORDelay
VDD
Monitor
Reset
Power-On
Reset
Figure 9.2. Power-On and VDD Monitor Reset Timing
9.2.
Power-Fail Reset/VDD Monitor
When a power-down transition or power irregularity causes VDD to drop below VRST, the power supply
monitor will drive the RST pin low and hold the CIP-51 in a reset state (see Figure 9.2). When VDD returns
to a level above VRST, the CIP-51 will be released from the reset state. Note that even though internal data
memory contents are not altered by the power-fail reset, it is impossible to determine if VDD dropped below
the level required for data retention. If the PORSF flag reads ‘1’, the data may no longer be valid. The VDD
monitor is disabled after power-on resets; however its defined state (enabled/disabled) is not altered by
any other reset source. For example, if the VDD monitor is enabled and a software reset is performed, the
VDD monitor will still be enabled after the reset. The VDD monitor is enabled by writing a ‘1’ to the PORSF
84
Rev. 2.9
C8051F300/1/2/3/4/5
bit in register RSTSRC. See Figure 9.2 for VDD monitor timing; note that the reset delay is not incurred
after a VDD monitor reset. See Table 9.2 for electrical characteristics of the VDD monitor.
Important Note: Enabling the VDD monitor will immediately generate a system reset. The device will then
return from the reset state with the VDD monitor enabled. Writing a logic ‘1’ to the PORSF flag when the
VDD monitor is enabled does not cause a system reset.
9.3.
External Reset
The external RST pin provides a means for external circuitry to force the device into a reset state. Asserting an active-low signal on the RST pin generates a reset; an external pullup and/or decoupling of the RST
pin may be necessary to avoid erroneous noise-induced resets. See Table 9.2 for complete RST pin specifications. The PINRSF flag (RSTSRC.0) is set on exit from an external reset.
9.4.
Missing Clock Detector Reset
The Missing Clock Detector (MCD) is a one-shot circuit that is triggered by the system clock. If the system
clock remains high or low for more than 100 µs, the one-shot will time out and generate a reset. After a
MCD reset, the MCDRSF flag (RSTSRC.2) will read ‘1’, signifying the MCD as the reset source; otherwise,
this bit reads ‘0’. Writing a ‘1’ to the MCDRSF bit enables the Missing Clock Detector; writing a ‘0’ disables
it. The state of the RST pin is unaffected by this reset.
9.5.
Comparator0 Reset
Comparator0 can be configured as a reset source by writing a ‘1’ to the C0RSEF flag (RSTSRC.5). Comparator0 should be enabled and allowed to settle prior to writing to C0RSEF to prevent any turn-on chatter
on the output from generating an unwanted reset. The Comparator0 reset is active-low: if the non-inverting
input voltage (on CP0+) is less than the inverting input voltage (on CP0–), the device is put into the reset
state. After a Comparator0 reset, the C0RSEF flag (RSTSRC.5) will read ‘1’ signifying Comparator0 as the
reset source; otherwise, this bit reads ‘0’. The state of the RST pin is unaffected by this reset.
9.6.
PCA Watchdog Timer Reset
The programmable Watchdog Timer (WDT) function of the Programmable Counter Array (PCA) can be
used to prevent software from running out of control during a system malfunction. The PCA WDT function
can be enabled or disabled by software as described in Section “16.3. Watchdog Timer Mode” on
page 164; the WDT is enabled and clocked by SYSCLK / 12 following any reset. If a system malfunction
prevents user software from updating the WDT, a reset is generated and the WDTRSF bit (RSTSRC.5) is
set to ‘1’. The state of the RST pin is unaffected by this reset.
Rev. 2.9
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C8051F300/1/2/3/4/5
9.7.
Flash Error Reset
If a Flash read/write/erase or program read targets an illegal address, a system reset is generated. This
may occur due to any of the following:
•
A Flash write or erase is attempted above user code space. This occurs when PSWE is set to ‘1’ and a
MOVX operation is attempted above the user code space address limit.
A Flash read is attempted above user code space. This occurs when a MOVC operation is attempted
above the user code space address limit.
A Program read is attempted above user code space. This occurs when user code attempts to branch
to an address above the user code space address limit.
•
•
Table 9.1. User Code Space Address Limits
Device
User Code Space Address Limit
C8051F300/1/2/3
0x1DFF
C8051F304
0x0FFF
C8051F305
0x07FF
The FERROR bit (RSTSRC.6) is set following a Flash error reset. The state of the RST pin is unaffected by
this reset.
9.8.
Software Reset
Software may force a reset by writing a ‘1’ to the SWRSF bit (RSTSRC.4). The SWRSF bit will read ‘1’ following a software forced reset. The state of the RST pin is unaffected by this reset.
Table 9.2. Reset Electrical Characteristics
–40 to +85 °C unless otherwise specified.
Parameter
Conditions
Min
Typ
Max
Units
RST Output Low Voltage
IOL = 8.5 mA, VDD = 2.7 V to
3.6 V
—
—
0.6
V
RST Input High Voltage
0.7 x VDD
—
—
V
RST Input Low Voltage
—
—
0.3 x VDD
—
25
40
µA
2.40
2.55
2.70
V
100
220
500
µs
5.0
—
—
µs
15
—
—
µs
—
—
1
ms
RST Input Leakage Current
RST = 0.0 V
VDD Monitor Threshold (VRST)
Missing Clock Detector Timeout Time from last system clock rising edge to reset initiation
Reset Time Delay
Delay between release of any
reset source and code execution
at location 0x0000
Minimum RST Low Time to
Generate a System Reset
VDD Ramp Time
86
VDD = 0 to VRST
Rev. 2.9
C8051F300/1/2/3/4/5
SFR Definition 9.1. RSTSRC: Reset Source
R
—
Bit7
R
R/W
FERROR C0RSEF
Bit6
Bit5
R/W
SWRSF
Bit4
R
R/W
WDTRSF MCDRSF
Bit3
Bit2
R/W
R
PORSF
PINRSF
Reset Value
Variable
Bit1
Bit0
SFR Address:
0xEF
(Note: Do not use read-modify-write operations (ORL, ANL) on this register)
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
UNUSED. Read = 0. Write = don’t care.
FERROR: Flash Error Indicator.
0: Source of last reset was not a Flash read/write/erase error.
1: Source of last reset was a Flash read/write/erase error.
C0RSEF: Comparator0 Reset Enable and Flag.
Write
0: Comparator0 is not a reset source.
1: Comparator0 is a reset source (active-low).
Read
0: Source of last reset was not Comparator0.
1: Source of last reset was Comparator0.
SWRSF: Software Reset Force and Flag.
Write
0: No Effect.
1: Forces a system reset.
Read
0: Source of last reset was not a write to the SWRSF bit.
1: Source of last was a write to the SWRSF bit.
WDTRSF: Watchdog Timer Reset Flag.
0: Source of last reset was not a WDT timeout.
1: Source of last reset was a WDT timeout.
MCDRSF: Missing Clock Detector Flag.
Write:
0: Missing Clock Detector disabled.
1: Missing Clock Detector enabled; triggers a reset if a missing clock condition is detected.
Read:
0: Source of last reset was not a Missing Clock Detector timeout.
1: Source of last reset was a Missing Clock Detector timeout.
PORSF: Power-On Reset Force and Flag.
This bit is set anytime a power-on reset occurs. This may be due to a true power-on reset or
a VDD monitor reset. In either case, data memory should be considered indeterminate following the reset. Writing this bit enables/disables the VDD monitor.
Write:
0: VDD monitor disabled.
1: VDD monitor enabled.
Read:
0: Last reset was not a power-on or VDD monitor reset.
1: Last reset was a power-on or VDD monitor reset; all other reset flags indeterminate.
PINRSF: HW Pin Reset Flag.
0: Source of last reset was not RST pin.
1: Source of last reset was RST pin.
Rev. 2.9
87
C8051F300/1/2/3/4/5
NOTES:
88
Rev. 2.9
C8051F300/1/2/3/4/5
10. Flash Memory
On-chip, reprogrammable Flash memory is included for program code and non-volatile data storage. The
Flash memory can be programmed in-system, a single byte at a time, through the C2 interface or by software using the MOVX instruction. Once cleared to logic 0, a Flash bit must be erased to set it back to logic
1. Flash bytes would typically be erased (set to 0xFF) before being reprogrammed. The write and erase
operations are automatically timed by hardware for proper execution; data polling to determine the end of
the write/erase operation is not required. Code execution is stalled during a Flash write/erase operation.
Refer to Table 10.1 for complete Flash memory electrical characteristics.
10.1. Programming The Flash Memory
The simplest means of programming the Flash memory is through the C2 interface using programming
tools provided by Silicon Labs or a third party vendor. This is the only means for programming a non-initialized device. For details on the C2 commands to program Flash memory, see Section “17. C2 Interface”
on page 173.
To ensure the integrity of Flash contents, it is strongly recommended that the on-chip VDD Monitor
be enabled in any system that includes code that writes and/or erases Flash memory from software.
10.1.1. Flash Lock and Key Functions
Flash writes and erases by user software are protected with a lock and key function; Flash reads by user
software are unrestricted. The Flash Lock and Key Register (FLKEY) must be written with the correct key
codes, in sequence, before Flash operations may be performed. The key codes are: 0xA5, 0xF1. The timing does not matter, but the codes must be written in order. If the key codes are written out of order, or the
wrong codes are written, Flash writes and erases will be disabled until the next system reset. Flash writes
and erases will also be disabled if a Flash write or erase is attempted before the key codes have been written properly. The Flash lock resets after each write or erase; the key codes must be written again before a
following Flash operation can be performed. The FLKEY register is detailed in SFR Definition 10.2.
10.1.2. Flash Erase Procedure
The Flash memory can be programmed by software using the MOVX instruction with the address and data
byte to be programmed provided as normal operands. Before writing to Flash memory using MOVX, Flash
write operations must be enabled by: (1) setting the PSWE Program Store Write Enable bit (PSCTL.0) to
logic 1 (this directs the MOVX writes to target Flash memory); and (2) Writing the Flash key codes in
sequence to the Flash Lock register (FLKEY). The PSWE bit remains set until cleared by software.
A write to Flash memory can clear bits but cannot set them; only an erase operation can set bits in Flash.
A byte location to be programmed should be erased before a new value is written. The 8k byte Flash
memory is organized in 512-byte pages. The erase operation applies to an entire page (setting all bytes in
the page to 0xFF). To erase an entire 512-byte page, perform the following steps:
Step 1.
Step 2.
Step 3.
Step 4.
Step 5.
Step 6.
Disable interrupts (recommended).
Set the Program Store Erase Enable bit (PSEE in the PSCTL register).
Set the Program Store Write Enable bit (PSWE in the PSCTL register).
Write the first key code to FLKEY: 0xA5.
Write the second key code to FLKEY: 0xF1.
Using the MOVX instruction, write a data byte to any location within the 512-byte page to
be erased.
Rev. 2.9
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C8051F300/1/2/3/4/5
10.1.3. Flash Write Procedure
Flash bytes are programmed by software with the following sequence:
Step 1. Disable interrupts (recommended).
Step 2. Erase the 512-byte Flash page containing the target location, as described in Section
10.1.2.
Step 3. Set the PSWE bit in PSCTL.
Step 4. Clear the PSEE bit in PSCTL.
Step 5. Write the first key code to FLKEY: 0xA5.
Step 6. Write the second key code to FLKEY: 0xF1.
Step 7. Using the MOVX instruction, write a single data byte to the desired location within the 512byte sector.
Steps 5–7 must be repeated for each byte to be written. After Flash writes are complete, PSWE should be
cleared so that MOVX instructions do not target program memory. Writing to and erasing the Reserved
area of Flash should be avoided.
Table 10.1. Flash Electrical Characteristics
Parameter
Flash Size
Conditions
Min
C8051F300/1/2/3
8192*
bytes
C8051F304
4096
bytes
C8051F305
2048
bytes
Endurance
Typ
20k
100k
Max
Units
Erase/Write
Erase Cycle Time
25 MHz System Clock
10
15
20
ms
Write Cycle Time
25 MHz System Clock
40
55
70
µs
SYSCLK Frequency (Flash
writes from application code)
100
kHz
*Note: 512 bytes at location 0x1E00 to 0x1FFF are reserved.
10.2. Non-Volatile Data Storage
The Flash memory can be used for non-volatile data storage as well as program code. This allows data
such as calibration coefficients to be calculated and stored at run time. Data is written using the MOVX
instruction and read using the MOVC instruction.
10.3. Security Options
The CIP-51 provides security options to protect the Flash memory from inadvertent modification by software as well as to prevent the viewing of proprietary program code and constants. The Program Store
Write Enable (bit PSWE in register PSCTL) and the Program Store Erase Enable (bit PSEE in register
PSCTL) bits protect the Flash memory from accidental modification by software. PSWE must be explicitly
set to ‘1’ before software can modify the Flash memory; both PSWE and PSEE must be set to ‘1’ before
software can erase Flash memory. Additional security features prevent proprietary program code and data
constants from being read or altered across the C2 interface.
A security lock byte stored at the last byte of Flash user space protects the Flash program memory from
being read or altered across the C2 interface. See Table 10.2 for the security byte description; see
Figure 10.1 for a program memory map and the security byte locations for each device.
90
Rev. 2.9
C8051F300/1/2/3/4/5
Table 10.2. Security Byte Decoding
Bits
Description
7–4
Write Lock: Clearing any of these bits to logic 0 prevents all Flash
memory from being written or page-erased across the C2 interface
3–0
Read/Write Lock: Clearing any of these bits to logic 0 prevents all
Flash memory from being read, written, or page-erased across the
C2 interface.
The lock bits can always be read and cleared to logic 0 regardless of the security settings.
Important note: The only means of removing a lock (write or read/write) once set is to erase the
entire program memory space via a C2 Device Erase command.
C8051F300/1/2/3
Reserved
C8051F304
0x1E00
Lock Byte
0x1DFF
0x1DFE
C8051F305
Reserved
0x1000
Lock Byte
0x0FFF
Reserved
0x0800
0x0FFE
Lock Byte
FLASH memory
organized in 512-byte
pages
FLASH memory
organized in 512-byte
pages
0x0000
0x07FF
0x07FE
FLASH memory
organized in 512-byte
pages
0x0000
0x0000
Figure 10.1. Flash Program Memory Map
The level of Flash security depends on the Flash access method. The three Flash access methods that
can be restricted are reads, writes, and erases from the C2 debug interface, user firmware executing on
unlocked pages, and user firmware executing on locked pages.
Accessing Flash from the C2 debug interface:
1.
2.
3.
4.
5.
6.
Any unlocked page may be read, written, or erased.
Locked pages cannot be read, written, or erased.
The page containing the Lock Byte may be read, written, or erased if it is unlocked.
Reading the contents of the Lock Byte is always permitted only if no pages are locked.
Locking additional pages (changing ‘1’s to ‘0’s in the Lock Byte) is not permitted.
Unlocking Flash pages (changing ‘0’s to ‘1’s in the Lock Byte) requires the C2 Device Erase command, which erases all Flash pages including the page containing the Lock Byte and the Lock
Byte itself.
7. The Reserved Area cannot be read, written, or erased.
Rev. 2.9
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C8051F300/1/2/3/4/5
Accessing Flash from user firmware executing from an unlocked page:
1. Any unlocked page except the page containing the Lock Byte may be read, written, or erased.
2. Locked pages cannot be read, written, or erased. An erase attempt on the page containing the
Lock Byte will result in a Flash Error device reset.
3. The page containing the Lock Byte cannot be erased. It may be read or written only if it is
unlocked. An erase attempt on the page containing the Lock Byte will result in a Flash Error device
reset.
4. Reading the contents of the Lock Byte is always permitted.
5. Locking additional pages (changing ‘1’s to ‘0’s in the Lock Byte) is not permitted.
6. Unlocking Flash pages (changing ‘0’s to ‘1’s in the Lock Byte) is not permitted.
7. The Reserved Area cannot be read, written, or erased. Any attempt to access the reserved area,
or any other locked page, will result in a Flash Error device reset.
Accessing Flash from user firmware executing from a locked page:
1. Any unlocked page except the page containing the Lock Byte may be read, written, or erased.
2. Any locked page except the page containing the Lock Byte may be read, written, or erased. An
erase attempt on the page containing the Lock Byte will result in a Flash Error device reset.
3. The page containing the Lock Byte cannot be erased. It may only be read or written. An erase
attempt on the page containing the Lock Byte will result in a Flash Error device reset.
4. Reading the contents of the Lock Byte is always permitted.
5. Locking additional pages (changing ‘1’s to ‘0’s in the Lock Byte) is not permitted.
6. Unlocking Flash pages (changing ‘0’s to ‘1’s in the Lock Byte) is not permitted.
7. The Reserved Area cannot be read, written, or erased. Any attempt to access the reserved area,
or any other locked page, will result in a Flash Error device reset.
SFR Definition 10.1. PSCTL: Program Store R/W Control
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
—
—
—
—
—
—
PSEE
PSWE
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0x8F
Bits7–2: UNUSED: Read = 000000b, Write = don’t care.
Bit1:
PSEE: Program Store Erase Enable
Setting this bit (in combination with PSWE) allows an entire page of Flash program memory
to be erased. If this bit is logic 1 and Flash writes are enabled (PSWE is logic 1), a write to
Flash memory using the MOVX instruction will erase the entire page that contains the location addressed by the MOVX instruction. The value of the data byte written does not matter.
0: Flash program memory erasure disabled.
1: Flash program memory erasure enabled.
Bit0:
PSWE: Program Store Write Enable
Setting this bit allows writing a byte of data to the Flash program memory using the MOVX
instruction. The Flash location should be erased before writing data.
0: Writes to Flash program memory disabled.
1: Writes to Flash program memory enabled; the MOVX instruction targets Flash memory.
92
Rev. 2.9
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SFR Definition 10.2. FLKEY: Flash Lock and Key
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0xB7
Bits7–0: FLKEY: Flash Lock and Key Register
Write:
This register must be written to before Flash writes or erases can be performed. Flash
remains locked until this register is written to with the following key codes: 0xA5, 0xF1. The
timing of the writes does not matter, as long as the codes are written in order. The key codes
must be written for each Flash write or erase operation. Flash will be locked until the next
system reset if the wrong codes are written or if a Flash operation is attempted before the
codes have been written correctly.
Read:
When read, bits 1–0 indicate the current Flash lock state.
00: Flash is write/erase locked.
01: The first key code has been written (0xA5).
10: Flash is unlocked (writes/erases allowed).
11: Flash writes/erases disabled until the next reset.
SFR Definition 10.3. FLSCL: Flash Scale
R/W
FOSE
Bit7
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
Reserved Reserved Reserved Reserved Reserved Reserved Reserved 10000000
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0xB6
Bits7:
FOSE: Flash One-shot Enable
This bit enables the 50 ns Flash read one-shot. When the Flash one-shot disabled, the
Flash sense amps are enabled for a full clock cycle during Flash reads.
0: Flash one-shot disabled.
1: Flash one-shot enabled.
Bits6–0: RESERVED. Read = 0. Must Write 0.
Rev. 2.9
93
C8051F300/1/2/3/4/5
10.4. Flash Write and Erase Guidelines
Any system which contains routines which write or erase Flash memory from software involves some risk
that the write or erase routines will execute unintentionally if the CPU is operating outside its specified
operating range of VDD, system clock frequency, or temperature. This accidental execution of Flash modifying code can result in alteration of Flash memory contents causing a system failure that is only recoverable by re-Flashing the code in the device.
The following guidelines are recommended for any system which contains routines which write or erase
Flash from code.
10.4.1. VDD Maintenance and the VDD monitor
1. If the system power supply is subject to voltage or current "spikes," add sufficient transient
protection devices to the power supply to ensure that the supply voltages listed in the Absolute
Maximum Ratings table are not exceeded.
2. Make certain that the minimum VDD rise time specification of 1 ms is met. If the system cannot
meet this rise time specification, then add an external VDD brownout circuit to the RST pin of
the device that holds the device in reset until VDD reaches 2.7 V and re-asserts RST if VDD
drops below 2.7 V.
3. Enable the on-chip VDD monitor and enable the VDD monitor as a reset source as early in code
as possible. This should be the first set of instructions executed after the Reset Vector. For 'C'based systems, this will involve modifying the startup code added by the 'C' compiler. See your
compiler documentation for more details. Make certain that there are no delays in software
between enabling the VDD monitor and enabling the VDD monitor as a reset source. Code
examples showing this can be found in “AN201: Writing to Flash from Firmware", available
from the Silicon Laboratories web site.
4. As an added precaution, explicitly enable the VDD monitor and enable the VDD monitor as a
reset source inside the functions that write and erase Flash memory. The VDD monitor enable
instructions should be placed just after the instruction to set PSWE to a '1', but before the
Flash write or erase operation instruction.
5. Make certain that all writes to the RSTSRC (Reset Sources) register use direct assignment
operators and explicitly DO NOT use the bit-wise operators (such as AND or OR). For example, "RSTSRC = 0x02" is correct. "RSTSRC |= 0x02" is incorrect.
6. Make certain that all writes to the RSTSRC register explicitly set the PORSF bit to a '1'. Areas
to check are initialization code which enables other reset sources, such as the Missing Clock
Detector or Comparator, for example, and instructions which force a Software Reset. A global
search on "RSTSRC" can quickly verify this.
10.4.2. PSWE Maintenance
7. Reduce the number of places in code where the PSWE bit (b0 in PSCTL) is set to a '1'. There
should be exactly one routine in code that sets PSWE to a '1' to write Flash bytes and one routine in code that sets PSWE and PSEE both to a '1' to erase Flash pages.
8. Minimize the number of variable accesses while PSWE is set to a '1'. Handle pointer address
updates and loop variable maintenance outside the "PSWE = 1; ... PSWE = 0;" area. Code
examples showing this can be found in AN201, "Writing to Flash from Firmware", available
from the Silicon Laboratories web site.
9. Disable interrupts prior to setting PSWE to a '1' and leave them disabled until after PSWE has
been reset to '0'. Any interrupts posted during the Flash write or erase operation will be ser-
94
Rev. 2.9
C8051F300/1/2/3/4/5
viced in priority order after the Flash operation has been completed and interrupts have been
re-enabled by software.
10. Make certain that the Flash write and erase pointer variables are not located in XRAM. See
your compiler documentation for instructions regarding how to explicitly locate variables in different memory areas.
11. Add address bounds checking to the routines that write or erase Flash memory to ensure that
a routine called with an illegal address does not result in modification of the Flash.
10.4.3. System Clock
12. If operating from an external crystal, be advised that crystal performance is susceptible to
electrical interference and is sensitive to layout and to changes in temperature. If the system is
operating in an electrically noisy environment, use the internal oscillator or use an external
CMOS clock.
13. If operating from the external oscillator, switch to the internal oscillator during Flash write or
erase operations. The external oscillator can continue to run, and the CPU can switch back to
the external oscillator after the Flash operation has completed.
Additional Flash recommendations and example code can be found in AN201, "Writing to Flash from Firmware", available from the Silicon Laboratories web site.
Rev. 2.9
95
C8051F300/1/2/3/4/5
NOTES:
96
Rev. 2.9
C8051F300/1/2/3/4/5
11. Oscillators
C8051F300/1/2/3/4/5 devices include a programmable internal oscillator and an external oscillator drive
circuit. The internal oscillator can be enabled/disabled and calibrated using the OSCICN and OSCICL registers, as shown in Figure 11.1. The system clock can be sourced by the external oscillator circuit, the
internal oscillator, or a scaled version of the internal oscillator. The internal oscillator's electrical specifications are given in Table 11.1 on page 99.
OSCICN
IFRDY
CLKSL
IOSCEN
IFCN1
IFCN0
OSCICL
Option 3
XTAL2
Option 4
EN
XTAL2
Option 2
VDD
Programmable
Internal Clock
Generator
n
SYSCLK
Option 1
XTAL1
Input
Circuit
10MΩ
XTAL2
OSC
XFCN2
XFCN1
XFCN0
XTLVLD
XOSCMD2
XOSCMD1
XOSCMD0
XTAL2
OSCXCN
Figure 11.1. Oscillator Diagram
11.1. Programmable Internal Oscillator
All C8051F300/1/2/3/4/5 devices include a programmable internal oscillator that defaults as the system
clock after a system reset. The internal oscillator period can be adjusted via the OSCICL register as
defined by SFR Definition 11.1. On C8051F300/1 devices, OSCICL is factory calibrated to obtain a
24.5 MHz frequency. On C8051F302/3/4/5 devices, the oscillator frequency is a nominal 20 MHz and may
vary ±20% from device-to-device.
Electrical specifications for the precision internal oscillator are given in Table 11.1 on page 99. The programmed internal oscillator frequency must not exceed 25 MHz. Note that the system clock may be
derived from the programmed internal oscillator divided by 1, 2, 4, or 8, as defined by the IFCN bits in register OSCICN. The divide value defaults to 8 following a reset.
Rev. 2.9
97
C8051F300/1/2/3/4/5
SFR Definition 11.1. OSCICL: Internal Oscillator Calibration
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
—
Bit7
Variable
0xB3
Bit7:
UNUSED. Read = 0. Write = don’t care.
Bits 6–0: OSCICL: Internal Oscillator Calibration Register.
This register calibrates the internal oscillator period. The reset value for OSCICL defines the
internal oscillator base frequency. On C8051F300/1 devices, the reset value is factory calibrated to generate an internal oscillator frequency of 24.5 MHz.
SFR Definition 11.2. OSCICN: Internal Oscillator Control
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
Reset Value
—
—
—
IFRDY
CLKSL
IOSCEN
IFCN1
IFCN0
00010100
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0xB2
Bits7–5: UNUSED. Read = 000b, Write = don't care.
Bit4:
IFRDY: Internal Oscillator Frequency Ready Flag.
0: Internal Oscillator is not running at programmed frequency.
1: Internal Oscillator is running at programmed frequency.
Bit3:
CLKSL: System Clock Source Select Bit.
0: SYSCLK derived from the Internal Oscillator, and scaled as per the IFCN bits.
1: SYSCLK derived from the External Oscillator circuit.
Bit2:
IOSCEN: Internal Oscillator Enable Bit.
0: Internal Oscillator Disabled.
1: Internal Oscillator Enabled.
Bits1–0: IFCN1-0: Internal Oscillator Frequency Control Bits.
00: SYSCLK derived from Internal Oscillator divided by 8.
01: SYSCLK derived from Internal Oscillator divided by 4.
10: SYSCLK derived from Internal Oscillator divided by 2.
11: SYSCLK derived from Internal Oscillator divided by 1.
98
Rev. 2.9
C8051F300/1/2/3/4/5
Table 11.1. Internal Oscillator Electrical Characteristics
–40 to +85 °C unless otherwise specified
Parameter
Conditions
Min
Typ
Max
Units
C8051F300/1 devices
–40 to +85 °C
24
24.5
25
MHz
C8051F300/1 devices
0 to +70 °C
24.3
24.7
25
MHz
Uncalibrated Internal Oscillator
Frequency
C8051F302/3/4/5 devices
16
20
24
MHz
Internal Oscillator Supply Current
(from VDD)
OSCICN.2 = 1
Calibrated Internal Oscillator
Frequency
450
µA
11.2. External Oscillator Drive Circuit
The external oscillator circuit may drive an external crystal, ceramic resonator, capacitor, or RC network. A
CMOS clock may also provide a clock input. For a crystal or ceramic resonator configuration, the crystal/resonator must be wired across the XTAL1 and XTAL2 pins as shown in Option 1 of Figure 11.1. A
10 MΩ resistor also must be wired across the XTAL2 and XTAL1 pins for the crystal/resonator configuration. In RC, capacitor, or CMOS clock configuration, the clock source should be wired to the XTAL2 pin as
shown in Option 2, 3, or 4 of Figure 11.1. The type of external oscillator must be selected in the OSCXCN
register, and the frequency control bits (XFCN) must be selected appropriately (see SFR Definition 11.3).
Important Note on External Oscillator Usage: Port pins must be configured when using the external
oscillator circuit. When the external oscillator drive circuit is enabled in crystal/resonator mode, Port pins
P0.2 and P0.3 are occupied as XTAL1 and XTAL2 respectively. When the external oscillator drive circuit is
enabled in capacitor, RC, or CMOS clock mode, Port pin P0.3 is occupied as XTAL2. The Port I/O Crossbar should be configured to skip the occupied Port pins; see Section “12.1. Priority Crossbar Decoder”
on page 104 for Crossbar configuration. Additionally, when using the external oscillator circuit in crystal/resonator, capacitor, or RC mode, the associated Port pins should be configured as analog inputs. In
CMOS clock mode, the associated pin should be configured as a digital input. See Section “12.2. Port
I/O Initialization” on page 106 for details on Port input mode selection.
11.3. System Clock Selection
The CLKSL bit in register OSCICN selects which oscillator is used as the system clock. CLKSL must be
set to ‘1’ for the system clock to run from the external oscillator; however the external oscillator may still
clock peripherals (timers, PCA) when the internal oscillator is selected as the system clock. The system
clock may be switched on-the-fly between the internal and external oscillator, so long as the selected oscillator is enabled and has settled. The internal oscillator requires little start-up time and may be enabled and
selected as the system clock in the same write to OSCICN. External crystals and ceramic resonators typically require a start-up time before they are settled and ready for use as the system clock. The Crystal
Valid Flag (XTLVLD in register OSCXCN) is set to ‘1’ by hardware when the external oscillator is settled. To
avoid reading a false XTLVLD, in crystal mode software should delay at least 1 ms between enabling the
external oscillator and checking XTLVLD. RC and C modes typically require no start-up time.
Rev. 2.9
99
C8051F300/1/2/3/4/5
SFR Definition 11.3. OSCXCN: External Oscillator Control
R
R/W
R/W
R/W
XTLVLD XOSCMD2 XOSCMD1 XOSCMD0
Bit7
Bit6
Bit5
Bit4
R
R/W
R/W
R/W
Reset Value
—
XFCN2
XFCN1
XFCN0
00000000
Bit3
Bit2
Bit1
Bit0
SFR Address:
0xB1
Bit7:
XTLVLD: Crystal Oscillator Valid Flag.
(Read only when XOSCMD = 11x.)
0: Crystal Oscillator is unused or not yet stable.
1: Crystal Oscillator is running and stable.
Bits6–4: XOSCMD2-0: External Oscillator Mode Bits.
00x: External Oscillator circuit off.
010: External CMOS Clock Mode.
011: External CMOS Clock Mode with divide by 2 stage.
100: RC Oscillator Mode with divide by 2 stage.
101: Capacitor Oscillator Mode with divide by 2 stage.
110: Crystal Oscillator Mode.
111: Crystal Oscillator Mode with divide by 2 stage.
Bit3:
RESERVED. Read = 0, Write = don't care.
Bits2–0: XFCN2-0: External Oscillator Frequency Control Bits.
000-111: See table below:
XFCN
000
001
010
011
100
101
110
111
Crystal (XOSCMD = 11x)
f ≤ 32 kHz
32 kHz < f ≤ 84 kHz
84 kHz < f ≤ 225 kHz
225 kHz < f ≤ 590 kHz
590 kHz < f ≤ 1.5 MHz
1.5 MHz < f ≤ 4 MHz
4 MHz < f ≤ 10 MHz
10 MHz < f ≤ 30 MHz
RC (XOSCMD = 10x)
f ≤ 25 kHz
25 kHz < f ≤ 50 kHz
50 kHz < f ≤ 100 kHz
100 kHz < f ≤ 200 kHz
200 kHz < f ≤ 400 kHz
400 kHz < f ≤ 800 kHz
800 kHz < f ≤ 1.6 MHz
1.6 MHz < f ≤ 3.2 MHz
CRYSTAL MODE (Circuit from Figure 11.1, Option 1; XOSCMD = 11x)
Choose XFCN value to match crystal frequency.
RC MODE (Circuit from Figure 11.1, Option 2; XOSCMD = 10x)
Choose XFCN value to match frequency range:
f = 1.23(103) / (R x C), where
f = frequency of oscillation in MHz
C = capacitor value in pF
R = Pull-up resistor value in kΩ
C MODE (Circuit from Figure 11.1, Option 3; XOSCMD = 10x)
Choose K Factor (KF) for the oscillation frequency desired:
f = KF / (C x VDD), where
f = frequency of oscillation in MHz
C = capacitor value the XTAL2 pin in pF
VDD = Power Supply on MCU in volts
100
Rev. 2.9
C (XOSCMD = 10x)
K Factor = 0.87
K Factor = 2.6
K Factor = 7.7
K Factor = 22
K Factor = 65
K Factor = 180
K Factor = 664
K Factor = 1590
C8051F300/1/2/3/4/5
11.4. External Crystal Example
If a crystal or ceramic resonator is used as an external oscillator source for the MCU, the circuit should be
configured as shown in Figure 11.1, Option 1. The External Oscillator Frequency Control value (XFCN)
should be chosen from the Crystal column of the table in SFR Definition 11.3 (OSCXCN register). For
example, an 11.0592 MHz crystal requires an XFCN setting of 111b.
When the crystal oscillator is first enabled, the oscillator amplitude detection circuit requires a settling time
to achieve proper bias. Introducing a delay of 1 ms between enabling the oscillator and checking the
XTLVLD bit will prevent a premature switch to the external oscillator as the system clock. Switching to the
external oscillator before the crystal oscillator has stabilized can result in unpredictable behavior. The recommended procedure is:
Step 1.
Step 2.
Step 3.
Step 4.
Step 5.
Step 6.
Force the XTAL1 and XTAL2 pins low by writing 0’s to the port latch.
Configure XTAL1 and XTAL2 as analog inputs.
Enable the external oscillator.
Wait at least 1 ms.
Poll for XTLVLD => ‘1’.
Switch the system clock to the external oscillator.
Note: Tuning-fork crystals may require additional settling time before XTLVLD returns a valid
result.
The capacitors shown in the external crystal configuration provide the load capacitance required by the
crystal for correct oscillation. These capacitors are “in series” as seen by the crystal and “in parallel” with
the stray capacitance of the XTAL1 and XTAL2 pins.
Note: The load capacitance depends upon the crystal and the manufacturer. Please refer to the
crystal data sheet when completing these calculations.
For example, a tuning-fork crystal of 32.768 kHz with a recommended load capacitance of 12.5 pF should
use the configuration shown in Figure 12.1, Option 1. The total value of the capacitors and the stray capacitance of the XTAL pins should equal 25 pF. With a stray capacitance of 3 pF per pin, the 22 pF capacitors
yield an equivalent capacitance of 12.5 pF across the crystal, as shown in Figure 11.2.
22 pF
XTAL1
32.768 kHz
10 MΩ
XTAL2
22 pF
Figure 11.2. 32.768 kHz External Crystal Example
Rev. 2.9
101
C8051F300/1/2/3/4/5
11.5. External RC Example
If an RC network is used as an external oscillator source for the MCU, the circuit should be configured as
shown in Figure 11.1, Option 2. The capacitor should be no greater than 100 pF; however for very small
capacitors, the total capacitance may be dominated by parasitic capacitance in the PCB layout. To determine the required External Oscillator Frequency Control value (XFCN) in the OSCXCN Register, first
select the RC network value to produce the desired frequency of oscillation. If the frequency desired is
100 kHz, let R = 246 kΩ and C = 50 pF:
f = 1.23( 103 ) / RC = 1.23 ( 103 ) / [ 246 x 50 ] = 0.1 MHz = 100 kHz
Referring to the table in SFR Definition 11.3, the required XFCN setting is 010b.
11.6. External Capacitor Example
If a capacitor is used as an external oscillator for the MCU, the circuit should be configured as shown in
Figure 11.1, Option 3. The capacitor should be no greater than 100 pF; however for very small capacitors,
the total capacitance may be dominated by parasitic capacitance in the PCB layout. To determine the
required External Oscillator Frequency Control value (XFCN) in the OSCXCN Register, select the capacitor to be used and find the frequency of oscillation from the equations below. Assume VDD = 3.0 V and
f = 150 kHz:
f = KF / (C x VDD)
0.150 MHz = KF / (C x 3.0)
Since the frequency of roughly 150 kHz is desired, select the K Factor from the table in SFR Definition 11.3
as KF = 22:
0.150 MHz = 22 / (C x 3.0)
C x 3.0 = 22 / 0.150 MHz
C = 146.6 / 3.0 pF = 48.8 pF
Therefore, the XFCN value to use in this example is 011b and C = 50 pF.
102
Rev. 2.9
C8051F300/1/2/3/4/5
12. Port Input/Output
Digital and analog resources are available through a byte-wide digital I/O Port, Port0. Each of the Port pins
can be defined as general-purpose I/O (GPIO), analog input, or assigned to one of the internal digital
resources as shown in Figure 12.3. The designer has complete control over which functions are assigned,
limited only by the number of physical I/O pins. This resource assignment flexibility is achieved through the
use of a Priority Crossbar Decoder. Note that the state of a Port I/O pin can always be read in the corresponding Port latch, regardless of the Crossbar settings.
The Crossbar assigns the selected internal digital resources to the I/O pins based on the Priority Decoder
(Figure 12.3 and Figure 12.4). The registers XBR0, XBR1, and XBR2, defined in SFR Definition 12.1, SFR
Definition 12.2, and SFR Definition 12.3 are used to select internal digital functions.
All Port I/Os are 5 V tolerant (refer to Figure 12.2 for the Port cell circuit). The Port I/O cells are configured
as either push-pull or open-drain in the Port0 Output Mode register (P0MDOUT). Complete Electrical
Specifications for Port I/O are given in Table 12.1 on page 110.
XBR0, XBR1,
XBR2 Registers
P0MDOUT,
P0MDIN Registers
Priority
Decoder
Highest
Priority
UART
(Internal Digital Signals)
SMBus
CP0
Outputs
2
2
Digital
Crossbar
2
SYSCLK
PCA
T0, T1
P0.0
P0
I/O
Cells
8
P0.7
4
2
8
Lowest
Priority
Port Latch
P0
(P0.0-P0.7)
Figure 12.1. Port I/O Functional Block Diagram
/WEAK-PULLUP
VDD
PUSH-PULL
/PORT-OUTENABLE
VDD
(WEAK)
PORT
PAD
PORT-OUTPUT
GND
Analog Select
ANALOG INPUT
PORT-INPUT
Figure 12.2. Port I/O Cell Block Diagram
Rev. 2.9
103
C8051F300/1/2/3/4/5
12.1. Priority Crossbar Decoder
The Priority Crossbar Decoder (Figure 12.3) assigns a priority to each I/O function, starting at the top with
UART0. When a digital resource is selected, the least significant unassigned Port pin is assigned to that
resource (excluding UART0, which is always at pins 4 and 5). If a Port pin is assigned, the Crossbar skips
that pin when assigning the next selected resource. Additionally, the Crossbar will skip Port pins whose
associated bits in the XBR0 register are set. The XBR0 register allows software to skip Port pins that are to
be used for analog input or GPIO.
Important Note on Crossbar Configuration: If a Port pin is claimed by a peripheral without use of the
Crossbar, its corresponding XBR0 bit should be set. This applies to P0.0 if VREF is enabled, P0.3 and/or
P0.2 if the external oscillator circuit is enabled, P0.6 if the ADC is configured to use the external conversion
start signal (CNVSTR), and any selected ADC or Comparator inputs. The Crossbar skips selected pins as
if they were already assigned, and moves to the next unassigned pin. Figure 12.3 shows the Crossbar
Decoder priority with no Port pins skipped (XBR0 = 0x00); Figure 12.4 shows the Crossbar Decoder priority with pins 6 and 2 skipped (XBR0 = 0x44).
P0
SF Signals VREF
PIN I/O
0
1
x1
2
x2
3
4
5
0
0
0
0
0
CNVSTR
6
7
TX0
RX0
Signals Unavailable
SDA
SCL
CP0
CP0A
SYSCLK
CEX0
CEX1
CEX2
ECI
T0
T1
0
0
0
XBR0[0:7]
Port pin potentially available to peripheral
SF Signals Special Function Signals are not assigned by the crossbar.
When these signals are enabled, the CrossBar must be
manually configured to skip their corresponding port pins.
Note: x1 refers to the XTAL1 signal; x2 refers to the XTAL2
signal.
Figure 12.3. Crossbar Priority Decoder with XBR0 = 0x00
104
Rev. 2.9
C8051F300/1/2/3/4/5
P0
SF Signals VREF
0
PIN I/O
1
x1
2
x2
3
4
5
0
1
0
0
0
CNVSTR
6
7
Signals Unavailable
TX0
RX0
SDA
SCL
CP0
CP0A
SYSCLK
CEX0
CEX1
CEX2
ECI
T0
T1
0
1
0
XBR0[0:7]
Port pin potentially available to peripheral
Port pin skipped by CrossBar
SF Signals
Special Function Signals are not assigned by the crossbar. When
these signals are enabled, the CrossBar must be manually
configured to skip their corresponding port pins. Note: x1 refers to
the XTAL1 signal; x2 refers to the XTAL2 signal.
Figure 12.4. Crossbar Priority Decoder with XBR0 = 0x44
Registers XBR1 and XBR2 are used to assign the digital I/O resources to the physical I/O Port pins. Note
that when the SMBus is selected, the Crossbar assigns both pins associated with the SMBus (SDA and
SCL). Either or both of the UART signals may be selected by the Crossbar. UART0 pin assignments are
fixed for bootloading purposes: when UART TX0 is selected, it is always assigned to P0.4; when UART
RX0 is selected, it is always assigned to P0.5. Standard Port I/Os appear contiguously after the prioritized
functions have been assigned. For example, if assigned functions that take the first 3 Port I/O (P0.[2:0]), 5
Port I/O are left for analog or GPIO use.
Rev. 2.9
105
C8051F300/1/2/3/4/5
12.2. Port I/O Initialization
Port I/O initialization consists of the following steps:
Step 1. Select the input mode (analog or digital) for all Port pins, using the Port0 Input Mode
register (P0MDIN).
Step 2. Select the output mode (open-drain or push-pull) for all Port pins, using the Port0 Output
Mode register (P0MDOUT).
Step 3. Set XBR0 to skip any pins selected as analog inputs or special functions.
Step 4. Assign Port pins to desired peripherals.
Step 5. Enable the Crossbar.
All Port pins must be configured as either analog or digital inputs. Any pins to be used as Comparator or
ADC inputs should be configured as an analog inputs. When a pin is configured as an analog input, its
weak pull-up, digital driver, and digital receiver is disabled. This process saves power and reduces noise
on the analog input. Pins configured as digital inputs may still be used by analog peripherals; however this
practice is not recommended.
Additionally, all analog input pins should be configured to be skipped by the Crossbar (accomplished by
setting the associated bits in XBR0). Port input mode is set in the P0MDIN register, where a ‘1’ indicates a
digital input, and a ‘0’ indicates an analog input. All pins default to digital inputs on reset. See SFR Definition 12.5 for the P0MDIN register details.
The output driver characteristics of the I/O pins are defined using the Port0 Output Mode register P0MDOUT (see SFR Definition 12.6). Each Port Output driver can be configured as either open drain or pushpull. This selection is required even for the digital resources selected in the XBRn registers, and is not
automatic. The only exception to this is the SMBus (SDA, SCL) pins, which are configured as open-drain
regardless of the P0MDOUT settings. When the WEAKPUD bit in XBR2 is ‘0’, a weak pull-up is enabled
for all Port I/O configured as open-drain. WEAKPUD does not affect the push-pull Port I/O. Furthermore,
the weak pull-up is turned off on an open-drain output that is driving a ‘0’ to avoid unnecessary power dissipation.
Registers XBR0, XBR1 and XBR2 must be loaded with the appropriate values to select the digital I/O functions required by the design. Setting the XBARE bit in XBR2 to ‘1’ enables the Crossbar. Until the Crossbar
is enabled, the external pins remain as standard digital inputs (output drivers disabled) regardless of the
XBRn Register settings. For given XBRn Register settings, one can determine the I/O pin-out using the
Priority Decode Table; as an alternative, the Configuration Wizard utility of the Silicon Labs IDE software
will determine the Port I/O pin assignments based on the XBRn Register settings.
106
Rev. 2.9
C8051F300/1/2/3/4/5
SFR Definition 12.1. XBR0: Port I/O Crossbar Register 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
—
XSKP6
XSKP5
XSKP4
XSKP3
XSKP2
XSKP1
XSKP0
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0xE1
Bit7:
UNUSED. Read = 0b; Write = don’t care.
Bits6–0: XSKP[6:0]: Crossbar Skip Enable Bits
These bits select Port pins to be skipped by the Crossbar Decoder. Port pins used as analog inputs (for ADC or Comparator) or used as special functions (VREF input, external oscillator circuit, CNVSTR input) should be skipped by the Crossbar.
0: Corresponding P0.n pin is not skipped by the Crossbar.
1: Corresponding P0.n pin is skipped by the Crossbar.
SFR Definition 12.2. XBR1: Port I/O Crossbar Register 1
R/W
R/W
PCA0ME
Bit7
Bit6
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
CP0AOEN CP0OEN SYSCKE SMB0OEN URX0EN UTX0EN 00000000
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0xE2
Bits7–6: PCA0ME: PCA Module I/0 Enable Bits
00: All PCA I/O unavailable at Port pins.
01: CEX0 routed to Port pin.
10: CEX0, CEX1 routed to Port pins.
11: CEX0, CEX1, CEX2 routed to Port pins.
Bit5:
CP0AOEN: Comparator0 Asynchronous Output Enable
0: Asynchronous CP0 unavailable at Port pin.
1: Asynchronous CP0 routed to Port pin.
Bit4:
CP0OEN: Comparator0 Output Enable
0: CP0 unavailable at Port pin.
1: CP0 routed to Port pin.
Bit3:
SYSCKE: /SYSCLK Output Enable
0: /SYSCLK unavailable at Port pin.
1: /SYSCLK output routed to Port pin.
Bit2:
SMB0OEN: SMBus I/O Enable
0: SMBus I/O unavailable at Port pins.
1: SDA, SCL routed to Port pins.
Bit1:
URX0EN: UART RX Enable
0: UART RX0 unavailable at Port pin.
1: UART RX0 routed to Port pin P0.5.
Bit0:
UTX0EN: UART TX Output Enable
0: UART TX0 unavailable at Port pin.
1: UART TX0 routed to Port pin P0.4.
Rev. 2.9
107
C8051F300/1/2/3/4/5
SFR Definition 12.3. XBR2: Port I/O Crossbar Register 2
R/W
R/W
R/W
WEAKPUD
XBARE
—
Bit7
Bit6
Bit5
R/W
R/W
R/W
R/W
R/W
Reset Value
—
—
T1E
T0E
ECIE
00000000
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0xE3
Bit7:
WEAKPUD: Port I/O Weak Pull-up Disable.
0: Weak Pull-ups enabled (except for Ports whose I/O are configured as push-pull).
1: Weak Pull-ups disabled.
Bit6:
XBARE: Crossbar Enable.
0: Crossbar disabled.
1: Crossbar enabled.
Bits5–3: UNUSED: Read = 000b. Write = don’t care.
Bit2:
T1E: T1 Enable.
0: T1 unavailable at Port pin.
1: T1 routed to Port pin.
Bit1:
T0E: T0 Enable.
0: T0 unavailable at Port pin.
1: T0 routed to Port pin.
Bit0:
ECIE: PCA0 Counter Input Enable.
0: ECI unavailable at Port pin.
1: ECI routed to Port pin.
12.3. General Purpose Port I/O
Port pins that remain unassigned by the Crossbar and are not used by analog peripherals can be used for
general purpose I/O. Port0 is accessed through a corresponding special function register (SFR) that is
both byte addressable and bit addressable. When writing to a Port, the value written to the SFR is latched
to maintain the output data value at each pin. When reading, the logic levels of the Port's input pins are
returned regardless of the XBRn settings (i.e., even when the pin is assigned to another signal by the
Crossbar, the Port register can always read its corresponding Port I/O pin). The exception to this is the
execution of the read-modify-write instructions. The read-modify-write instructions when operating on a
Port SFR are the following: ANL, ORL, XRL, JBC, CPL, INC, DEC, DJNZ and MOV, CLR or SET, when the
destination is an individual bit in a Port SFR. For these instructions, the value of the register (not the pin) is
read, modified, and written back to the SFR.
108
Rev. 2.9
C8051F300/1/2/3/4/5
SFR Definition 12.4. P0: Port0 Register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
P0.7
P0.6
P0.5
P0.4
P0.3
P0.2
P0.1
P0.0
11111111
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
(bit addressable)
Reset Value
0x80
Bits7–0: P0.[7:0]
Write - Output appears on I/O pins per XBR0, XBR1, and XBR2 Registers
0: Logic Low Output.
1: Logic High Output (open-drain if corresponding P0MDOUT.n bit = 0)
Read - Always reads ‘1’ if selected as analog input in register P0MDIN. Directly reads Port
pin when configured as digital input.
0: P0.n pin is logic low.
1: P0.n pin is logic high.
SFR Definition 12.5. P0MDIN: Port0 Input Mode
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
11111111
0xF1
Bits7–0: Input Configuration Bits for P0.7-P0.0 (respectively)
Port pins configured as analog inputs have their weak pull-up, digital driver, and digital
receiver disabled.
0: Corresponding P0.n pin is configured as an analog input.
1: Corresponding P0.n pin is configured as a digital input.
Rev. 2.9
109
C8051F300/1/2/3/4/5
SFR Definition 12.6. P0MDOUT: Port0 Output Mode
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0xA4
Bits7–0: Output Configuration Bits for P0.7–P0.0 (respectively): ignored if corresponding bit in register P0MDIN is logic 0.
0: Corresponding P0.n Output is open-drain.
1: Corresponding P0.n Output is push-pull.
(Note: When SDA and SCL appear on any of the Port I/O, each are open-drain regardless
of the value of P0MDOUT).
Table 12.1. Port I/O DC Electrical Characteristics
VDD = 2.7 to 3.6 V, –40 to +85 °C unless otherwise specified.
Parameters
Output High Voltage
Output Low Voltage
Input High Voltage
Input Low Voltage
Input Leakage Current
110
Conditions
IOH = –3 mA, Port I/O push-pull
IOH = –10 µA, Port I/O push-pull
IOH = –10 mA, Port I/O push-pull
IOL = 8.5 mA
IOL = 10 µA
IOL = 25 mA
Weak Pull-up Off
Weak Pull-up On, VIN = 0 V
Rev. 2.9
Min
VDD – 0.7
VDD – 0.1
Typ
Max
—
Units
V
V
VDD-0.8
—
—
—
—
—
1.0
0.6
0.1
—
2.0
—
—
—
—
—
0.8
±1
40
25
V
V
µA
C8051F300/1/2/3/4/5
13. SMBus
The SMBus I/O interface is a two-wire bidirectional serial bus. The SMBus is compliant with the System
Management Bus Specification, version 1.1, and compatible with the I2C serial bus. Reads and writes to
the interface by the system controller are byte oriented with the SMBus interface autonomously controlling
the serial transfer of the data. Data can be transferred at up to 1/20th of the system clock operating as
master or slave (this can be faster than allowed by the SMBus specification, depending on the system
clock used). A method of extending the clock-low duration is available to accommodate devices with different speed capabilities on the same bus.
The SMBus interface may operate as a master and/or slave, and may function on a bus with multiple masters. The SMBus provides control of SDA (serial data), SCL (serial clock) generation and synchronization,
arbitration logic, and START/STOP control and generation. Three SFRs are associated with the SMBus:
SMB0CF configures the SMBus; SMB0CN controls the status of the SMBus; and SMB0DAT is the data
register, used for both transmitting and receiving SMBus data and slave addresses.
SMB0CN
MT S S A A A S
A X T T CRC I
SMAOK B K
TO
R L
E D
QO
R E
S
T
SMB0CF
E I B E S S
N N U XMM
S HS T B B
M Y H T F
B
OOT
L E E
D
B
A
U
D
1
B
A
U
D
0
00
T0 Overflow
01
T1 Overflow
10
TMR2H Overflow
11
TMR2L Overflow
SMBUS CONTROL LOGIC
Interrupt
Request
Arbitration
SCL Synchronization
SCL Generation (Master Mode)
SDA Control
Data Path
IRQ Generation
Control
SCL
FILTER
SCL
Control
N
C
R
O
S
S
B
A
R
SDA
Control
SMB0DAT
7 6 5 4 3 2 1 0
Port I/O
SDA
FILTER
N
Figure 13.1. SMBus Block Diagram
Rev. 2.9
111
C8051F300/1/2/3/4/5
13.1. Supporting Documents
It is assumed the reader is familiar with or has access to the following supporting documents:
1. The I2C-Bus and How to Use It (including specifications), Philips Semiconductor.
2. The I2C-Bus Specification – Version 2.0, Philips Semiconductor.
3. System Management Bus Specification – Version 1.1, SBS Implementers Forum.
13.2. SMBus Configuration
Figure 13.2 shows a typical SMBus configuration. The SMBus specification allows any recessive voltage
between 3.0 and 5.0 V; different devices on the bus may operate at different voltage levels. The bidirectional SCL (serial clock) and SDA (serial data) lines must be connected to a positive power supply voltage
through a pull-up resistor or similar circuit. Every device connected to the bus must have an open-drain or
open-collector output for both the SCL and SDA lines, so that both are pulled high (recessive state) when
the bus is free. The maximum number of devices on the bus is limited only by the requirement that the rise
and fall times on the bus not exceed 300 ns and 1000 ns, respectively.
VDD = 5V
VDD = 3V
VDD = 5V
VDD = 3V
Master
Device
Slave
Device 1
Slave
Device 2
SDA
SCL
Figure 13.2. Typical SMBus Configuration
13.3. SMBus Operation
Two types of data transfers are possible: data transfers from a master transmitter to an addressed slave
receiver (WRITE), and data transfers from an addressed slave transmitter to a master receiver (READ).
The master device initiates both types of data transfers and provides the serial clock pulses on SCL. The
SMBus interface may operate as a master or a slave, and multiple master devices on the same bus are
supported. If two or more masters attempt to initiate a data transfer simultaneously, an arbitration scheme
is employed with a single master always winning the arbitration. Note that it is not necessary to specify one
device as the Master in a system; any device that transmits a START and a slave address becomes the
master for the duration of that transfer.
A typical SMBus transaction consists of a START condition followed by an address byte (Bits7–1: 7-bit
slave address; Bit0: R/W direction bit), one or more bytes of data, and a STOP condition. Each byte that is
received (by a master or slave) must be acknowledged (ACK) with a low SDA during a high SCL (see
Figure 13.3). If the receiving device does not ACK, the transmitting device will read a NACK (not acknowledge), which is a high SDA during a high SCL.
112
Rev. 2.9
C8051F300/1/2/3/4/5
The direction bit (R/W) occupies the least significant bit position of the address byte. The direction bit is set
to logic 1 to indicate a "READ" operation and cleared to logic 0 to indicate a "WRITE" operation.
All transactions are initiated by a master, with one or more addressed slave devices as the target. The
master generates the START condition and then transmits the slave address and direction bit. If the transaction is a WRITE operation from the master to the slave, the master transmits the data a byte at a time
waiting for an ACK from the slave at the end of each byte. For READ operations, the slave transmits the
data waiting for an ACK from the master at the end of each byte. At the end of the data transfer, the master
generates a STOP condition to terminate the transaction and free the bus. Figure 13.3 illustrates a typical
SMBus transaction.
SCL
SDA
SLA6
START
SLA5-0
Slave Address + R/W
R/W
D7
ACK
D6-0
Data Byte
NACK
STOP
Figure 13.3. SMBus Transaction
13.3.1. Arbitration
A master may start a transfer only if the bus is free. The bus is free after a STOP condition or after the SCL
and SDA lines remain high for a specified time (see Section “13.3.4. SCL High (SMBus Free) Timeout”
on page 114). In the event that two or more devices attempt to begin a transfer at the same time, an arbitration scheme is employed to force one master to give up the bus. The master devices continue transmitting until one attempts a HIGH while the other transmits a LOW. Since the bus is open-drain, the bus will
be pulled LOW. The master attempting the HIGH will detect a LOW SDA and lose the arbitration. The winning master continues its transmission without interruption; the losing master becomes a slave and
receives the rest of the transfer if addressed. This arbitration scheme is non-destructive: one device
always wins, and no data is lost.
Rev. 2.9
113
C8051F300/1/2/3/4/5
13.3.2. Clock Low Extension
SMBus provides a clock synchronization mechanism, similar to I2C, which allows devices with different
speed capabilities to coexist on the bus. A clock-low extension is used during a transfer in order to allow
slower slave devices to communicate with faster masters. The slave may temporarily hold the SCL line
LOW to extend the clock low period, effectively decreasing the serial clock frequency.
13.3.3. SCL Low Timeout
If the SCL line is held low by a slave device on the bus, no further communication is possible. Furthermore,
the master cannot force the SCL line high to correct the error condition. To solve this problem, the SMBus
protocol specifies that devices participating in a transfer must detect any clock cycle held low longer than
25 ms as a “timeout” condition. Devices that have detected the timeout condition must reset the communication no later than 10 ms after detecting the timeout condition.
When the SMBTOE bit in SMB0CF is set, Timer 2 is used to detect SCL low timeouts. Timer 2 is forced to
reload when SCL is high, and allowed to count when SCL is low. With Timer 2 enabled and configured to
overflow after 25 ms (and SMBTOE set), the Timer 2 interrupt service routine can be used to reset (disable
and reenable) the SMBus in the event of an SCL low timeout. Timer 2 configuration details can be found in
Section “15.2. Timer 2” on page 151.
13.3.4. SCL High (SMBus Free) Timeout
The SMBus specification stipulates that if the SCL and SDA lines remain high for more that 50 µs, the bus
is designated as free. When the SMBFTE bit in SMB0CF is set, the bus will be considered free if SCL and
SDA remain high for more than 10 SMBus clock source periods. If the SMBus is waiting to generate a
Master START, the START will be generated following this timeout. Note that a clock source is required for
free timeout detection, even in a slave-only implementation.
114
Rev. 2.9
C8051F300/1/2/3/4/5
13.4. Using the SMBus
The SMBus can operate in both Master and Slave modes. The interface provides timing and shifting control for serial transfers; higher level protocol is determined by user software. The SMBus interface provides
the following application-independent features:
•
•
•
•
•
•
•
Byte-wise serial data transfers
Clock signal generation on SCL (Master Mode only) and SDA data synchronization
Timeout/bus error recognition, as defined by the SMB0CF configuration register
START/STOP timing, detection, and generation
Bus arbitration
Interrupt generation
Status information
SMBus interrupts are generated for each data byte or slave address that is transferred. When transmitting,
this interrupt is generated after the ACK cycle so that software may read the received ACK value; when
receiving data, this interrupt is generated before the ACK cycle so that software may define the outgoing
ACK value. See Section “13.5. SMBus Transfer Modes” on page 123 for more details on transmission
sequences.
Interrupts are also generated to indicate the beginning of a transfer when a master (START generated), or
the end of a transfer when a slave (STOP detected). Software should read the SMB0CN (SMBus Control
register) to find the cause of the SMBus interrupt. The SMB0CN register is described in Section
“13.4.2. SMB0CN Control Register” on page 119; Table 13.4 provides a quick SMB0CN decoding reference.
SMBus configuration options include:
•
•
•
•
Timeout detection (SCL Low Timeout and/or Bus Free Timeout)
SDA setup and hold time extensions
Slave event enable/disable
Clock source selection
These options are selected in the SMB0CF register, as described in Section “13.4.1. SMBus Configuration Register” on page 116.
Rev. 2.9
115
C8051F300/1/2/3/4/5
13.4.1. SMBus Configuration Register
The SMBus Configuration register (SMB0CF) is used to enable the SMBus Master and/or Slave modes,
select the SMBus clock source, and select the SMBus timing and timeout options. When the ENSMB bit is
set, the SMBus is enabled for all master and slave events. Slave events may be disabled by setting the
INH bit. With slave events inhibited, the SMBus interface will still monitor the SCL and SDA pins; however,
the interface will NACK all received addresses and will not generate any slave interrupts. When the INH bit
is set, all slave events will be inhibited following the next START (interrupts will continue for the duration of
the current transfer).
Table 13.1. SMBus Clock Source Selection
SMBCS1
SMBCS0
SMBus Clock Source
0
0
Timer 0 Overflow
0
1
Timer 1 Overflow
1
0
Timer 2 High Byte Overflow
1
1
Timer 2 Low Byte Overflow
The SMBCS1-0 bits select the SMBus clock source, which is used only when operating as a master or
when the Free Timeout detection is enabled. When operating as a master, overflows from the selected
source determine the absolute minimum SCL low and high times as defined in Equation 13.1. Note that the
selected clock source may be shared by other peripherals so long as the timer is left running at all times.
For example, Timer 1 overflows may generate the SMBus and UART baud rates simultaneously. Timer
configuration is covered in Section “15. Timers” on page 143.
1
T HighMin = T LowMin = ---------------------------------------------f ClockSourceOverflow
Equation 13.1. Minimum SCL High and Low Times
The selected clock source should be configured to establish the minimum SCL High and Low times as per
Equation 13.1. When the interface is operating as a master (and SCL is not driven or extended by any
other devices on the bus), the typical SMBus bit rate is approximated by Equation 13.2.
f ClockSourceOverflow
BitRate = ---------------------------------------------3
Equation 13.2. Typical SMBus Bit Rate
Figure 13.4 shows the typical SCL generation described by Equation 13.2. Notice that THIGH is typically
twice as large as TLOW. The actual SCL output may vary due to other devices on the bus (SCL may be
extended low by slower slave devices, or driven low by contending master devices). The bit rate when
operating as a master will never exceed the limits defined by equation Equation 13.1.
116
Rev. 2.9
C8051F300/1/2/3/4/5
Timer Source
Overflows
SCL
TLow
SCL High Timeout
THigh
Figure 13.4. Typical SMBus SCL Generation
Setting the EXTHOLD bit extends the minimum setup and hold times for the SDA line. The minimum SDA
setup time defines the absolute minimum time that SDA is stable before SCL transitions from low-to-high.
The minimum SDA hold time defines the absolute minimum time that the current SDA value remains stable
after SCL transitions from high-to-low. EXTHOLD should be set so that the minimum setup and hold times
meet the SMBus Specification requirements of 250 ns and 300 ns, respectively. Table 13.2 shows the minimum setup and hold times for the two EXTHOLD settings. Setup and hold time extensions are typically
necessary when SYSCLK is above 10 MHz.
Table 13.2. Minimum SDA Setup and Hold Times
EXTHOLD
Minimum SDA Setup Time
Minimum SDA Hold Time
0
Tlow – 4 system clocks
OR
1 system clock + s/w delay*
3 system clocks
1
11 system clocks
12 system clocks
*Note: Setup Time for ACK bit transmissions and the MSB of all data transfers. The s/w
delay occurs between the time SMB0DAT or ACK is written and when SI is cleared.
Note that if SI is cleared in the same write that defines the outgoing ACK value, s/w
delay is zero.
With the SMBTOE bit set, Timer 2 should be configured to overflow after 25 ms in order to detect SCL low
timeouts (see Section “13.3.3. SCL Low Timeout” on page 114). The SMBus interface will force Timer 2
to reload while SCL is high, and allow Timer 2 to count when SCL is low. The Timer 2 interrupt service routine should be used to reset SMBus communication by disabling and reenabling the SMBus. Timer 2 configuration is described in Section “15.2. Timer 2” on page 151.
SMBus Free Timeout detection can be enabled by setting the SMBFTE bit. When this bit is set, the bus will
be considered free if SDA and SCL remain high for more than 10 SMBus clock source periods (see
Figure 13.4). When a Free Timeout is detected, the interface will respond as if a STOP was detected (an
interrupt will be generated, and STO will be set).
Rev. 2.9
117
C8051F300/1/2/3/4/5
SFR Definition 13.1. SMB0CF: SMBus Clock/Configuration
R/W
R/W
R
ENSMB
INH
BUSY
Bit7
Bit6
Bit5
R/W
R/W
R/W
R/W
R/W
Reset Value
EXTHOLD SMBTOE SMBFTE SMBCS1 SMBCS0 00000000
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0xC1
Bit7:
ENSMB: SMBus Enable.
This bit enables/disables the SMBus interface. When enabled, the interface constantly monitors the SDA and SCL pins.
0: SMBus interface disabled.
1: SMBus interface enabled.
Bit6:
INH: SMBus Slave Inhibit.
When this bit is set to logic 1, the SMBus does not generate an interrupt when slave events
occur. This effectively removes the SMBus slave from the bus. Master Mode interrupts are
not affected.
0: SMBus Slave Mode enabled.
1: SMBus Slave Mode inhibited.
Bit5:
BUSY: SMBus Busy Indicator.
This bit is set to logic 1 by hardware when a transfer is in progress. It is cleared to logic 0
when a STOP or free timeout is sensed.
Bit4:
EXTHOLD: SMBus Setup and Hold Time Extension Enable.
This bit controls the SDA setup and hold times according to Table 13.2.
0: SDA Extended Setup and Hold Times disabled.
1: SDA Extended Setup and Hold Times enabled.
Bit3:
SMBTOE: SMBus SCL Timeout Detection Enable.
This bit enables SCL low timeout detection. If set to logic 1, the SMBus forces Timer 2 to
reload while SCL is high and allows Timer 2 to count when SCL goes low. If Timer 2 is configured in split mode (T2SPLIT is set), only the high byte of Timer 2 is held in reload while
SCL is high. Timer 2 should be programmed to generate interrupts at 25 ms, and the Timer
2 interrupt service routine should reset SMBus communication.
Bit2:
SMBFTE: SMBus Free Timeout Detection Enable.
When this bit is set to logic 1, the bus will be considered free if SCL and SDA remain high for
more than 10 SMBus clock source periods.
Bits1–0: SMBCS1-SMBCS0: SMBus Clock Source Selection.
These two bits select the SMBus clock source, which is used to generate the SMBus bit
rate. The selected device should be configured according to Equation 13.1.
118
SMBCS1
SMBCS0
SMBus Clock Source
0
0
Timer 0 Overflow
0
1
Timer 1 Overflow
1
0
Timer 2 High Byte Overflow
1
1
Timer 2 Low Byte Overflow
Rev. 2.9
C8051F300/1/2/3/4/5
13.4.2. SMB0CN Control Register
SMB0CN is used to control the interface and to provide status information (see SFR Definition 13.2). The
higher four bits of SMB0CN (MASTER, TXMODE, STA, and STO) form a status vector that can be used to
jump to service routines. MASTER and TXMODE indicate the master/slave state and transmit/receive
modes, respectively.
The STA bit indicates that a START has been detected or generated since the last SMBus interrupt. When
set to ‘1’, the STA bit will cause the SMBus to enter Master mode and generate a START when the bus
becomes free. STA is not cleared by hardware after the START is generated; it must be cleared by software.
As a master, writing the STO bit will cause the hardware to generate a STOP condition and end the current
transfer after the next ACK cycle. STO is cleared by hardware after the STOP condition is generated. As a
slave, STO indicates that a STOP condition has been detected since the last SMBus interrupt. STO is also
used in slave mode to manage the transition from slave receiver to slave transmitter; see Section 13.5.4
for details on this procedure.
If STO and STA are both set to ‘1’ (while in Master Mode), a STOP followed by a START will be generated.
As a receiver, writing the ACK bit defines the outgoing ACK value; as a transmitter, reading the ACK bit
indicates the value received on the last ACK cycle. ACKRQ is set each time a byte is received, indicating
that an outgoing ACK value is needed. When ACKRQ is set, software should write the desired outgoing
value to the ACK bit before clearing SI. A NACK will be generated if software does not write the ACK bit
before clearing SI. SDA will reflect the defined ACK value immediately following a write to the ACK bit;
however SCL will remain low until SI is cleared. If a received slave address is not acknowledged, further
slave events will be ignored until the next START is detected.
The ARBLOST bit indicates that the interface has lost an arbitration. This may occur anytime the interface
is transmitting (master or slave). A lost arbitration while operating as a slave indicates a bus error condition. ARBLOST is cleared by hardware each time SI is cleared.
The SI bit (SMBus Interrupt Flag) is set at the beginning and end of each transfer, after each byte frame, or
when an arbitration is lost; see Table 13.3 for more details.
Important Note About the SI Bit: The SMBus interface is stalled while SI is set; thus SCL is held low, and
the bus is stalled until software clears SI.
Table 13.3 lists all sources for hardware changes to the SMB0CN bits. Refer to Table 13.4 for SMBus status decoding using the SMB0CN register.
Rev. 2.9
119
C8051F300/1/2/3/4/5
SFR Definition 13.2. SMB0CN: SMBus Control
R
R
MASTER TXMODE
Bit7
Bit6
R/W
R/W
STA
STO
Bit5
Bit4
R
R
ACKRQ ARBLOST
Bit3
Bit2
R/W
R/W
Reset Value
ACK
SI
00000000
Bit0
SFR Address:
Bit1
(bit addressable)
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
120
0xC0
MASTER: SMBus Master/Slave Indicator.
This read-only bit indicates when the SMBus is operating as a master.
0: SMBus operating in Slave Mode.
1: SMBus operating in Master Mode.
TXMODE: SMBus Transmit Mode Indicator.
This read-only bit indicates when the SMBus is operating as a transmitter.
0: SMBus in Receiver Mode.
1: SMBus in Transmitter Mode.
STA: SMBus Start Flag.
Write:
0: No Start generated.
1: When operating as a master, a START condition is transmitted if the bus is free (If the bus
is not free, the START is transmitted after a STOP is received or a free timeout is detected).
If STA is set by software as an active Master, a repeated START will be generated after the
next ACK cycle.
Read:
0: No Start or repeated Start detected.
1: Start or repeated Start detected.
STO: SMBus Stop Flag.
Write:
As a master, setting this bit to ‘1’ causes a STOP condition to be transmitted after the next
ACK cycle. STO is cleared to ‘0’ by hardware when the STOP is generated.
As a slave, software manages this bit when switching from Slave Receiver to Slave Transmitter mode. See Section 13.5.4 for details.
Read:
0: No Stop condition detected.
1: Stop condition detected (if in Slave Mode) or pending (if in Master Mode).
ACKRQ: SMBus Acknowledge Request.
This read-only bit is set to logic 1 when the SMBus has received a byte and needs the ACK
bit to be written with the correct ACK response value.
ARBLOST: SMBus Arbitration Lost Indicator.
This read-only bit is set to logic 1 when the SMBus loses arbitration while operating as a
transmitter. A lost arbitration while a slave indicates a bus error condition.
ACK: SMBus Acknowledge Flag.
This bit defines the outgoing ACK level and records incoming ACK levels. It should be written each time a byte is received (when ACKRQ=1), or read after each byte is transmitted.
0: A "not acknowledge" has been received (if in Transmitter Mode) OR will be transmitted (if
in Receiver Mode).
1: An "acknowledge" has been received (if in Transmitter Mode) OR will be transmitted (if in
Receiver Mode).
SI: SMBus Interrupt Flag.
This bit is set by hardware under the conditions listed in Table 13.3. SI must be cleared by
software. While SI is set, SCL is held low and the SMBus is stalled.
Rev. 2.9
C8051F300/1/2/3/4/5
Table 13.3. Sources for Hardware Changes to SMB0CN
Bit
MASTER
TXMODE
STA
STO
ACKRQ
ARBLOST
ACK
SI
Set by Hardware When:
Cleared by Hardware When:
• A START is generated.
• A STOP is generated.
• Arbitration is lost.
• START is generated.
• A START is detected.
• The SMBus interface enters transmitter mode • Arbitration is lost.
(after SMB0DAT is written before the start of
• SMB0DAT is not written before the
start of an SMBus frame.
an SMBus frame).
• A START followed by an address byte is
• Must be cleared by software.
received.
• A pending STOP is generated.
• A STOP is detected while addressed as a
slave.
• Arbitration is lost due to a detected STOP.
• After each ACK cycle.
• A byte has been received and an ACK
response value is needed.
• A repeated START is detected as a MASTER • Each time SI is cleared.
when STA is low (unwanted repeated START).
• SCL is sensed low while attempting to generate a STOP or repeated START condition.
• SDA is sensed low while transmitting a ‘1’
(excluding ACK bits).
• The incoming ACK value is low (ACKNOWL- • The incoming ACK value is high (NOT
EDGE).
ACKNOWLEDGE).
• Must be cleared by software.
• A START has been generated.
• Lost arbitration.
• A byte has been transmitted and an
ACK/NACK received.
• A byte has been received.
• A START or repeated START followed by a
slave address + R/W has been received.
• A STOP has been received.
Rev. 2.9
121
C8051F300/1/2/3/4/5
13.4.3. Data Register
The SMBus Data register SMB0DAT holds a byte of serial data to be transmitted or one that has just been
received. Software may safely read or write to the data register when the SI flag is set. Software should not
attempt to access the SMB0DAT register when the SMBus is enabled and the SI flag is cleared to logic 0,
as the interface may be in the process of shifting a byte of data into or out of the register.
Data in SMB0DAT is always shifted out MSB first. After a byte has been received, the first bit of received
data is located at the MSB of SMB0DAT. While data is being shifted out, data on the bus is simultaneously
being shifted in. SMB0DAT always contains the last data byte present on the bus. In the event of lost arbitration, the transition from master transmitter to slave receiver is made with the correct data or address in
SMB0DAT.
SFR Definition 13.3. SMB0DAT: SMBus Data
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0xC2
Bits7–0: SMB0DAT: SMBus Data.
The SMB0DAT register contains a byte of data to be transmitted on the SMBus serial interface or a byte that has just been received on the SMBus serial interface. The CPU can read
from or write to this register whenever the SI serial interrupt flag (SMB0CN.0) is set to logic
one. The serial data in the register remains stable as long as the SI flag is set. When the SI
flag is not set, the system may be in the process of shifting data in/out and the CPU should
not attempt to access this register.
122
Rev. 2.9
C8051F300/1/2/3/4/5
13.5. SMBus Transfer Modes
The SMBus interface may be configured to operate as master and/or slave. At any particular time, it will be
operating in one of the following four modes: Master Transmitter, Master Receiver, Slave Transmitter, or
Slave Receiver. The SMBus interface enters Master Mode any time a START is generated, and remains in
Master Mode until it loses arbitration or generates a STOP. An SMBus interrupt is generated at the end of
all SMBus byte frames; however, note that the interrupt is generated before the ACK cycle when operating
as a receiver, and after the ACK cycle when operating as a transmitter.
13.5.1. Master Transmitter Mode
Serial data is transmitted on SDA while the serial clock is output on SCL. The SMBus interface generates
the START condition and transmits the first byte containing the address of the target slave and the data
direction bit. In this case the data direction bit (R/W) will be logic 0 (WRITE). The master then transmits
one or more bytes of serial data. After each byte is transmitted, an acknowledge bit is generated by the
slave. The transfer is ended when the STO bit is set and a STOP is generated. Note that the interface will
switch to Master Receiver Mode if SMB0DAT is not written following a Master Transmitter interrupt.
Figure 13.5 shows a typical Master Transmitter sequence. Two transmit data bytes are shown, though any
number of bytes may be transmitted. Notice that the ‘data byte transferred’ interrupts occur after the ACK
cycle in this mode.
S
SLA
W
Interrupt
A
Interrupt
Data Byte
A
Data Byte
Interrupt
A
P
Interrupt
S = START
P = STOP
A = ACK
W = WRITE
SLA = Slave Address
Received by SMBus
Interface
Transmitted by
SMBus Interface
Figure 13.5. Typical Master Transmitter Sequence
Rev. 2.9
123
C8051F300/1/2/3/4/5
13.5.2. Master Receiver Mode
Serial data is received on SDA while the serial clock is output on SCL. The SMBus interface generates the
START condition and transmits the first byte containing the address of the target slave and the data direction bit. In this case the data direction bit (R/W) will be logic 1 (READ). Serial data is then received from the
slave on SDA while the SMBus outputs the serial clock. The slave transmits one or more bytes of serial
data. After each byte is received, ACKRQ is set to ‘1’ and an interrupt is generated. Software must write
the ACK bit (SMB0CN.1) to define the outgoing acknowledge value (Note: writing a ‘1’ to the ACK bit generates an ACK; writing a ‘0’ generates a NACK). Software should write a ‘0’ to the ACK bit after the last
byte is received, to transmit a NACK. The interface exits Master Receiver Mode after the STO bit is set and
a STOP is generated. Note that the interface will switch to Master Transmitter Mode if SMB0DAT is written
while an active Master Receiver. Figure 13.6 shows a typical Master Receiver sequence. Two received
data bytes are shown, though any number of bytes may be received. Notice that the ‘data byte transferred’
interrupts occur before the ACK cycle in this mode.
S
SLA
R
Interrupt
A
Interrupt
Data Byte
A
Interrupt
Data Byte
N
Interrupt
S = START
P = STOP
A = ACK
N = NACK
R = READ
SLA = Slave Address
Received by SMBus
Interface
Transmitted by
SMBus Interface
Figure 13.6. Typical Master Receiver Sequence
124
Rev. 2.9
P
C8051F300/1/2/3/4/5
13.5.3. Slave Receiver Mode
Serial data is received on SDA and the clock is received on SCL. When slave events are enabled (INH =
0), the interface enters Slave Receiver Mode when a START followed by a slave address and direction bit
(WRITE in this case) is received. Upon entering Slave Receiver Mode, an interrupt is generated and the
ACKRQ bit is set. Software responds to the received slave address with an ACK, or ignores the received
slave address with a NACK. If the received slave address is ignored, slave interrupts will be inhibited until
the next START is detected. If the received slave address is acknowledged, zero or more data bytes are
received. Software must write the ACK bit after each received byte to ACK or NACK the received byte. The
interface exits Slave Receiver Mode after receiving a STOP. Note that the interface will switch to Slave
Transmitter Mode if SMB0DAT is written while an active Slave Receiver; see Section 13.5.4 for details on
this procedure. Figure 13.7 shows a typical Slave Receiver sequence. Two received data bytes are shown,
though any number of bytes may be received. Notice that the ‘data byte transferred’ interrupts occur
before the ACK cycle in this mode.
Interrupt
S
SLA
W
A
Interrupt
Data Byte
A
Interrupt
Data Byte
A
P
Interrupt
S = START
P = STOP
A = ACK
R = READ
SLA = Slave Address
Received by SMBus
Interface
Transmitted by
SMBus Interface
Figure 13.7. Typical Slave Receiver Sequence
Rev. 2.9
125
C8051F300/1/2/3/4/5
13.5.4. Slave Transmitter Mode
Serial data is transmitted on SDA and the clock is received on SCL. When slave events are enabled (INH
= 0), the interface enters Slave Receiver Mode (to receive the slave address) when a START followed by a
slave address and direction bit (READ in this case) is received. Software responds to the received slave
address with an ACK, or ignores the received slave address with a NACK. If the received address is
ignored, slave interrupts will be inhibited until the next START is detected. If the received slave address is
acknowledged, software should write data to SMB0DAT to force the SMBus into Slave Transmitter Mode.
The switch from Slave Receiver to Slave Transmitter requires software management. Software should perform the steps outlined below only when a valid slave address is received (indicated by the label “RX-to-TX
Steps” in Figure 13.8).
Step 1.
Step 2.
Step 3.
Step 4.
Step 5.
Step 6.
Step 7.
Set ACK to ‘1’.
Write outgoing data to SMB0DAT.
Check SMB0DAT.7; if ‘1’, do not perform steps 4, 6 or 7.
Set STO to ‘1’.
Clear SI to ‘0’.
Poll for TXMODE => ‘1’.
Clear STO to ‘0’ (must be done before the next ACK cycle).
The interface enters Slave Transmitter Mode and transmits one or more bytes of data (the above steps are
only required before the first byte of the transfer). After each byte is transmitted, the master sends an
acknowledge bit; if the acknowledge bit is an ACK, SMB0DAT should be written with the next data byte. If
the acknowledge bit is a NACK, SMB0DAT should not be written to before SI is cleared (Note: an error
condition may be generated if SMB0DAT is written following a received NACK while in Slave Transmitter
Mode). The interface exits Slave Transmitter Mode after receiving a STOP. Note that the interface will
switch to Slave Receiver Mode if SMB0DAT is not written following a Slave Transmitter interrupt.
Figure 13.8 shows a typical Slave Transmitter sequence. Two transmitted data bytes are shown, though
any number of bytes may be transmitted. Notice that the ‘data byte transferred’ interrupts occur after the
ACK cycle in this mode.
Perform RX-to-TX
Steps Here
S
SLA
R
A
Interrupt
Interrupt
Data Byte
A
Data Byte
Interrupt
N
P
Interrupt
S = START
P = STOP
N = NACK
W = WRITE
SLA = Slave Address
Received by SMBus
Interface
Transmitted by
SMBus Interface
Figure 13.8. Typical Slave Transmitter Sequence
126
Rev. 2.9
C8051F300/1/2/3/4/5
13.6. SMBus Status Decoding
The current SMBus status can be easily decoded using the SMB0CN register. In the table below, STATUS
VECTOR refers to the four upper bits of SMB0CN: MASTER, TXMODE, STA, and STO. Note that the
shown response options are only the typical responses; application-specific procedures are allowed as
long as they conform with the SMBus specification. Highlighted responses are allowed but do not conform
to the SMBus specification.
Table 13.4. SMBus Status Decoding
1100
0
0
0
0
X A master START was generated. Load slave address + R/W
into SMB0DAT.
0 A master data or address byte
Set STA to restart transfer.
was transmitted; NACK received. Abort transfer.
Load next data byte into
1 A master data or address byte
was transmitted; ACK received. SMB0DAT
End transfer with STOP
End transfer with STOP and
start another transfer.
Send repeated START
Switch to Master Receiver
Mode (clear SI without writing new data to SMB0DAT).
Rev. 2.9
ACK
0
Values
Written
STO
ARBLOST
0
Typical Response Options
STA
ACKRQ
1110
Current SMbus State
ACK
Status
Vector
Master Transmitter
Mode
Values Read
0
0
X
1
0
0
0
1
0
X
X
X
0
1
1
1
X
X
1
0
0
0
X
X
127
C8051F300/1/2/3/4/5
Table 13.4. SMBus Status Decoding (Continued)
0
0
0
0
1
0
X
Rev. 2.9
ACK
0101
0
X A master data byte was received; Acknowledge received byte;
ACK requested.
Read SMB0DAT.
Send NACK to indicate last
byte, and send STOP.
Send NACK to indicate last
byte, and send STOP followed by START.
Send ACK followed by
repeated START.
Send NACK to indicate last
byte, and send repeated
START.
Send ACK and switch to
Master Transmitter Mode
(write to SMB0DAT before
clearing SI).
Send NACK and switch to
Master Transmitter Mode
(write to SMB0DAT before
clearing SI).
0 A slave byte was transmitted;
No action required (expectNACK received.
ing STOP condition).
1 A slave byte was transmitted;
Load SMB0DAT with next
ACK received.
data byte to transmit.
X A Slave byte was transmitted;
No action required (expecterror detected.
ing Master to end transfer).
X An illegal STOP or bus error was Clear STO.
detected while a Slave Transmission was in progress.
Values
Written
STO
SLAVE TRANSMITTER
128
0100
Typical Response Options
STA
0
Current SMbus State
ACK
ARBLOST
1
MASTER RECEIVER
1000
ACKRQ
Status
Vector
Mode
Values Read
0
0
1
0
1
0
1
1
0
1
0
1
1
0
0
0
0
1
0
0
0
0
0
X
0
0
X
0
0
X
0
0
X
C8051F300/1/2/3/4/5
Table 13.4. SMBus Status Decoding (Continued)
1
1
X
0010
0
1
X
0001
1
1
X
0
0
X
0
1
X
1
0
X
1
1
X
SLAVE RECEIVER
0000
STA
Values
Written
ACK
X A slave address was received;
ACK requested.
Typical Response Options
STO
ARBLOST
0
0010
ACK
ACKRQ
Current SMbus State
1
Status
Vector
Mode
Values Read
Acknowledge received
0
0
1
address (received slave
address match, R/W bit =
READ).
0
0
0
Do not acknowledge
received address.
Acknowledge received
0
0
1
address, and switch to transmitter mode (received slave
address match, R/W bit =
WRITE); see Section 13.5.4
for procedure.
Lost arbitration as master; slave Acknowledge received
0
0
1
address (received slave
address received; ACK
requested.
address match, R/W bit =
READ).
0
0
0
Do not acknowledge
received address.
Acknowledge received
0
0
1
address, and switch to transmitter mode (received slave
address match, R/W bit =
WRITE); see Section 13.5.4
for procedure.
1
0
0
Reschedule failed transfer;
do not acknowledge received
address
Lost arbitration while attempting a Abort failed transfer.
0
0 X
repeated START.
Reschedule failed transfer.
1
0 X
0
0
0
Lost arbitration while attempting a No action required (transfer
complete/aborted).
STOP.
A STOP was detected while
Clear STO.
0
0 X
addressed as a Slave Transmitter
or Slave Receiver.
Lost arbitration due to a detected Abort transfer.
0
0 X
STOP.
Reschedule failed transfer.
1
0 X
0
1
A slave byte was received; ACK Acknowledge received byte; 0
Read SMB0DAT.
requested.
Do not acknowledge
0
0
0
received byte.
Lost arbitration while transmitting Abort failed transfer.
0
0
0
a data byte as master.
Reschedule failed transfer. 1
0
0
Rev. 2.9
129
C8051F300/1/2/3/4/5
NOTES:
130
Rev. 2.9
C8051F300/1/2/3/4/5
14. UART0
UART0 is an asynchronous, full duplex serial port offering modes 1 and 3 of the standard 8051 UART.
Enhanced baud rate support allows a wide range of clock sources to generate standard baud rates (details
in Section “14.1. Enhanced Baud Rate Generation” on page 132). Received data buffering allows
UART0 to start reception of a second incoming data byte before software has finished reading the previous
data byte.
UART0 has two associated SFRs: Serial Control Register 0 (SCON0) and Serial Data Buffer 0 (SBUF0).
The single SBUF0 location provides access to both transmit and receive registers. Reading SBUF0
accesses the buffered Receive register; writing SBUF0 accesses the Transmit register.
With UART0 interrupts enabled, an interrupt is generated each time a transmit is completed (TI0 is set in
SCON0), or a data byte has been received (RI0 is set in SCON0). The UART0 interrupt flags are not
cleared by hardware when the CPU vectors to the interrupt service routine. They must be cleared manually
by software, allowing software to determine the cause of the UART0 interrupt (transmit complete or receive
complete).
SFR Bus
Write to
SBUF
TB8
SBUF
(TX Shift)
SET
D
Q
TX
CLR
Crossbar
Zero Detector
Stop Bit
Shift
Start
Data
Tx Control
Tx Clock
Send
Tx IRQ
SCON0
TI
Serial
Port
Interrupt
MCE0
REN0
TB80
RB80
TI0
RI0
S0MODE
UART Baud
Rate Generator
Port I/O
RI
Rx IRQ
Rx Clock
Rx Control
Start
Shift
0x1FF
RB8
Load
SBUF
Input Shift Register
(9 bits)
Load SBUF0
SBUF
(RX Latch)
Read
SBUF
SFR Bus
RX
Crossbar
Figure 14.1. UART0 Block Diagram
Rev. 2.9
131
C8051F300/1/2/3/4/5
14.1. Enhanced Baud Rate Generation
The UART0 baud rate is generated by Timer 1 in 8-bit auto-reload mode. The TX clock is generated by
TL1; the RX clock is generated by a copy of TL1 (shown as RX Timer in Figure 14.2), which is not user
accessible. Both TX and RX Timer overflows are divided by two to generate the TX and RX baud rates.
The RX Timer runs when Timer 1 is enabled, and uses the same reload value (TH1). However, an
RX Timer reload is forced when a START condition is detected on the RX pin. This allows a receive to
begin any time a START is detected, independent of the TX Timer state.
Timer 1
TL1
UART0
Overflow
2
TX Clock
Overflow
2
RX Clock
TH1
Start
Detected
RX Timer
Figure 14.2. UART0 Baud Rate Logic
Timer 1 should be configured for Mode 2, 8-bit auto-reload (see Section “15.1.3. Mode 2: 8-bit
Counter/Timer with Auto-Reload” on page 145). The Timer 1 reload value should be set so that overflows will occur at two times the desired UART baud rate frequency. Note that Timer 1 may be clocked by
one of five sources: SYSCLK, SYSCLK / 4, SYSCLK / 12, SYSCLK / 48, or the external oscillator clock / 8.
For any given Timer 1 clock source, the UART0 baud rate is determined by Equation 14.1.
T1 CLK
1
UartBaudRate = ------------------------------- × --( 256 – T1H ) 2
Equation 14.1. UART0 Baud Rate
Where T1CLK is the frequency of the clock supplied to Timer 1, and T1H is the high byte of Timer 1 (reload
value). Timer 1 clock frequency is selected as described in Section “15.2. Timer 2” on page 151. A quick
reference for typical baud rates and system clock frequencies is given in Tables 14.1 through 14.6. Note
that the internal oscillator may still generate the system clock when the external oscillator is driving Timer 1
(see Section “15.1. Timer 0 and Timer 1” on page 143 for more details).
132
Rev. 2.9
C8051F300/1/2/3/4/5
14.2. Operational Modes
UART0 provides standard asynchronous, full duplex communication. The UART mode (8-bit or 9-bit) is
selected by the S0MODE bit (SCON0.7). Typical UART connection options are shown below.
TX
RS-232
LEVEL
XLTR
RS-232
RX
C8051Fxxx
OR
TX
TX
RX
RX
MCU
C8051Fxxx
Figure 14.3. UART Interconnect Diagram
14.2.1. 8-Bit UART
8-Bit UART mode uses a total of 10 bits per data byte: one start bit, eight data bits (LSB first), and one stop
bit. Data are transmitted LSB first from the TX pin and received at the RX pin. On receive, the eight data
bits are stored in SBUF0 and the stop bit goes into RB80 (SCON0.2).
Data transmission begins when software writes a data byte to the SBUF0 register. The TI0 Transmit Interrupt Flag (SCON0.1) is set at the end of the transmission (the beginning of the stop-bit time). Data reception can begin any time after the REN0 Receive Enable bit (SCON0.4) is set to logic 1. After the stop bit is
received, the data byte will be loaded into the SBUF0 receive register if the following conditions are met:
RI0 must be logic 0, and if MCE0 is logic 1, the stop bit must be logic 1. In the event of a receive data overrun, the first received 8 bits are latched into the SBUF0 receive register and the following overrun data bits
are lost.
If these conditions are met, the eight bits of data is stored in SBUF0, the stop bit is stored in RB80 and the
RI0 flag is set. If these conditions are not met, SBUF0 and RB80 will not be loaded and the RI0 flag will not
be set. An interrupt will occur if enabled when either TI0 or RI0 is set.
MARK
SPACE
START
BIT
D0
D1
D2
D3
D4
D5
D6
D7
STOP
BIT
BIT TIMES
BIT SAMPLING
Figure 14.4. 8-Bit UART Timing Diagram
Rev. 2.9
133
C8051F300/1/2/3/4/5
14.2.2. 9-Bit UART
9-bit UART mode uses a total of eleven bits per data byte: a start bit, 8 data bits (LSB first), a programmable ninth data bit, and a stop bit. The state of the ninth transmit data bit is determined by the value in TB80
(SCON0.3), which is assigned by user software. It can be assigned the value of the parity flag (bit P in register PSW) for error detection, or used in multiprocessor communications. On receive, the ninth data bit
goes into RB80 (SCON0.2) and the stop bit is ignored.
Data transmission begins when an instruction writes a data byte to the SBUF0 register. The TI0 Transmit
Interrupt Flag (SCON0.1) is set at the end of the transmission (the beginning of the stop-bit time). Data
reception can begin any time after the REN0 Receive Enable bit (SCON0.4) is set to ‘1’. After the stop bit
is received, the data byte will be loaded into the SBUF0 receive register if the following conditions are met:
(1) RI0 must be logic 0, and (2) if MCE0 is logic 1, the 9th bit must be logic 1 (when MCE0 is logic 0, the
state of the ninth data bit is unimportant). If these conditions are met, the eight bits of data are stored in
SBUF0, the ninth bit is stored in RB80, and the RI0 flag is set to ‘1’. If the above conditions are not met,
SBUF0 and RB80 will not be loaded and the RI0 flag will not be set to ‘1’. A UART0 interrupt will occur if
enabled when either TI0 or RI0 is set to ‘1’.
MARK
SPACE
START
BIT
D0
D1
D2
D3
D4
D5
D6
BIT TIMES
BIT SAMPLING
Figure 14.5. 9-Bit UART Timing Diagram
134
Rev. 2.9
D7
D8
STOP
BIT
C8051F300/1/2/3/4/5
14.3. Multiprocessor Communications
9-Bit UART mode supports multiprocessor communication between a master processor and one or more
slave processors by special use of the ninth data bit. When a master processor wants to transmit to one or
more slaves, it first sends an address byte to select the target(s). An address byte differs from a data byte
in that its ninth bit is logic 1; in a data byte, the ninth bit is always set to logic 0.
Setting the MCE0 bit (SCON.5) of a slave processor configures its UART such that when a stop bit is
received, the UART will generate an interrupt only if the ninth bit is logic one (RB80 = 1) signifying an
address byte has been received. In the UART interrupt handler, software will compare the received
address with the slave's own assigned 8-bit address. If the addresses match, the slave will clear its MCE0
bit to enable interrupts on the reception of the following data byte(s). Slaves that weren't addressed leave
their MCE0 bits set and do not generate interrupts on the reception of the following data bytes, thereby
ignoring the data. Once the entire message is received, the addressed slave resets its MCE0 bit to ignore
all transmissions until it receives the next address byte.
Multiple addresses can be assigned to a single slave and/or a single address can be assigned to multiple
slaves, thereby enabling "broadcast" transmissions to more than one slave simultaneously. The master
processor can be configured to receive all transmissions or a protocol can be implemented such that the
master/slave role is temporarily reversed to enable half-duplex transmission between the original master
and slave(s).
Master
Device
Slave
Device
Slave
Device
Slave
Device
+5V
RX
TX
RX
TX
RX
TX
RX
TX
Figure 14.6. UART Multi-Processor Mode Interconnect Diagram
Rev. 2.9
135
C8051F300/1/2/3/4/5
SFR Definition 14.1. SCON0: Serial Port 0 Control
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
S0MODE
—
MCE0
REN0
TB80
RB80
TI0
RI0
01000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
(bit addressable)
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
136
Reset Value
0x98
S0MODE: Serial Port 0 Operation Mode.
This bit selects the UART0 Operation Mode.
0: Mode 0: 8-bit UART with Variable Baud Rate
1: Mode 1: 9-bit UART with Variable Baud Rate
UNUSED. Read = 1b. Write = don’t care.
MCE0: Multiprocessor Communication Enable.
The function of this bit is dependent on the Serial Port 0 Operation Mode.
Mode 0: Checks for valid stop bit.
0: Logic level of stop bit is ignored.
1: RI0 will only be activated if stop bit is logic level 1.
Mode 1: Multiprocessor Communications Enable.
0: Logic level of ninth bit is ignored.
1: RI0 is set and an interrupt is generated only when the ninth bit is logic 1.
REN0: Receive Enable.
This bit enables/disables the UART receiver.
0: UART0 reception disabled.
1: UART0 reception enabled.
TB80: Ninth Transmission Bit.
The logic level of this bit will be assigned to the ninth transmission bit in 9-bit UART Mode. It
is not used in 8-bit UART Mode. Set or cleared by software as required.
RB80: Ninth Receive Bit.
RB80 is assigned the value of the STOP bit in Mode 0; it is assigned the value of the 9th
data bit in Mode 1.
TI0: Transmit Interrupt Flag.
Set by hardware when a byte of data has been transmitted by UART0 (after the 8th bit in 8bit UART Mode, or at the beginning of the STOP bit in 9-bit UART Mode). When the UART0
interrupt is enabled, setting this bit causes the CPU to vector to the UART0 interrupt service
routine. This bit must be cleared manually by software
RI0: Receive Interrupt Flag.
Set to ‘1’ by hardware when a byte of data has been received by UART0 (set at the STOP bit
sampling time). When the UART0 interrupt is enabled, setting this bit to ‘1’ causes the CPU
to vector to the UART0 interrupt service routine. This bit must be cleared manually by software.
Rev. 2.9
C8051F300/1/2/3/4/5
SFR Definition 14.2. SBUF0: Serial (UART0) Port Data Buffer
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0x99
Bits7–0: SBUF0[7:0]: Serial Data Buffer Bits 7–0 (MSB-LSB)
This SFR accesses two registers; a transmit shift register and a receive latch register. When
data is written to SBUF0, it goes to the transmit shift register and is held for serial transmission. Writing a byte to SBUF0 is what initiates the transmission. A read of SBUF0 returns the
contents of the receive latch.
Rev. 2.9
137
C8051F300/1/2/3/4/5
Table 14.1. Timer Settings for Standard Baud Rates Using The Internal 24.5 MHz
Oscillator
Frequency: 24.5 MHz
Target
Baud Rate
(bps)
Baud Rate
% Error
230400
–0.32%
SYSCLK from
Internal Osc.
115200
–0.32%
Oscillator Timer Clock
Divide
Source
Factor
106
212
SCA1–SCA0
(pre-scale
select)1
T1M1
Timer 1
Reload
Value (hex)
SYSCLK
XX2
1
0xCB
SYSCLK
XX2
1
0x96
2
1
0x2B
57600
0.15%
426
SYSCLK
XX
28800
–0.32%
848
SYSCLK / 4
01
0
0x96
14400
0.15%
1704
SYSCLK / 12
00
0
0xB9
9600
–0.32%
2544
SYSCLK / 12
00
0
0x96
2400
–0.32%
10176
SYSCLK / 48
10
0
0x96
1200
0.15%
20448
SYSCLK / 48
10
0
0x2B
Notes:
1. SCA1-SCA0 and T1M bit definitions can be found in Section 15.1.
2. X = Don’t care.
Table 14.2. Timer Settings for Standard Baud Rates Using an External 25 MHz
Oscillator
SYSCLK from
Internal Osc.
SYSCLK from
External Osc.
Frequency: 25.0 MHz
Target
Baud Rate
(bps)
Baud Rate
% Error
230400
–0.47%
Oscillator Timer Clock
Divide
Source
Factor
108
SCA1–SCA0
(pre-scale
select)1
T1M1
Timer 1
Reload
Value (hex)
SYSCLK
XX2
1
0xCA
2
1
0x93
115200
0.45%
218
SYSCLK
XX
57600
–0.01%
434
SYSCLK
XX2
1
0x27
28800
0.45%
872
SYSCLK / 4
01
0
0x93
14400
–0.01%
1736
SYSCLK / 4
01
0
0x27
9600
0.15%
2608
EXTCLK / 8
11
0
0x5D
2400
0.45%
10464
SYSCLK / 48
10
0
0x93
1200
–0.01%
20832
SYSCLK / 48
10
0
0x27
57600
–0.47%
432
EXTCLK / 8
11
0
0xE5
28800
–0.47%
864
EXTCLK / 8
11
0
0xCA
14400
0.45%
1744
EXTCLK / 8
11
0
0x93
9600
0.15%
2608
EXTCLK / 8
11
0
0x5D
Notes:
1. SCA1–SCA0 and T1M bit definitions can be found in Section 15.1.
2. X = Don’t care
138
Rev. 2.9
C8051F300/1/2/3/4/5
Table 14.3. Timer Settings for Standard Baud Rates Using an External 22.1184 MHz
Oscillator
SYSCLK from
Internal Osc.
SYSCLK from
External Osc.
Frequency: 22.1184 MHz
Target
Baud Rate
(bps)
Baud Rate
% Error
Oscillator Timer Clock
Divide
Source
Factor
SCA1–SCA0
(pre-scale
select)1
T1M1
Timer 1
Reload
Value (hex)
230400
0.00%
96
SYSCLK
XX2
1
0xD0
115200
0.00%
192
SYSCLK
XX2
1
0xA0
57600
0.00%
384
SYSCLK
XX2
1
0x40
28800
0.00%
768
SYSCLK / 12
00
0
0xE0
14400
0.00%
1536
SYSCLK / 12
00
0
0xC0
9600
0.00%
2304
SYSCLK / 12
00
0
0xA0
2400
0.00%
9216
SYSCLK / 48
10
0
0xA0
1200
0.00%
18432
SYSCLK / 48
10
0
0x40
230400
0.00%
96
EXTCLK / 8
11
0
0xFA
115200
0.00%
192
EXTCLK / 8
11
0
0xF4
57600
0.00%
384
EXTCLK / 8
11
0
0xE8
28800
0.00%
768
EXTCLK / 8
11
0
0xD0
14400
0.00%
1536
EXTCLK / 8
11
0
0xA0
9600
0.00%
2304
EXTCLK / 8
11
0
0x70
Notes:
1. SCA1–SCA0 and T1M bit definitions can be found in Section 15.1.
2. X = Don’t care.
Rev. 2.9
139
C8051F300/1/2/3/4/5
Table 14.4. Timer Settings for Standard Baud Rates Using an External 18.432 MHz
Oscillator
SYSCLK from
Internal Osc.
SYSCLK from
External Osc.
Frequency: 18.432 MHz
Target
Baud Rate
(bps)
Baud Rate
% Error
Oscillator Timer Clock
Divide
Source
Factor
SCA1–SCA0
(pre-scale
select)1
T1M1
Timer 1
Reload
Value (hex)
230400
0.00%
80
SYSCLK
XX2
1
0xD8
115200
0.00%
160
SYSCLK
XX2
1
0xB0
57600
0.00%
320
SYSCLK
XX2
1
0x60
28800
0.00%
640
SYSCLK / 4
01
0
0xB0
14400
0.00%
1280
SYSCLK / 4
01
0
0x60
9600
0.00%
1920
SYSCLK / 12
00
0
0xB0
2400
0.00%
7680
SYSCLK / 48
10
0
0xB0
1200
0.00%
15360
SYSCLK / 48
10
0
0x60
230400
0.00%
80
EXTCLK / 8
11
0
0xFB
115200
0.00%
160
EXTCLK / 8
11
0
0xF6
57600
0.00%
320
EXTCLK / 8
11
0
0xEC
28800
0.00%
640
EXTCLK / 8
11
0
0xD8
14400
0.00%
1280
EXTCLK / 8
11
0
0xB0
9600
0.00%
1920
EXTCLK / 8
11
0
0x88
Notes:
1. SCA1–SCA0 and T1M bit definitions can be found in Section 15.1.
2. X = Don’t care
140
Rev. 2.9
C8051F300/1/2/3/4/5
Table 14.5. Timer Settings for Standard Baud Rates Using an External 11.0592 MHz
Oscillator
Frequency: 11.0592 MHz
Target
Baud Rate
(bps)
Baud Rate
% Error
Oscillator
Divide
Factor
Timer Clock
Source
SCA1-SCA0
(pre-scale
select)1
T1M1
Timer 1
Reload
Value (hex)
230400
0.00%
48
SYSCLK
XX2
1
0xE8
SYSCLK
XX2
1
0xD0
SYSCLK
XX
2
1
0xA0
2
1
0x40
SYSCLK from
Internal Osc.
SYSCLK from
External Osc.
115200
57600
0.00%
0.00%
96
192
28800
0.00%
384
SYSCLK
XX
14400
0.00%
768
SYSCLK / 12
00
0
0xE0
9600
0.00%
1152
SYSCLK / 12
00
0
0xD0
2400
0.00%
4608
SYSCLK / 12
00
0
0x40
1200
0.00%
9216
SYSCLK / 48
10
0
0xA0
230400
0.00%
48
EXTCLK / 8
11
0
0xFD
115200
0.00%
96
EXTCLK / 8
11
0
0xFA
57600
0.00%
192
EXTCLK / 8
11
0
0xF4
28800
0.00%
384
EXTCLK / 8
11
0
0xE8
14400
0.00%
768
EXTCLK / 8
11
0
0xD0
9600
0.00%
1152
EXTCLK / 8
11
0
0xB8
Notes:
1. SCA1–SCA0 and T1M bit definitions can be found in Section 15.1.
2. X = Don’t care
Rev. 2.9
141
C8051F300/1/2/3/4/5
Table 14.6. Timer Settings for Standard Baud Rates Using an External 3.6864 MHZ
Oscillator
Frequency: 3.6864 MHz
Target
Baud Rate
(bps)
Baud Rate
% Error
230400
0.00%
SYSCLK from
Internal Osc.
SYSCLK from
External Osc.
115200
57600
28800
0.00%
0.00%
0.00%
Oscillator Timer Clock
Divide
Source
Factor
16
32
64
128
SCA1–SCA0
(pre-scale
select)1
T1M1
Timer 1
Reload
Value (hex)
SYSCLK
XX2
1
0xF8
SYSCLK
2
XX
1
0xF0
SYSCLK
XX2
1
0xE0
SYSCLK
2
1
0xC0
2
XX
14400
0.00%
256
SYSCLK
XX
1
0x80
9600
0.00%
384
SYSCLK
XX2
1
0x40
2400
0.00%
1536
SYSCLK / 12
00
0
0xC0
1200
0.00%
3072
SYSCLK / 12
00
0
0x80
230400
0.00%
16
EXTCLK / 8
11
0
0xFF
115200
0.00%
32
EXTCLK / 8
11
0
0xFE
57600
0.00%
64
EXTCLK / 8
11
0
0xFC
28800
0.00%
128
EXTCLK / 8
11
0
0xF8
14400
0.00%
256
EXTCLK / 8
11
0
0xF0
9600
0.00%
384
EXTCLK / 8
11
0
0xE8
Notes:
1. SCA1–SCA0 and T1M bit definitions can be found in Section 15.1.
2. X = Don’t care
142
Rev. 2.9
C8051F300/1/2/3/4/5
15. Timers
Each MCU includes 3 counter/timers: two are 16-bit counter/timers compatible with those found in the
standard 8051, and one is a 16-bit auto-reload timer for use with the ADC, SMBus, or for general purpose
use. These timers can be used to measure time intervals, count external events and generate periodic
interrupt requests. Timer 0 and Timer 1 are nearly identical and have four primary modes of operation.
Timer 2 offers 16-bit and split 8-bit timer functionality with auto-reload.
Timer 0 and Timer 1 Modes:
Timer 2 Modes:
13-bit counter/timer
16-bit timer with auto-reload
16-bit counter/timer
8-bit counter/timer with auto-reload
Two 8-bit timers with auto-reload
Two 8-bit counter/timers (Timer 0 only)
Timers 0 and 1 may be clocked by one of five sources, determined by the Timer Mode Select bits (T1M–
T0M) and the Clock Scale bits (SCA1–SCA0). The Clock Scale bits define a pre-scaled clock from which
Timer 0 and/or Timer 1 may be clocked (See SFR Definition 15.3 for pre-scaled clock selection).
Timer 0/1 may then be configured to use this pre-scaled clock signal or the system clock. Timer 2 may be
clocked by the system clock, the system clock divided by 12, or the external oscillator clock source divided
by 8.
Timer 0 and Timer 1 may also be operated as counters. When functioning as a counter, a counter/timer
register is incremented on each high-to-low transition at the selected input pin. Events with a frequency of
up to one-fourth the system clock's frequency can be counted. The input signal need not be periodic, but it
should be held at a given level for at least two full system clock cycles to ensure the level is properly sampled.
15.1. Timer 0 and Timer 1
Each timer is implemented as 16-bit register accessed as two separate bytes: a low byte (TL0 or TL1) and
a high byte (TH0 or TH1). The Counter/Timer Control register (TCON) is used to enable Timer 0 and Timer
1 as well as indicate their status. Timer 0 interrupts can be enabled by setting the ET0 bit in the IE register
(Section “8.3.5. Interrupt Register Descriptions” on page 75); Timer 1 interrupts can be enabled by
setting the ET1 bit in the IE register (Section 8.3.5). Both counter/timers operate in one of four primary
modes selected by setting the Mode Select bits T1M1–T0M0 in the Counter/Timer Mode register (TMOD).
Each timer can be configured independently. Each operating mode is described below.
15.1.1. Mode 0: 13-bit Counter/Timer
Timer 0 and Timer 1 operate as 13-bit counter/timers in Mode 0. The following describes the configuration
and operation of Timer 0. However, both timers operate identically, and Timer 1 is configured in the same
manner as described for Timer 0.
The TH0 register holds the eight MSBs of the 13-bit counter/timer. TL0 holds the five LSBs in bit positions
TL0.4-TL0.0. The three upper bits of TL0 (TL0.7-TL0.5) are indeterminate and should be masked out or
ignored when reading. As the 13-bit timer register increments and overflows from 0x1FFF (all ones) to
0x0000, the timer overflow flag TF0 (TCON.5) is set and an interrupt will occur if Timer 0 interrupts are
enabled.
Rev. 2.9
143
C8051F300/1/2/3/4/5
The C/T0 bit (TMOD.2) selects the counter/timer's clock source. When C/T0 is set to logic 1, high-to-low
transitions at the selected Timer 0 input pin (T0) increment the timer register (Refer to Section
“12.1. Priority Crossbar Decoder” on page 104 for information on selecting and configuring external I/O
pins). Clearing C/T selects the clock defined by the T0M bit (CKCON.3). When T0M is set, Timer 0 is
clocked by the system clock. When T0M is cleared, Timer 0 is clocked by the source selected by the Clock
Scale bits in CKCON (see SFR Definition 15.3).
Setting the TR0 bit (TCON.4) enables the timer when either GATE0 (TMOD.3) is logic 0 or the input signal
/INT0 is active as defined by bit IN0PL in register IT01CF (see SFR Definition 8.11). Setting GATE0 to ‘1’
allows the timer to be controlled by the external input signal /INT0 (see Section “8.3.5. Interrupt Register
Descriptions” on page 75), facilitating pulse width measurements.
TR0
GATE0
/INT0
Counter/Timer
0
1
1
1
X*
0
1
1
X*
X*
0
1
Disabled
Enabled
Disabled
Enabled
*Note: X = Don't Care
Setting TR0 does not force the timer to reset. The timer registers should be loaded with the desired initial
value before the timer is enabled.
TL1 and TH1 form the 13-bit register for Timer 1 in the same manner as described above for TL0 and TH0.
Timer 1 is configured and controlled using the relevant TCON and TMOD bits just as with Timer 0. The
input signal /INT1 is used with Timer 1; the /INT1 polarity is defined by bit IN1PL in register IT01CF (see
SFR Definition 8.11).
CKCON
TTTT
2 2 1 0
MMMM
HL
Pre-scaled Clock
TMOD
SS
CC
AA
1 0
G
A
T
E
1
C
/
T
1
T T
1 1
MM
1 0
G
A
T
E
0
C
/
T
0
IT01CF
T T
0 0
MM
1 0
I
N
1
P
L
I
N
1
S
L
2
I
N
1
S
L
1
I
N
1
S
L
0
I
N
0
P
L
I
N
0
S
L
2
I
N
0
S
L
1
I
N
0
S
L
0
0
0
SYSCLK
1
1
TCLK
TR0
TL0
(5 bits)
TH0
(8 bits)
GATE0
Crossbar
/INT0
IN0PL
XOR
Figure 15.1. T0 Mode 0 Block Diagram
144
Rev. 2.9
TCON
T0
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
Interrupt
C8051F300/1/2/3/4/5
15.1.2. Mode 1: 16-bit Counter/Timer
Mode 1 operation is the same as Mode 0, except that the counter/timer registers use all 16 bits. The
counter/timers are enabled and configured in Mode 1 in the same manner as for Mode 0.
15.1.3. Mode 2: 8-bit Counter/Timer with Auto-Reload
Mode 2 configures Timer 0 and Timer 1 to operate as 8-bit counter/timers with automatic reload of the start
value. TL0 holds the count and TH0 holds the reload value. When the counter in TL0 overflows from all
ones to 0x00, the timer overflow flag TF0 (TCON.5) is set and the counter in TL0 is reloaded from TH0. If
Timer 0 interrupts are enabled, an interrupt will occur when the TF0 flag is set. The reload value in TH0 is
not changed. TL0 must be initialized to the desired value before enabling the timer for the first count to be
correct. When in Mode 2, Timer 1 operates identically to Timer 0.
Both counter/timers are enabled and configured in Mode 2 in the same manner as Mode 0. Setting the
TR0 bit (TCON.4) enables the timer when either GATE0 (TMOD.3) is logic 0 or when the input signal /INT0
is active as defined by bit IN0PL in register IT01CF (see Section “8.3.2. External Interrupts” on page 73
for details on the external input signals /INT0 and /INT1).
CKCON
TTTT
2 2 1 0
MMMM
HL
Pre-scaled Clock
TMOD
SS
CC
AA
1 0
G
A
T
E
1
C
/
T
1
T T
1 1
MM
1 0
G
A
T
E
0
C
/
T
0
IT01CF
T T
0 0
MM
1 0
I
N
1
P
L
I
N
1
S
L
2
I
N
1
S
L
1
I
N
1
S
L
0
I
N
0
P
L
I
N
0
S
L
2
I
N
0
S
L
1
I
N
0
S
L
0
0
0
SYSCLK
1
1
T0
TL0
(8 bits)
TCON
TCLK
TR0
Crossbar
GATE0
TH0
(8 bits)
/INT0
IN0PL
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
Interrupt
Reload
XOR
Figure 15.2. T0 Mode 2 Block Diagram
Rev. 2.9
145
C8051F300/1/2/3/4/5
15.1.4. Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)
In Mode 3, Timer 0 is configured as two separate 8-bit counter/timers held in TL0 and TH0. The
counter/timer in TL0 is controlled using the Timer 0 control/status bits in TCON and TMOD: TR0, C/T0,
GATE0 and TF0. TL0 can use either the system clock or an external input signal as its timebase. The TH0
register is restricted to a timer function sourced by the system clock or prescaled clock. TH0 is enabled
using the Timer 1 run control bit TR1. TH0 sets the Timer 1 overflow flag TF1 on overflow and thus controls
the Timer 1 interrupt.
Timer 1 is inactive in Mode 3. When Timer 0 is operating in Mode 3, Timer 1 can be operated in Modes 0,
1 or 2, but cannot be clocked by external signals nor set the TF1 flag and generate an interrupt. However,
the Timer 1 overflow can be used to generate baud rates for the SMBus and/or UART, and/or initiate ADC
conversions. While Timer 0 is operating in Mode 3, Timer 1 run control is handled through its mode settings. To run Timer 1 while Timer 0 is in Mode 3, set the Timer 1 Mode as 0, 1, or 2. To disable Timer 1,
configure it for Mode 3.
CKCON
T T T T
2 2 1 0
MMMM
HL
Pre-scaled Clock
TMOD
SS
CC
AA
1 0
G
A
T
E
1
C
/
T
1
T T
1 1
MM
1 0
G
A
T
E
0
C
/
T
0
T T
0 0
MM
1 0
0
TR1
SYSCLK
TH0
(8 bits)
1
TCON
0
1
T0
TL0
(8 bits)
TR0
Crossbar
/INT0
GATE0
IN0PL
XOR
Figure 15.3. T0 Mode 3 Block Diagram
146
Rev. 2.9
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
Interrupt
Interrupt
C8051F300/1/2/3/4/5
SFR Definition 15.1. TCON: Timer Control
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
(bit addressable)
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
Reset Value
0x88
TF1: Timer 1 Overflow Flag.
Set by hardware when Timer 1 overflows. This flag can be cleared by software but is automatically cleared when the CPU vectors to the Timer 1 interrupt service routine.
0: No Timer 1 overflow detected.
1: Timer 1 has overflowed.
TR1: Timer 1 Run Control.
0: Timer 1 disabled.
1: Timer 1 enabled.
TF0: Timer 0 Overflow Flag.
Set by hardware when Timer 0 overflows. This flag can be cleared by software but is automatically cleared when the CPU vectors to the Timer 0 interrupt service routine.
0: No Timer 0 overflow detected.
1: Timer 0 has overflowed.
TR0: Timer 0 Run Control.
0: Timer 0 disabled.
1: Timer 0 enabled.
IE1: External Interrupt 1.
This flag is set by hardware when an edge/level of type defined by IT1 is detected. It can be
cleared by software but is automatically cleared when the CPU vectors to the External Interrupt 1 service routine if IT1 = 1. When IT1 = 0, this flag is set to ‘1’ when /INT1 is active as
defined by bit IN1PL in register IT01CF (see SFR Definition 8.11).
IT1: Interrupt 1 Type Select.
This bit selects whether the configured /INT1 interrupt will be edge or level sensitive. /INT1
is configured active low or high by the IN1PL bit in the IT01CF register (see SFR Definition
8.11).
0: /INT1 is level triggered.
1: /INT1 is edge triggered.
IE0: External Interrupt 0.
This flag is set by hardware when an edge/level of type defined by IT0 is detected. It can be
cleared by software but is automatically cleared when the CPU vectors to the External Interrupt 0 service routine if IT0 = 1. When IT0 = 0, this flag is set to ‘1’ when /INT0 is active as
defined by bit IN0PL in register IT01CF (see SFR Definition 8.11).
IT0: Interrupt 0 Type Select.
This bit selects whether the configured /INT0 interrupt will be edge or level sensitive. /INT0
is configured active low or high by the IN0PL bit in register IT01CF (see SFR Definition
8.11).
0: /INT0 is level triggered.
1: /INT0 is edge triggered.
Rev. 2.9
147
C8051F300/1/2/3/4/5
SFR Definition 15.2. TMOD: Timer Mode
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
GATE1
C/T1
T1M1
T1M0
GATE0
C/T0
T0M1
T0M0
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0x89
Bit7:
GATE1: Timer 1 Gate Control.
0: Timer 1 enabled when TR1 = 1 irrespective of /INT1 logic level.
1: Timer 1 enabled only when TR1 = 1 AND /INT1 is active as defined by bit IN1PL in register IT01CF (see SFR Definition 8.11).
Bit6:
C/T1: Counter/Timer 1 Select.
0: Timer Function: Timer 1 incremented by clock defined by T1M bit (CKCON.4).
1: Counter Function: Timer 1 incremented by high-to-low transitions on external input pin
(T1).
Bits5–4: T1M1–T1M0: Timer 1 Mode Select.
These bits select the Timer 1 operation mode.
T1M1
T1M0
Mode
0
0
Mode 0: 13-bit counter/timer
0
1
Mode 1: 16-bit counter/timer
1
0
Mode 2: 8-bit counter/timer with autoreload
1
1
Mode 3: Timer 1 inactive
Bit3:
GATE0: Timer 0 Gate Control.
0: Timer 0 enabled when TR0 = 1 irrespective of /INT0 logic level.
1: Timer 0 enabled only when TR0 = 1 AND /INT0 is active as defined by bit IN0PL in register IT01CF (see SFR Definition 8.11).
Bit2:
C/T0: Counter/Timer Select.
0: Timer Function: Timer 0 incremented by clock defined by T0M bit (CKCON.3).
1: Counter Function: Timer 0 incremented by high-to-low transitions on external input pin
(T0).
Bits1–0: T0M1–T0M0: Timer 0 Mode Select.
These bits select the Timer 0 operation mode.
148
T0M1
T0M0
Mode
0
0
Mode 0: 13-bit counter/timer
0
1
Mode 1: 16-bit counter/timer
1
0
Mode 2: 8-bit counter/timer with autoreload
1
1
Mode 3: Two 8-bit counter/timers
Rev. 2.9
C8051F300/1/2/3/4/5
SFR Definition 15.3. CKCON: Clock Control
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
—
T2MH
T2ML
T1M
T0M
—
SCA1
SCA0
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0x8E
Bit7:
Bit6:
UNUSED. Read = 0b, Write = don’t care.
T2MH: Timer 2 High Byte Clock Select
This bit selects the clock supplied to the Timer 2 high byte if Timer 2 is configured in split 8bit timer mode. T2MH is ignored if Timer 2 is in any other mode.
0: Timer 2 high byte uses the clock defined by the T2XCLK bit in TMR2CN.
1: Timer 2 high byte uses the system clock.
Bit5:
T2ML: Timer 2 Low Byte Clock Select
This bit selects the clock supplied to Timer 2. If Timer 2 is configured in split 8-bit timer
mode, this bit selects the clock supplied to the lower 8-bit timer.
0: Timer 2 low byte uses the clock defined by the T2XCLK bit in TMR2CN.
1: Timer 2 low byte uses the system clock.
Bit4:
T1M: Timer 1 Clock Select.
This select the clock source supplied to Timer 1. T1M is ignored when C/T1 is set to logic 1.
0: Timer 1 uses the clock defined by the prescale bits, SCA1–SCA0.
1: Timer 1 uses the system clock.
Bit3:
T0M: Timer 0 Clock Select.
This bit selects the clock source supplied to Timer 0. T0M is ignored when C/T0 is set to
logic 1.
0: Counter/Timer 0 uses the clock defined by the prescale bits, SCA1–SCA0.
1: Counter/Timer 0 uses the system clock.
Bit2:
UNUSED. Read = 0b, Write = don’t care.
Bits1–0: SCA1–SCA0: Timer 0/1 Prescale Bits
These bits control the division of the clock supplied to Timer 0 and/or Timer 1 if configured
to use prescaled clock inputs.
SCA1
SCA0
Prescaled Clock
0
0
System clock divided by 12
0
1
System clock divided by 4
1
0
System clock divided by 48
1
1
External clock divided by 8
Note: External clock divided by 8 is synchronized with the
system clock, and the external clock must be less
than or equal to the system clock to operate in this
mode.
Rev. 2.9
149
C8051F300/1/2/3/4/5
SFR Definition 15.4. TL0: Timer 0 Low Byte
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0x8A
Bits 7–0: TL0: Timer 0 Low Byte.
The TL0 register is the low byte of the 16-bit Timer 0
SFR Definition 15.5. TL1: Timer 1 Low Byte
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
00000000
0x8B
Bits 7–0: TL1: Timer 1 Low Byte.
The TL1 register is the low byte of the 16-bit Timer 1.
SFR Definition 15.6. TH0: Timer 0 High Byte
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
00000000
0x8C
Bits 7–0: TH0: Timer 0 High Byte.
The TH0 register is the high byte of the 16-bit Timer 0.
SFR Definition 15.7. TH1: Timer 1 High Byte
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
00000000
0x8D
Bits 7–0: TH1: Timer 1 High Byte.
The TH1 register is the high byte of the 16-bit Timer 1.
150
Rev. 2.9
C8051F300/1/2/3/4/5
15.2. Timer 2
Timer 2 is a 16-bit timer formed by two 8-bit SFRs: TMR2L (low byte) and TMR2H (high byte). Timer 2 may
operate in 16-bit auto-reload mode or (split) 8-bit auto-reload mode. The T2SPLIT bit (TMR2CN.3) defines
the Timer 2 operation mode.
Timer 2 may be clocked by the system clock, the system clock divided by 12, or the external oscillator
source divided by 8. The external clock mode is ideal for real-time clock (RTC) functionality, where the
internal oscillator drives the system clock while Timer 2 (and/or the PCA) is clocked by an external precision oscillator. Note that the external oscillator source divided by 8 is synchronized with the system clock.
15.2.1. 16-bit Timer with Auto-Reload
When T2SPLIT (TMR2CN.3) is zero, Timer 2 operates as a 16-bit timer with auto-reload. Timer 2 can be
clocked by SYSCLK, SYSCLK divided by 12, or the external oscillator clock source divided by 8. As the
16-bit timer register increments and overflows from 0xFFFF to 0x0000, the 16-bit value in the Timer 2
reload registers (TMR2RLH and TMR2RLL) is loaded into the Timer 2 register as shown in Figure 15.4,
and the Timer 2 High Byte Overflow Flag (TMR2CN.7) is set. If Timer 2 interrupts are enabled (if IE.5 is
set), an interrupt will be generated on each Timer 2 overflow. Additionally, if Timer 2 interrupts are enabled
and the TF2LEN bit is set (TMR2CN.5), an interrupt will be generated each time the lower 8 bits (TMR2L)
overflow from 0xFF to 0x00.
CKCON
T2XCLK
SS
CC
AA
1 0
TMR2L
Overflow
0
TR2
External Clock / 8
SYSCLK
To ADC,
SMBus
To SMBus
0
1
TCLK
TMR2L
TMR2H
TMR2CN
SYSCLK / 12
TTTT
2 2 1 0
MMMM
HL
1
TF2H
TF2L
TF2LEN
Interrupt
T2SPLIT
TR2
T2XCLK
TMR2RLL TMR2RLH
Reload
Figure 15.4. Timer 2 16-Bit Mode Block Diagram
Rev. 2.9
151
C8051F300/1/2/3/4/5
15.2.2. 8-bit Timers with Auto-Reload
When T2SPLIT is set, Timer 2 operates as two 8-bit timers (TMR2H and TMR2L). Both 8-bit timers operate in auto-reload mode as shown in Figure 15.5. TMR2RLL holds the reload value for TMR2L; TMR2RLH
holds the reload value for TMR2H. The TR2 bit in TMR2CN handles the run control for TMR2H. TMR2L is
always running when configured for 8-bit Mode.
Each 8-bit timer may be configured to use SYSCLK, SYSCLK divided by 12, or the external oscillator clock
source divided by 8. The Timer 2 Clock Select bits (T2MH and T2ML in CKCON) select either SYSCLK or
the clock defined by the Timer 2 External Clock Select bit (T2XCLK in TMR2CN), as follows:
T2MH
T2XCLK TMR2H Clock Source
T2ML
T2XCLK TMR2L Clock Source
0
0
SYSCLK / 12
0
0
SYSCLK / 12
0
1
External Clock / 8
0
1
External Clock / 8
1
X
SYSCLK
1
X
SYSCLK
Note: External clock divided by 8 is synchronized with the system clock, and the external clock must be
less than or equal to the system clock to operate in this mode.
The TF2H bit is set when TMR2H overflows from 0xFF to 0x00; the TF2L bit is set when TMR2L overflows
from 0xFF to 0x00. When Timer 2 interrupts are enabled (IE.5), an interrupt is generated each time
TMR2H overflows. If Timer 2 interrupts are enabled and TF2LEN (TMR2CN.5) is set, an interrupt is generated each time either TMR2L or TMR2H overflows. When TF2LEN is enabled, software must check the
TF2H and TF2L flags to determine the source of the Timer 2 interrupt. The TF2H and TF2L interrupt flags
are not cleared by hardware and must be manually cleared by software.
CKCON
TTTT
2 2 1 0
MMMM
HL
T2XCLK
SYSCLK / 12
0
External Clock / 8
1
SS
CC
AA
1 0
TMR2RLH
Reload
To SMBus
0
TCLK
TR2
TMR2H
TMR2RLL
SYSCLK
Reload
TMR2CN
1
TF2H
TF2L
TF2LEN
T2SPLIT
TR2
T2XCLK
1
TCLK
TMR2L
To ADC,
SMBus
0
Figure 15.5. Timer 2 8-Bit Mode Block Diagram
152
Rev. 2.9
Interrupt
C8051F300/1/2/3/4/5
SFR Definition 15.8. TMR2CN: Timer 2 Control
R/W
R/W
R/W
R/W
R/W
R/W
TF2H
TF2L
Bit7
Bit6
R/W
TF2LEN
—
T2SPLIT
TR2
—
Bit5
Bit4
Bit3
Bit2
Bit1
R/W
T2XCLK 00000000
Bit0
(bit addressable)
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
Reset Value
SFR Address:
0xC8
TF2H: Timer 2 High Byte Overflow Flag
Set by hardware when the Timer 2 high byte overflows from 0xFF to 0x00. In 16 bit mode,
this will occur when Timer 2 overflows from 0xFFFF to 0x0000. When the Timer 2 interrupt is
enabled, setting this bit causes the CPU to vector to the Timer 2 interrupt service routine.
TF2H is not automatically cleared by hardware and must be cleared by software.
TF2L: Timer 2 Low Byte Overflow Flag
Set by hardware when the Timer 2 low byte overflows from 0xFF to 0x00. When this bit is
set, an interrupt will be generated if TF2LEN is set and Timer 2 interrupts are enabled. TF2L
will set when the low byte overflows regardless of the Timer 2 mode. This bit is not automatically cleared by hardware.
TF2LEN: Timer 2 Low Byte Interrupt Enable.
This bit enables/disables Timer 2 Low Byte interrupts. If TF2LEN is set and Timer 2 interrupts are enabled, an interrupt will be generated when the low byte of Timer 2 overflows.
This bit should be cleared when operating Timer 2 in 16-bit mode.
0: Timer 2 Low Byte interrupts disabled.
1: Timer 2 Low Byte interrupts enabled.
UNUSED. Read = 0b. Write = don’t care.
T2SPLIT: Timer 2 Split Mode Enable
When this bit is set, Timer 2 operates as two 8-bit timers with auto-reload.
0: Timer 2 operates in 16-bit auto-reload mode.
1: Timer 2 operates as two 8-bit auto-reload timers.
TR2: Timer 2 Run Control.
This bit enables/disables Timer 2. In 8-bit mode, this bit enables/disables TMR2H only;
TMR2L is always enabled in this mode.
0: Timer 2 disabled.
1: Timer 2 enabled.
UNUSED. Read = 0b. Write = don’t care.
T2XCLK: Timer 2 External Clock Select
This bit selects the external clock source for Timer 2. If Timer 2 is in 8-bit mode, this bit
selects the external oscillator clock source for both timer bytes. However, the Timer 2 Clock
Select bits (T2MH and T2ML in register CKCON) may still be used to select between the
external clock and the system clock for either timer.
0: Timer 2 external clock selection is the system clock divided by 12.
1: Timer 2 external clock selection is the external clock divided by 8. Note that the external
oscillator source divided by 8 is synchronized with the system clock.
Rev. 2.9
153
C8051F300/1/2/3/4/5
SFR Definition 15.9. TMR2RLL: Timer 2 Reload Register Low Byte
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
00000000
0xCA
Bits 7–0: TMR2RLL: Timer 2 Reload Register Low Byte.
TMR2RLL holds the low byte of the reload value for Timer 2.
SFR Definition 15.10. TMR2RLH: Timer 2 Reload Register High Byte
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
00000000
0xCB
Bits 7–0: TMR2RLH: Timer 2 Reload Register High Byte.
The TMR2RLH holds the high byte of the reload value for Timer 2.
SFR Definition 15.11. TMR2L: Timer 2 Low Byte
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0xCC
Bits 7–0: TMR2L: Timer 2 Low Byte.
In 16-bit mode, the TMR2L register contains the low byte of the 16-bit Timer 2. In 8-bit mode,
TMR2L contains the 8-bit low byte timer value.
SFR Definition 15.12. TMR2H Timer 2 High Byte
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0xCD
Bits 7–0: TMR2H: Timer 2 High Byte.
In 16-bit mode, the TMR2H register contains the high byte of the 16-bit Timer 2. In 8-bit
mode, TMR2H contains the 8-bit high byte timer value.
154
Rev. 2.9
C8051F300/1/2/3/4/5
16. Programmable Counter Array
The Programmable Counter Array (PCA0) provides enhanced timer functionality while requiring less CPU
intervention than the standard 8051 counter/timers. The PCA consists of a dedicated 16-bit counter/timer
and three 16-bit capture/compare modules. Each capture/compare module has its own associated I/O line
(CEXn) which is routed through the Crossbar to Port I/O when enabled (See Section “12.1. Priority
Crossbar Decoder” on page 104 for details on configuring the Crossbar). The counter/timer is driven by
a programmable timebase that can select between six sources: system clock, system clock divided by four,
system clock divided by twelve, the external oscillator clock source divided by 8, Timer 0 overflow, or an
external clock signal on the ECI input pin. Each capture/compare module may be configured to operate
independently in one of six modes: Edge-Triggered Capture, Software Timer, High-Speed Output, Frequency Output, 8-Bit PWM, or 16-Bit PWM (each mode is described in Section “16.2. Capture/Compare
Modules” on page 157). The external oscillator clock option is ideal for real-time clock (RTC) functionality,
allowing the PCA to be clocked by a precision external oscillator while the internal oscillator drives the system clock. The PCA is configured and controlled through the system controller's Special Function Registers. The basic PCA block diagram is shown in Figure 16.1.
Important Note: The PCA Module 2 may be used as a watchdog timer (WDT), and is enabled in this mode
following a system reset. Access to certain PCA registers is restricted while WDT mode is enabled. See
Section 16.3 for details.
SYSCLK/12
SYSCLK/4
Timer 0 Overflow
ECI
PCA
CLOCK
MUX
16-Bit Counter/Timer
SYSCLK
External Clock/8
Capture/Compare
Module 0
Capture/Compare
Module 1
Capture/Compare
Module 2 / WDT
CEX2
CEX1
CEX0
ECI
Digital Crossbar
Port I/O
Figure 16.1. PCA Block Diagram
Rev. 2.9
155
C8051F300/1/2/3/4/5
16.1. PCA Counter/Timer
The 16-bit PCA counter/timer consists of two 8-bit SFRs: PCA0L and PCA0H. PCA0H is the high byte
(MSB) of the 16-bit counter/timer and PCA0L is the low byte (LSB). Reading PCA0L automatically latches
the value of PCA0H into a “snapshot” register; the following PCA0H read accesses this “snapshot” register.
Reading the PCA0L Register first guarantees an accurate reading of the entire 16-bit PCA0 counter.
Reading PCA0H or PCA0L does not disturb the counter operation. The CPS2-CPS0 bits in the PCA0MD
register select the timebase for the counter/timer as shown in Table 16.1. Note that in ‘External oscillator
source divided by 8’ mode, the external oscillator source is synchronized with the system clock,
and must have a frequency less than or equal to the system clock.
When the counter/timer overflows from 0xFFFF to 0x0000, the Counter Overflow Flag (CF) in PCA0MD is
set to logic 1 and an interrupt request is generated if CF interrupts are enabled. Setting the ECF bit in
PCA0MD to logic 1 enables the CF flag to generate an interrupt request. The CF bit is not automatically
cleared by hardware when the CPU vectors to the interrupt service routine, and must be cleared by software (Note: PCA0 interrupts must be globally enabled before CF interrupts are recognized. PCA0 interrupts are globally enabled by setting the EA bit and the EPCA0 bit to logic 1). Clearing the CIDL bit in the
PCA0MD register allows the PCA to continue normal operation while the CPU is in Idle mode.
Table 16.1. PCA Timebase Input Options
CPS2
CPS1
CPS0
Timebase
0
0
0
System clock divided by 12
0
0
1
System clock divided by 4
0
1
0
Timer 0 overflow
0
1
1
High-to-low transitions on ECI (max rate = system clock divided by 4)
1
0
0
System clock
1
0
1
External oscillator source divided by 8*
*Note: External oscillator source divided by 8 is synchronized with the system clock.
IDLE
PCA0MD
CWW
I D D
D T L
L E C
K
C
P
S
2
C
P
S
1
CE
PC
S F
0
PCA0CN
CC
FR
C
C
F
2
C
C
F
1
C
C
F
0
To SFR Bus
PCA0L
read
Snapshot
Register
SYSCLK/12
SYSCLK/4
Timer 0 Overflow
ECI
SYSCLK
External Clock/8
000
001
010
0
011
1
PCA0H
PCA0L
Overflow
100
101
To PCA Modules
Figure 16.2. PCA Counter/Timer Block Diagram
156
To PCA Interrupt System
CF
Rev. 2.9
C8051F300/1/2/3/4/5
16.2. Capture/Compare Modules
Each module can be configured to operate independently in one of six operation modes: Edge-triggered
Capture, Software Timer, High Speed Output, Frequency Output, 8-bit Pulse Width Modulator, or 16-bit
Pulse Width Modulator. Each module has Special Function Registers (SFRs) associated with it in the CIP51 system controller. These registers are used to exchange data with a module and configure the module's
mode of operation.
Table 16.2 summarizes the bit settings in the PCA0CPMn registers used to select the PCA capture/compare module’s operating modes. Setting the ECCFn bit in a PCA0CPMn register enables the module's
CCFn interrupt. Note: PCA0 interrupts must be globally enabled before individual CCFn interrupts are recognized. PCA0 interrupts are globally enabled by setting the EA bit and the EPCA0 bit to logic 1. See
Figure 16.3 for details on the PCA interrupt configuration.
Table 16.2. PCA0CPM Register Settings for PCA Capture/Compare Modules
PWM16 ECOM
MAT
TOG
PWM
ECCF
Operation Mode
X*
X*
CAPP CAPN
1
0
0
0
0
X*
Capture triggered by positive edge
on CEXn
X*
X*
0
1
0
0
0
X*
Capture triggered by negative
edge on CEXn
X*
X*
1
1
0
0
0
X*
Capture triggered by transition on
CEXn
X*
1
0
0
1
0
0
X*
Software Timer
X*
1
0
0
1
1
0
X*
High Speed Output
X*
1
0
0
X*
1
1
X*
Frequency Output
0
1
0
0
X*
0
1
X*
8-bit Pulse Width Modulator
1
1
0
0
X*
0
1
X*
16-bit Pulse Width Modulator
*Note: X = Don’t Care
(for n = 0 to 2)
PCA0CPMn
P ECCMT P E
WC A A AOWC
MOPP TGMC
1 MP N n n n F
6 n n n
n
n
PCA0CN
CC
FR
CCC
CCC
FFF
2 1 0
PCA0MD
C WW
I DD
DTL
LEC
K
CCCE
PPPC
SSSF
2 1 0
0
PCA Counter/
Timer Overflow
1
EPCA0
ECCF0
0
PCA Module 0
(CCF0)
1
EA
0
0
1
1
Interrupt
Priority
Decoder
ECCF1
0
PCA Module 1
(CCF1)
1
ECCF2
PCA Module 2
(CCF2)
0
1
Figure 16.3. PCA Interrupt Block Diagram
Rev. 2.9
157
C8051F300/1/2/3/4/5
16.2.1. Edge-triggered Capture Mode
In this mode, a valid transition on the CEXn pin causes the PCA to capture the value of the PCA counter/
timer and copy it into the corresponding module's 16-bit capture/compare register (PCA0CPLn and
PCA0CPHn). The CAPPn and CAPNn bits in the PCA0CPMn register are used to select the type of transition that triggers the capture: low-to-high transition (positive edge), high-to-low transition (negative edge),
or either transition (positive or negative edge). When a capture occurs, the Capture/Compare Flag (CCFn)
in PCA0CN is set to logic 1 and an interrupt request is generated if CCF interrupts are enabled. The CCFn
bit is not automatically cleared by hardware when the CPU vectors to the interrupt service routine, and
must be cleared by software. If both CAPPn and CAPNn bits are set to logic 1, then the state of the Port
pin associated with CEXn can be read directly to determine whether a rising-edge or falling-edge caused
the capture.
PCA Interrupt
PCA0CPMn
P ECCMT P E
WC A A AOWC
MOPP TGMC
1 MP N n n n F
6 n n n
n
n
0 0 0 x
0
Port I/O
Crossbar
CEXn
CCC
CCC
FFF
2 1 0
(to CCFn)
x 0
PCA0CN
CC
FR
1
PCA0CPLn
PCA0CPHn
Capture
0
1
PCA
Timebase
PCA0L
PCA0H
Figure 16.4. PCA Capture Mode Diagram
Note: The CEXn input signal must remain high or low for at least 2 system clock cycles to be recognized by the
hardware.
158
Rev. 2.9
C8051F300/1/2/3/4/5
16.2.2. Software Timer (Compare) Mode
In Software Timer mode, the PCA counter/timer value is compared to the module's 16-bit capture/compare
register (PCA0CPHn and PCA0CPLn). When a match occurs, the Capture/Compare Flag (CCFn) in
PCA0CN is set to logic 1 and an interrupt request is generated if CCF interrupts are enabled. The CCFn bit
is not automatically cleared by hardware when the CPU vectors to the interrupt service routine, and must
be cleared by software. Setting the ECOMn and MATn bits in the PCA0CPMn register enables Software
Timer mode.
Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Capture/
Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the ECOMn bit
to ‘0’; writing to PCA0CPHn sets ECOMn to ‘1’.
Write to
PCA0CPLn
0
ENB
Reset
Write to
PCA0CPHn
PCA Interrupt
ENB
1
PCA0CPMn
P ECCMT P E
WC A A AOWC
MOPP TGMC
1 MP N n n n F
6 n n n
n
n
x
0 0
PCA0CN
PCA0CPLn
CC
FR
PCA0CPHn
CCC
CCC
FFF
2 1 0
0 0 x
Enable
16-bit Comparator
PCA
Timebase
PCA0L
Match
0
1
PCA0H
Figure 16.5. PCA Software Timer Mode Diagram
Rev. 2.9
159
C8051F300/1/2/3/4/5
16.2.3. High Speed Output Mode
In High Speed Output mode, a module’s associated CEXn pin is toggled each time a match occurs
between the PCA Counter and the module's 16-bit capture/compare register (PCA0CPHn and
PCA0CPLn) Setting the TOGn, MATn, and ECOMn bits in the PCA0CPMn register enables the HighSpeed Output mode.
Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Capture/
Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the ECOMn bit
to ‘0’; writing to PCA0CPHn sets ECOMn to ‘1’.
Write to
PCA0CPLn
0
ENB
Reset
Write to
PCA0CPHn
PCA0CPMn
P ECCMT P E
WC A A A OWC
MOPP TGMC
1 MP N n n n F
6 n n n
n
n
ENB
1
x
0 0
0 x
PCA Interrupt
PCA0CN
PCA0CPLn
Enable
CC
FR
PCA0CPHn
Match
16-bit Comparator
CCC
CCC
FFF
2 1 0
0
1
TOGn
Toggle
PCA
Timebase
0 CEXn
1
PCA0L
Crossbar
PCA0H
Figure 16.6. PCA High Speed Output Mode Diagram
160
Rev. 2.9
Port I/O
C8051F300/1/2/3/4/5
16.2.4. Frequency Output Mode
Frequency Output Mode produces a programmable-frequency square wave on the module’s associated
CEXn pin. The capture/compare module high byte holds the number of PCA clocks to count before the output is toggled. The frequency of the square wave is then defined by Equation 16.1.
F PCA
F CEXn = ----------------------------------------2 × PCA0CPHn
Equation 16.1. Square Wave Frequency Output
Where FPCA is the frequency of the clock selected by the CPS2–0 bits in the PCA mode register,
PCA0MD. The lower byte of the capture/compare module is compared to the PCA counter low byte; on a
match, CEXn is toggled and the offset held in the high byte is added to the matched value in PCA0CPLn.
Frequency Output Mode is enabled by setting the ECOMn, TOGn, and PWMn bits in the PCA0CPMn register.
Write to
PCA0CPLn
0
ENB
Reset
PCA0CPMn
Write to
PCA0CPHn
ENB
1
P ECCMT P E
WC A A AOWC
MOPP TGMC
1 MP N n n n F
6 n n n
n
n
x
0 0 0
PCA0CPLn
8-bit Adder
PCA0CPHn
Adder
Enable
TOGn
Toggle
x
Enable
PCA Timebase
8-bit
Comparator
match
0 CEXn
1
Crossbar
Port I/O
PCA0L
Figure 16.7. PCA Frequency Output Mode
Rev. 2.9
161
C8051F300/1/2/3/4/5
16.2.5. 8-Bit Pulse Width Modulator Mode
Each module can be used independently to generate a pulse width modulated (PWM) output on its associated CEXn pin. The frequency of the output is dependent on the timebase for the PCA counter/timer. The
duty cycle of the PWM output signal is varied using the module's PCA0CPLn capture/compare register.
When the value in the low byte of the PCA counter/timer (PCA0L) is equal to the value in PCA0CPLn, the
output on the CEXn pin will be set to ‘1’. When the count value in PCA0L overflows, the CEXn output will
be set to ‘0’ (see Figure 16.8). Also, when the counter/timer low byte (PCA0L) overflows from 0xFF to
0x00, PCA0CPLn is reloaded automatically with the value stored in the module’s capture/compare high
byte (PCA0CPHn) without software intervention. Setting the ECOMn and PWMn bits in the PCA0CPMn
register enables 8-bit Pulse Width Modulator mode. The duty cycle for 8-bit PWM Mode is given by
Equation 16.2.
Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Capture/
Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the ECOMn bit
to ‘0’; writing to PCA0CPHn sets ECOMn to ‘1’.
( 256 – PCA0CPHn )
DutyCycle = --------------------------------------------------256
Equation 16.2. 8-Bit PWM Duty Cycle
Using Equation 16.2, the largest duty cycle is 100% (PCA0CPHn = 0), and the smallest duty cycle is
0.39% (PCA0CPHn = 0xFF). A 0% duty cycle may be generated by clearing the ECOMn bit to ‘0’.
Write to
PCA0CPLn
0
PCA0CPHn
ENB
Reset
Write to
PCA0CPHn
ENB
1
PCA0CPMn
P ECCMT P E
WC A A AOWC
MOPP TGMC
1 MP N n n n F
6 n n n
n
n
0
0 0 x 0
PCA0CPLn
x
Enable
8-bit
Comparator
match
S
R
PCA Timebase
SET
CLR
Q
CEXn
Q
PCA0L
Overflow
Figure 16.8. PCA 8-Bit PWM Mode Diagram
162
Rev. 2.9
Crossbar
Port I/O
C8051F300/1/2/3/4/5
16.2.6. 16-Bit Pulse Width Modulator Mode
A PCA module may also be operated in 16-bit PWM mode. In this mode, the 16-bit capture/compare module defines the number of PCA clocks for the low time of the PWM signal. When the PCA counter matches
the module contents, the output on CEXn is set to ‘1’; when the counter overflows, CEXn is set to ‘0’. To
output a varying duty cycle, new value writes should be synchronized with PCA CCFn match interrupts.
16-bit PWM Mode is enabled by setting the ECOMn, PWMn, and PWM16n bits in the PCA0CPMn register.
For a varying duty cycle, match interrupts should be enabled (ECCFn = 1 AND MATn = 1) to help synchronize the capture/compare register writes. The duty cycle for 16-bit PWM Mode is given by Equation 16.3.
Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Capture/
Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the ECOMn bit
to ‘0’; writing to PCA0CPHn sets ECOMn to ‘1’.
( 65536 – PCA0CPn )
DutyCycle = ----------------------------------------------------65536
Equation 16.3. 16-Bit PWM Duty Cycle
Using Equation 16.3, the largest duty cycle is 100% (PCA0CPn = 0), and the smallest duty cycle is
0.0015% (PCA0CPn = 0xFFFF). A 0% duty cycle may be generated by clearing the ECOMn bit to ‘0’.
Write to
PCA0CPLn
0
ENB
Reset
Write to
PCA0CPHn
ENB
1
PCA0CPMn
P ECCMT P E
WC A A AOWC
MOPP TGMC
1 MP N n n n F
6 n n n
n
n
1
0 0 x 0
PCA0CPHn
PCA0CPLn
x
Enable
16-bit Comparator
match
S
R
PCA Timebase
PCA0H
SET
CLR
Q
CEXn
Crossbar
Port I/O
Q
PCA0L
Overflow
Figure 16.9. PCA 16-Bit PWM Mode
Rev. 2.9
163
C8051F300/1/2/3/4/5
16.3. Watchdog Timer Mode
A programmable watchdog timer (WDT) function is available through the PCA Module 2. The WDT is used
to generate a reset if the time between writes to the WDT update register (PCA0CPH2) exceed a specified
limit. The WDT can be configured and enabled/disabled as needed by software.
With the WDTE bit set in the PCA0MD register, Module 2 operates as a watchdog timer (WDT). The Module 2 high byte is compared to the PCA counter high byte; the Module 2 low byte holds the offset to be
used when WDT updates are performed. The Watchdog Timer is enabled on reset. Writes to some
PCA registers are restricted while the Watchdog Timer is enabled.
16.3.1. Watchdog Timer Operation
While the WDT is enabled:
•
•
•
•
•
•
PCA counter is forced on.
Writes to PCA0L and PCA0H are not allowed.
PCA clock source bits (CPS2–CPS0) are frozen.
PCA Idle control bit (CIDL) is frozen.
Module 2 is forced into software timer mode.
Writes to the module 2 mode register (PCA0CPM2) are disabled.
While the WDT is enabled, writes to the CR bit will not change the PCA counter state; the counter will run
until the WDT is disabled. The PCA counter run control (CR) will read zero if the WDT is enabled but user
software has not enabled the PCA counter. If a match occurs between PCA0CPH2 and PCA0H while the
WDT is enabled, a reset will be generated. To prevent a WDT reset, the WDT may be updated with a write
of any value to PCA0CPH2. Upon a PCA0CPH2 write, PCA0H plus the offset held in PCA0CPL2 is loaded
into PCA0CPH2 (See Figure 16.10).
PCA0MD
CWW
I DD
DT L
L E C
K
CCCE
PPPC
SSSF
2 1 0
PCA0CPH2
Enable
PCA0CPL2
Write to
PCA0CPH2
8-bit Adder
8-bit
Comparator
PCA0H
Match
Reset
PCA0L Overflow
Adder
Enable
Figure 16.10. PCA Module 2 with Watchdog Timer Enabled
164
Rev. 2.9
C8051F300/1/2/3/4/5
Note that the 8-bit offset held in PCA0CPH2 is compared to the upper byte of the 16-bit PCA counter. This
offset value is the number of PCA0L overflows before a reset. Up to 256 PCA clocks may pass before the
first PCA0L overflow occurs, depending on the value of the PCA0L when the update is performed. The
total offset is then given (in PCA clocks) by Equation 16.4, where PCA0L is the value of the PCA0L register
at the time of the update.
Offset = ( 256 × PCA0CPL2 ) + ( 256 – PCA0L )
Equation 16.4. Watchdog Timer Offset in PCA Clocks
The WDT reset is generated when PCA0L overflows while there is a match between PCA0CPH2 and
PCA0H. Software may force a WDT reset by writing a ‘1’ to the CCF2 flag (PCA0CN.2) while the WDT is
enabled.
16.3.2. Watchdog Timer Usage
To configure the WDT, perform the following tasks:
•
•
•
•
•
•
Disable the WDT by writing a ‘0’ to the WDTE bit.
Select the desired PCA clock source (with the CPS2–CPS0 bits).
Load PCA0CPL2 with the desired WDT update offset value.
Configure the PCA Idle mode (set CIDL if the WDT should be suspended while the CPU is in Idle
mode).
Enable the WDT by setting the WDTE bit to ‘1’.
Reload the WDT by writing any value to PCA0CPH2.
The PCA clock source and Idle mode select cannot be changed while the WDT is enabled. The Watchdog
Timer is enabled by setting the WDTE or WDLCK bits in the PCA0MD register. When WDLCK is set, the
WDT cannot be disabled until the next system reset. If WDLCK is not set, the WDT is disabled by clearing
the WDTE bit.
The WDT is enabled following any reset. The PCA0 counter clock defaults to the system clock divided by
12, PCA0L defaults to 0x00, and PCA0CPL2 defaults to 0x00. Using Equation 16.4, this results in a WDT
timeout interval of 3072 system clock cycles. Table 16.3 lists some example timeout intervals for typical
system clocks, assuming SYSCLK / 12 as the PCA clock source.
Rev. 2.9
165
C8051F300/1/2/3/4/5
Table 16.3. Watchdog Timer Timeout Intervals1
System Clock (Hz)
PCA0CPL2
Timeout Interval (ms)
24,500,000
255
32.1
24,500,000
128
16.2
24,500,000
32
4.1
18,432,000
255
42.7
18,432,000
128
21.5
18,432,000
32
5.5
11,059,200
255
71.1
11,059,200
128
35.8
11,059,200
32
9.2
3,062,5002
255
257
3,062,5002
128
129.5
3,062,500
32
33.1
32,000
255
24576
32,000
128
12384
32,000
32
3168
2
Notes:
1. Assumes SYSCLK / 12 as the PCA clock source, and a PCA0L value of 0x00
at the update time.
2. Internal oscillator reset frequency for devices with a calibrated internal
oscillator. The reset system clock for devices with an uncalibrated internal
oscillator will vary.
166
Rev. 2.9
C8051F300/1/2/3/4/5
16.4. Register Descriptions for PCA
Following are detailed descriptions of the special function registers related to the operation of the PCA.
SFR Definition 16.1. PCA0CN: PCA Control
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
CF
CR
—
—
—
CCF2
CCF1
CCF0
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
(bit addressable)
0xD8
Bit7:
CF: PCA Counter/Timer Overflow Flag.
Set by hardware when the PCA Counter/Timer overflows from 0xFFFF to 0x0000. When the
Counter/Timer Overflow (CF) interrupt is enabled, setting this bit causes the CPU to vector
to the PCA interrupt service routine. This bit is not automatically cleared by hardware and
must be cleared by software.
Bit6:
CR: PCA Counter/Timer Run Control.
This bit enables/disables the PCA Counter/Timer.
0: PCA Counter/Timer disabled.
1: PCA Counter/Timer enabled.
Bits5–3: UNUSED. Read = 000b, Write = don't care.
Bit2:
CCF2: PCA Module 2 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF2 interrupt is
enabled, setting this bit causes the CPU to vector to the PCA interrupt service routine. This
bit is not automatically cleared by hardware and must be cleared by software.
Bit1:
CCF1: PCA Module 1 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF1 interrupt is
enabled, setting this bit causes the CPU to vector to the PCA interrupt service routine. This
bit is not automatically cleared by hardware and must be cleared by software.
Bit0:
CCF0: PCA Module 0 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF0 interrupt is
enabled, setting this bit causes the CPU to vector to the PCA interrupt service routine. This
bit is not automatically cleared by hardware and must be cleared by software.
Rev. 2.9
167
C8051F300/1/2/3/4/5
SFR Definition 16.2. PCA0MD: PCA Mode
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
CIDL
WDTE
Bit7
Bit6
Reset Value
WDLCK
—
CPS2
CPS1
CPS0
ECF
01000000
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0xD9
Bit7:
CIDL: PCA Counter/Timer Idle Control.
Specifies PCA behavior when CPU is in Idle Mode.
0: PCA continues to function normally while the system controller is in Idle Mode.
1: PCA operation is suspended while the system controller is in Idle Mode.
Bit6:
WDTE: Watchdog Timer Enable
If this bit is set, PCA Module 2 is used as the Watchdog Timer.
0: Watchdog Timer disabled.
1: PCA Module 2 enabled as Watchdog Timer.
Bit5:
WDLCK: Watchdog Timer Lock
This bit locks/unlocks the Watchdog Timer Enable. When WDLCK is set, the Watchdog
Timer may not be disabled until the next system reset.
0: Watchdog Timer Enable unlocked.
1: Watchdog Timer Enable locked.
Bit4:
UNUSED. Read = 0b, Write = don't care.
Bits3–1: CPS2–CPS0: PCA Counter/Timer Pulse Select.
These bits select the clock source for the PCA counter
CPS2
CPS1
CPS0
Timebase
0
0
0
System clock divided by 12
0
0
1
System clock divided by 4
0
1
0
Timer 0 overflow
0
1
1
High-to-low transitions on ECI (max rate = system clock
divided by 4)
1
0
0
System clock
1
0
1
External clock divided by 8*
1
1
0
Reserved
1
1
1
Reserved
*Note: External oscillator source divided by 8 is synchronized with the system clock.
Bit0:
ECF: PCA Counter/Timer Overflow Interrupt Enable.
This bit sets the masking of the PCA Counter/Timer Overflow (CF) interrupt.
0: Disable the CF interrupt.
1: Enable a PCA Counter/Timer Overflow interrupt when CF (PCA0CN.7) is set.
Note: When the WDTE bit is set to ‘1’, the PCA0MD register cannot be modified. To change the
contents of the PCA0MD register, the Watchdog Timer must first be disabled.
168
Rev. 2.9
C8051F300/1/2/3/4/5
SFR Definition 16.3. PCA0CPMn: PCA Capture/Compare Mode
R/W
R/W
PWM16n ECOMn
Bit7
Bit6
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
CAPPn
CAPNn
MATn
TOGn
PWMn
ECCFn
00000000
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0xDA, 0xDB, 0xDC
PCA0CPMn Address:
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
PCA0CPM0 = 0xDA (n = 0)
PCA0CPM1 = 0xDB (n = 1)
PCA0CPM2 = 0xDC (n = 2)
PWM16n: 16-bit Pulse Width Modulation Enable.
This bit selects 16-bit mode when Pulse Width Modulation mode is enabled (PWMn = 1).
0: 8-bit PWM selected.
1: 16-bit PWM selected.
ECOMn: Comparator Function Enable.
This bit enables/disables the comparator function for PCA Module n.
0: Disabled.
1: Enabled.
CAPPn: Capture Positive Function Enable.
This bit enables/disables the positive edge capture for PCA Module n.
0: Disabled.
1: Enabled.
CAPNn: Capture Negative Function Enable.
This bit enables/disables the negative edge capture for PCA Module n.
0: Disabled.
1: Enabled.
MATn: Match Function Enable.
This bit enables/disables the match function for PCA Module n. When enabled, matches of the
PCA counter with a module's capture/compare register cause the CCFn bit in PCA0MD register
to be set to logic 1.
0: Disabled.
1: Enabled.
TOGn: Toggle Function Enable.
This bit enables/disables the toggle function for PCA Module n. When enabled, matches of the
PCA counter with a module's capture/compare register cause the logic level on the CEXn pin to
toggle. If the PWMn bit is also set to logic 1, the module operates in Frequency Output Mode.
0: Disabled.
1: Enabled.
PWMn: Pulse Width Modulation Mode Enable.
This bit enables/disables the PWM function for PCA Module n. When enabled, a pulse width
modulated signal is output on the CEXn pin. 8-bit PWM is used if PWM16n is cleared; 16-bit
mode is used if PWM16n is set to logic 1. If the TOGn bit is also set, the module operates in Frequency Output Mode.
0: Disabled.
1: Enabled.
ECCFn: Capture/Compare Flag Interrupt Enable.
This bit sets the masking of the Capture/Compare Flag (CCFn) interrupt.
0: Disable CCFn interrupts.
1: Enable a Capture/Compare Flag interrupt request when CCFn is set.
Rev. 2.9
169
C8051F300/1/2/3/4/5
SFR Definition 16.4. PCA0L: PCA Counter/Timer Low Byte
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0xF9
Bits 7–0: PCA0L: PCA Counter/Timer Low Byte.
The PCA0L register holds the low byte (LSB) of the 16-bit PCA Counter/Timer.
SFR Definition 16.5. PCA0H: PCA Counter/Timer High Byte
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
00000000
0xFA
Bits 7–0: PCA0H: PCA Counter/Timer High Byte.
The PCA0H register holds the high byte (MSB) of the 16-bit PCA Counter/Timer.
170
Rev. 2.9
C8051F300/1/2/3/4/5
SFR Definition 16.6. PCA0CPLn: PCA Capture Module Low Byte
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
00000000
0xFB, 0xE9, 0xEB
PCA0CPLn Address:
PCA0CPL0 = 0xFB (n = 0)
PCA0CPL1 = 0xE9 (n = 1)
PCA0CPL2 = 0xEB (n = 2)
Bits7–0: PCA0CPLn: PCA Capture Module Low Byte.
The PCA0CPLn register holds the low byte (LSB) of the 16-bit capture Module n.
SFR Definition 16.7. PCA0CPHn: PCA Capture Module High Byte
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0xFC, 0xEA, 0xEC
PCA0CPHn Address:
PCA0CPH0 = 0xFC (n = 0)
PCA0CPH1 = 0xEA (n = 1)
PCA0CPH2 = 0xEC(n = 2)
Bits7–0: PCA0CPHn: PCA Capture Module High Byte.
The PCA0CPHn register holds the high byte (MSB) of the 16-bit capture Module n.
Rev. 2.9
171
C8051F300/1/2/3/4/5
NOTES:
172
Rev. 2.9
C8051F300/1/2/3/4/5
17. C2 Interface
C8051F300/1/2/3/4/5 devices include an on-chip Silicon Labs 2-Wire (C2) debug interface to allow Flash
programming and in-system debugging with the production part installed in the end application. The C2
interface operates using only two pins: a bi-directional data signal (C2D) and a clock input (C2CK). See the
C2 Interface Specification for details on the C2 protocol.
17.1. C2 Interface Registers
The following describes the C2 registers necessary to perform Flash programming functions through the
C2 interface. All C2 registers are accessed through the C2 interface as described in the C2 Interface Specification.
C2 Register Definition 17.1. C2ADD: C2 Address
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Bits7–0: The C2ADD register is accessed via the C2 interface to select the target Data register for
C2 Data Read and Data Write commands.
Address
Description
0x00
Selects the Device ID register for Data Read instructions
0x01
Selects the Revision ID register for Data Read instructions
0x02
Selects the C2 Flash Programming Control register for Data
Read/Write instructions
0xB4
Selects the C2 Flash Programming Data register for Data
Read/Write instructions
0x80
Selects the Port0 register for Data Read/Write instructions
0xF1
Selects the Port0 Input Mode register for Data Read/Write instructions
0xA4
Selects the Port0 Output Mode register for Data Read/Write
instructions
C2 Register Definition 17.2. DEVICEID: C2 Device ID
Reset Value
00000100
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
This read-only register returns the 8-bit device ID: 0x04 (C8051F300/1/2/3/4/5).
Rev. 2.9
173
C8051F300/1/2/3/4/5
C2 Register Definition 17.3. REVID: C2 Revision ID
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
This read-only register returns the 8-bit revision ID: 0x00 (Revision A)
C2 Register Definition 17.4. FPCTL: C2 Flash Programming Control
Reset Value
00000000
Bit7
Bits7–0
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
FPCTL: Flash Programming Control Register
This register is used to enable Flash programming via the C2 interface. To enable C2 Flash
programming, the following codes must be written in order: 0x02, 0x01. Note that once C2
Flash programming is enabled, a system reset must be issued to resume normal operation.
C2 Register Definition 17.5. FPDAT: C2 Flash Programming Data
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Bits7–0: FPDAT: C2 Flash Programming Data Register
This register is used to pass Flash commands, addresses, and data during C2 Flash
accesses. Valid commands are listed below.
174
Code
Command
0x06
Flash Block Read
0x07
Flash Block Write
0x08
Flash Page Erase
0x03
Device Erase
Rev. 2.9
C8051F300/1/2/3/4/5
17.2. C2 Pin Sharing
The C2 protocol allows the C2 pins to be shared with user functions so that in-system debugging and
Flash programming functions may be performed. This is possible because C2 communication is typically
performed when the device is in the halt state, where all on-chip peripherals and user software are stalled.
In this halted state, the C2 interface can safely ‘borrow’ the C2CK (normally RST) and C2D (normally P0.7)
pins. In most applications, external resistors are required to isolate C2 interface traffic from the user application. A typical isolation configuration is shown in Figure 17.1.
C8051F300
/Reset (a)
C2CK (/RST)
Input (b)
C2D (P0.7)
Output (c)
C2 Interface Master
Figure 17.1. Typical C2 Pin Sharing
The configuration in Figure 17.1 assumes the following:
1. The user input (b) cannot change state while the target device is halted.
2. The RST pin on the target device is used as an input only.
Additional resistors may be necessary depending on the specific application.
Rev. 2.9
175
C8051F300/1/2/3/4/5
DOCUMENT CHANGE LIST
Revision 2.5 to Revision 2.6
•
Revision 2.3 to Revision 2.4
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Removed preliminary tag.
Changed all references of MLP package to
QFN package.
Pinout chapter: Figure 4.3: Changed title to
“Typical QFN-11 Solder Paste Mask.”
ADC chapter: Added reference to minimum
tracking time in the Tracking Modes section.
Comparators chapter: SFR Definition 7.3,
CPT0MD: Updated the register reset value and
the CP0 response time table.
CIP51 chapter: Updated IDLE mode and recommendations.
CIP51 chapter: Updated Interrupt behavior and
EA recommendations.
CIP51 chapter: SFR Definition 8.4, PSW: Clarified OV flag description.
CIP51 chapter: SFR Definition 8.8, IP register:
Changed “default priority order” to “low priority”
for low priority descriptions.
Reset Sources chapter: Clarified description of
VDD Ramp Time.
Reset Sources chapter: Table 9.2, “Reset Electrical Characteristics”: Added VDD Ramp Time
and changed “VDD POR Threshold” to “VDD
Monitor Threshold.”
FLASH Memory chapter: Clarified descriptions
of FLASH security features.
Oscillators chapter: Table 11.1 “Internal Oscillator Electrical Characteristics”: Added Calibrated Internal Oscillator specification over a
smaller temperature range.
Oscillators chapter: Clarified external crystal
initialization steps and added a specific
32.768 kHz crystal example.
Oscillators chapter: Clarified external capacitor
example.
SMBus chapter: Figure 14.5, SMB0CF register: Added a description of the behavior of
Timer 3 in split mode if SMBTOE is set.
Timers chapter: Changed references to “TL2”
and “TH2” to “TMR2L” and “TMR2H,” respectively.
Revision 2.6 to Revision 2.7
•
•
•
•
•
176
Removed non-RoHS compliant devices from
Table 1.1, “Product Selection Guide,” on
page 14.
Added MIN and MAX specifications for ADC
Offset Error and ADC Full Scale Error to
Table 5.1, “ADC0 Electrical Characteristics,”
on page 47.
Improved power supply specifications in
Table 3.1, “Global Electrical Characteristics,”
on page 25.
Added Section “10.4. Flash Write and Erase
Guidelines” on page 94.
Fixed minor typographical errors throughout.
Revision 2.7 to Revision 2.8
•
Updated block diagram on page 1.
Revision 2.8 to Revision 2.9
•
•
•
•
•
•
•
Revision 2.4 to Revision 2.5
•
Updated Table 1.1 Product Selection Guide to
include Lead-free information.
Fixed variables and applied formatting
changes.
Rev. 2.9
Updated QFN package drawings and notes.
Added SOIC-14 package information.
Added text to CPT0CN's SFR definition to indicate that the SFR is bit addressable.
Changed SMBus maximum transfer speed
from 1/10th system clock to 1/20th system
clock in SMBus section.
Added information pertaining to Slave
Receiver and Slave Transmitter states in Table
13.4.
Changed Table 5.1 and Figure 5.4 to indicate
that 11 SAR clocks are needed for a SAR conversion to complete.
Changed SCON0s SFR definition to show that
SCON0 bit 6 always resets to a value of 1.
C8051F300/1/2/3/4/5
NOTES:
Rev. 2.9
177
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Silicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers
using or intending to use the Silicon Laboratories products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific
device, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Laboratories
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