Si 5 3 1 0 - EVB EVALUATION BOARD FOR Si5310 PRECISION CLOCK M U L T I PL I E R / R E G E N E R A T O R I C Description Features The Si5310 evaluation board provides a platform for testing and characterizing the Silicon Laboratories Si5310 precision clock multiplier/regenerator IC. Single 2.5 V power supply Differential I/Os ac coupled Simple jumper configuration All high-speed I/Os are AC coupled to ease interfacing to industry standard test equipment. Function Block Diagram Spectrum Analyzer Pulse Generator ZC = 50 ZC = 50 + CLKOUT – + REFCLK – ZC = 50 ZC = 50 Si5310 Freq. Synth. ZC = 50 ZC = 50 + CLKIN – Scope + MULTOUT – MULTSEL PWRDN/CAL ZC = 50 ZC = 50 Spectrum Analyzer LOL REXT 10 k Jumpers Test Point Si5310-EVB Rev C Preliminary Rev. 0.71 1/16 Copyright © 2002 by Silicon Laboratories Si5310-EVB-071 Si5310-EVB Functional Description The evaluation board simplifies characterization of the Si5310 precision clock multiplier/regenerator IC by providing access to all of the Si5310 I/Os. Device performance can be evaluated by following the “Test Configuration” section. Specific performance metrics include jitter tolerance, jitter generation, and jitter transfer. Power supply The evaluation board requires one 2.5 V supply. Supply filtering is placed on the board to filter typical system noise components; however, initial performance testing should use a linear supply capable of supplying 2.5 V ±5% DC. CAUTION: The evaluation board is designed so that the body of the SMA jacks and GND are shorted. Care must be taken when powering the PCB at potentials other than GND at 0.0 V and VDD at 2.5 V relative to chassis GND. Self-Calibration only one side will degrade the performance of the Si5310 device. The CLKIN inputs are terminated on the die with 50 resistors. Note: The 50 termination is for each terminal/side of a differential signal, thus the differential termination is actually 50 + 50 = 100 . REFCLK REFCLK is used to center the frequency of the Si5310 DSPLL so that the device can lock to the CLKIN signal. For a given CLKIN rate, there are five choices for the REFCLK frequency. These five options are all multiples of the CLKIN frequency, as indicated in Table 1. The REFCLK frequency is automatically detected by the Si5310 device, so no digital control inputs are needed for REFCLK frequency selection. REFCLK may be synchronous or asynchronous with respect to CLKIN. However, REFCLK must be within ±100 PPM of the target CLKIN frequency multiple. REFCLK is ac coupled to the SMA jacks located on the top side of the evaluation board. The REFCLK inputs are terminated on the die with 50 resistors. The Si5310 device provides an internal self-calibration function that optimizes the loop gain parameters within the internal DSPLLTM. Self-calibration is initiated by a high-to-low transition of the PWRDN/CAL signal while a valid reference clock is supplied to the REFCLK input. On the Si5310-EVB board, a voltage detector IC is utilized to initiate self-calibration. The voltage detector drives the PWRDN/CAL signal low after the supply voltage has reached a specific voltage level. This circuit is described in Silicon Laboratories application note AN42. On the Si5310-EVB, the PWRDN/CAL signal is also accessible via a jumper located in the lower lefthand corner of the evaluation board. PWRDN/CAL is wired to the center post (signal post) between 2.5 V and GND. Note: The 50 termination is for each terminal/side of a differential signal, thus the differential termination is actually 50 + 50 = 100 . Device Power Down The jumper configurations for MULTSEL are indicated in Figure 1. The Si5310 device can be powered down via the PWRDN/CAL signal. When PWRDN/CAL is driven high (2.5 V) the evaluation board will draw minimal current. On the Si5310-EVB board, the PWRDN/CAL signal may be controlled via a jumper located in the lower left-hand corner of the evaluation board. PWRDN/CAL is wired to the center post (signal post) between 2.5 V and GND. MULTSEL MULTSEL is a binary input to the Si5310 device that selects the frequency range for the MULTOUT clock output. The MULTOUT output frequency is a multiple of the CLKIN input frequency. The frequency for MULTOUT will be in either the 150–167 MHz frequency range or the 600–668 MHz frequency range depending on the state of the MULTSEL signal as indicated in Table 1. On the Si5310 evaluation board, MULTSEL is controlled via a jumper located in the lower left-hand corner of the board. MULTSEL is wired to the center post (signal post) between 2.5 V and GND. CLKIN, CLKOUT, MULTOUT These high-speed I/Os are wired to the board perimeter on 30 mil (0.030 inch) 50 microstrip lines to the endlaunch SMA jacks as labeled on the PCB. These I/Os are AC coupled to simplify direct connection to a wide array of standard test hardware. Because each of these signals are differential both the positive (+) and negative (–) terminals must be terminated to 50 . Terminating 2 Rev. 0.71 Si5310-EVB Table 1. CLKIN, CLKOUT, MULTOUT, REFCLK Operating Ranges CLKIN Range (MHz) REFCLK = 2n x CLKIN ±100 ppm (see Note 2) CLKOUT MULTOUT 37.500–41.750 n = –2, –1, 0, 1, or 2 1xCLKIN 16xCLKIN 75.000–83.500 n = –3, –2, –1, 0, or 1 1xCLKIN 8xCLKIN 150.000–167.000 n = –4, –3, –2, –1, or 0 1xCLKIN 4xCLKIN 300.000–334.000 n = –5, –4, –3, –2, or –1 1xCLKIN 2xCLKIN 600.000–668.000 n = –6, –5, –4, –3, or –2 See Note 1 1xCLKIN 9.375–10.438 n = 0, 1, 2, 3, or 4 1xCLKIN 16xCLKIN 18.750–20.875 n = –1, 0, 1, 2, or 3 1xCLKIN 8xCLKIN 37.500–41.750 n = –2, –1, 0, 1, or 2 1xCLKIN 4xCLKIN 75.000–83.500 n = –3, –2, –1, 0, or 1 1xCLKIN 2xCLKIN 150.000–167.000 n = –4, –3, –2, –1, or 0 See Note 1 1xCLKIN MULTSEL 0 (MULTOUT = 600–668 MHz) 1 (MULTOUT = 150–167 MHz) Note: 1. The CLKOUT output is not valid for MULTOUT:CLKIN ratios of 1:1 (MULTOUT = 1 x CLKIN.) 2. The REFCLK input can be set to any one of the five CLKIN multiples indicated. The REFCLK input can be asynchronous to the CLKIN input, but must be within ±100 ppm of the stated CLKIN multiple. Test Configuration 2.5 V GN D 2.5 V GN D upper right-hand side of the evaluation board. MU L TSEL MU LTSEL PWR D N / C AL PWR D N / C AL MULTSEL High Range 60 0–668 MHz MULTSEL Low Range 15 0–167 MHz Figure 1. MULTSEL Jumper Configurations Loss-of-Lock (LOL) LOL is an indicator of the relative frequency between the REFCLK input, which is nominally a multiple of CLKIN, and an internally generated multiple of CLKIN. LOL will assert when the frequency difference is greater than ±600 PPM. In order to prevent LOL from deasserting prematurely, there is hysterisis in returning from the out of lock condition. LOL will be de-asserted (indicating a lock condition) when the frequency difference is less than ±300 PPM. LOL is wired to a test point which is located on the The characterization of clock sources typically involves measuring the output jitter or phase noise of the source. The overall output jitter is a function of the input jitter (jitter transfer) and the jitter generated (output jitter) by the internal PLL. Jitter can be measured using several different techniques and hardware. An oscilloscope, a spectrum analyzer, and a phase-noise analyzer are three such instruments capable of measuring output jitter. A spectrum analyzer is the best choice for measuring jitter transfer. Output Jitter Output jitter is a measure of the output clock short-term stability. In Figure 2, either position A or B can be used when measuring this parameter. Oscilloscope An oscilloscope can measure jitter from the clock edges within the trigger-to-capture bandwidth. Typically the jitter measured is expressed in picoseconds (peak-topeak and RMS) relative to the average edge position. A histogram can be used to capture the jitter distribution. Rev. 0.71 3 Si5310-EVB Spectrum Analyzer Jitter Transfer A spectrum analyzer measures the power of the carrier source and its associated phase noise. Analysis of the offset power distribution provides the data from which jitter can be derived. Simple integration of the offset power distribution over the desired offset range and filtered amplitudes provides a RMS jitter value. Jitter transfer is the ratio of the input jitter spectrum to the output jitter spectrum. Comparing the power levels from the input jitter spectrum with the output jitter spectrum provides the jitter transfer details. To characterize this parameter, a modulation source is added to the synthesizer. The FM modulation frequency is the jitter frequency, and its relative amplitude on the output verses the input describes the amount transferred. In Figure 2, position A should be used when measuring this parameter. Phase-noise Analyzer A phase-noise analyzer behaves similarly to a spectrum analyzer, but only provides details regarding the power offset from the carrier. Simple integration of the offset power distribution over the desired offset range and filtered amplitudes provides a RMS jitter value. 2.5 V + – Pulse Generator + REFCLK – CLKOUT + – B A Pulse Generator + CLKIN – M ULTOUT Si5310-EVB Synthesizer Signal Source + – Sam pling Scope Spectrum Analyzer Phase Noise Analyzer FM M odulation Signal Source Reference Frequency Figure 2. Test Configuration for Jitter Tolerance, Transfer, and Generation 4 Rev. 0.71 POS2 POS1 2 1 MKDSN 2,5/3-5,08 J9 1206 BLM31A601S L1 C13 0603 100pF 2 2 2 SIG SIG SIG 1 JC 142-0701-801 BODY J2 1 JC 142-0701-801 BODY J1 JC 142-0701-801 1 JC 142-0701-801 BODY J8 2 SIG 1 C16 0603 100pF BODY J7 C15 0603 100pF VDD 2 C9 VDD REXT REFCLK- REFCLK+ CLKIN- CLKIN+ NC MULTSEL PWRDN/CAL R1 0603 10k 1 5 4 10 9 20 19 15 Figure 3. Si5310-EVB Schematic 0603 0.1uF C7 0603 0.1uF C8 0603 0.1uF C6 0603 0.1uF C5 0603 2.5k R2 0805 Do Not Install VDD VDD MAX6376XR23-T OUT V? U4 tantalum 10uF C12 1 GND 3 VCC 2.5V JP2 2 7 11 14 LOL VDD Si5310 MULTOUT+ MULTOUT- CLKOUT+ CLKOUT- U5 VDDA VDDB VDDC VDDD GNDA GNDB GNDC Rev. 0.71 3 8 18 JP1 17 16 13 12 6 JP4 0603 0.1uF C1 0603 0.1uF C2 0603 0.1uF C3 0603 0.1uF C4 1 1 2 2 JC 142-0701-801 SIG BODY JC 142-0701-801 2 JC 142-0701-801 SIG SIG J6 2 JC 142-0701-801 BODY J4 SIG BODY BODY J5 1 1 J3 Si5310-EVB 5 Si5310-EVB Bill of Materials Si5310EVB Assy Rev C-01 BOM Reference C1,C2,C3,C4,C5,C6, C7,C8 C12 C13,C15,C16 JP1,JP4 JP2 J1,J2,J3,J4,J5,J6,J7, J8 J9 L1 R1 R2 U4 U5 PCB No Load C9 6 Part Desc Part Number Manufacturer CAP, SM, 0.1uF, 0603 C0603X7R160-104KNE CAP, SM, 10 uF, TANTALUM, 3216 TA010TCM106KAR CAP, SM, 100 pF, 16V, 0603 C0603C0G500101KNE CONNECTOR, HEADER, 2X1 2340-6111TN or 2380-6121TN CONNECTOR, HEADER, 3X1 2340-6111TN or 2380-6121TN Venkel Venkel Venkel 3M 3M CONNECTOR, SMA, SIDE MOUNT 901-10003 CONNECTOR, POWER, 2 POS 1729018 RESISTOR, SM, 0 OHM, 1206 CR1206-8W-000T RESISTOR, SM, 10K, 1%, 0603 CR0603-16W-1002FT RESISTOR, SM, 2.55K, 1%, 0603 CR0603-16W-2551FT MAX6376XR23-T MAX6376XR23-T Si5310 SI5310-BM PRINTED CIRCUIT BOARD Si5310-EVB PCB Rev C Amphenol Phoenix Contact Venkel Venkel Venkel Maxim Silicon Laboratories Silicon Laboratories SPARE,0805 Rev. 0.71 Si5310-EVB Figure 4. Si5310 Silkscreen Rev. 0.71 7 Si5310-EVB Figure 5. Si5310 Component Side 8 Rev. 0.71 Si5310-EVB Figure 6. Si5310 Solder Side Rev. 0.71 9 Si5310-EVB Document Change List Revision 0.7 to Revision 0.71 Added bill of materials. Evaluation Board Assembly Revision History 10 Assembly Level PCB Si5310 Device Assembly Notes B-01 B B Assemble per BOM rev B-01. C-01 C C Assemble per BOM rev C-01. Rev. 0.71 Si5310-EVB Notes: Rev. 0.71 11 ClockBuilder Pro One-click access to Timing tools, documentation, software, source code libraries & more. Available for Windows and iOS (CBGo only). www.silabs.com/CBPro Timing Portfolio www.silabs.com/timing SW/HW Quality Support and Community www.silabs.com/CBPro www.silabs.com/quality community.silabs.com Disclaimer Silicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or intending to use the Silicon Laboratories products. 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