Si 5 0 2 0 - EVB E V A L U A T I O N B O A R D F O R S i 5 0 2 0 S i P H Y ™ M U L TI -R A T E S O N E T / S D H C L O C K A N D D ATA R E C O V E R Y I C Description Features The Si5020 evaluation board provides a platform for testing and characterizing Silicon Laboratories’ Si5020 SiPHY™ multi-rate SONET/SDH clock and data recovery IC. The Si5020 CDR supports OC-48/12/3, STM-16/4/1, Gigabit Ethernet, and 2.7 Gbps FEC rates. Single 2.5 V power supply Differential I/Os ac coupled Simple jumper configuration All high-speed I/Os are AC coupled to ease interfacing to industry standard test equipment. Function Block Diagram Jitter Analyzer Pulse Generator ZC = 50 ZC = 50 + REFCLK – + CLKOUT – ZC = 50 ZC = 50 Si5020 Pattern Generator ZC = 50 ZC = 50 + DATAIN – RATESEL0 RATESEL1 PWRDN/CAL Scope + DATAOUT – ZC = 50 ZC = 50 Pattern Analyzer LOL REXT 10 k Jumpers Test Point Si5020-EVB Rev C Rev. 1.0 12/02 Copyright © 2016 by Silicon Laboratories Si5020-EVB-10 Si5020-EVB Functional Description The evaluation board simplifies characterization of the Si5020 Clock and Data Recovery (CDR) device by providing access to all of the Si5020 I/Os. Device performance can be evaluated by following the Test Configuration section below. Specific performance metrics include jitter tolerance, jitter generation, and jitter transfer. Power Supply The evaluation board requires one 2.5 V supply. Supply filtering is placed on the board to filter typical system noise components, however, initial performance testing should use a linear supply capable of supplying 2.5 V ±5% dc. CAUTION: The evaluation board is designed so that the body of the SMA jacks and GND are shorted. Care must be taken when powering the PCB at potentials other than GND at 0.0 V and VDD at 2.5 V relative to chassis GND. To improve the DATAOUT eye-diagram, short 100 transmission line segments precede the 50 highspeed traces. These segments increase the interface bandwidth from the chip to the 50 traces and reduce data inter-symbol-interference. Please refer to Silicon Laboratories application note AN43 for more details. Note: The 50 termination is for each terminal/side of a differential signal, thus the differential termination is actually 50 + 50 = 100 . REFCLK REFCLK is used to center the frequency of the DSPLL™ so that the device can lock to the data. Ideally the REFCLK frequency should be 1/128th, 1/32nd, or 1/16th the VCO frequency and must have a frequency accuracy of ±100 PPM. Internally, the CDR automatically recognizes the REFCLK frequency within one of these three frequency ranges. Typical REFCLK frequencies are given in Table 1. REFCLK is AC coupled to the SMA jacks located on the top side of the evaluation board. Self-Calibration The Si5020 device provides an internal self-calibration function that optimizes the loop gain parameters within the internal DSPLLTM. Self-calibration is initiated by a high-to-low transition of the PWRDN/CAL signal while a valid reference clock is supplied to the REFCLK input. On the Si5020-EVB board, a voltage detector IC is utilized to initiate self-calibration. The voltage detector drives the PWRDN/CAL signal low after the supply voltage has reached a specific voltage level. This circuit is described in Silicon Laboratories application note AN42. On the Si5020-EVB, the PWRDN/CAL signal is also accessible via a jumper located in the lower lefthand corner of the evaluation board. PWRDN/CAL is wired to the signal post adjacent to the 2.5 V post. Device Powerdown The CDR can be powered down via the PWRDN/CAL signal. When asserted the evaluation board will draw minimal current. PWRDN/CAL is controlled via one jumper located in the lower left-hand corner of the evaluation board. PWRDN/CAL is wired to the signal post adjacent to the 2.5 V post. CLKOUT, DATAOUT, DATAIN These high-speed I/Os are wired to the board perimeter on 30 mil (0.030 inch) 50 microstrip lines to the endlaunch SMA jacks as labeled on the PCB. These I/Os are AC coupled to simplify direct connection to a wide array of standard test hardware. Because each of these signals are differential both the positive (+) and negative (–) terminals must be terminated to 50 . Terminating only one side will adversely degrade the performance of the CDR. The inputs are terminated on the die with 50 resistors. 2 Table 1. Typical REFCLK Frequencies SONET/SDH Gigabit Ethernet SONET/ SDH with Ratio of 15/14 FEC REFCLK VCO to 19.44 MHz 19.53 MHz 20.83 MHz 128 77.76 MHz 78.125 MHz 83.31 MHz 32 155.52 MHz 156.25 MHz 166.63 MHz 16 RATESEL RATESEL is used to configure the CDR to recover clock and data at different data rates. RATESEL is a two bit binary input that is controlled via two jumpers located in the lower left-hand corner of the evaluation board. RATESEL0/1 are wired to the center posts (signal post) between 2.5 V and GND. For example, the OC-48 data rate is selected by jumping RATESEL0 to 0.0 V and RATESEL1 to 0.0 V. The table given on the evaluation board lists approximate data rates for the jumper configurations shown in Figure 1. Applications with data rates within ±7% of the given data rate are also accommodated. Rev. 1.0 RATESEL1 RATESEL1 RATESEL0 RATESEL0 PWRDN/ CAL PWRDN/ CAL GND 2.5 V 1244 Mbps 2.5 V GND 2488 Mbps Jitter Generation: Referring to Figure 2, this test requires a pattern generator, a clock source (synthesizer signal source), a jitter analyzer, and a pulse generator (all unconnected high-speed outputs must be terminated to 50 ). During this test, there is no modulation of the Data Clock, so the data that is sent to the CDR is jitter free. The Jitter Analyzer measures the RMS and peak-to-peak jitter on the CDR CLKOUT. Thus, any jitter measured is jitter generated by the CDR. 2.5 V GND 2.5 V GND Si5020-EVB RATESEL1 RATESEL1 RATESEL0 RATESEL0 PWRDN/ CAL PWRDN/ CAL 622 Mbps 155 Mbps Figure 1. RATESEL Jumper Configurations Loss-of-Lock (LOL) LOL is an indicator of the relative frequency between the data and the REFCLK. LOL will assert when the frequency difference is greater than ±600 PPM. In order to prevent LOL from de-asserting prematurely, there is hysterisis in returning from the out-of-lock condition. LOL will be de-asserted when the frequency difference is less than ±300 PPM. Jitter Transfer: Referring to Figure 2, this test requires a pattern generator, a clock source (synthesizer signal source), a modulation source, a jitter analyzer, and a pulse generator (all unconnected high-speed outputs must be terminated to 50 ). During this test the Jitter Analyzer modulates the data pattern and data clock reference. The modulated data clock reference is compared with the CLKOUT of the CDR. Jitter on CLKOUT relative to the jitter on the data clock reference is plotted versus modulation frequency at predefined jitter amplitudes. LOL is wired to a test point which is located on the upper right-hand side of the evaluation board. Test Configuration The three critical tests that are typically performed on a CDR device are jitter transfer, jitter tolerance, and jitter generation. By connecting the Si5020 Evaluation Board as shown in Figure 2, all three measurements can be easily made. REFCLK should be within ±100 PPM of the frequency selected from Table 1. RATESEL must be configured to match the desired data rate, and PWRDN/CAL must be unjumpered. Jitter Tolerance: Referring to Figure 2, this test requires a pattern generator, a clock source (synthesizer signal source), a modulation source, a jitter analyzer, a pattern analyzer, and a pulse generator (all unconnected high-speed outputs must be terminated to 50 ). During this test the Jitter Analyzer causes a modulation on the data pattern which drives the DATAIN ports of the CDR. The Bit-Error-Rate (BER) is monitored on the Pattern Analyzer. The modulation (jitter) frequency and amplitude is recorded when the BER approaches a specified threshold. Rev. 1.0 3 Si5020-EVB Pulse Generator Scope DATAOUT– Pattern Analyzer GPIB 2.5 V + – REFCLK+ REFCLK– DATAIN+ + REFCLK – + DATAIN – DATAIN– Pattern Generator DATAOUT + – CLKOUT + – Si5020-EVB DATAOUT+ CLKOUT+ CLKOUT– Jitter Analyzer Data Clock+ GPIB GPIB Clock Synthesizer Signal Source FM Modulation Source GPIB Figure 2. Test Configuration for Jitter Tolerance, Transfer, and Generation 4 Rev. 1.0 POS2 POS1 2 1 MKDSN 2,5/3-5,08 J9 1206 BLM31A601S L1 C13 0603 100pF 2 2 2 SIG SIG SIG 1 JC 142-0701-801 BODY J2 1 JC 142-0701-801 BODY J1 JC 142-0701-801 1 JC 142-0701-801 BODY J8 2 SIG 1 C16 0603 100pF BODY J7 C15 0603 100pF VDD 2 C9 VDD 1 5 4 10 9 20 19 15 REXT REFCLK- REFCLK+ DIN- DIN+ RATESEL1 RATESEL0 PWRDN/CAL R1 0603 10k VDD JP3 Figure 3. Si5020 Schematic 0603 0.1uF C7 0603 0.1uF C8 0603 0.1uF C6 0603 0.1uF C5 0603 2.5k R2 0805 Do Not Install VDD VDD MAX6376XR23-T OUT V? U4 tantalum 10uF C12 1 GND 3 VCC 2.5V JP2 2 7 11 14 DOUT+ DOUT- LOL VDD Si5020 CLKOUT+ CLKOUT- U5 VDDA VDDB VDDC VDDD GNDA GNDB GNDC Rev. 1.0 3 8 18 JP1 17 16 13 12 6 JP4 0603 0.1uF C1 0603 0.1uF C2 0603 0.1uF C3 0603 0.1uF C4 1 1 2 2 JC 142-0701-801 SIG BODY JC 142-0701-801 2 JC 142-0701-801 SIG SIG J6 2 JC 142-0701-801 BODY J4 SIG BODY BODY J5 1 1 J3 Si5020-EVB 5 Si5020-EVB Bill of Materials Si5020EVB Assy Rev B-02 BOM Reference C1,C2,C3,C4,C5, C6,C7,C8 C12 C13,C15,C16 JP1,JP4 JP2,JP3 J1,J2,J3,J4,J5,J6, J7,J8 J9 L1 R1 R2 U4 U5 PCB No Load C9 6 Part Desc Part Number Manufacturer CAP, SM, 0.1uF, 0603 CAP, SM, 10 uF, TANTALUM, 3216 CAP, SM, 100 pF, 16V, 0603 CONNECTOR, HEADER, 2X1 CONNECTOR, HEADER, 3X1 C0603X7R160-104KNE TA010TCM106KAR C0603C0G500101KNE 2340-6111TN or 2380-6121TN 2340-6111TN or 2380-6121TN Venkel Venkel Venkel 3M 3M CONNECTOR, SMA, SIDE MOUNT CONNECTOR, POWER, 2 POS RESISTOR, SM, 0 OHM, 1206 RESISTOR, SM, 10K, 1%, 0603 RESISTOR, SM, 2.55K, 1%, 0603 MAX6376XR23-T Si5020 PRINTED CIRCUIT BOARD 901-10003 1729018 CR1206-8W-000T CR0603-16W-1002FT CR0603-16W-2551FT MAX6376XR23-T SI5020-BM Si5020-EVB PCB Rev C SPARE,0805 Rev. 1.0 Amphenol Phoenix Contact Venkel Venkel Venkel Maxim Silicon Laboratories Silicon Laboratories Si5020-EVB Figure 4. Si5020 Silkscreen Rev. 1.0 7 Si5020-EVB Figure 5. Si5020 Component Side 8 Rev. 1.0 Si5020-EVB Figure 6. Si5020 Solder Side Rev. 1.0 9 Si5020-EVB Document Change List Revision 0.41 to Revision 1.0 “Preliminary” language removed. Evaluation Board Assembly Revision History 10 Assembly Level PCB Si5020 Device Assembly Notes A-01 A A Assemble per BOM rev A-01. B-01 B B Assemble per BOM rev B-01. B-02 C B Assemble per BOM rev B-02. Rev. 1.0 Si5020-EVB Notes: Rev. 1.0 11 ClockBuilder Pro One-click access to Timing tools, documentation, software, source code libraries & more. Available for Windows and iOS (CBGo only). www.silabs.com/CBPro Timing Portfolio www.silabs.com/timing SW/HW Quality Support and Community www.silabs.com/CBPro www.silabs.com/quality community.silabs.com Disclaimer Silicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or intending to use the Silicon Laboratories products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Laboratories reserves the right to make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included information. 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