Si 5 3 6 4 - EVB EVALUATION BOARD FOR Si5364 SONET/SDH PRECISION PORT CARD CLOCK IC Description Features The Si5364-EVB is the evaluation board for the Si5364 SONET/SDH Precision Port Card Clock IC. This evaluation board provides access to all signals associated with normal operation of the device. This circuit board also is designed to provide access to signals that are reserved for factory testing purposes. Si5364 device can be powered directly from either a 3.3 or 2.5 V supply Differential I/Os ac-coupled on board Differential inputs terminated on board Control input signals are switch/jumper configurable Status outputs brought out to headers for access LED status indicators reflect state of status outputs LED status indicators can be disabled for device power measurements Function Block Diagram 2.5 V LDO Regulator 3.3 V or 2.5 V Supply Control Input Jum per Header Power Supply Input Status O utput Signal Header LED S tatus Indicators LED Drivers t e x t 3.3 V/2.5 V S upply S election C LKO U T_1 t e x t C LKIN _A Control Inputs Status O utputs + 50 – 50 + 50 – 50 + 50 – 50 + 50 – 50 CLKO UT_1 t e x t C LKO U T_2 + CLKIN_A – CLKO UT_2 + C LKIN _B t e x t Si5364 CLKIN_B – CLKO UT_3 + RE F/CLKIN_F t e x t C LKO U T_3 – CLKO UT_4 t e x t R EF/C LKIN_F Factory Test Input Header Preliminary Rev. 0.33 06/02 Factory Test O utput Header Factory Test S erial Input Factory Test Serial O utput Factory Test Analog O utput Copyright © 2002 by Silicon Laboratories t e x t C LKO U T_4 t e x t Si5364-EVB-033 Si5364-EVB Functional Description The Si5364-EVB is the evaluation board for the Si5364 SONET/SDH Precision Port Card Clock IC. This evaluation board provides access to all signals associated with normal operation of the device. This circuit board also is designed to provide access to signals that are reserved for factory testing purposes. Power Supply Selection and Connections The Si5364-EVB board is switch selectable for operation using either a single 3.3 V or a single 2.5 V supply. For operation using a 3.3 V supply, configure the board as follows: 1. Remove power supply connections from the VDD and GND terminals of the board’s power connector, J15. 2. Remove the connection between VDD33 and VDD25 by removing the jumper on header JPI. 3. Set VSEL33 high by sliding the switch on the VSEL33 (JP3) to the side marked “1”. 4. Connect the power supply ground lead and 3.3 V supply lead to the GND and VDD terminals of the board’s power connector, J15. For operation using a 2.5 V supply, configure the board as follows: 1. Remove power supply connections from the VDD and GND terminals of the board’s power connector, J15. 2. Set VSEL33 low by sliding the switch on the VSEL33 (JP3) to the side marked “0”. 3. Connect VDD33 and VDD25 by installing a jumper between one of the 3.3 V pins and one of the 2.5 V pins on header JPI. 4. Connect the power supply ground lead and 2.5 V supply lead to the GND and VDD terminals of the board’s power connector, J15. Power Consumption Typical supply current draw for the Si5364-EVB with LED indicators disabled and one clock output enabled is 120 mA. Each additional clock output that is enabled adds approximately 15 mA. LED indicators, when enabled, adds approximately 8 mA for each indicator that is illuminated. Si5364 Control Inputs Most of the control inputs to the Si5364 are routed to the center post of a SPDT switch located at JP1. The switches are wired with the signal on the center pin, VDD33 on one side pin, and GND on the other side pin. Each input is easily configurable to a high or a low state. There are three inputs to the Si5364 that are not routed to switches at JP1. Two of these signals are INCDELAY and 2 DECDELAY. They are routed to push button switches SW1 and SW2, respectively, through headers JP4 and JP5. Inverters U6 and U7 condition the action of these switches before being sent to the Si5364 device. Pressing and releasing these switches provides a single pulse to the control input for the Si5364. This is a convenient method for evaluating the operation of the INCDELAY and DECDELAY functions. Resistors R26 and R27 allow the user to disconnect the switches from the device and drive the inputs from another source. JP4 and JP5 are not populated when shipped from the factory. If an external source is required to drive the INCDELAY and DECDELAY inputs, then populate these two headers. This provides the user a convenient location to connect the source. Each LVTTL input on the Si5364 device has an internal pull-down mechanism. The control inputs default to a low state if no device drives the input. RSTN/CAL Settings for Normal Operation and Self-Calibration The RSTN/CAL signal is an LVTTL input to the Si5364 and has an on-chip pull down mechanism. This pin must be set high to enable normal operation of the Si5364 device. Setting RSTN/CAL low forces the Si5364 into a reset state. A low-to-high transition of RSTN/CAL enables the part and initiates a self-calibration sequence. The Si5364 device automatically initiates a selfcalibration at power-up if the RSTN/CAL signal is held high. A self-calibration of the device also can be manually initiated by pushing the RSTN/CAL switch, SW3, then releasing. Self-calibration must be initiated manually after changing the state of either the BWSEL[1:0] control inputs or the FEC[1:0] inputs. Whether manually initiated or automatically initiated at power-up, the self-calibration process requires the presence of a valid input clock. If the self-calibration is initiated without a valid clock present, the device waits for a valid clock before completing the self-calibration. The Si5364 clock outputs drift to the lower end of the operating frequency range as the device waits for a valid clock. After the input clock is validated, the calibration process runs to completion, the device locks to the input, and the clock outputs shifts to their target frequencies. Subsequent losses of the input clock do not require recalibration. If the clock input is lost after self-calibration, the device enters Digital Hold mode. When the input clock returns, the device re-locks to the input clock without performing a self-calibration. Rev. 0.33 Si5364-EVB Status Signals The status outputs from the Si5364 device are each routed to one pin of a two-row header, JP11. The header is wired so that the signals are present on one side of the header and a ground reference is present on the other. The letter S marks the row of signal pins and the row of ground pins is marked with the letter G. On the Si5364-EVB board, the status outputs are also routed to two buffer/driver ICs (U4 and U5) that drive one LED indicator for each status signal. Enabling and Disabling the Status Indicator LEDs The status LED driver outputs can be disabled. The disabled driver outputs are placed into a high impedance state to get a more accurate measurement of the current/ power being consumed by the Si5364 device. The LED drivers are enabled when the switch at JP9 is switched to ON. The driver outputs are disabled when the switch is set to OFF. Factory Test Headers Locations for headers JP8 and JP10 are included on the SI5364-EVB for factory testing. For customer evaluation, these locations are not populated. Differential Clock Input Signals tantalum capacitor. This is the suggested compensation circuit for Si5364 devices. There are two considerations for selecting this combination of compensation resistor and capacitor. First, is the stability of the regulator. The second is noise filtering. The acceptable range for the time constant at this node is 15 s to 50 s. The capacitor used on the board is a 33 F capacitor with an ESR of .8 . This yields a time constant of 26.4 s. The designer could decide to use a 330 F capacitor with an ESR of .15 . This yields a time constant of 49.5 s. Each of these cases provide a compensation circuit that makes the output of the regulator stable. The second issue is noise filtering. For this, more capacitance is usually better. For the two cases described above, the 330 F case provides greater noise filtering. However, the large case size of the 330 F capacitor might make it impractical for many applications. The Si5364 device is specified with the 33 F cap. Default Jumper Settings The default jumper settings for the Si5364-EVB board are given in Table 1 on page 4. These settings configure the board for operation from a 3.3 V supply. The differential clock inputs to the Si5364-EVB are terminated on the board at a location near the input SMA connectors. The input SMA connectors are ac coupled to the termination circuit. The termination circuit consists of two 50 resistors and a 0.1 F capacitor, connected so that the positive and negative inputs of the differential pair each see a 50 termination to "ac ground", and the lineto-line termination impedance is 100 . The signals are then routed to the Si5364 device. Single-ended operation is accomplished by supplying a signal to one of the differential inputs, typically the positive input. The other input should be shorted to ground with an SMA shorting plug. Differential Clock Output Signals The differential clock outputs from the Si5364 device are routed to the perimeter of the circuit board using 50 transmission structures. The capacitors that provide accoupling are located near the clock output SMA connectors. Internal Regulator Compensation The Si5364-EVB contains pad locations for a resistor and a capacitor between the VDD25 node and ground. The resistor pads are populated with a 0 resistor. The capacitor pads are populated with a low ESR 33 F Rev. 0.33 3 Si5364-EVB Table 1. Si5364-EVB Assembly Rev B-01 Default Jumper/Switch Settings 4 Location Signal State Notes JP3 VSEL33 1 Si5364 device Internal Regulator enabled JP12 VDD33 Open Si5364 device VDD33 pins not connected to 2.5 V supply plane JP1 VALTIME 0 100 ms Validation Time SMC/S3N 1 SONET Minimum Clock criteria selected DSBLFOS 0 Frequency Offset alarms enabled RVRT 1 Revertive clock switching mode selected AUTOSEL 1 Automatic input Selection enabled DSBLFSYNC 0 FSYNC output enabled MANCNTRL[0] 0 CLKIN_A would be selected if AUTOSEL = 0 MANCNTRL[1] 1 CLKIN_A would be selected if AUTOSEL = 0 FEC[0] 0 FEC scaling factor = 1/1 (no FEC scaling) FEC[1] 0 FEC scaling factor = 1/1 (no FEC scaling) BWSEL[0] 1 Loop Bandwidth = 6400 Hz BWSEL[1] 1 Loop Bandwidth = 6400 Hz FRQSEL_1[0] 1 CLKOUT_1 = 622 MHz Range FRQSEL_1[1] 1 CLKOUT_1 = 622 MHz Range FRQSEL_2[0] 1 CLKOUT_2 = 622 MHz Range FRQSEL_2[1] 1 CLKOUT_2 = 622 MHz Range FRQSEL_3[0] 1 CLKOUT_3 = 622 MHz Range FRQSEL_3[1] 1 CLKOUT_3 = 622 MHz Range FRQSEL_4[0] 1 CLKOUT_4 = 622 MHz Range FRQSEL_4[1] 1 CLKOUT_4 = 622 MHz Range FXD_DELAY 0 Fixed Delay mode disabled JP9 LED ENABLE_N ON LED Status Indicators enabled JP2 SYNCIN No Jumper Installed Header for SYNCIN input signal JP15 FSYNC No Jumper Installed Header for FSYNC output signal Rev. 0.33 Rev. 0.33 SW1 101-0161 3.3V 1 3 1 3 2 2 62 59 56 53 50 47 44 41 38 35 32 29 26 23 20 17 14 11 8 5 2 2 2 U6 3 5 3.3V 4 74SZ14 VSEL33 0.1uf, 0603 C1 1x3 HEADER JP3 SYNCIN FXDDELAY FRQSEL_4[1] FRQSEL_4[0] FRQSEL_3[1] FRQSEL_3[0] FRQSEL_2[1] FRQSEL_2[0] FRQSEL_1[1] FRQSEL_1[0] BWSEL[1] BWSEL[0] FEC[1] FEC[0] MANCNTRL[1] MANCNTRL[0] DSBLFSYNC AUTOSEL RVRT DSBLFOS SMC/S3N VALTIME 1 3 JP4 1 3 0, 0402 R26 3.3V 2 1 3 4 6 7 9 10 12 13 15 16 18 19 21 2 20 17 14 11 8 5 2 20 17 14 11 8 5 2 K1 J3 J4 J6 J7 J10 J9 G9 H9 A2 B2 A3 B3 A4 B4 H2 B1 C10 K2 J2 B9 B5 C5 H1 C3 C4 D3 C2 C1 G1 G2 E2 E1 U1 Si5364_revB 1 3 5 7 1 3 5 7 JP10 2 4 6 8 2 4 6 8 2 0.1uf, 0603 C2 U7 3 5 4 74SZ14 1 3 JP5 1 3 2 0, 0402 R27 2 R28 3.3V 101-0161 SW3 RES/TMODE[0] RES/TMODE[1] RES/TMODE[2] RES/REFIN[0] RES/REFIN[1] RES/REFIN[2] RES/PFDTEST RES/DEV_ID[0] RES-DEV)ID[1] REV/DEV_ID[2] RES/ANAOUT LOS_A LOS_B LOS_F FOS_A FOS_B A_ACTV B_ACTV F_ACTV DH_ACTV CAL_ACTV FSYNC CLKOUT_1+ CLKOUT_1CLKOUT_2+ CLKOUT_2CLKOUT_3+ CLKOUT_3CLKOUT_4+ CLKOUT_4- 4.99k, 0603 C9 C8 C7 D2 F1 F2 D1 B8 B7 B6 C6 F10 E10 D10 A5 A6 A7 A8 A9 A10 B10 J1 K4 K3 K6 K7 K10 K9 H10 G10 DECDELAY RES/TMODE[0] RES/TMODE[1] RES/TMODE[2] RES/REFIN[0] RES/REFIN[1] RES/REFIN[2] RES/PFDTEST RES/DEV_ID[0] RES/DEV_ID[1] RES/DEV_ID[2] RES/ANAOUT LOS_A LOS_B LOS_F FOS_A FOS_B A_ACTV B_ACTV F_ACTV DH_ACTV CAL_ACTV FSYNC CLKOUT_1+ CLKOUT_1CLKOUT_2+ CLKOUT_2CLKOUT_3+ CLKOUT_3CLKOUT_4+ CLKOUT_4- 1 3 JP6 1 3 0, 0402 R29 2 2 DH_ACTV CAL_ACTV F_ACTV B_ACTV A_ACTV FOS_A FOS_B LOS_F LOS_B LOS_A 10 11 13 15 17 2 4 6 8 20 10 11 13 15 17 2 4 6 8 20 2 2 2OE 2Y1 2Y2 2Y3 2Y4 1Y1 1Y2 1Y3 1Y4 1OE 19 9 7 5 3 18 16 14 12 1 19 9 7 5 3 18 16 14 12 1 1x3 HEADER JP9 U5 1 3 GND 2A1 2A2 2A3 2A4 1A1 1A2 1A3 1A4 VCC 1 3 2OE 2Y1 2Y2 2Y3 2Y4 1Y1 1Y2 1Y3 1Y4 U4 74LCX244 GND 2A1 2A2 2A3 2A4 1A1 1A2 1A3 1A4 1OE 74LCX244 VCC RSTN/CAL 3.3V Figure 1. Si5364-EVB Typical Application Schematic (page 1 of 2) 101-0161 SW2 R3 100k, 0402 3.3V For engineering test purposes only. Not needed for customer application. RES/PFDTEST RES/REFIN[2] RES/REFIN[1] RES/REFIN[0] RES/TMODE[2] RES/TMODE[1] RES/DEV_ID[0] RES-DEV)ID[1] REV/DEV_ID[2] RES/ANAOUT 10k, 0603 R1 REXT FRQSEL_1[0] FRQSEL_1[1] FRQSEL_2[0] FRQSEL_2[1] FRQSEL_3[0] FRQSEL_3[1] FRQSEL_4[0] FRQSEL_4[1] BWSEL[0] BWSEL[1] FEC[0] FEC[1] MANCNTRL[0] MANCNTRL[1] DSBLFSYNC AUTOSEL RVRT RSTN/CAL VALTIME SMC/S3N DSBLFOS FXDDELAY SYNCIN INCDELAY DECDELAY VSEL33 CLKIN_A+ CLKIN_ACLKIN_B+ CLKIN_BREF/CLKIN_F+ REF/CLKIN_F- RES/TMODE[0] INCDELAY 7x3 HEADER 1 3 4 6 7 9 10 12 13 15 16 18 19 21 JP8 FRQSEL_1[0] FRQSEL_1[1] FRQSEL_2[0] FRQSEL_2[1] FRQSEL_3[0] FRQSEL_3[1] FRQSEL_4[0] FRQSEL_4[1] BWSEL[0] BWSEL[1] FEC[0] FEC[1] MANCNTRL[0] MANCNTRL[1] DSBLFSYNC AUTOSEL RVRT RSTN/CAL VALTIME SMC/S3N DSBLFOS FXDDELAY SYNCIN INCDELAY DECDELAY VSEL33 CLKIN_A+ CLKIN_ACLKIN_B+ CLKIN_BREF/CLKIN_F+ REF/CLKIN_F- 2.5V E4 E5 E6 F4 F5 F6 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 3.3V E7 E8 E9 F7 F8 F9 G4 G5 G6 G7 G8 H8 J8 K8 VDD25 VDD25 VDD25 VDD25 VDD25 VDD25 VDD25 VDD25 VDD25 VDD25 VDD25 VDD25 VDD25 VDD25 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND D4 D5 D6 D7 D8 D9 E3 F3 G3 H3 H4 H5 H6 H7 J5 K5 2 1x3 HEADER JP2 JP1 R2 100k, 0402 1 3 1 3 1 3 4 6 7 9 10 12 13 15 16 18 19 21 22 24 25 27 28 30 31 33 34 36 37 39 40 42 43 45 46 48 49 51 52 54 55 57 58 60 61 63 R6 R7 R8 D3 D4 D5 FSYNC LOS_A LOS_B LOS_F FOS_A FOS_B A_ACTV B_ACTV F_ACTV DH_ACTV CAL_ACTV 3.3V 20 18 16 14 12 10 8 6 4 2 20 18 16 14 12 10 8 6 4 2 2 19 17 15 13 11 9 7 5 3 1 19 17 15 13 11 9 7 5 3 1 C4 0.1uf, 0603 1k, 0603 120, 0603 120, 0603 120, 0603 120, 0603 1k, 0603 1k, 0603 1k, 0603 1k, 0603 1k, 0603 JP15 1 JP11 C3 0.1uf, 0603 R13 R12 D10 R11 D9 R10 D8 D7 R9 R5 D2 D6 R4 D1 Si5364-EVB 5 6 Rev. 0.33 POS2 POS1 1 1 1 1 + 0.1uf, 0603 C13 49.9, 0603 49.9, 0603 0.1uf, 0603 C12 0.1uf, 0603 C6 0.1uf, 0603 C5 600 ohm, 1206 SMA, thruhole RA L1 BODY SIG J4 SMA, thruhole RA BODY SIG J3 SMA, thruhole RA BODY SIG J2 SMA, thruhole RA BODY power connector, 2 pin J15 2 2 2 2 SIG J1 R16 R19 0.1uf, 0603 C14 C26 33uf, 3528 0, 0402 R21 R20 0, 0402 R18 0, 0402 R17 0.1uf, 0603 R15 49.9, 0603 C7 R14 49.9, 0603 0, 0402 2 JP12 C29 22pf, 0603 1 + C30 330uf, 7343 2.5V 2 2 1 1 + 0.1uf, 0603 C20 49.9, 0603 49.9, 0603 0.1uf, 0603 C19 C31 330uf, 7343 SMA, thruhole RA BODY SIG J6 SMA, thruhole RA BODY SIG J5 + R25 C32 330uf, 7343 0, 0402 R32 0, 0402 R23 0.1uf, 0603 C21 R22 0, 0402 R24 + REF/CLKIN_F- C33 33uf, 3528 C23 Spare, 0402 C22 Spare, 0402 REF/CLKIN_F+ Figure 2. Si5364-EVB Typical Application Schematic (page 2 of 2) C27 0.1uf, 0603 3.3V C28 2200pf, 0603 CLKIN_B+ C16 Spare, 0402 C15 Spare, 0402 CLKIN_B- CLKIN_A+ C9 Spare, 0402 C8 Spare, 0402 CLKIN_A- CLKOUT_4- CLKOUT_4+ CLKOUT_3- CLKOUT_3+ CLKOUT_2- CLKOUT_2+ CLKOUT_1- CLKOUT_1+ 0.1uf, 0603 C41 0.1uf, 0603 C40 0.1uf, 0603 C39 0.1uf, 0603 C38 0.1uf, 0603 C37 0.1uf, 0603 C36 0.1uf, 0603 C35 0.1uf, 0603 C34 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 SMA, thruhole RA SIG BODY J14 SMA, thruhole RA SIG BODY J13 SMA, thruhole RA SIG BODY J12 SMA, thruhole RA SIG BODY SMA, thruhole RA J11 SIG BODY J10 SMA, thruhole RA SIG BODY J9 SMA, thruhole RA SIG BODY J8 SMA, thruhole RA SIG BODY J7 Si5364-EVB Si5364-EVB Bill of Materials Reference C1-C7,C12-C14,C19-C21 C27,C34-C41 C8,C9,C15,C16,C22,C23 C26,C33 C28 C29 C30,C31,C32 D1,D2,D3,D4,D5,D10 D6,D7,D8,D9 JP1 JP2,JP3,JP4,JP5,JP6,JP9 JP8 JP10 JP11 JP12,JP15 J1,J2,J3,J4,J5,J6,J7,J8, J9,J10,J11,J12,J13,J14 J15 L1 R1 R2,R3 R4,R5,R6,R7,R8,R13 R9,R10,R11,R12 R14,R15,R20,R21,R22,R23 R16,R17,R18,R19,R24,R25, R26,R27,R29,R32 R28 SW1,SW2,SW3 U1 U4,U5 U7,U6 Description 0.1uf, 0603 Spare, 0402 33uf, 3528 2200pf, 0603 22pf, 0603 330uf, 7343 LED, SM, red, superbright LED, SM, green 21x3 HEADER 1x3 HEADER 7x3 HEADER 4x2 HEADER 10x2 Header HEADER 2X1 SMA, thruhole RA Manufacturer Venkel Part Number C0603X7R160-104KNE Venkel Venkel Venkel Venkel Panasonic Panasonic TA6R3TCR336KBR C0603X7R160-222KNE C0603C0G500-220KNE TA6R3TCR337KER LN1271RAL LN1371G Johnson Components 142-0701-301 power connector, 2 pin 600 ohm, 1206 10k, 0603 100k, 0402 1k, 0603 120, 0603 49.9, 0603 0, 0402 Phoenix Contact MURATA Venkel Venkel Venkel Venkel Venkel Venkel 140-A-111-02 1729018 BLM31A601S CR0603-16W-1002FT CR0402-16W-1003FT CR0603-16W-1001FT CR0603-16W-121JT CR0603-16W-49R9FT CR0402-16W-000T 4.99k, 0603 101-0161 Si5364_revB 74LCX244 74SZ14 Venkel Mouser CR0603-16W-4991FT 101-0161 Fairchild Fairchild 74LCX244MTC NC7SZ14M5X Rev. 0.33 7 Si5364-EVB Figure 3. Si5364-EVB Top Silkscreen Figure 4. Si5364-EVB—Layer 1, Component Side 8 Rev. 0.33 Si5364-EVB Figure 5. Si5364-EVB—Layer 2, High Speed Signals Figure 6. Si5364-EVB—Layer 3, GND Rev. 0.33 9 Si5364-EVB Figure 7. Si5364-EVB—Layer 4, VDD 2.5 Figure 8. Si5364-EVB—Layer 5, GND 10 Rev. 0.33 Si5364-EVB Figure 9. Si5364-EVB—Layer 6, VDD 3.3 Figure 10. Si5364-EVB—Layer 7, GND Rev. 0.33 11 Si5364-EVB Figure 11. Si5364-EVB—Layer 8, Bottom Figure 12. Si5364-EVB Bottom Silkscreen 12 Rev. 0.33 Si5364-EVB Document Revision Change List Revision 0.28 to Revision 0.33 Updated to reflect Rev. D printed circuit boards. Evaluation Board Assembly Revision History Assembly Level PCB Rev. Si5364 Rev. C-01 Rev. D Rev. C Assembly Notes Assemble per BOM rev C-01 Rev. 0.33 13 ClockBuilder Pro One-click access to Timing tools, documentation, software, source code libraries & more. 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