Si 5 3 2 0 - EVB EVALUATION BOARD FOR Si5320 SONET/SDH PRECISION C L O C K M U L T I PL I E R I C Description Features The Si5320-EVB is the customer evaluation board for the Si5320 SONET/SDH Precision Port Card Clock IC. This board is supplied to customers for evaluation of the Si5320 device. The board provides access to signals associated with normal operation of the device and signals that are reserved for factory testing purposes. Single supply at either 3.3 or 2.5 V (jumper configurable) Differential I/Os ac coupled on board Differential inputs terminated on board Control input signals are switch configurable Status outputs brought out to headers for easy access. Function Block Diagram 3.3 V or 2.5 V Supply Power Supply Input Control Input Jumper Header Status Output Signal Header Control Inputs Status Outputs 3.3 V/2.5 V Supply Selection + CLKIN CLKIN Factory Test Input Header Rev. 0.4 6/02 Factory Test Output Header Factory Test Serial Input 50 – 50 CLKOUT CLKOUT Si5320 – + t e x t Factory Test Serial Output t e x t Factory Test Analog Output Copyright © 2002 by Silicon Laboratories Si5320-EVB-04 Si5320-EVB Functional Overview The Si5320-EVB is the customer evaluation board for the Si5320 SONET/SDH Precision Port Card Clock IC. It is supplied to customers for evaluation of the Si5320 device. The board provides access to signals associated with normal operation of the device and signals that are reserved for factory testing purposes. Power Supply Selection and Connections The Si5320-EVB board is switch selectable for operation using either a single 3.3 V or a single 2.5 V supply. For operation using a 3.3 V supply, configure the board as follows: 1. Remove power supply connections from the VDD and GND terminals of the board’s power connector, J3. 2. Remove the connection between VDD33 and VDD25 by removing the jumper on header JPI. 3. Set VSEL33 high by sliding the switch on the VSEL33 (JP6) to the side marked “1”. 4. Connect the power supply ground lead and 3.3 V supply lead to the GND and VDD terminals of the board’s power connector, J3. For operation using a 2.5 V supply, configure the board as follows: 1. Remove power supply connections from the VDD and GND terminals of the board’s power connector, J3. 2. Set VSEL33 low by sliding the switch on the VSEL33 (JP6) to the side marked “0”. 3. Connect VDD33 and VDD25 by installing a jumper between one of the 3.3 V pins and one of the 2.5 V pins on header JPI. 4. Connect the power supply ground lead and 2.5 V supply lead to the GND and VDD terminals of the board’s power connector, J3. Power Consumption Typical supply current draw for the Si5320-EVB is 110 mA. Si5320 Control Inputs The control inputs to the Si5320 are each routed from the center pin of a SPDT switch, JP5, to the Si5320 device. Additionally, the switches at JP5 are connected to GND on one side of the switch and to VDD33 on the other side. This arrangement allows easy configuration of each input to either a high or low state. To further reduce the coupling of noise into the device through these control inputs, the signals are routed on internal layers between ground planes. 2 RSTN/CAL Settings for Normal Operation and Self-Calibration The RSTN/CAL signal is an LVTTL input to the Si5320 and has an on-chip pulldown mechanism. This pin must be set high for normal operation of the Si5320 device. Setting RSTN/CAL low forces the Si5320 into the reset state. A low-to-high transition of RSTN/CAL enables the part and initiates a self-calibration sequence. The Si5320 device initiates self-calibration at powerup if the RSTN/CAL signal is held high. A self-calibration of the device also can be manually initiated by momentarily pushing the RSTN/CAL switch, SWI and then releasing. Manually initiate self-calibration after changing the state of either the BWSEL[1:0] control inputs or the FEC[1:0] inputs. Whether manually initiated or automatically initiated at powerup, the self-calibration process requires a valid input clock. If the self-calibration is initiated without a valid clock present, the device waits for a valid clock before completing the self-calibration. The Si5320 clock output is set to the lower end of the operating frequency range while the device waits for a valid clock. After the clock input is validated, the calibration process runs to completion, the device locks to the clock input, and the clock output shifts to its target frequency. Subsequent losses of the input clock signal do not require recalibration. If the clock input is lost after self-calibration, the device enters Digital Hold mode. When the input clock returns, the device re-locks to the input clock without performing a self-calibration. Status Signals The status outputs from the Si5320 device are each routed to one pin of a two-row header. The signals are arranged so that each signal has a ground pin adjacent to the signal pin for reference. The row of signal pins is marked with an “S”, and the row of ground pins is marked with a “G”. Visible indicators are added to the LOS and CAL_ACTV signals. The LEDs glow when the signal is active and the LED enable switch is set to ON. The LOS LED is illuminated when the device does not recognize a valid clock input. The CAL_ACTV LED is illuminated when the device is calibrating to an input clock. Differential Clock Input Signals The differential Clock inputs to the Si5320-EVB board are ac coupled and terminated on the board at a location near the SMA input connectors. The termination components are located on the top side of the board. The termination circuit consists of two 50 Rev. 0.4 Si5320-EVB and a 0.1 F capacitor, such that the positive and negative inputs of the differential pair each see a 50 termination to “ac ground,” and the line-to-line termination impedance is 100 . There are two considerations for selecting this combination of compensation resistor and capacitor. First, is the stability of the regulator. The second is noise filtering. For single-ended operation, supply a signal to one of the differential inputs (usually the positive input). The other input should be shorted to ground using an SMA shorting plug. The on-board termination circuit provides a 50 termination to ac-ground for each leg of the differential pair. The acceptable range for the time constant at this node is 15 s to 50 s. The capacitor used on the board is a 33 F capacitor with an ESR of .8 . This yields a time constant of 26.4 s. The designer could decide to use a 330 F capacitor with an ESR of .15 . This yields a time constant of 49.5 s. Each of these cases provide a compensation circuit that makes the output of the regulator stable. Differential Clock Output Signals The differential clock outputs from the Si5320 device are routed to the perimeter of the circuit board using 50 transmission line structures. The capacitors that provide ac-coupling are located near the clock output SMA connectors. Internal Regulator Compensation The Si5320-EVB contains pad locations for a resistor and a capacitor between the VDD25 node and ground. The resistor pads are populated with a 0 resistor. The capacitor pads are populated with a low ESR 33 F tantalum capacitor. This is the suggested compensation circuit for Si5320 devices. The second issue is noise filtering. For this, more capacitance is usually better. For the two cases described above, the 330 F case provides greater noise filtering. However, the large case size of the 330 F capacitor might make it impractical for many applications. The Si5320 device is specified with the 33 F cap. Default Jumper Settings The default jumper settings for the Si5320-EVB board are given in Table 1. These settings configure the board for operation from a 3.3 V supply. Table 1. Si5320-EVB Assembly Rev B-01 Default Jumper/Switch Settings Location Signal State Notes JP6 VSEL33 1 Internal Regulator enabled JP1 VDD33 Open 3.3 V plane not connected to 2.5 V plane JP5 VALTIME 0 100 ms Validation Time FEC[0] 0 No FEC scaling FEC[1] 0 No FEC scaling BWSEL[0] 0 Loop Filter Bandwidth = 800 Hz BWSEL[1] 1 Loop Filter Bandwidth = 800 Hz INFRQSEL[0] 1 Clock IN = 19.44 MHz INFRQSEL[1] 0 Clock IN = 19.44 MHz INFRQSEL[2] 0 Clock IN = 19.44 MHz FRQSEL[0] 1 Clock Out = 622.08 MHz FRQSEL[1] 1 Clock Out = 622.08 MHz DBLBW 1 Selected bandwidth not doubled FXDDELAY 0 Fixed Delay disabled LED ENABLE On LED Indicators enabled JP7 Rev. 0.4 3 J3 3.3V POS2 3.3V 35 32 29 26 23 20 17 14 11 8 5 2 Rev. 0.4 2 101-0161 SW1 + 2 12x3 HEADER 35 32 29 26 23 20 17 14 11 8 5 2 1x3 HEADER 1 3 JP6 1 3 4 6 7 9 10 12 13 15 16 18 19 21 22 24 25 27 28 30 31 33 34 36 JP5 R13 4.99k, 0603 1 3 1 3 4 6 7 9 10 12 13 15 16 18 19 21 22 24 25 27 28 30 31 33 34 36 L1 1 3 1 3 JP8 0, 0402 R14 VSEL33 2 FXDDELAY VALTIME BWSEL[0] BWSEL[1] DBLBW FEC[0] FEC[1] FRQSEL[0] FRQSEL[1] 2 INFRQSEL[0] INFRQSEL[1] INFRQSEL[2] C8 33uf, 3528 ClkIn- R3 49.9, 0603 ClkIn+ 22pf, 0603 C11 C10 2200pf, 0603 RSTN/CAL C9 0.1uf, 0603 2 0, 0402 R8 0.1uf, 0603 C3 3.3V R2 49.9, 0603 0, 0402 R7 JP1 1 1 3 4 6 7 9 10 12 13 15 JP4 RSTN/CAL VALTIME FXDDELAY VSEL33 DBLBW BWSEL[1] BWSEL[0] FEC[1] FEC[0] FRQSEL[1] FRQSEL[0] 14 11 8 5 2 14 11 8 5 2 TIN[2] TIN[1] TMOD[2] TMOD[1] TMOD[0] 1 3 5 3.3V + C15 33uf, 3528 REXT 2 4 6 DEV_ID[0] DEV_ID[1] DEV_ID[2] DEV_ID[3] DEV_ID[4] DEV_ID[5] ANAOUT JP2 2 4 6 RSTN/CAL VALTIME FXDDELAY VSEL33 DBLBW BWSEL[1] BWSEL[0] FEC[1] FEC[0] FRQSEL[1] FRQSEL[0] INFRQSEL[2] INFRQSEL[1] INFRQSEL[0] R1 10k, 0603 H2 H3 H4 B4 C2 D2 C1 B1 A2 A3 H8 H5 H1 G1 F1 CLKIN+ CLKIN- C14 330uf, 7343 D1 E1 1 3 5 + 0, 0402 R9 2.5V U1 Si5320_revC 1 3 5 7 9 11 13 1 3 5 7 9 11 13 JP3 2 4 6 8 10 12 14 2 4 6 8 10 12 14 RES/TMOD[0] RES/TMOD[1] RES/TMOD[2] RES/TIN[1] RES/TIN[2] NC/ANAOUT NC/DEV_ID[0] NC/DEV_ID[1] NC/DEV_ID[2] NC/DEV_ID[3] NC/DEV_ID[4] NC/DEV_ID[5] CAL_ACTV DH_ACTV LOS CLKOUT+ CLKOUT- C8 B7 B6 B3 B2 B5 A6 A5 A4 A7 A8 B8 E8 D8 F8 H6 H7 Figure 1. Si5320-EVB Schematic For engineering test purposes only. Not needed for customer application. 1 3 4 6 7 9 10 12 13 15 C13 330uf, 7343 CAL_ACTV DH_ACTV LOS C5 Spare, 0402 + INFRQSEL[2] INFRQSEL[1] INFRQSEL[0] C12 330uf, 7343 C4 Spare, 0402 + 2.5V D3 D4 D5 E3 E4 E5 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 HEADER 2X1 D6 D7 E6 E7 F3 F4 F5 F6 F7 VDD25 VDD25 VDD25 VDD25 VDD25 VDD25 VDD25 VDD25 VDD25 GND GND GND GND GND GND GND GND GND GND GND GND GND GND C3 C4 C5 C6 C7 E2 F2 G2 G3 G4 G5 G6 G7 G8 3.3V TMOD[0] TMOD[1] TMOD[2] TIN[1] TIN[2] ANAOUT DEV_ID[0] DEV_ID[1] DEV_ID[2] DEV_ID[3] DEV_ID[4] DEV_ID[5] CAL_ACTV DH_ACTV LOS ClkOut+ ClkOut- 2 2 C1 0.1uf, 0603 1 C2 0.1uf, 0603 1 CAL_ACTV SMA, thruhole RA BODY SIG J2 SMA, thruhole RA BODY SIG J1 G ClkIn- ClkIn+ D S 600 ohm, 1206 Q2 FDN337N LN1271RAL D2 R12 1k, 0603 LOS ClkOut- ClkOut+ G J4 BODY SIG 1 J5 BODY SIG Q1 FDN337N LN1271RAL D1 R6 1k, 0603 SMA, thruhole RA 0.1uf, 0603 C7 1 SMA, thruhole RA 0.1uf, 0603 C6 D 4 S POS1 1 3 2 2 1 3 2 2 3.3V 1x3 HEADER JP7 Si5320-EVB . Si5320-EVB Bill of Materials Reference Description Manufacturer Part Number C1,C2,C3,C6,C7,C9 C4,C5 C15,C8 C10 C11 C12,C13,C14 D2 D3 JP2,JP5,JP7 JP3 JP4 JP6 JP9 JP10 J1,J2,J4,J5 J3 L1 Q1,Q2 R1 R2,R3 R4,R7,R8,R9 R5 R6,R10 SW1 U4 0.1uf, 0603 Spare, 0402 33uf, 3528 2200pf, 0603 22pf, 0603 330uf, 7343 LED, SM, red LED, SM, green 1x3 HEADER HEADER 2X1 HEADER 3x2 12x3 HEADER 5x3 7x2 Header SMA, thruhole RA power connector, 2 pin 600 ohm, 1206 MOS, SM, FDN337N 4.99k, 0603 49.9, 0603 0, 0402 10k, 0402 60.4, 0402 101-0161 Si5320_revC Venkel C0603X7R160-104KNE Venkel Venkel Venkel Venkel Panasonic Panasonic TA6R3TCR336KBR C0603X7R160-222KNE C0603C0G500-220KNE TA6R3TCR337KER LN1274R LN1371G Johnson Components Phoenix Contact MURATA Fairchild Venkel Venkel Venkel Venkel Venkel Mouser 142-0701-301 140-A-111-02 1729018 BLM31A601S FDN337N CR0603-16W-4991FT CR0603-16W-49R9FT CR0402-16W-000T CR0402-16W-1002FT CR0402-16W-60R4FT 101-0161 Rev. 0.4 5 Si5320-EVB Figure 2. Si5320-EVB Top Silkscreen 6 Rev. 0.4 Si5320-EVB Figure 3. Si5320-EVB—Layer 1, Component Side Rev. 0.4 7 Si5320-EVB Figure 4. Si5320-EVB—Layer 2, High Speed Signals 8 Rev. 0.4 Si5320-EVB Figure 5. Si5320-EVB—Layer 3, GND Rev. 0.4 9 Si5320-EVB Figure 6. Si5320-EVB—Layer 4, VDD 2.5 10 Rev. 0.4 Si5320-EVB Figure 7. Si5320-EVB—Layer 5, GND Rev. 0.4 11 Si5320-EVB Figure 8. Si5320-EVB—Layer 6, VDD 3.3 12 Rev. 0.4 Si5320-EVB Figure 9. Si5320-EVB—Layer 7, GND Rev. 0.4 13 Si5320-EVB Figure 10. Si5320-EVB—Layer 8, Bottom 14 Rev. 0.4 Si5320-EVB Figure 11. Si5320-EVB Bottom Silkscreen Rev. 0.4 15 Si5320-EVB Document Revision Change List Revision 0.33 to Revision 0.4 Default jumper settings added. Evaluation Board Assembly Revision History 16 Assembly Level PCB Rev. Si5320 Rev. C-01 Rev. D Rev. C Assembly Notes Assemble per BOM rev C-01 Rev. 0.4 Si5320-EVB Notes: Rev. 0.4 17 ClockBuilder Pro One-click access to Timing tools, documentation, software, source code libraries & more. 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