AN1369

AN1369
Full-Bridge Quarter Brick DC/DC Converter Reference Design
Using a dsPIC® DSC
Author:
Ramesh Kankanala
Microchip Technology Inc.
ABSTRACT
This
application
note
provides
the
digital
implementation of a telecom input 36 VDC-76 VDC to
output 12 VDC, 200W Quarter Brick DC/DC Brick
Converter using the Full-Bridge topology. This topology
combines the advantages of Pulse-Width Modulation
(PWM) control and resonant conversion.
The dsPIC33F “GS” family series of Digital Signal
Controllers (DSCs) was introduced by Microchip
Technology Inc., to digitally control Switched Mode
Power Converters. The dsPIC33F “GS” family of
devices consists of an architecture that combines the
dedicated Digital Signal Processor (DSP) and a
microcontroller. These devices support all of the
prominent power conversion technologies that are
used today in the power supply industry.
In addition, the dsPIC33F “GS” family of devices
controls the closed loop feedback, circuit protection,
fault management and reporting, soft start, and output
voltage sequencing. A DSC-based Switched Mode
Power Supply (SMPS) design offers reduced
component count, high reliability and flexibility to have
modular construction to reuse the designs. Selection of
peripherals such as the PWM module, Analog-toDigital Converter (ADC), Analog Comparator, Oscillator
and communication ports are critical to design a good
power supply. MATLAB® based simulation results are
compared to the actual test results and are discussed
in subsequent sections.
INTRODUCTION
Recently, Intermediate Bus Converters (IBCs) have
become popular in the telecom power supply industry.
Most telecom and data communication systems
contain ASIC, FPGAs and integrated high-end
processors. These systems require higher currents at
multiple low-level voltages with tight load regulations.
Traditionally, bulk power supplies deliver different load
voltages. In the conventional Distributed Power
Architecture (DPA), the front-end AC/DC power supply
generates 24V/48V and an individual Isolated Brick
Converter supports the required low system voltages.
These systems become inefficient and costly where
© 2011 Microchip Technology Inc.
very low voltages are required. In the Intermediate Bus
Architecture (IBA), the IBC generates 12V/5V. Further,
these voltages are stepped down to the required load
voltages by Point of Loads (PoLs).
In IBA, the high-density power converters, IBC and
PoLs are near to the load points, which lower costs due
to the improved performance. Because these
converters are at the load points, the PCB design is
simpler, which also reduces costs.
Electromagnetic
Interference
(EMI)
is
also
considerably reduced due to minimum routing length of
high current tracks. Due to the position of these
converters, the transient response is good and the
system performance is improved. Modern systems
require voltage sequencing, load sharing between the
converters, external communication and data logging.
Conventional Switched Mode Power Supplies are
designed with Analog PWM control to achieve the
required regulated outputs, and an additional
microcontroller performs the data communication and
load sequencing. To maximize the advantages of IBC,
the converter must be designed with reduced
component count, higher efficiency, and density with
lower cost. These requirements can be achieved by
integrating the PWM controller, communication and load
sharing with a single intelligent controller. The dsPIC33F
“GS” series family of DSCs have combined these design
features in a single chip that is suitable for the bus
converters.
Some of the topics covered in this application note
include:
• DC/DC power module basics
• Topology selection for the Quarter Brick DC/DC
Converter
• DSC placement choices and mode of control
• Hardware design for the isolated Full-Bridge
Quarter Brick DC/DC Converter
• Planar magnetics design
• Digital Full-Bridge Quarter Brick DC/DC Converter
design
• Digital control system design
• Digitally controlled load sharing
• MATLAB modeling
• Digital nonlinear control techniques
• Circuit schematics and laboratory test results
• Test demonstration
DS01369A-page 1
AN1369
DISTRIBUTED POWER ARCHITECTURE (DPA)
Isolation Barrier
FIGURE 1:
Load
DC/DC Brick
Converter
3.3 VDC
Load
Load
AC/DC Power
Supply
24V/48V Bus
DC/DC Brick
Converter
2.5 VDC
Load
Load
DC/DC Brick
Converter
1.8 VDC
Load
INTERMEDIATE BUS ARCHITECTURE (IBA)
Isolation Barrier
FIGURE 2:
AC/DC Power
Supply
24V/48V Bus
Intermediate
Bus Converter
(IBC)
1.3 VDC
PoL
Load
1.8 VDC
PoL
12V/5V Bus
Load
1.5 VDC
Load
PoL
1.2 VDC
PoL
Load
1.0 VDC
PoL
Load
0.8 VDC
PoL
Load
PoL = Point of Load
DS01369A-page 2
© 2011 Microchip Technology Inc.
AN1369
QUARTER BRICK CONVERTER
Remote ON/OFF Control
The Distributed-Power Open Standards Alliance
(DOSA) defines the specifications for the single output
pin Quarter Brick DC/DC Converter. These
specifications are applicable to all Quarter Bricks
(unregulated, semi-regulated and fully regulated) for an
output current range up to 50A.
Remote ON/OFF control is used to enable or disable
the DC/DC converter through an external control
signal. The most common method to enable or disable
the converter is from the primary side (input side).
Because the controller exists in the secondary side of
the isolated barrier, an isolation circuit must be used to
transfer the signal from the primary side to the
secondary side. This can be achieved using the optoisolator, which is illustrated in Figure 3.
The AC/DC converter output is 48V in the IBA. This
voltage is further stepped down to an intermediate
voltage of 12V by an isolated IBC. This voltage is
further stepped down to the required low voltage using
PoL.
DOSA Quarter Brick DC/DC converters are offered in
through-hole configurations only.
FIGURE 3:
REMOTE ON/OFF
Remote ON/OFF – (I/P)
+3.3V ANA
Some advantages of the Quarter Brick Converter are:
•
•
•
•
•
Improved dynamic response
Highest packaging density
Improved converter efficiency
Isolation near the load end
Output voltage ripple below the required limit
R
U
1
DC/DC POWER MODULES BASICS
Before discussing the design aspects of the Quarter
Brick Converter, the following requirements should be
understood:
•
•
•
•
•
•
•
•
Input Capacitance
Output Capacitance
Remote ON/OFF Control
Ripple and Noise
Remote Sense
Forced Air Cooling
Overvoltage
Overcurrent
Input Capacitance
For DC/DC converters with tight output regulation
requirements, it is recommended to use an electrolytic
capacitor of 1 µF/W output power at the input to the
Quarter Brick Converter. In the Quarter Brick Converter
designs, these capacitors are external to the converter.
Output Capacitance
To meet the dynamic current requirements and the
output voltage regulations at the load end, additional
electrolytic capacitors must be added. As a design
guideline, in Quarter Brick Converter designs, 100 µF/A
to 200 µF/A of output current can be added and an
effective lower Equivalent Series Resistance (ESR) can
be achieved by using a number of capacitors in parallel.
© 2011 Microchip Technology Inc.
Remote ON/OFF
Signal to DSC
C
R
C
GND
DIG_GND
Ripple and Noise
The output of a rectifier consists of a DC component
and an AC component. The AC component, also
known as ripple, is undesirable and causes pulsations
in the rectifier output. Ripple is an artifact of the power
converter switching and filtering action, and has a
frequency of some integral multiple of the power
converter operating switching frequency.
Noise occurs at multiples of the power converter
switching frequency, and is caused by a quick charge
and discharge of the small parasitic capacitances in the
power converter operations. Noise amplitude depends
highly on load impedance, filter components and the
measurement techniques.
Remote Sense
Remote sense can be used to compensate voltage
drop in the set voltage when long traces/wires are used
to connect the load. In applications where remote
sensing is not required, the sense pins can be
connected to the respective output pins.
DS01369A-page 3
AN1369
Forced Air Cooling
To remove heat from the high density board mount
power supplies, forced air cooling is applied using a
fan.
Forced air cooling greatly reduces the required PCB
size and heat sink. However, installation of a fan
consumes additional power, causes acoustic noise and
significantly increases the maintenance requirements.
In forced air cooling SMPS applications, reliability of
the converter highly depends on the fan. A temperature
sensing device is used to monitor the temperature and
shuts down the converter when the Quarter Brick
Converter
exceeds
the
maximum operating
temperature.
Overvoltage
Overvoltage protection is required to protect the load
circuit from excessive rated voltage because of a
malfunction from the converter’s internal circuit. This
protection can be implemented by Latch mode or
Cycle-by-Cycle mode. In Latch mode, the circuit will be
in the OFF condition on the occurrence of overvoltage
fault until the input voltage is cycled. The system
automatically recovers in the Cycle-by-Cycle mode. If
faults still exist in the system, the system is turned OFF
and this cycle is repeated.
Overcurrent
Overcurrent protection prevents damaging the
converter from short circuit or overload conditions. In
Hiccup mode, the converter will be OFF when an
overcurrent or short circuit occurs, and will recover in
the specified time period. If the converter still sees the
fault, it will turn OFF the converter again and this cycle
repeats. In the Latch mode, the circuit is recovered only
after recycling the input power.
higher switching losses while the switch turns ON or
OFF, which results in a reduction in the efficiency of the
converter.
Soft switching techniques are used to reduce the
switching losses of the PWM converter by controlling
the ON/OFF switching of the power devices. Soft
switching can be done using the Zero Voltage
Switching (ZVS) and Zero Current Switching (ZCS)
techniques. These soft switching techniques have
some design complexity and in turn, produce higher
efficiency at high-power levels.
Non-Isolated Forward Mode Buck
Converter
If the required output voltage is always less than the
specified input voltage, the Buck Converter can be
selected from the following three basic topologies:
Buck, Boost and Buck Boost.
The Buck topology can be implemented in the isolated
and non-isolated versions. As per the bus converter
specification requirement, isolated converter design is
selected for this application. In the Forward Mode Buck
Converter, energy is transferred from the primary side
to the secondary side when the primary side switch is
turned ON. The output voltage can be controlled by
varying the duty cycle with respect to the input voltage
and load current. This is done with the feedback loop
from the output that controls the duty cycle of the
converter to maintain the regulated output.
FIGURE 4:
NON-ISOLATED FORWARD
MODE BUCK CONVERTER
Q1
L1
VOUT+
VIN+
D1
C1
TOPOLOGY SELECTION
VOUT-
VIN -
The bus converter specifications are standardized, and
are used or assembled as one of the components in the
final system. The user must consider the end-system
characteristics such as reliability, efficiency, foot prints
and cost. There is no universally accepted topology for
the bus converters. However, the following sections
describe a few topologies that are commonly used for
DC/DC converter applications with their pros and cons.
A fundamental distinction among the PWM switching
topologies is hard switching and soft switching/
resonant topologies. Typically, high frequency
switching power converters reduce the size and weight
of the converter by using small magnetics and filters.
This in turn increases the power density of the
converter. However, high frequency switching causes
DS01369A-page 4
Isolated Forward Converter
In the Forward Converter, the energy from the input to
the output is transferred when the switch Q1 is ON.
During this time, diode D1 is forward biased and diode
D2 is reverse biased. The power flow is from D1 and L1
to output. During the switch Q1 OFF time, the
transformer (T1) primary voltages reverse its polarity
due to change in primary current. This also forces the
secondary of T1 to reverse polarity. Now, the secondary
diode, D2 is forward biased and freewheels the energy
stored in the inductor during switch Q1 ON time. This
simple topology can be used for power levels of 100W.
Some of the commonly used variations in Forward
© 2011 Microchip Technology Inc.
AN1369
Converter topologies are active Reset Forward
Converter, Two Transistor Forward or Double-ended
Forward Converter.
FIGURE 7:
HALF-BRIDGE CONVERTER
VIN+
D1
FIGURE 5:
ISOLATED FORWARD
CONVERTER
D1
VIN+
L1
T1
L1
VOUT+
Q3
T1
VOUT+
C1
Q4
VOUTD2
D2
C1
VIN-
Q1
VOUT-
VIN-
Push-Pull Converter
The Push-Pull Converter is a two transistor topology
that uses a tapped primary on the converter
transformer T1. The switches Q1 and Q2 conduct their
respective duty cycles and the current in the primary
changes, resulting in a bipolar secondary current
waveform. This converter is preferred in low input
voltage applications because the voltage stress is twice
the input voltage due to the tapped primary
transformer.
FIGURE 6:
PUSH-PULL CONVERTER
Full-Bridge Converter
The Full-Bridge Converter is configured using the four
switches: Q1, Q2, Q3 and Q4. The diagonal switches
Q1, Q4 and Q2, Q3 are switched ON simultaneously.
This provides full input voltage (VIN) across the primary
winding of the transformer. During each half cycle of
the converter, the diagonal switches Q1, Q4 and Q2,
Q3 are turned ON, and the polarity of the transformer
reverses in each half cycle. In the Full-Bridge
Converter, at a given power compared to the HalfBridge Converter, the switch current and primary
current will be half. This makes the Full-Bridge
Converter suitable for high-power levels.
FIGURE 8:
FULL-BRIDGE CONVERTER
VIN +
Q1
D1
T1
-
VIN
D1
L1
VOUT +
Q1
Q3
T1
Q2
Q4
+
L1
VOUT +
C1
C1
VOUT D2
VOUT D2
VIN -
Q2
Half-Bridge Converter
Half-Bridge converters are also known as two switch
converters. Half the input voltage level is generated by
the two input capacitors, C1 and C2. The transformer
primary is switched alternatively between VIN+ and
input return VIN- such that the transformer primary sees
only half the input voltage (VIN/2). The input switches,
Q1 and Q2, measure the maximum input voltage, VIN
compared to 2 * VIN in the Push-Pull Converter. This
allows the Half-Bridge Converter to use higher power
levels.
© 2011 Microchip Technology Inc.
However, the diagonal switches are hard switched
resulting in high turn ON and turn OFF switching
losses. These losses increase with frequency, which in
turn limits the frequency of the operation. The Hard
Switched Full-Bridge topology is attractive where the
converter is functioning in low input voltages.
DS01369A-page 5
AN1369
FIGURE 9:
ZERO VOLTAGE
SWITCHING (ZVS)
FIGURE 10:
VDS(t)
FULL-BRIDGE CONVERTER
WITH SYNCHRONOUS
RECTIFICATIONS
PWMH
PWMH
VDS
ID(t)
Q3
Q1
Q6
PWML
ID
TX
TXVPRI
ZVS
t
PWM
PWML
PWML
t
Q4
Q2
PWMH
Q5
Synchronous Rectification
In synchronous rectification, the secondary diodes, D1
and D2 are replaced with MOSFETs. This yields lower
rectification losses because a MOSFET will have
minimum DC losses compared to the Schottky
rectifiers. The forward DC losses of a Schottky rectifier
diode will be forward voltage drop multiplied by the
forward current. The power dissipation by a conducting
MOSFET will be RDS(ON) multiplied by the square of
the forward current. The loss comparison will be
significant at considerably higher current >15A and
lower output voltages.
This configuration involves complexity and cost to an
extent because a gate drive circuit is required to control
the synchronous MOSFET. The efficiency of this
configuration can be further increased by designing the
complex gate drive signals, which are discussed in the
section “Digital Nonlinear Implementations”.
Many topologies are available and one of them can be
chosen depending on the given power level, efficiency
of the converter, input voltage variations, output voltage
levels, availability of the components, cost, reliability of
the design, and good performance characteristics.
This application note discusses the design
considerations of Full-Bridge topology for Quarter Brick
DC/DC converter design.
TABLE 1:
TOPOLOGY COMPARISON
No. of Switches in the
Primary
Stress Level of Primary
Switches
Power Levels (Typical)
2
VIN
100W
Push-Pull converter
2
2 * VIN
150W
Half-Bridge converter
2
VIN
200W
Full-Bridge converter
4
VIN
PSFB converter
4
VIN
Topology
Forward converter
DS01369A-page 6
~ 200W
~ 200W
© 2011 Microchip Technology Inc.
AN1369
PRIMARY SIDE CONTROL VS.
SECONDARY SIDE CONTROL
After selecting the topologies based on the merits for
the given application, the next challenge faced by
designers is to position the controller either on the
primary or secondary side. The power converter
demands
the
galvanic
isolation
between
primary (input) and secondary (output load) due to
safety reasons. There should not be any direct
conductive path between the primary and secondary.
Isolation is required when signals are crossing from the
primary to the secondary and vice versa. The power
path isolation will be given by the high frequency
transformers. Gate drive signals can be routed through
optocouplers or gate drive transformers.
FIGURE 11:
In the primary side controllers, the output feedback
signal is transferred from the secondary to the primary
using the optocouplers. These devices have limited
bandwidth, poor accuracy, and tend to degrade over
time and temperature.
Again, the transfer of signals from the primary to the
secondary or the secondary to the primary is
dependant on the features demanded by the
application. Figure 11, Figure 12 and Table 2 show the
comparison between the primary side controller and
the secondary side controller. The secondary side
controller is selected in this application.
SECONDARY SIDE CONTROL
VOUT +
VIN +
12V/17A
Sync Rectifier
Full-Bridge
36V-76V
200W
MOSFET
VIN -
VOUT Driver
Current TX
Drive TX
Driver
Drive TX
Driver
dsPIC®
DSC
Communication
Remote Control
OPTO
VINOV
VINUV
3.3V Reg
NCP 1031
© 2011 Microchip Technology Inc.
Auxiliary TX
3.8V
12V
To Driver’s VCC
DS01369A-page 7
AN1369
TABLE 2:
PRIMARY SIDE CONTROL VS. SECONDARY SIDE CONTROL
Primary Side dsPIC® DSC Control
Secondary Side dsPIC® DSC Control
Isolated feedback is required to regulate the output. A
linear optocoupler can be used to achieve the
regulation, which requires an auxiliary supply and an
amplifier in the secondary.
Isolated feedback is not required because the controller is
on the secondary.
Remote ON/OFF signal isolation is not required.
Remote ON/OFF signal isolation is required.
Isolation is required for communication signals.
Isolation is not required for communication signals.
Load sharing signal is transferred from the secondary to Load sharing isolation is not required because the
the primary.
controller is in the secondary.
Overvoltage protection signal is transferred from the
secondary to the primary.
Isolation for overvoltage is not required because the
controller is in the secondary.
Frequency synchronization signal is transferred from the Isolation for frequency synchronization is not required
secondary to the primary.
because the controller is in the secondary.
Input undervoltage and overvoltage can be measured
without isolation.
Isolation is required. However, in this application, the input
undervoltage or overvoltage protection is provided by the
NCP 1031 auxiliary converter controller.
Gate drive design for the primary side switches is
simple.
Gate drive is transferred from the secondary to the primary
either by using driver transformers or opto isolators.
FIGURE 12:
PRIMARY SIDE CONTROL
VOUT+
VIN+
12V/17A
Sync Rectifier
Full-Bridge
36V-76V
200W
MOSFET
VIN-
VOUT Current TX
Drive TX
Drive TX
Driver1
Driver2
dsPIC®
DSC
I/P UV
O/P OV
To Driver’s ICs
Remote ON/OFF
Drive TX
Linear
OPTO
Driver3
LM358
OPTO
Communication
+12V
Reg 3.3V
3.8V
Isolated 12V for Driver3
VIN+
NCP1031
Auxiliary
TX
VIN-
DS01369A-page 8
© 2011 Microchip Technology Inc.
AN1369
VOLTAGE MODE CONTROL (VMC) VS.
CURRENT MODE CONTROL (CMC)
FIGURE 13:
The preference to implement VMC or CMC as the
feedback control method is based on applicationspecific requirements. In VMC, change in load current
will have effect on the output voltage before the
feedback loop reacts and performs a duty cycle
correction. In CMC, change in load current is sensed
directly and corrects the loop before the outer voltage
loop reacts.
This cause and then react process in the VMC is slower
to respond than in the CMC for highly varying load
transients.
The fundamental difference between VMC and CMC is
that CMC requires accurate and high grade current
sensing. In VMC, output voltage regulation is
independent of the load current. Therefore, relatively
low grade current sensing is enough for overload
protection. This saves significant circuit complexity and
power losses.
TABLE 3:
ID
IL
L
S
PWM1H
+
Comp
-
FIGURE 14:
Ramp
Generator
Dual feedback loop.
Provides good noise
margin.
Poor noise immunity.
Current measurement not Current measurement
required for feedback.
required.
Slope compensation not
required.
Slope compensation
required, instability at
more than 50% duty
cycles.
Poor dynamic response.
Good dynamic response.
© 2011 Microchip Technology Inc.
C
EA
+
Ref
CURRENT MODE
CONTROLLER (CMC)
IL
L
ID
IS
IO
D
S
PWM1H
C
CMC
Single feedback loop.
IO
D
IS
VMC AND CMC DIFFERENCES
VMC
VOLTAGE MODE
CONTROLLER (VMC)
+
Comp
-
EA
+
Ref
DS01369A-page 9
AN1369
HARDWARE DESIGN FOR THE
ISOLATED QUARTER BRICK DC/DC
CONVERTER
The average Current mode control Full-Bridge
topology with secondary side controller was selected
for this design. The digital Quarter Brick DC/DC
Converter design is discussed in the following sections.
Full-Bridge Converter Design
In the Full-Bridge topology, output voltage is controlled
by adjusting the duty of the Primary side diagonal
switching MOSFETs. The maximum duty is limited to
50% of the period.
• Time interval T0 – T1: Q1, Q4 = ON; Q2, Q3 = OFF
The Full-Bridge converter operation is described with
the power transfer from primary side to secondary
side with the conduction of diagonal MOSFETs, Q1
and Q4. The primary side current (IPRI) was
conducting through the MOSFETs, Q1 and Q4. In
this period, the full input voltage VIN is across the
primary side of the transformer TX and VIN/N is
across the secondary of the transformer. The slope
of the current is determined by VIN, magnetizing
inductance and the output inductance.
• Time interval T1 – T2: Q1, Q4 = OFF; Q2, Q3 = OFF
An intentional minimum dead band is introduced
between the turn OFF of Q1,Q4 and turn ON of
Q2,Q3. This is to avoid the input source short circuit.
T1-T2 is the off time of the Full-Bridge and in this
state no voltage is applied across primary of the
transformer. T1-T2 time will be increasing with the
increase in voltage.
• Time interval T2 – T3: Q1,Q4 = OFF; Q2,Q3 = ON
Q2, Q3 is tuned ON after the dead band time, now
the current flows in the transformer opposite to the
previous current conduction path. During the turn ON
and OFF of the diagonal MOSFETs always there will
be a definite amount of drain current, drain to source
voltage and this causes switching losses in the
MOSFETs.
Operation of the Full-Bridge converter and detailed
primary side waveforms with different time intervals are
illustrated in Figure 15.
DS01369A-page 10
© 2011 Microchip Technology Inc.
AN1369
FIGURE 15:
FULL-BRIDGE CONVERTER WITH FULL WAVE SYNCHRONOUS RECTIFICATION
OPERATIONAL WAVEFORMS
Q1
Q3
PWMH
PWML
Q6
TX
PWML
Q4
Q2
PWMH
Q5
PWMH
PWML
Q1
Q2
Q3
Q4
VPRI
IPRI
Q5
Q6
T0
© 2011 Microchip Technology Inc.
T1
T2
T3
DS01369A-page 11
AN1369
HARDWARE DESIGN AND
SELECTION OF COMPONENTS
RDS(ON) HOT can be calculated either from the graphs
provided in the data sheet or by using the empirical
formula shown in Equation 3.
Selection of components for a Quarter Brick Converter
design is critical to achieve high efficiency and high
density.
EQUATION 3:
RDS(ON) HOT =
RDS(ON) @ 25 * [1+0.0075*(TMAX-TAMB)
Specifications
•
•
•
•
•
•
•
•
•
•
•
Input voltage: VIN = 36 VDC - 76 VDC
Output voltage: VO = 12V
Rated output current: IORATED = 17A
Maximum output current: IO = 20A
Output power: PO = 200W
Estimated efficiency: 95%
Switching frequency of the converter:
FSW = 150 kHz
Switching period of the converter:
TP = 1/150 kHz = 6.66 µs
Chosen duty cycle: D = 43.4%
Full duty cycle: DMAX = 2 * 43.4% = 86.8%
Input power pin = 214.75W
EQUATION 1:
TURN ON TIME
43.4
TurnOnTime = 6.66μs × ---------- = 2.89μs
100
Full-Bridge MOSFET Selection
where:
RDS(ON) at 25 = 0.015E
Maximum junction temperature, TMAX = 125oC
Ambient temperature, TAMB = 25oC
EQUATION 4:
Conduction losses of the MOSFET at 48V:
P COND = I
2
Srms
× R DS ( ON ) HOT = 0.171W
where:
ISrms = Switch rms current
Conduction losses of all the four Full-Bridge
MOSFETs = 0.687W
EQUATION 5:
SWITCHING LOSSES OF
MOSFET
1
P SW = --- × V IN × I SRMS × T F × F SW = 0.05W
2
Input line current at 36V:
P IN
I AVE = ----------------- = 5.96A
V INMIN
Maximum Line Current at 36V:
I AVE
5.96- = 6.87A
= -------------= -----------D MAX
0.868
where:
TF = Fall time of the MOSFET = 5.7ns
Switching losses of all the four Full-Bridge
MOSFETs = 0.42W
EQUATION 6:
Line rms current at 36V:
I RMS = I MAX ×
D = 6.40A
D
---- = 4.53A
2
Because the maximum input voltage is 76 VDC, select
a MOSFET voltage rating that is higher than 76V and
the current rating higher than IMAX at 36 VDC.
MOSFET GATE CHARGE
LOSS
MOSFETGateCh arg eLosses = Q G × F SW × V DD
= 0.126W
Switch rms current at 36V:
I SRMS = I MAX ×
]
RDS(ON) HOT = 0.02625E
EQUATION 2:
I MAX
RDS(ON) EMPIRICAL
FORMULA
where:
For all four Full-Bridge MOSFETs = 0.504W
Bias voltage to the gate drive, VDD = 12V
MOSFET total gate charge, QG = 70 ns
The device selected is Renesas HAT2173 (LFPAK),
and has VDS 100V, ID 25A, RDS(ON) 0.015E.
DS01369A-page 12
© 2011 Microchip Technology Inc.
AN1369
Synchronous MOSFET Selection
DESIGN OF PLANAR MAGNETICS
The ability of the MOSFET channel to conduct current
in the reverse direction makes it possible to use a
MOSFET where a fast diode or Schottky diode is used.
In the fast diodes, junction contact potential limits to
reduce the forward voltage drop of diodes. Schottky
diodes will have reduced junction potential compared
to the fast diode. In the MOSFETs, the conduction
losses will be RDS(ON) * I2rms. The on-resistance can be
decreased by using parallel MOSFETs; which further
reduces cost.
Planar magnetics are becoming popular in high density power supply designs where the winding height
is the thickness of the PCB. Planar magnetics design
can be constructed stand-alone with a stacked layer
design or as a small multi-layer PCB, or integrated
into a multi-layer board of the power supply.
When full wave center tapped winding is used in the
transformer secondary side, the MOSFET voltage
stress is twice the output voltage, as shown in
Equation 7.
EQUATION 7:
MOSFET VOLTAGE STRESS
MOSFETVoltageStress = 2 × ( V O + V FET + V DROP )
= 2 × ( 12 + 0.6 + 0.2 )
where:
= 25.6V
Secondary MOSFET Drop, VFET = 0.6V
Total Trace Drops, VDROP = 0.2V
This is the minimum voltage stress, seen by the
MOSFET when the lower input voltage is 36V. For the
maximum input voltage of 76V, the stress is as shown
in Equation 8.
EQUATION 8:
25.6
MOSFET Voltage Stress @ 76V = 76 × ---------- = 54.04V
36
The
device
selected
HAT2173 (LFPAK).
is
the
Renesas
Magnetics Design
Magnetics design plays a crucial role in achieving high
efficiency and density. In the Quarter Brick DC/DC
Converter design, planar magnetics are used to gain
high efficiency and density.
© 2011 Microchip Technology Inc.
The advantages of planar magnetics are:
•
•
•
•
•
•
Low leakage inductance
Very low profile
Excellent repeatability of performance
Economical assembly
Mechanical integrity
Superior thermal characteristics
Planar E cores offer excellent thermal resistance.
Under normal operating conditions, it is less than 50%
as compared to the conventional wire wound
magnetics with the same effective core volume, VE.
This is caused by the improved surface to the volume
ratio. This results in better cooling capability and can
handle higher power densities, while the temperature is
within the acceptable limits.
The magnetic cross section area must be large to
minimize the number of turns that are required for the
given application. Ensure that the core covers the
winding that is laid on the PCB. Such design types
reduce the EMI, heat dissipation and allow small height
cores. Copper losses can be reduced by selecting the
round center leg core because this reduces the length
of turns.
The Planar Magnetics design procedure is the same as
that of the wire wound magnetics design:
1.
2.
3.
4.
5.
6.
7.
8.
Select the optimum core cross-section.
Select the optimum core window height.
Iterate turns versus duty cycle.
Iterate the core loss.
Iterate the copper loss (Cu).
Evaluate the thermal methods.
Estimate the temperature rise.
What is the cost trade-off versus the number of
layers.
9. Does the mechanical design fit the envelope
and pad layout?
10. Fit within core window height.
11. Is the size sufficient for power loss and thermal
solution?
DS01369A-page 13
AN1369
Full-Bridge Planar Transformer Design
The two considerations for secondary rectifications are
Full Wave Center Tapped (FWCT) rectifier configuration and Full Wave Current Doubler rectifier configurations. It is observed that the FWCT rectifier makes
optimum use of board space and efficiency goals.
Preliminary testing has validated this conclusion.
A further optimization goal is to offer a broad operating
frequency from 125 kHz to 200 kHz to provide wide
latitude for customers to optimize efficiency.
The iteration method is followed again to select the
core size from the available cores.
The selected core has the following magnetic
parameters:
• AC = 0.45 cm2
• LE = 3.09 cm
• VE = 1.57 cm3
FIGURE 16:
PLANAR TRANSFORMER
21.00 mm
(0.83'')
The input voltage range is 36 VDC-76 VDC nominal with
an extended VINMIN of 32.5 VDC.
14.90 mm
(0.59'')
Analysis of the transformer design begins with the
given input parameters:
• VIN = 36V
• Frequency = 150 kHz
• TP = 6.667 x 10-6
Champs Technologies
MCHP-045-V31-1
The intended output voltage was meant to supply a
typical bus voltage for distributed power applications
and the output voltage. VO = 12.00V and the maximum
output load current, IO = 25A
In the design of the magnetics, users must select the
minimum number of turns. There is a cost or penalty to
placing real-world turns on a magnetic structure such
as, resistance, voltage drop and power loss. Therefore,
use the least number of integer turns possible.
Thereafter, a reasonable assessment for turn ratio,
duty cycle, peak flux density, and core loss can be done
until a satisfactory point is reached for the designer.
The duty cycle (more than each half-period) to produce
the desired output is as follows:
• TON = 2.89 µs
• D = TON/TP = 0.434
Over a full period, the duty cycle is 86.8% at a VIN of
36 VDC.
In this design, the following regulation drops are used:
• Secondary MOSFET drop, VFETSEC = 0.1V
• Total trace drops, VDROP = 0.2V
• Primary MOSFET drop, VFETPRI = 0.6V
EQUATION 9:
VO
=
NS
( V IN – V FETPRI ) × ------- – V FETSEC – V DROP × 2D
NP
5.90 mm
(0.23'')
9.80 mm (0.39'')
No substitute exists for the necessary work to perform
calculations sufficient to evaluate a particular core size,
turns, and core and copper losses. These must be
iterated for each design. One of the design
considerations is to maximize the duty cycle, but the
limitation of resolution offered by integer turns will
quickly lead to the turn ratio of NP = 5 and NS = 2.
16.90''
(0.67 mm)
This core shape is a tooled core and is available from
Champs Technologies. In general, a power material in
the frequency range of interest must be considered.
Materials such as 2M, 3H from Nicera™, the PC95
from TDK™, or the 3C96, 3C95 from Ferroxcube™ are
the most recommended options. The peak-to-peak and
rms flux densities arising from this core choice are
shown in Equation 10.
EQUATION 10:
8
( V IN × t ON ) × 10
B PKPK = -------------------------------------------NP × AC
3
B PKPK = 4.624 × 10 Gauss
t ON
B RMS =
2----×
TP
∫
8 2
( V IN × t ON ) × 10
-------------------------------------------- dT
2 × NP × AC
O
3
B RMS = 2.153 × 10 Gauss
= 12.03V
DS01369A-page 14
© 2011 Microchip Technology Inc.
AN1369
The power loss density is calculated using the
parameters shown in Table 4.
TABLE 4:
Material
3C92
3C96
3F35
Note:
FIT PARAMETERS TO CALCULATE THE POWER LOSS DENSITY
f (kHz)
Cm
x
y
Ct1
Ct0
20-100
26.500
1.19
2.65
2.68E-04
5.43E-02
3.75
100-200
0.349
1.59
2.67
1.51E-04
3.05E-02
2.55
200-400
1.19E-04
2.24
2.66
2.08E-04
4.37E-02
3.29
20-100
5.120
1.34
2.66
5.48E-04
1.10E-01
6.56
100-200
8.27E-02
1.72
2.80
1.83E-04
3.66E-02
2.83
200-400
9.17E-05
2.22
2.46
2.33E-04
4.72E-02
3.39
400-1000
1.23E-08
2.95
2.94
1.38E-04
2.41E-02
2.03
Source – New ER Cores for Planar Converters, Ferroxcube™ Publication 939828800911, Sept. 2002.
Core loss density can be approximated by the formula
shown in Equation 11. The core constants are made
available by Ferroxcube™. In this design:
•
•
•
•
•
•
•
•
•
Ct2
Temp = 50oC
Frequency = 150000 Hz
B = Brms * 10-4 = 0.2153 Tesla
x =1.72
y = 2.80
Ct2 = 1.83 * 10-4
Ct1 = 3.66 * 10-2
Ct0 = 2.83
Cm = 8.27 * 10-2
EQUATION 11:
SECONDARY RMS
CURRENT
I SEC = I O ×
D
I SEC = 16.47A
Primary rms current is calculated as shown in
Equation 13:
EQUATION 13:
PRIMARY RMS CURRENT
I PRI = I O ×
CORE LOSS DENSITY
Core Loss Density Pcore
2
x
y
C m × Freq × B × ⎛ C t0 – C t1 × Temp + C t2 × Temp ⎞
⎝
⎠
= -----------------------------------------------------------------------------------------------------------------------------------------------1000
3
P = 1.307 × 10 mW/Cm3
CoreLoss = P × V E × 10
EQUATION 12:
–3
CoreLoss = 2.052W
NS
2D × ------NP
I PRI = 9.317A
The DCR values are computed from the CAD
drawings:
• Secondary DCR: SecDCR = 0.0023E
• Primary DCR: PriDCR = 0.025E
Secondary copper loss is multiplied by two because it
is a center tapped winding.
EQUATION 14:
Sec_Loss = 2 * I2SEC * Sec_DCR = 1.248W
One of the benefits of using planar construction is the
opportunity to utilize 2 oz., 3 oz., and 4 oz. copper
weight, which results in very thin copper. The impact is
that skin depth and proximity loss factors are usually
considerably reduced versus using wire wound
magnetic structures. The copper losses are calculated
using DC Resistance (DCR).
Pri_Loss = I2PRI* Pri_DCR = 2.17W
Total_Loss = Sec_Loss + Pri_Loss + Core Loss
Total_Loss = 5.466W
The secondary rms current in each half of the center
tapped winding is shown in Equation 12.
© 2011 Microchip Technology Inc.
DS01369A-page 15
AN1369
The stacking of the main transformer
arrangement is shown in Table 5.
TABLE 5:
Planar Output Inductor Design
layers
The output inductor serves the following functions:
• Stores the energy during the OFF period to keep
the output current flowing continuously to the
load.
• Smooths out and averages the output voltage
ripple to an acceptable level.
STACKING LAYERS FOR
PLANAR TRANSFORMER
Layers
Cu Weight
(Oz.)
Winding
Primary
Sec1
Layer 1
Sec2
Sec2
2
Layer 2
2
Layer 3
Sec1
2
Layer 4
2
Layer 5
Primary
4
Layer 6
4
Layer 7
Sec1
2
Layer 8
2
Layer 9
Primary
2
Layer 10
3
Layer 11
Sec2
3
Layer 12
Layer 13
2
Primary
4
Layer 14
4
Layer 15
Sec1
2
Layer 16
2
Layer 17
Sec2
2
Layer 18
Turns
2
5
FIGURE 17:
Q1
2
2
FULL-BRIDGE CONVERTER WITH CENTER TAPPED FULL WAVE SYNCHRONOUS
RECTIFIER
Q3
TX
Q6
LL
VPK2
IPRI
L0
VPRI
C0
Q2
DS01369A-page 16
Q4
V0
Q5
© 2011 Microchip Technology Inc.
AN1369
FIGURE 18:
PLANAR OUTPUT
INDUCTOR
• Switch turn ON time, TON = 2.89 μs
• Total Switching period, TP = 6.667μs
• Duty cycle, D = TON/TP = 0.434
18.35 mm
(0.72'')
Over a full period the duty cycle is 86.8% at a
VINMIN of 36 VDC.
12.00 mm
(0.47'')
The duty cycle (more than each half-period) to produce
the desired output is as follows:
Champs Technologies
MCHP1825-V31-1
EQUATION 15:
V
O
= (V
IN
–V
FETPRI
N
S
) × ------- – V
–V
× 2D
FETSEC
DROP
N
P
15.0 mm
(0.59'')
V O = 12.03V
5.40 mm
(0.21'')
9.80 mm (0.39'')
In the case of output inductor, consider the choice of
inductance value at the maximum off time. This occurs
in PWM regulated DC/DC converters at the maximum
input voltage, VINMAX = 76V, and the feedback loop
adjusts the switch ON time accordingly.
TONMIN = 1.415 µs
The duty cycle is as follows:
D_MIN = TONMIN/TP = 1.3689 µs
The peak voltage at the transformer secondary is as
shown in Equation 16.
EQUATION 16:
NS
V PK2 = ( V INMAX – V FETPRI ) × ------- – V FETSEC – V DROP
NP
V PK2 = 28.26V
Maximum output load current, IO = 25A. A ripple current of 25% of the total output current is considered in
this design.
EQUATION 17:
I MIN = I O × 0.25 = 6.5A
EQUATION 18:
OUTPUT INDUCTANCE
(LOMIN)
( V PK2 – V O ) × T ONMIN
L OMIN = --------------------------------------------------------- = 3.54μH
I MIN
This core is also a tooled core as the main
transformer, TX1. It is available from Champs
Technologies as PN MCHP1825-V31-1. Materials such
as 7H from Nicera™, the PC95 from TDK™, or the
3C94, 3C92 from Ferroxcube™ are the recommended
choices.
•
•
•
•
Core cross section, AC = 0.4 cm2
Core path length, LCORE = 3.09 cm
Rated output current: IRATED = 17A
Defined saturation current: ISAT = 20A
The process of inductor design involves iterating the
number of turns possible and solving for a core air gap.
The air gap is checked for operating the flux below
maximum rated flux in the core material at the two
operating current values that is rated current and
saturation current.
In this design, if the 18 layers are available, these
layers can be split into balanced integer turns. This is a
practical method and the number of turns, Nt = 6.
In this design, a fringing flux factor assumption of 15%
is done, which is FFF = 1.15.
The iterative process begins by calculating the air gap
equation. The air gap is calculated using Equation 19.
EQUATION 19:
2
In this design, the core window height and its adequacy
in terms of accommodating the 18 layer PCB stack is to
be assessed since the windings/turns for the inductor
are also embedded.
© 2011 Microchip Technology Inc.
–8
⎛ 0.4 × π × Nt × A C × 10 ⎞
L GAP = ⎜ ------------------------------------------------------------------⎟ × FFF
L OMIN
⎝
⎠
= 0.058cm
L GAP
- = 0.023inch
L GAPIN = -----------2.54
DS01369A-page 17
AN1369
EQUATION 20:
OPERATING FLUX DENSITY
AT DEFINED SATURATION
CURRENT
0.4 × π × Nt × I SAT
B DC = -----------------------------------------------L GAP
3
B DC = 2.598 × 10 Gauss
EQUATION 21:
OPERATING FLUX DENSITY
AT RATED CURRENT
0.4 × π × Nt × I RATED
B RATED = ------------------------------------------------------L GAP
3
B RATED = 2.208 × 10 Gauss
The BDC and BRATED values are conservative
compared to the commercially rated devices. Typical
BMAX values are 3000 Gauss at 100ºC.
The required AL value is calculated, as shown in
Equation 22.
EQUATION 22:
AL VALUE
9
L OMIN × 10
A L = ------------------------------- = 98.32mH
2
Nt
This is helpful for instructing the core manufacturer for
gapping instructions. The inductor traces are designed
using a CAD package and are integrated into the PCB
layout package. The CAD package facilitates the
calculation of trace resistance for each layer. The
calculated DCR values DCRRATED = 3.5 * 10-3E.
Copper loss is computed at the DC values of rated and
saturation-defined currents, as shown in Equation 23.
EQUATION 23:
2
Cu LossSAT = ( I SAT ) × DCR RATED
To drive each leg (high side and low side) of the gates,
the high side/low side driver, or low side driver with
isolated drive transformer is required. A minimum of
500 VDC isolation is required in the drive transformer
from the high side to low side winding. Because the
gate drive is derived from the secondary side controller,
primary to secondary 2500 VDC isolation is required.
The following critical parameters must be controlled
while designing the gate drive transformer:
• Leakage inductance
• Winding capacitance
A high leakage inductance and capacitance causes an
undesirable gate signal in the secondary, such as
phase shift, timing error, overshoot and noise. High
winding capacitance occurs when the design has a
higher number of turns. High leakage inductance
occurs when the turns are not laid uniformly. Because
planar magnetics are used in this application, these
parameters may not be a problem. Since the absolute
number of turns required is low and the primary and
secondary side high/low drive windings can be
interleaved to minimize leakage without increasing the
overall capacitance.
Typical gate drive transformers are designed with
ferrite cores to reduce cost and to operate them at high
frequencies. Ferrite is a special material that comprises
high electrical resistivity and can be magnetized quickly
with minor hysteresis losses. Because of its high
resistance, eddy currents are also minimal at high
frequency.
Selection of Core Materials and Core
Selection of core material depends on the frequency of
the operation. 3F3 from Ferroxcube™ is one of the best
options for the operating frequencies below 500 kHz.
The power loss levels of gate drive transformers is
usually not a problem and thus Ferroxcube RM4/ILP is
selected. The magnetic parameters of Ferroxcube
RM4/ILP are as follows:
•
•
•
•
Cu LossSAT = 1.4W
EQUATION 24:
2
Cu LossRATED = ( I RATED ) × DCR RATED
Cu LossRATED = 1.012W
One of the design goals is to make it universal for other
lower and higher power implementations of the digital
converter and to keep the overall efficiency high. It fits
comfortably with its footprint in the PCB. However, we
consider that a smaller core and footprint optimization
is quite possible.
DS01369A-page 18
Planar Drive Transformer Design
AC = 0.113 cm2
Lm = 1.73 cm
AL =1200 nH
µEFF = 1140
One of the primary goals of the design is to embed all
the magnetics as part of the overall PCB design of the
main power stage. A small size core geometry is
selected, that has sufficient window height to
accommodate the overall PCB thickness and also
gives reasonable window width to accommodate the
PCB trace width that comprises the turns. The
resulting “footprint” or core cut-out required of the RM4/
ILP was found to be acceptable.
© 2011 Microchip Technology Inc.
AN1369
We will iterate the primary turns to arrive at a suitable
peak flux density and magnetizing current using the
formula shown in Equation 25.
The peak and rms flux densities can be pushed higher.
However, a reasonably low value of magnetizing current has been maintained such that the driver is not
loaded much.
EQUATION 25:
EQUATION 29:
8
NP
( V IN × T ON ) × 10
= ---------------------------------------------B PKPK × A C
CALCULATION OF
MAGNETIZING
INDUCTANCE
2
In the application, VIN = 12V, as set by the bias supply.
The operating frequency for main power processing is
selected as 150 kHz. The result is the gate drive
transformer operates at the same frequency.
The duty cycle is also determined by the power stage.
The basic input parameters, TP and TON are set.
Iterating for primary turns, NP = 10.
The peak-to-peak flux density can be achieved, as
shown in Equation 26:
LA L = N P × A L × 10
–9
–4
LA L = 1.2 × 10 Henry
Or,
2
–8
0.4 × π × μEFF × ( N P ) × A C × 10
L M = ------------------------------------------------------------------------------------------Lm
–5
L M = 9.57 × 10 Henry
Conversely, the inductance minimum will be
between ~70 µH.
L MIN = 0.75L M Henry
EQUATION 26:
PEAK-TO-PEAK FLUX
DENSITY
–5
L MIN = 6.699 × 10 Henry
8
( V IN × T ON ) × 10
B PKPK = ---------------------------------------------NP × AC
The magnetizing current is thus reasonable for this
application, and is shown in Equation 30:
3
B PKPK = 3.069 × 10 Gauss
EQUATION 30:
The peak flux density is shown in Equation 27, which
yields a volt-µs rating of (VIN * TON) = 37.7. This is well
below the typical saturation curves for 3F3 of 3000
Gauss at 85ºC operational ambient temperature.
However, potential saturation is not a design concern.
EQUATION 27:
PEAK FLUX DENSITY
( V IN × T ON ) × 10
= ---------------------------------------------2 × NP × AC
The rms flux density is calculated, as shown in
Equation 28.
1
F R = --------------------------------------------------2 × π × ( LM × CD )
F R = 2.3MHz
RMS FLUX DENSITY
T ON
B RMS =
Assuming the worst case, the distributed capacitance
is taken is as follows: CD = 50 * 10-12 Farad.
EQUATION 31:
3
B PK = 1.534 × 10 Gauss
EQUATION 28:
di = 0.362A
Any ringing on the gate drive waveforms due to the
transformer will possess a frequency of 2.3 MHz.
8
B PK
V IN × T ON
di = ------------------------LM
2----×
TP
∫
8 2
( V IN × T ON ) × 10
---------------------------------------------2 × NP × AC
× DT
O
3
B RMS = 1.363 × 10 Gauss
results in mW of core loss.
© 2011 Microchip Technology Inc.
DS01369A-page 19
AN1369
In this design, the selection of track width or trace width
was fairly conservative. Given the RM4/ILP core
window width of 2.03 mm (80 mils), and an allowable
PCB width accommodated inside this core
of 1.63 mm (64 mils), and a further conservative
assumption of trace-to-trace clearance of 0.3 mm (12
mils), we can either place 2T/layer of 0.39 mm (15 mil)
width or 3T/layer of 0.18 mm (7 mils) width. If 4 oz.
copper was used per layer the 0.18 mm trace width
would result in too much “under-etch” in the fabrication.
We had ~14 layers dictated by the power stage and the
resulting PCB thickness of 3.5 mm -3.8 mm could be
easily accommodated by the RM4/ILP core window
height. Hence, it is easier to select 2T/layer. This
selection also allowed three opportunities for an
interleave to occur between the primary and each
secondary drive winding. A choice of 3T/layer may
have resulted in an imbalance and with less opportunity
for interleave.
EQUATION 34:
–6
T ON = 2.89 × 10 Sec
T
T OFF = -----P- – T ON
2
–7
T OFF = 4.433 × 10 Sec
The core used on this part = E5.3/2.7/2-3C96
The core parameters are as follows:
• LM = 1.25 cm
• AC = 0.0263 cm2
• VE = 0.0333 cm3
The nominal current sense termination resistor
value: RB = 10.0E.
EQUATION 35:
I MAX
V PKSECY = ------------ × R B
NS
Current Sense Transformer Design
The current sense transformer selected is a
conventional stand-alone magnetic device. The
decision was made earlier to have a 1:100 current
transformation ratio. Therefore, it is difficult to
implement this device as an embedded structure.
We repeat some aspects of the TX1 main transformer
design such as switching frequency.
3
F SW = 150 × 10 HZ
1
T p = ---------F SW
–6
T P = 6.667 × 10 Sec
The transformation ratio, NC = NS/NP = 100
Maximum rated current, IMAX = 10A
Therefore, secondary rms current is computed, as
shown in Equation 33:
SECONDARY RMS
CURRENT
I RMSPRIM
I RMSSECY = ----------------------NC
I RMSSECY = 0.093A
DS01369A-page 20
Therefore, the rating is 0.1 V/amp.
EQUATION 36:
8
( V PKSECY × T ON ) × 10
B PK = -----------------------------------------------------------NS × AC
EQUATION 32:
EQUATION 33:
V PKSECY = 1V
B PK = 109.886Gauss
It is considered that the peak flux density is very low
and it is acceptable. Usually, the current to voltage gain
is this low in most switched mode converters. The
current ramp signal at the current sense (CS) input for
most analog controllers is <1V, so always select a low
value termination resistor. In this case, the voltage gain
is conditioned with differential op amps prior to sending
it to the input ADC of the dsPIC® DSC.
It is helpful to know that higher current to voltage gains
are possible simply by selecting higher value
termination resistors. The only limitation will be a
ceiling imposed by the saturation of the ferrite core.
The volt-µs rating of the CH-1005 Champs
Technologies is 58V-µs. In this design, if a termination
impedance of 100Ω is selected, a 10V signal amplitude
is gained. The current transformer reproduces the
current wave shape until it is not saturated, that is as
long as it is performing as a transformer. In this design,
a maximum ON time of 5.8 µs can be permitted.
© 2011 Microchip Technology Inc.
AN1369
EQUATION 38:
The rated maximum flux is shown in Equation 37.
RMS FLUX DENSITY
t ON
EQUATION 37:
–6
B RMS =
8
( 58 × 10 ) × 10 B RATED = -------------------------------------------NS × AC
2----×
TP
∫
8 2
( V PKSECY × T ON ) × 10
------------------------------------------------------------ dTp
2 × NS × AC
O
B RMS = 51.159Gauss
3
B RATED = 2.205 × 10 Gauss
The BPK is rated as 2200 Gauss peak for 100ºC
operation unipolar excursion. The rms flux density is
calculated, as shown in Equation 38.
EQUATION 39:
x
2
y
C m × F × ( B RMS ) × ( C t0 – Ct1 × Temp + C t2 × Temp )
CoreLossDensity, P = ---------------------------------------------------------------------------------------------------------------------------------------1000
3
P = 0.048 mW/cm
where setting up core loss coefficients:
Cm = 8.27 * 10-2
x = 1.72
y = 2.80
Temp = 30
Ct1 = 3.66 * 10-2
Ct2 = 1.83 *10-4
Ct0 = 2.83
F = 1.5 * 105
CoreLoss = P × V E × 10
–3
–6
CoreLoss = 1.592 × 10 W
Core loss is about zero or negligible.
Secondary SecDCR = 6.6E.
© 2011 Microchip Technology Inc.
DS01369A-page 21
AN1369
FIGURE 19:
CURRENT TRANSFORMER
2
3.70 mm
(0.146'')
Secloss = ( I RMSSECY ) × SecDCR
2
Priloss = ( I RMSPRIM ) × PriDCR
1.85 mm
(0.073'')
1
8
= 0.057W
100T
7
1T
3
= 0.173W
5.3 mm
(0.21'')
EQUATION 40:
7
+
8
TotalLoss = Secloss + Priloss + Coreloss
= 0.23W
where:
4.9 mm
(0.19'')
Secloss = Secondary copper losses
Priloss = Primary copper losses
0.25 mm
(0.010'')
PriDCR = 0.002E
SecDCR = 6.6E
Total loss for this device at maximum ratings is less
than 1/4W.
Calculate the inductance value for the selected 3C96
material.
7.80 mm
(0.31'')
5.3 mm
(0.21'')
EQUATION 41:
2
L AL = ( N S ) × A L × 10
L AL = 3 × 10
–3
–9
~ 3mH
0.006
where:
Ns = 100
0.15
6.8 mm
(0.27'')
AL = 300 nH
EQUATION 42:
L MIN = L AL × 0.75
= 2.25mH
Minimum secondary inductance = 2.25 mH.
X L = 2 × π × f × L MIN
3
= 2.12 × 10 E
Effective termination impedance is as shown in
Equation 43:
Planar Auxiliary Power Supply
Transformer Design
The digital DC/DC converter requires an auxiliary
power supply. The dsPIC DSC requires 3.3V and the
gate drivers require 12V.
The dsPIC DSC must have power supplied to it prior to
start-up of the power converter. The scheme to
accomplish this is to utilize an analog converter for
start-up and also for continuous operation. This avoids
possible glitches or uncontrolled operation events
during abnormal operation or unanticipated transient
conditions. The analog controller requires a boot strap
supply once it has gone through soft-start.
EQUATION 43:
X L × Rb
X EFF = -------------------X L + Rb
X EFF = 9.953E
Deviation from ideal is < 0.1%.
DS01369A-page 22
© 2011 Microchip Technology Inc.
AN1369
The dsPIC DSC requires 3.3V. A linear regulator is
inserted prior to 3.3V so that the headroom required at
one output is 4V. The 3.3V output voltage before
regulator V01 = 4V.
•
•
•
•
•
•
EQUATION 49:
2 × I SCDC
PeakSecondaryCurrent, I SCPK = -----------------------DS
Load current, I3.3V = 0.3A
12V output voltage before regulator, V02 = 12V
Load current, I12V = 0.4A
Total output power = 6W
Consider an overall efficiency of 80%
Input power = 7.5W
2----------------× 0.1 = 3.33A
0.6
D
------S × I SCPK
3
= 1.489A
SecondaryRMSCurrent, I SRMS =
Consider minimum input voltage, VINMIN = 32V. The
converter is designed to operate at a maximum duty
cycle, D = 40%. The nominal operating frequency, FSW
of the IC is 250 kHz.
where:
Short circuit current: ISCDC = 1A
Secondary duty cycle: DS = 0.6
The turns ratio for 12V and 3.3V output is shown in
Equation 50.
EQUATION 44:
3
F SW = 250 × 10 Hz
EQUATION 50:
N P [ V IN – ( I PPK × R DS ( ON ) ) ] × D
------- ≥ ---------------------------------------------------------------------------NS
( V OUT + V fD1 ) × ( 0.8 – D )
Total period, TP = 4 µs
On period, TON = 1.6 µs
NP
---------- = 2.60
N S12
EQUATION 45:
InputPower
AverageCurrent, I AVE = ----------------------------------------------------------MinimumInputVoltage
NP
------------- = 7.828
N S 3.3
7.5W
= ------------ = 0.234A
32V
where:
Voltage drop on the diode, VFD1 = 0.7V
RDS(ON) = 4E
Peak current of a Discontinuous mode Flyback
Converter, IPPK, is shown in Equation 46.
A quick check of the available standard core structures
indicates that there was a distinct possibility to use a
standard size RM-4 core.
EQUATION 46:
I AVE
I PPK = 2 × ----------- = 1.17A
D
Primary rms current, IrmsPRIM is shown in Equation 47:
The RM-4 core parameters are:
EQUATION 47:
I RMSPRI = I PPK ×
An important feature of this core for this design is, it
consists of a core window with nominal 4.3 mm that clears
the 4.0 mm PCB thickness. The overall height of this core
is 7.8 mm, so its height is < 10 mm of the DC/DC
Converter mechanical height.
T ON
--------------- = 0.427A
3 × TP
•
•
•
•
AE = 0.145 cm2
ICORE = 1.73 cm
µ = 2000
VE = 0.25 cm3
EQUATION 48:
V INMIN × D
PrimaryInduc tan ceL P = ----------------------------F SW × I PPK
32 × 0.4
= ----------------------------------= 43.6μH
250000 × 1.17
© 2011 Microchip Technology Inc.
DS01369A-page 23
AN1369
FIGURE 20:
AUXILIARY PLANAR
TRANSFORMER
EQUATION 53:
9
L P × 10
A L = --------------------2
( N PRI )
15.51 mm
(0.61'')
2
1
5
A L = 164.063nH
6
The flux density is calculated, as shown in Equation 54.
11.51 mm
(0.45'')
EQUATION 54:
7
4
0.4 × π × N PRI × I PPK
B PK = ------------------------------------------------------L GAP
8
3
3
B PK = 1.959 × 10 Gauss
Inner Layer Top Points
1
*
BPK is lesser than the BSAT limitation of 3000 Gauss
at 85ºC. The required maximum output power for DCM
operation, factoring in efficiency is shown in
Equation 55.
5
*
6T
16T
6
2
3
*
7
*
6T
EQUATION 55:
2T
4
1
2
P O = --- × L P × ( I PPK ) × F SW
2
8
The footprint (length x width) of the device is not greater
than that of a stand-alone magnetic device. The
footprint shown in Figure 20 has been further reduced
in the final implementation and the entire bias converter
has been implemented as part of the embedded
design.
P O = 7.46W
The peak AC flux density is calculated, as shown in
Equation 56:
EQUATION 56:
8
( V IN × T ON ) × 10
B PKAC = ---------------------------------------------N PRI × A E
EQUATION 51:
8
V INMIN × T ON × 10
- = 16T
N PRI = --------------------------------------------------B MAX × A E
3
B PKAC = 2.48 × 10 Gauss
where:
The rms flux density is calculated, as shown in
Equation 57.
BMAX = 2200Gauss
The required center post air gap based on the formula
is shown in Equation 52:
EQUATION 57:
T ON
EQUATION 52:
2
–8
0.4 × π × ( N PRI ) × A E × 10
L GAP = ----------------------------------------------------------------------------- × FFF
LP
B RMS =
1----×
TP
∫
8 2
( V IN × T ON ) × 10
---------------------------------------------- dTp
2 × N PRI × A E
O
B RMS = 771.454Gauss
L GAP = 0.012cm
L GAPIN
The core loss equation parameters are used for
Ferroxcube “3C92” material at 40ºC rise in
temperature.
L GAP
= -----------2.54
–3
L GAPIN = 4.591 × 10 in
The AL value is calculated, as shown in Equation 53.
DS01369A-page 24
© 2011 Microchip Technology Inc.
AN1369
EQUATION 58:
A calculated core loss value of 76 mW is acceptable,
so using ferrite for the core material is a good choice.
B RMS
B = -------------10000
1
f = ----TP
The CAD package is used in the PCB trace design to
calculate the trace DCR for the primary and secondary
DC resistance.
• DCRSEC = 0.023E
• DCRPRI = 0.088E
5
f = 2.5 × 10 Hz
The overall loss is shown in Equation 60.
°
Temp = 40 C
EQUATION 60:
The operating coefficients are:
TotalLoss = CuLoss + CoreLoss
Cm = 9.17 x 10-5
TotalLoss = 0.142
EQUATION 59:
CORE LOSS DENSITY
FORMULA
2
( C t0 – C t1 ) × Temp + C t2 × Temp
x
y
P = C M × f × B × --------------------------------------------------------------------------------------1000
P = 303.063 mW/cm3
The only efficiency penalty in using a digital controller
is the bias supply converted efficiency of 80%. All
converters will share approximately the same FET
driver loss.
The only further penalty is the footprint or space occupied by the bias supply within the available outline
package of the converter itself. The main advantage as
discussed at the outset is that the controller is “always
on”, that is, it supplies power in a controlled fashion and
rides out abnormalities and transients that might at the
least require a hiccup start-up for an analog controller.
where:
Ct2 = 2.33 * 10-4
Ct1 = 4.72 * 10-2
Ct0 = 3.39
x = 2.22
y = 2.46
CoreLoss = P × V OL × 10
–3
CoreLoss = 0.076W
EQUATION 61:
2
2
CopperLoss = ( I rmsPRI × DCR PRI ) + ( I rmsSEC × DCR SEC )
CopperLoss = 0.067W
© 2011 Microchip Technology Inc.
DS01369A-page 25
AN1369
DESIGNING A DIGITAL QUARTER
BRICK CONVERTER
The Quarter Brick DC/DC Converter was designed
using the dsPIC33FJ16GS502. The design analysis is
described in the following sections.
FIGURE 21:
Sensing
Element
REAL WORLD SIGNAL
CHAIN: DIGITAL POWER
SUPPLY
Scaling
Filter
What is a Digitally Controlled Power
Supply?
A digital power supply can be broadly divided into
power control and power management. Power control
is a relatively new trend when compared to power
management.
Power management is data communication,
monitoring, data logging, power supply protection, and
sequencing of the outputs. This is not real-time
because the switching frequencies of the converters
are higher than the power management functions.
Power control is defined as the flow of power in the
converter and it is controlled from one PWM cycle to
another PWM cycle. Power control is performed with
both the DSCs and analog controllers without much
variation in the design.
ADC
CMP
Load
Power Converter
Analog Hardware
DSC Core
PWM
Digital Signal Controller (DSC)
DIGITAL FULL-BRIDGE DESIGN
In the digital power supply design, the power train is the
same as the analog power converter design. The
difference exists in the way it is controlled in the digital
domain. The analog signals, such as voltage and
current, are digitized by using the ADC, and fed to the
DSC. These feedback signals are processed with the
digital compensator and modulate the PWM gate drive
to get the desired control on the output.
Advantages of DSCs
A few critical peripherals that are used in digital power
supplies are:
In modern SMPS applications, power conversion is
only part of the total system solution. In addition, many
other requirements and features are required to make
the system more reliable. These features can be
realized using a DSC and are as follows:
• PWM generator
• ADC
• Analog comparator
• Improved level of portability to other converter
topologies
• Adaptive and predictive control mechanism to
achieve high efficiency and improved dynamic
response
• Software implementation of the protections to
reduce the component count
• Improved scalability
• Active load balancing in the parallel connected
systems
• Improved overall system reliability and stability
• System performance monitoring capability
• Real time algorithms for the regulation of power
converters
• Less susceptibility to parameter variations from
thermal effects and aging
PWM Generator
The PWM generator must have the ability to generate
high operating frequencies with good resolution,
dynamically control PWM parameters such as duty
cycle, period, and phase, and to synchronously control
all PWMs, fault handling capability, and CPU load
staggering to execute multiple control loops.
The PWM resolution determines the smallest
correction to be done on the PWM time base.
EQUATION 62:
PWMClockFrequency PWMResolution = --------------------------------------------------------------DesiredPWMFrequency
EQUATION 63:
PWMClockFrequency
BitResolution = log 2 ⎛ ----------------------------------------------------------------⎞
⎝ DesiredPWMFrequency⎠
DS01369A-page 26
© 2011 Microchip Technology Inc.
AN1369
EXAMPLE 1:
EQUATION 64:
ADCResolution = FullScaleVoltage
----------------------------------------------n
2
where:
PWM Clock Frequency = 60 MHz
Desired PWM Frequency = 500 kHz
PWM Resolution = 120 = One part in 120
n = Number of bits in the ADC
Bit Resolution = log2 (120) ~ 7 bits
EXAMPLE 3:
EXAMPLE 2:
CALCULATING THE ADC
RESOLUTION
Example A:
PWM Clock Frequency = 1000 MHz
ADC full voltage = 3.3V
Desired PWM Frequency = 500 kHz
Number of bits in an ADC = 10
PWM Resolution = 2000 = One part in 2000
Therefore, ADC resolution = 3.22mV
Bit Resolution = log2 (2000) ~ 11 bits
A resolution of 11 bits indicates that the user can
have 2048 different steps from zero to full power of the
converter. This gives finer granularity in control of the
duty cycle when compared to the 7-bit resolution where
only 128 steps are available for control.
Analog-to-Digital Converter (ADC)
All the real world feedback signals are continuous
signals, and should be digitized to process in the DSC.
A built-in ADC performs this process. The ADC
requires a voltage signal that is to be provided as an
input. The input signals are scaled down to the ADC
reference voltage. These voltages are typically 3.3V
and 5V.
FIGURE 22:
ANALOG-TO-DIGITAL
CONVERTER (ADC)
AN1
Inputs
MUX
SAR
Core
Data
Format
ADC
Result
Buffers
ANx
Sample and Hold Circuit
In digital SMPS applications, higher bit resolutions and
higher speed are the two characteristics that determine
the ADC selection.
Another parameter to be considered is the sample and
conversion time (time taken by the ADC to sample an
analog signal and to deliver the equivalent digital
value). Usually, the conversion time is specified in
million samples per second (Msps). For example, if the
conversion time is specified as 2 Msps, the ADC can
convert two million samples in one second. Hence, the
sample and conversion time is 0.5 µs.
The conversion speed plays an important role to
replicate the sampled signal. As per Nyquist criterion,
the sampling frequency must be greater than twice the
bandwidth of the input signal (Nyquist frequency). As a
guideline in SMPS applications, sampling of the analog
signal at a frequency greater than 10x of the signal
bandwidth is required to maintain fidelity.
Analog Comparator
Most of the DSCs consist of an analog comparator as
a built-in peripheral, which enhances the performance
of SMPS applications. The analog comparator can be
used in the cycle-by-cycle control method to improve
the response time of the converter and also in fault
protection applications.
ADC and PWM Resolution in SMPS
Applications
Usually, analog controllers provide fine resolution to
position the output voltage. The output voltage can be
adjusted to any arbitrary value, and is only limited by
loop gain and noise levels. However, a DSC consists of
a finite set of discrete levels, because the quantizing
elements, ADC and PWM generator, exist in the digital
control loop. Therefore, the quantization of the ADC
and PWM generator is critical to both static and
dynamic performance of switched mode power
supplies.
The ADC resolution indicates the number of discrete
values it can produce over the range of analog values,
hence, the resolution is expressed in bits.
© 2011 Microchip Technology Inc.
DS01369A-page 27
AN1369
The ADC resolution must be lower than the permitted
output voltage variation to achieve the specified output
voltage regulation. The required ADC resolution is
shown in Equation 65.
EQUATION 65:
NA ⁄
D
Vo ⎞
⎛ V MAX A ⁄ D
= Int log 2 ⎜ -------------------------- × ----------⎟
V
ΔV
⎝
REF
o⎠
where:
VMAX A/D = ADC full range voltage in this
application
VREF = Reference voltage
The digital PWM produces an integer number of duty
values (it produces a discrete set of output voltage
values). If the desired output value does not belong to
any of these discrete values, the feedback controller
switches between two or more discrete values of the
duty ratio. In digital control system, this is called the
limit cycle and is not desirable.
Limit cycling can be avoided by selecting the change in
output voltage caused by one LSB change in the duty
ratio has to be smaller than the analog equivalent of the
LSB of ADC. For a buck type forward regulator, NPWM,
is shown in Equation 66.
EQUATION 66:
NPWM > = NA/D + log2
NA/D = Number of bits in ADC
VO = Signal to be measured (output voltage)
ΔVO = Allowed output voltage variation
Int [ ] = Denotes taking the upper rounded integer
EXAMPLE 4:
ADC Resolution
Vref
VMAX A/D * D
where:
NPWM = Number of bits in a PWM controller
D = Duty ratio
To generalize, NPWM must be a minimum of one
bit more than NA /D.
VMAX A/D = 3.3V
Note:
VO = 12V
Δ VO = 1% of 12V = 120 mV
VREF = 2.6V which is 80% of the ADC full range
voltage
To have a stable output, that is without
limit cycling, the downstream quantizer of
the ADC should have higher resolution.
NA/D = 7, (therefore, a 7-bit ADC can be used)
ADC resolution can also be expressed as follows:
ADC LSB << (VREF/VO) * ΔVO
TABLE 6:
SWITCHING FREQUENCIES OF THE CONVERTER
Signal Name
Description
Type of Signal
dsPIC® DSC
Resource
Frequency of
Operation
PWM1H
Gate Drive for Q1, Q4
PWM Output
PWM1H
150 kHz
PWM1L
Gate Drive for Q2, Q3
PWM Output
PWM1L
150 kHz
Synchronous Rectifier Gate Drive
PWM Output
PWM3H,PWM3L
150 kHz
—
—
75 kHz
PWM3H,PWM3L
—
DS01369A-page 28
Control Loop Frequency
© 2011 Microchip Technology Inc.
AN1369
TABLE 7:
Pin
DSC PERIPHERALS MAPPED
TO FULL-BRIDGE CONVERTER
Peripheral
Description
1
AN2
Load share
2
AN3
Temp
3
CMP2C
Output overvoltage
4
RP10
TX secondary voltage
5
VSS
Ground
6
CMP4A
TX overcurrent
7
RP2
EXT SYNCI1
8
PGD2
Programming
9
PGC2
Programming
10
VDD
Bias supply +ve
11
RB8
COM1
12
RB15
COM2
13
RB5
Remote ON/OFF
14
SCL1
COM4
15
SDA1
COM3
16
VSS
Ground
17
VCAP
VCAP
18
PWM3H
Sync gate drive
19
PWM3L
Sync gate drive
20
PWM2H
Not connected
21
PWM2L
Not connected
22
PWM1H
Full-Bridge gate drive
23
PWM1L
Full-Bridge gate drive
24
AVSS
Ground
25
AVDD
Bias supply +ve
26
MCLR
Master clear
27
AN0
TX current
28
AN1
12V output
© 2011 Microchip Technology Inc.
DS01369A-page 29
AN1369
FIGURE 23:
dsPIC® DSC RESOURCES FOR THE QUARTER BRICK CONVERTER
Full-Bridge Converter
+
Output Voltage
Synchronous Rectifier
+
CT
12V DC/ 7A
36V DC– 75V DC
Input Voltage
-
-
Drive TX
Drive IC
Drive IC
Drive TX
Drive IC
PWM1H PWM1L AN0
Remote ON/OFF
Opto
Isolator
AN1
dsPIC33FJ16GS502
RB5
RB8
PWM3
RB15
SCL1
SDA1
RP2
AN3
AN2
Ext
Sync
Over
Temp
Load
Share
Ext Communication
DS01369A-page 30
© 2011 Microchip Technology Inc.
AN1369
DIGITAL CONTROL SYSTEM DESIGN
Digital Average Current Mode Control
Technique
Digital control system design is a process of selecting
the difference equation or Z-domain transfer function
for the controller to achieve good closed loop response.
Parameters such as settling time, output overshoot,
rise time, control loop frequency and bandwidth must
be considered to achieve acceptable performance.
Digital current mode control is a new approach for
improving the dynamic performance of high frequency
switched mode PWM converters, and is used in this
design. In this method, the DSC performs the entire
control strategy in software. The Current Mode
Control (CMC) strategy consists of two control loops.
The inner current loop subtracts a scaled version of the
inductor current from the current reference. The current
error is further processed with the PID or PI
compensator and the result is appropriately converted
into duty or phase. Any dynamic changes in the output
load current directly modifies the duty or phase of the
converter. The outer loop subtracts the scaled output
voltage from a reference and the error is processed
using the PID or PI compensator. The output of the
voltage loop compensator provides the current
reference for the inner loop. Current and voltage
compensators allow tuning of the inner and outer loops
to ensure converter stability and to achieve the desired
transient response.
The denominator polynomial of the transfer function
provides the roots of the equation. These roots are the
poles of the transfer function. This equation is called
the characteristic equation.
The nature of the roots of the characteristic equation
provides an indication of the time response. The
system stability can be determined by finding the roots
of the characteristic equation and its location. The
system is considered to be stable if the roots of the
characteristic equation are located in the left half of
the ‘S’ plane. This causes the output response due to
the bounded input to decrease to zero as the time
approaches infinity.
In the Quarter Brick Converter design, the controller is
designed in the continuous time domain, and then
converted to an equivalent digital controller. This
approach is called the digital redesign approach or
digital design through emulation.
FIGURE 24:
AVERAGE CURRENT MODE CONTROL
DCR Compensation
Voltage Loop Compensation
VO*
+
Current Loop Compensation
IL *
VERROR
+
+
PI Control
-
P Control
-
VO
Phase/Duty
VO
Plant
+
IL
VO Decouple
Compensation
ITX
ADC
Sensor
ADC
Sensor
Digital Signal Controller (DSC)
© 2011 Microchip Technology Inc.
DS01369A-page 31
AN1369
Deriving the Characteristic Equation for
the Current Mode Control (CMC)
A simple Buck converter can be used to derive the
characteristic equation.
FIGURE 25:
BUCK CONVERTER
IL
VL
D * VIN
LM
DCR
VX
Buck Inductor
ESR
VIN
IC
Output
Capacitor
IO
VO
Load
C
Based on Figure 25, and applying Kirchhoff's laws
results in the expressions and equations shown in
Equation 67.
EQUATION 67:
(A)
IC = IL – IO
(B)
V O = D × V IN – V L
(C)
VL
V
VL
V
- = -------- = -----LI L = -----L- = ----------XL
2πfL
JωL
sL
(D)
IC
IC
Ic
= --------- = ----V O = I C × X c = -----------2πfC
JωC
sC
The current compensator proportional gain is denoted
as RA, and it has a dimension of resistance. The value
of RA can be determined from the system characteristic
equation. Higher value of RA implies higher current
loop bandwidth. With the current mode control, the ‘D’
term performance in the voltage PID can be achieved.
EQUATION 68:
VX = VO + VL
The current reference (IL*) is generated using the outer
voltage loop.
[IL* = (VO* - VO) * G] (because current loop performs the
function of differential gain in the voltage loop, the outer
voltage loop will have only proportional and integral
gain).
From the physical capacitor system, IC = IL - IO. In the
equation, IO is made as constant and analyzed the
relation between VO and VO*. Therefore, IL = SCVO.
EQUATION 69:
(F)
K
( I L )∗ = ( V O∗ – V O ) × ⎛ K P + -----I⎞
⎝
s⎠
KI
( Ra + sL )
I L × ------------------------ = [ ( V O∗ ) – V O ] × K P + ⎛ -----⎞
⎝
s⎠
Ra
Equation 69 is rearranged to find VO*/VO and the
results are shown in Equation 70.
EQUATION 70:
Ki
( K P × R A ) + ⎛ ----- × R A⎞
VO
⎝s
⎠
---------- = ------------------------------------------------------------------------------------------------------------∗
KI
VO
2
s LC + ( sC × R A ) + ( K P × R A ) + ⎛ -----⎞ × R A
⎝ s⎠
V X = V O + sLI L = R A × [ ( I L∗ ) – I L ] + [ V X – sLI L ]
(E)
[ R A × ( I L∗ ) ]
I L = ------------------------------R A + sL
DS01369A-page 32
© 2011 Microchip Technology Inc.
AN1369
The denominator [s2LC + sCRa + KPRa + (KI/s)Ra]
denotes the characteristic equation. The denominator
should have three roots known as three poles or three
bandwidths, f1 > f2 > f3 (units of Hz), of the controller.
These roots correspond to current loop bandwidth (f1),
proportional voltage loop bandwidth (f2) and integral
voltage loop bandwidth (f3). These roots should be
selected based on the system specifications. f1, f2 and
f3 should be separated with a factor minimum of three
between them. This ensures that any parameter
variation (L and C) due to manufacturing tolerance or
inductor saturation will not affect the stability of the
system.
EQUATION 73:
f3 determines the settling time (TS), that is the output
voltage of the converter takes to settle within 98% of
VO* for a step change in load. Ts should be selected
less than the specification settling time.
Substituting the actual design parameters used in the
Full-Bridge converter to have the KP, KI, RA gains.
TS = 4/2πf3
f2 determines the ability of the controller to track
changes in VO*. If VO* varies, VO can track VO*
variations up to a frequency f2 Hz.
f1 exists only to make the system non-oscillatory or
resonant at frequencies greater than f2.
The gains KP, KI and RA can be determined once f1, f2
and f3 are selected. The characteristic equation:
s3LC + s2CRa + s KP Ra + KI Ra = 0 is a cubic
equation.
Because ‘s’ is -2πf1(ω1), -2πf2 (ω2) and -2πf3 (ω3),
which are the roots of the characteristic equation and
should make the equation equal to zero after
substituting for ‘s’. The three unknown coefficients KP,
KI and RA can be obtained by solving the following
three equations shown in Equation 71:
EQUATION 71:
2
3
2
3
ω1 CR A + ω1 K P R A + K I R A = – ω1 LC
ω2 CR A + ω2 K P R A + K I R A = – ω2 LC
2
ω3 CR A
+ ω3 K P R A + K I R A =
3
– ω3 LC
These coefficients can be solved by using the matrix
method shown in Equation 72 and is made equivalent
to A * Y = B for simplicity purposes.
EQUATION 72:
ω1
2
ω2
2
ω3
2
ω1 1
3
– ω1 LC
CRa
3
ω2 1 × K P R A = – ω2 LC
KI RA
3
ω3 1
– ω3 LC
© 2011 Microchip Technology Inc.
Y1
–1
Y = Y2 = A × B
Y3
Y1 = C RA and RA = Y1/C
Y2 = KP RA and KP = Y2/RA
Y3 = KI RA and KI = Y3/RA
Finding the Gains
• Transformer turns ratio = 5:2
• Primary input voltage, VIN = 76V
• Nominal primary input voltage, VNOM = 48V
The maximum primary input current is selected
as 9.75A and is reflected to the secondary because the
controller exists on the secondary side of the isolation
barrier.
The base value of the current INBASE is 24.38A and the
base value of the voltage VNBASE is 14.2V. All the
voltage and current quantities are referenced with the
base values INBASE and VNBASE.
Transformer secondary voltage is:
• VINS = VIN/turns ratio = 30.4V
• Output inductor L = 3.4e-6 Henry
• DC resistance of the inductor and tracks is
considered as DCR = 0.05E
• Output capacitance, C = 4576e-6F (4400 µF
external to converter)
• Equivalent series resistance of the capacitor,
ESR = 0.0012E
• Switching frequency of the converter,
FSW = 150000 Hz
• Control loop frequency TS is 1/2 of the FSW that is:
1 T S = ------------------F SW ⁄ 2
• Integral voltage BW, f3 = -1000 * 2 * π
• Proportional voltage BW, f2 = -2000 * 2 * π
• Proportional current loop BW, f1 = -4000 * 2 * π
The characteristic equation is solved using the above
three bandwidths.
• RA = 0.1495
• KP = 57.5037
• KI = 2.0646e + 005
DS01369A-page 33
AN1369
FIGURE 26:
CONTROL LOOP COMPENSATOR DESIGN BLOCK DIAGRAM
Inner Current Loop Compensator
Outer Voltage Loop Compensator
IL * DCR
+
VERROR
+
IREF (IL*)
IERROR
+
Compensator
VO*
VO
Scaling
The gains calculated previously are based on real units
(volts, amps, and so on). The dsPIC DSC consists of a
fixed point processor and the values in the processor
comprise linear relationship with the actual physical
quantities they represent.
The gains calculated are in real units, and cannot be
directly applied to these scaled values (representation
of physical quantities). Therefore, for consistency
these gains must be scaled.
The scaling feedback section and the prescalar section
provide general concepts of scaling.
The basic idea behind scaling is the quantities that are
to be added or subtracted should have the same scale.
Scaling does not affect the structure of the control
system block diagram. Scaling only affects the software
representation of various quantities used in the
software.
Scaling Feedback
To properly scale the PID gains, it is imperative to
understand the feedback gain calculation. The
feedback can be represented in various formats.
Fractional format (Q15) is a very convenient
representation.
Fractional format allows easy migration of code from
one design to another with different ratings where most
of the changes that exist only in the coefficients and are
defined in the header file.
To use the available 16 bits in the processor, the Q15
format is most convenient as it allows signed
operations and full utilization of the available
bits (maximum resolution). Other formats can also be
used, but resolution is lost in the process. Q15 allows
effective use of the fractional multiply MAC and MPY
operation of the dsPIC DSC.
The feedback signal (typically voltage or current) is
usually from a 10-bit ADC. Based on the potential
divider or amplifier in the feedback circuitry, actual
voltage and current is scaled.
DS01369A-page 34
Compensator
VX
VL
Phase/Duty
+
IL
+
VO
Typically, the feedback 10-bit value (0 -1023) is brought
to the ±32767 range by multiplying with 32. This format
is also known as Q15 format: Q15(m) where -1 < m < 1
and is defined as (int) (m * 32767).
These formulae will have some error as 215 = 32768 is
required, but due to finite resolution of 15 bits, only
±32767 is used. From a control perspective, for most
systems these constraints hardly introduce any
significant error. In this format, +32767 corresponds
to +3.3V and 0 corresponds to 0V.
Prescalar
As most physical quantities are represented as the Q15
format for easy multiplication with gains, the gains must
also be represented in fractional format. If the value of
gain (G * VNBASE/INBASE) is between -1 and +1, it can
be easily represented as fractional format.
Multiplication can then be performed using fractional
multiply functions such as MAC or using builtin_mul
functions
and
shifting
appropriately.
For
example, z = (__builtin_mulss(x,y) >> 15)
results in z = Q15(fx,fy), where all x, y, and z are in Q15
format (fx and fy are the fractions that are represented
by x and y).
In many cases, the gain terms are greater than unity.
Because 16-bit fixed point is a limitation, a prescalar
may be used to bring the gain term within the ± range.
In this application, the voltage loop proportional gain KP
value is higher than one. Therefore, it is normalized
using the defined current, voltage base values with the
prescalar 32. For simplifying the calculations, the
voltage integral gain (KI) is also scaled with 32, which
means if a prescalar is used for the ‘P’ term in a control
block, it must also be used for the ‘I’ and ‘D’ term in the
control block since all the terms are added together.
To prevent number overflows, the PID output and ‘I’
output must be saturated to ±32767.
The saturation limits for the PID output must be set at
1/32 of the original ±32767 to account for the prescalar.
Therefore, saturation limits are set at ±1023. Finally,
after saturation, the output must be postscaled by five
to bring it to proper scale again.
© 2011 Microchip Technology Inc.
AN1369
Gain Scaling
LOAD SHARING
The voltage compensator input is in voltage
dimensions and the output is in current dimensions, the
voltage loop coefficients dimensions will be in
mho (Siemens).
In the traditional analog controller, regulation of the
converter is achieved by a simple PWM controller, and
load sharing of the converter is achieved by an
additional load sharing controller/equivalent amplifier
circuit. Recently, high end systems are calling for
logging of converter parameters, which requires a
microcontroller to communicate to the external world.
Therefore, each converter needs a PWM controller, a
load sharing controller, and a microcontroller to meet
the desired specifications.
The new value voltage loop proportional gain, KP after
normalizing and scaling, will be (KP * VNBASE)/(INBASE
* prescalar), which is 1.04.
The new value voltage loop integral gain, KI after
normalizing and scaling, will be KI * TS * VNBASE/
(INBASE * prescalar) = 0.0501.
The current compensator input is in current dimensions
and the output is in voltage dimensions, the current
loop coefficients dimensions will be in ohms.
The new value current loop Integral gain, RA after
normalizing, is [(RA/VINS) * INBASE] = 0.1495.
A few more contributors for the Phase/Duty control, are
the voltage decouple and DCR compensation terms.
These are discussed below.
Because at steady state (VL = 0), the average output of
switching action will be equal to VO. A contribution of
VO can be applied towards VX (the desired voltage at
primary of the transformer).
VO information is available in the software, so the
voltage decouple term can be easily calculated. This
will improve the dynamic performance and make the
design of control system easier. PI output performs
only small changes to correct for load and line
variations and most of the variation in PHASE/DUTY is
contributed by VO.
The voltage decouple term after scaling will be
VNBASE/VINS.
The other parameters that need to be addressed are
the resistance drops in the traces and magnetic
winding resistance drop, which may cause the current
loop to function less than ideal. The dimension of gain
of the current loop is in ohms. The physical resistance
may interfere with the control action. If this resistance
is known and measured during the design stage, this
resistance drop in the software can be compensated.
The DC resistance compensation term after scaling will
be (DCR/VINS) * INBASE.
The input quantity should be in fractional format (this
must be ensured in code). Then, the output current
quantity will automatically be in the correct fractional
quantity. This essentially solves the objective of scaling.
The same logic applies to any control block.
In the recent past, cost of the DSCs has reduced
drastically and are highly attractive for use by power
supply designers in their applications. Digital
controllers are immune to component variations and
have the ability to execute sophisticated nonlinear
control algorithms, which are not common or unknown
in analog controlled power systems.
Apart from closing the control loop digitally, the DSC
can perform fault management and communicate with
the external applications, which is becoming more and
more significant in server applications. Digitally
controlled power systems also offer advantages where
very high precision, flexibility and intelligence are
required.
For the overcurrent protection or short circuit protection
of the converters, load current or load equivalent
current will be measured and the same will be used for
the load sharing between the converters. Therefore, an
additional circuitry/additional controller is not required
in the case of a digitally controlled power supply
compared to its analog counterpart for load sharing.
This reduces overall cost as the component count is
lower and easier to implement by adding a few lines of
code to the stand-alone converter design.
Digital Load Sharing Implementation
Basic operation of the analog and digital load sharing
concept is the same; however, implementation is
completely different. In the digital implementation, the
ADC will sample the continuous signals of output
voltage and output current. The sampling frequency of
the output voltage and output current signal is user
configurable.
The
PID
compensator
design
calculations are performed in the Interrupt Service
Routine (ISR) and are updated based on the control
loop frequency.
By considering the input and output units and scale of
each block to be implemented in software, the proper
scaled values can be determined.
© 2011 Microchip Technology Inc.
DS01369A-page 35
AN1369
In the dual load sharing implementation, for additional
current, error information is added and this combined
data will be given to the PWM module to generate
appropriate phase/duty cycle. The PID compensator
design will be same as the standalone individual
converter. The load sharing compensator depends on
the expected dynamic performance and this depends
on the bandwidth of the current feedback. The current
loop compensator forces the steady state error, (δIL)
between individual converter currents IL1, IL2 and
average current (IAVE) to zero.
load sharing will be done with the single controller and
this results in fewer components, less complexity and
increased reliability. Poor noise immunity is a
disadvantage of this design.
The load sharing loop proportional gain, IKP, will
be 2πfL = 0.0021
The load sharing loop integral gain, IKI, will be 2πf5
IKI = 0.3356, where f5 (25 Hz) is the zero of the PI.
The new voltage loop proportional gain value, IKP after
normalizing and scaling is:
Typically, temperature is a criteria for stress on the
components and the junction temperature bandwidth is
around 5 ms (about 30 Hz). Therefore, it is sufficient to
use ~500 Hz bandwidth current data and the current
share loop can have a bandwidth of ~100 Hz. Here, the
DSC allows output voltage regulation by designing the
voltage/current loop compensator and load current
sharing by load current loop compensator design.
Effectively, both the output voltage regulation and the
FIGURE 27:
IKP * INBASE/VNBASE * prescaler2 * 1.25 = 0.0734
The new voltage loop proportional gain value, IKI after
normalizing and scaling is:
IKI * INBASE/VNBASE * prescaler2 * TSLOADSHARE
= 0.0092
In this application, the load sharing
time (TS LOADSHARE) is selected as 1 kHz.
sampling
SINGLE WIRE LOAD SHARE COMPENSATOR DESIGN BLOCK DIAGRAM
Outer Voltage Loop Compensator
(IL * DCR)
Inner Current Loop Compensator
VERROR
+
VO*
+
IREF(IL*)
+
IERROR
Compensator
VX
Phase/Duty
+
-
VO
+
VL
Compensator
+
IL1
VO
Load Share Loop Compensator
Load Share
IL1
Converter 1
δIL
Compensator
IAVEBLOCK
(IL1 + IL2)/2
Load Share Loop Compensator
Converter 2
δIL
Compensator
IL2
Load Share
Outer Voltage Loop Compensator
Inner Current Loop Compensator
+
I REF(I L*)
V ERROR
+
Compensator
VO *
(IL * DCR)
IL2
-
+
-
+
IERROR
Compensator
VL
Vx
+
Phase/Duty
+
VO
VO
DS01369A-page 36
© 2011 Microchip Technology Inc.
AN1369
MATLAB MODELING
The disturbance rejection plot is defined as: I(S)/VO(S).
The .m file is used to generate the coefficients that are
used in the MATLAB model (.mdl). This file also
generates the scaled values to be used in the software.
The generated values are in fractional format. In
software, the coefficients must be represented as
Q15(x), where ‘x’ is a fractional value.
For more detailed calculations, refer to the MATLAB
(.m) file in the FB_MATLAB file. For the MATLAB
Simulink block diagram, refer to the MATLAB (.mdl)
file.
The transfer function IO(S)/VO(S) (with VO*(S) = 0) is
called as dynamic stiffness or disturbance rejection.
This plot explains us for a unit amplitude distortion in
VO, the amount of load needed as a function of
frequency. The system needs to be as robust as
possible so that the output does not change under load.
The higher this absolute figure of merit, the
stiffer (better) the power supply output will be. The
minimum is 35 db in this application, which will
correlate to 56A (20logI = 35 dB) at approximately 1300
Hz of load producing 1.0V ripple on the output voltage.
The following Bode plots (Figure 29 through Figure 31)
are generated from the MATLAB (.m) file. Each plot is
used to describe the behavior of the system.
FIGURE 28:
MATLAB® DIGITAL IMPLEMENTATION FOR THE FULL-BRIDGE CONVERTER
(FROM MATLAB FILE)
Quantizer2
Quantizer1
VO
IL
12
VO *
Phifactor
VO*
VIN
Control System
Zero-Order
Hold2
Zero-Order
Hold1
Phifactor
VIN_PHIFACTOR
LC Voltage 1
IL1
VIN
IL1
VO1
VO2
ZVT Modulation
L1
13.6
iLoad
C
VIN
Scope1
Pulse Generator
© 2011 Microchip Technology Inc.
DS01369A-page 37
AN1369
FIGURE 29:
DS01369A-page 38
DISTURBANCE REJECTION PLOT
© 2011 Microchip Technology Inc.
AN1369
The loop gain voltage plot illustrated in Figure 30 is
used to calculate the phase and gain margin. In the
plot, the phase margin (difference between 180º and
the phase angle where the gain curve crosses 0 db) is
50º. To prevent the system from being conditionally
unstable, it is imperative that the gain plot drops below
0 db when the phase reaches 180º.
FIGURE 30:
The blue curve is for the analog implementation and
the green curve is for the digital implementation.
It is generally recommended to have a phase margin of
at least 40º to allow for parameter variations. The gain
margin is the difference between gain curve at 0 db and
where the phase curve hits 180º. The gain margin
(where the green line on the phase plot reaches 180º)
is -20 db.
LOOP GAIN PLOT
© 2011 Microchip Technology Inc.
DS01369A-page 39
AN1369
Figure 31 illustrates the closed loop Bode plot. The
point where the gain crosses -3 db or -45º in phase is
usually denoted as the bandwidth. In this system, the
bandwidth
of
the
voltage
loop
is
approximately 2700 Hz (17000 rad/s), which is closely
matched by the Bode plot.
FIGURE 31:
DS01369A-page 40
CLOSED LOOP PLOT
© 2011 Microchip Technology Inc.
AN1369
SOFTWARE IMPLEMENTATION
The Quarter Brick DC/DC Converter is controlled using
the dsPIC33FJ16GS502 device. This device controls
the power flow in the converter, fault protection, soft
start, remote ON/OFF functionality, external
communication, adaptive control for the synchronous
MOSFETs and single wire load sharing.
Note:
For more information on this device, refer
to the “dsPIC33FJ06GS101/X02 and
dsPIC33FJ16GSX02/X04 Data Sheet”
(DS70318).
For information on the peripherals, refer to
Section 43. “High-Speed PWM”
(DS70323), Section 44. “High-Speed
10-Bit Analog-to-Digital Converter
(ADC)” (DS70321), and Section 45.
“High-Speed Analog Comparator”
(DS70296) in the “dsPIC33F/PIC24H
Family Reference Manual”.
These documents are available from the
MIcrochip website (www.microchip.com).
Init_FB.c
Functions present in this file are:
init_FBDrive ()
Configure the primary MOSFET’s PWM module.
init_SYNCRECTDrive ()
Configure the synchronous MOSFET’s PWM
module.
init_ADC()
Configure the ADC module.
initRemoteON_OFF()
Configure the System state for remote ON/OFF
functionality.
init_Timer1()
Configure Timer1.
Variables_FB.c
Description of Software Functional
Blocks
Declarations and Initialization of all the global
variables.
The source files and header files describe the functions
used in the software.
Compensator_FB.c
Source Files
DigitalCompensator(void)
Main_FB.c
Function to execute the voltage PI compensator
and current P compensator.
LoadshareCompensator(void)
Functions present in this file are:
main()
Configures the operating frequency of the
device.
Function to execute
compensator.
the
load
share
PI
delay.s
Configures the auxiliary clock module.
Calls functions for configuring GPIO, ADC and
PWM modules.
_Delay to get ms delay.
_Delay_Us to get µs delay.
Checks for fault status.
ADCP1Interrupt()
Read values of currents and voltages.
Check for any fault condition.
If fault does not exist, execute the control loop.
If fault exists, disable PWM outputs.
INT1Interrupt()
Remote ON/OFF functionality.
T1Interrupt()
Averaging the PID output.
Over current limit selection.
Over temperature fault.
© 2011 Microchip Technology Inc.
DS01369A-page 41
AN1369
Header Files
dsp.h
Define_FB.h
Standard library file for all DSP related operations.
This file has all the global function prototype definitions
and global parameter definitions.
delay.h
This is the file where all the modifications must be done
based on the requirements of hardware components,
power level, control loop bandwidth and other
parameters. They are given below for reference.
Presentable delay definition in ms and µs.
Variables_FB.h
Supporting file for Variables_CMC.c and contains all
the external global definitions.
FIGURE 32:
SOFTWARE FLOW CONTROL CMC WITH LOAD SHARING
Initialization
Wait for A/D
Interrupt
ISHARE
Reset
IO
Soft Start
Load Sharing
PI Controller
Voltage PI
Controller
PWM
Duty
Current
P
Controller
IREF
VDC 12V
IO
DS01369A-page 42
© 2011 Microchip Technology Inc.
AN1369
Digital Nonlinear Implementations
DSCs allow implementing customized configurations to
gain performance improvements of the SMPS.
Adaptive Control to Improve the
Efficiency
Achieving ultra-high efficiency specifications in power
supply designs require unique configuration of the
PWM. This can be achieved by using external
hardware or with software in digital controllers. In the
Full-Bridge converter, the software is designed to get
the efficiency benefit at higher specified input voltages.
Most of the DC/DC converters (part of the AC/DC
converter/Brick DC/DC converter) are designed using
the isolation transformer for user safety and is also
imposed by regulatory bodies. These power supplies
are designed in the primary with push-pull, half-bridge,
full-bridge and PSFB, and in the secondary with
synchronous MOSFET configurations to gain high
efficiency.
To avoid cross conduction, there will be a defined dead
band and during this period neither of the synchronous
MOSFETs conduct, therefore, the current will take the
path of the MOSFET body diode. These MOSFET body
diodes have high forward drop compared to the
RDS(ON) of the MOSFET, that is, (VF * I) >> Irms2 *
RDS(ON). Therefore, the losses are higher and the
efficiency is less.
© 2011 Microchip Technology Inc.
These problems can be overcome by unique
configuration of the PWM gate drive of the
synchronous MOSFETs.
Losses occurring during zero state of the primary side
of the transformer can be avoided by overlapping the
PWM gate drive of the synchronous MOSFETs. This
method solves the problems that cause losses during
the zero states of the transformer.
• In the case of the center tapped transformer
secondary configuration, instead of one
synchronous MOSFET and one coil of the center
tapped transformer, two synchronous MOSFETs
and two transformer coils conduct simultaneously.
Therefore, the secondary current will have only
half the effective resistance, and the losses are
reduced by half compared to when only one
synchronous MOSFET is ON.
• In the conventional switching methodology, intentional dead time is introduced between the two
synchronous MOSFETs and typically this may be
10% of switching period based on the designs.
During this dead time, the high secondary current
flows through the high forward drop body MOSFET and cause losses. By configuring the overlap
of the PWM gate drive of the synchronous MOSFET, the high secondary currents flow through the
channel of the MOSFET. In this instance there will
be only RDS(ON) losses that are very less compared to the losses incurred by the MOSFET body
diodes in the dead time.
DS01369A-page 43
AN1369
FIGURE 33:
FULL-BRIDGE CONVERTER WITH CONVENTIONAL SYNCHRONOUS MOSFET
GATE DRIVES
Q1
Q3
Q6
TX
LO
TXVPRI
Q2
Q4
CO
Q5
Q1
Q2
Q3
Q4
VPRI
Q5
Q6
Zero States
Note:
In Zero States Q5, Q6 MOSFETs freewheeling body diodes will be conducting. The forward drop
of body diode will be much higher than the MOSFET RDS(ON).
DS01369A-page 44
© 2011 Microchip Technology Inc.
AN1369
FIGURE 34:
FULL-BRIDGE CONVERTER WITH OVERLAP OF SYNCHRONOUS MOSFET GATE
DRIVES
Q1
Q3
Q6
TX
L
LO
TXVPRI
Q2
Q4
CO
Q5
Q1
Q2
Q3
Q4
TXVPRI
Q5
Q6
Zero States
Intentional dead time between primary and secondary
© 2011 Microchip Technology Inc.
DS01369A-page 45
AN1369
Overcurrent Protection Implementation
PRINTED CIRCUIT BOARD (PCB)
A current transformer is located in the primary side of
the converter and the output of the current transformer
also varies with the line conditions. To have the specific
current limit across the line voltages, the compensator
final output is averaged over a period of 10 ms. The
compensator final output provides the line voltage
variation data. This data is used as a modifier to
change the current limit setting.
In the Quarter Brick DC/DC Converter design, an 18-layer
PCB is used to achieve the standard quarter brick
dimensions. The PCB tracks routing is a challenging task
in the 18 layer Quarter Brick design. The PCB layers are
described in Table 8.
TABLE 8:
PCB
Layer
Stacking of PCB Layers
PCB Layer Description
1
Top layer traces, magnetic winding and
component assembly.
2
Analog GND, magnetics and primary,
and secondary side Cu pours.
3
4
5
6
Analog GND, +3.3V, magnetics and
primary, and secondary side Cu pours.
7
Analog GND, gate drive traces,
magnetics and primary, and secondary
side Cu pours.
8
Analog GND, magnetics and primary,
and secondary side Cu pours.
9
10
11
Analog GND, DIG GND, magnetics and
primary, and secondary side Cu pours.
12
Analog GND, DIG GND, gate drive
traces, magnetics and primary, and
secondary side Cu pours.
13
Analog GND, DIG GND, magnetics and
primary, and secondary side Cu pours.
14
Analog GND, DIG GND, gate drive
traces, magnetics and primary, and
secondary side Cu pours.
15
Analog GND, DIG GND, magnetics and
primary, and secondary side Cu pours.
16
DS01369A-page 46
17
Digital GND and signal traces, magnetics
and primary, and secondary side Cu
pours.
18
Bottom layer traces, magnetic winding
and component assembly.
© 2011 Microchip Technology Inc.
AN1369
LABORATORY TEST RESULTS AND
CIRCUIT SCHEMATICS
The Laboratory test results provide an overview of the
Quarter Brick Full-Bridge electrical specifications as
well as the scope plots from initial test results. The test
results are illustrated in Figure 35 to Figure 66.
FIGURE 35:
OUTPUT VOLTAGE RIPPLE: 8.5A AT 75V
FIGURE 36:
OUTPUT VOLTAGE RIPPLE: 17A AT 75V
© 2011 Microchip Technology Inc.
DS01369A-page 47
AN1369
FIGURE 37:
OUTPUT VOLTAGE RIPPLE: 0A AT 75V
FIGURE 38:
OUTPUT VOLTAGE RIPPLE: 8.5A AT 48V
DS01369A-page 48
© 2011 Microchip Technology Inc.
AN1369
FIGURE 39:
OUTPUT VOLTAGE RIPPLE: 17A AT 48V
FIGURE 40:
OUTPUT VOLTAGE RIPPLE: 0A AT 75V
© 2011 Microchip Technology Inc.
DS01369A-page 49
AN1369
FIGURE 41:
OUTPUT VOLTAGE RIPPLE: 8.5A AT 36V
FIGURE 42:
OUTPUT VOLTAGE RIPPLE: 17A AT 36V
DS01369A-page 50
© 2011 Microchip Technology Inc.
AN1369
FIGURE 43:
OUTPUT VOLTAGE TRANSIENT: 4.25A, 12.75A AT 48V
FIGURE 44:
OUTPUT VOLTAGE TRANSIENT: 4.25A, 12.75A AT 75V
© 2011 Microchip Technology Inc.
DS01369A-page 51
AN1369
FIGURE 45:
OUTPUT VOLTAGE TRANSIENT: 4.25A, 12.75A AT 36V
FIGURE 46:
START-UP TIME: 8.5A AT 53V
DS01369A-page 52
© 2011 Microchip Technology Inc.
AN1369
FIGURE 47:
OUTPUT VOLTAGE RAMP UP TIME: 17A AT 53V
FIGURE 48:
OUTPUT VOLTAGE RIPPLE: 8.5A AT 53V
© 2011 Microchip Technology Inc.
DS01369A-page 53
AN1369
FIGURE 49:
OUTPUT VOLTAGE OVERSHOOT: 8.5A AT 53V
FIGURE 50:
REMOTE ON/OFF, OUTPUT VOLTAGE RISE TIME: 17A AT 53V
DS01369A-page 54
© 2011 Microchip Technology Inc.
AN1369
FIGURE 51:
REMOTE ON/OFF, OUTPUT VOLTAGE FALL TIME: 17A AT 53V
FIGURE 52:
REMOTE ON/OFF, OUTPUT VOLTAGE FALL TIME: 0A AT 53V
© 2011 Microchip Technology Inc.
DS01369A-page 55
AN1369
FIGURE 53:
PRIMARY TX AND SYNCHRONOUS FET GATE WAVEFORMS: 48V/8.5A
FIGURE 54:
PRIMARY TX AND SYNCHRONOUS FET GATE WAVEFORMS: 48V/17A
DS01369A-page 56
© 2011 Microchip Technology Inc.
AN1369
FIGURE 55:
PRIMARY TX AND SYNCHRONOUS FET GATE WAVEFORMS: 48V/0A
FIGURE 56:
PRIMARY TX AND SYNCHRONOUS FET GATE WAVEFORMS: 76V/8.5A
© 2011 Microchip Technology Inc.
DS01369A-page 57
AN1369
FIGURE 57:
PRIMARY TX AND SYNCHRONOUS FET GATE WAVEFORMS: 76V/17A
FIGURE 58:
PRIMARY TX AND SYNCHRONOUS FET GATE WAVEFORMS: 76V/0A
DS01369A-page 58
© 2011 Microchip Technology Inc.
AN1369
FIGURE 59:
PRIMARY TX AND SYNCHRONOUS FET GATE WAVEFORMS: 36V/8.5A
FIGURE 60:
PRIMARY TX AND SYNCHRONOUS FET GATE WAVEFORMS: 36V/17A
© 2011 Microchip Technology Inc.
DS01369A-page 59
AN1369
FIGURE 61:
PRIMARY TX AND SYNCHRONOUS FET GATE WAVEFORMS: 36V/0A
FIGURE 62:
SYNCHRONOUS MOSFET GATE AND DRAIN WAVEFORM: 48V/17A
DS01369A-page 60
© 2011 Microchip Technology Inc.
AN1369
FIGURE 63:
SYNCHRONOUS MOSFET GATE AND DRAIN WAVEFORM: 76V/17A
© 2011 Microchip Technology Inc.
DS01369A-page 61
AN1369
FIGURE 64:
LOOP GAIN PLOT: 36V AND 12V/9A
Phase Margin: 61.430
Gain Margin:-7.53 dB
Crossover frequency: 2.17 kHz
DS01369A-page 62
© 2011 Microchip Technology Inc.
AN1369
FIGURE 65:
LOOP GAIN PLOT: 48V AND 12V/9A
Phase Margin: 59.800
Gain Margin:-6.508 dB
Crossover frequency: 2.67 kHz
© 2011 Microchip Technology Inc.
DS01369A-page 63
AN1369
FIGURE 66:
LOOP GAIN PLOT: 76V AND 12V/9A
Phase Margin: 53.080
Gain Margin:-3.60 dB
Crossover frequency: 3.57 kHz
DS01369A-page 64
© 2011 Microchip Technology Inc.
AN1369
CONCLUSION
REFERENCES
This application note presents the design of a FullBridge Quarter Brick DC/DC Converter through the
average current mode control using a Microchip dsPIC
“GS” series Digital Signal Controller (DSC). Various
nonlinear techniques implemented in this design
explore the benefits of DSCs in Switched Mode Power
Converter applications.
The following resources are available from Microchip
Technology Inc., and describe the use of dsPIC DSC
devices for power conversion applications:
Microchip has various resources to assist you in
developing this integrated application. For more details
on the Full-Bridge Quarter Brick DC/DC Converter
Reference Design using a dsPIC DSC, please contact
your local Microchip sales office.
© 2011 Microchip Technology Inc.
• “dsPIC33FJ06GS101/X02 and
dsPIC33FJ16GSX02/X04 Data Sheet” (DS70318)
• Dedicated Switch Mode Power Supply (SMPS)
Web site: http://www.microchip.com/SMPS
In addition, the following resource was used in the
development of this application note:
“Design and Implementation of a Digital PWM
Controller for a High-Frequency Switching DC-DC
Power Converter”. Aleksandar Prodic, Dragan
Maksimovic and Robert W. Erickson
DS01369A-page 65
AN1369
APPENDIX A:
SOURCE CODE
Software License Agreement
The software supplied herewith by Microchip Technology Incorporated (the “Company”) is intended and supplied to you, the
Company’s customer, for use solely and exclusively with products manufactured by the Company.
The software is owned by the Company and/or its supplier, and is protected under applicable copyright laws. All rights are reserved.
Any use in violation of the foregoing restrictions may subject the user to criminal sanctions under applicable laws, as well as to civil
liability for the breach of the terms and conditions of this license.
THIS SOFTWARE IS PROVIDED IN AN “AS IS” CONDITION. NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR
STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. THE COMPANY SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE
FOR SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
All of the software covered in this application note is
available as a single WinZip archive file. This archive
can be downloaded from the Microchip corporate Web
site at:
www.microchip.com
DS01369A-page 66
© 2011 Microchip Technology Inc.
© 2011 Microchip Technology Inc.
APPENDIX B:
FIGURE B-1:
FULL-BRIDGE QUARTER BRICK DC/DC CONVERTER BOARD LAYOUT AND SCHEMATICS
Full-Bridge Quarter Brick DC/DC Converter Board Layout (Bottom View)
Output Inductor (L2)
Main Transformer (TX1)
DT1
VIN +ve
VO +ve
Q2
Q5
Remote ON/OFF
U5
VO -ve
VIN -ve
3.3V Regulator (U8)
dsPIC33FJ16GS502 (U1)
Q6
Note:
Auxiliary Transformer (TX3)
U7
Auxiliary Controller (U9)
This view lists a few key components. Refer to the Bottom Silk drawing in Figure B-2, which lists all board components.
AN1369
DS01369A-page 67
DT2
FB Quarter Brick DC/DC Converter Board Layout (Bottom Silk)
AN1369
DS01369A-page 68
FIGURE B-2:
C47
Q1
C10
C11
R1
R5
C7
Q5
Q6
D1
C9
R35
Q2
R41 R33
D25
R44
R46
C21 R80 C14
R81
C46
U5
C28
C19
R2
C31
U7
D18
R31
R54
R55
C48
C22
C32
C30
R73
C39
R58
C3
U8
C37
R40
C27
C24
C25
R59
R57
C41
D16
D15
C33
R47
C36
U9
C23
L3 R43
C26
R48
L4
U1
C40
© 2011 Microchip Technology Inc.
C29
R34
C20
C13
R61
R66
D2
R6 R62
C1
© 2011 Microchip Technology Inc.
FIGURE B-3:
FB Quarter Brick DC/DC Converter Board Layout (Top View)
Q3
TX1
Q14
Q13
L2
DT1
Q4
J4
TX2
U4
DT2
U6
Note:
U3
U2
This view lists a few key components. Refer to the Top Silk drawing in Figure B-4, which lists all board components.
AN1369
DS01369A-page 69
J1
TX3
FB Quarter Brick DC/DC Converter Board Layout (Top Silk)
AN1369
DS01369A-page 70
FIGURE B-4:
C4
Q3
Q4
C2
M
C5
C6
R7
R3
C8
Q13
Q14
R11
J4
D3
D28
R10
D27
R4
R13
D8
TX2
R12
R26
C42
C44
C18
D4
R52 R50
R49
R39
D7
R51
R8
U4
R22
D26
U2
U3
R28
D17
C17
R21
C34
R16
D14
C15
R36
C43
R20
R17
R18
R56
C45
C16
© 2011 Microchip Technology Inc.
R23
C33
R19
R69
U6
R64
R65
C12
R15
R14
R66
C38
R63
J1
R68
© 2011 Microchip Technology Inc.
FIGURE B-5:
FB Quarter Brick DC/DC Converter Board Dimensions
VO+
VIN+
ON/OFF
VIN-
VO-
AN1369
DS01369A-page 71
FB Quarter Brick DC/DC Converter Schematic (Sheet 1 of 4)
AN1369
DS01369A-page 72
FIGURE B-6:
+12V
C16
R23 10
2.2uF
GATE1
ANA_GND
U2
1
2
3
4
PWM1H
R26
10K
Vdd
IN
N/C
GND
Vdd
OUT
OUT
GND
C42 .1uF
8
7
6
5
DT1
TC4422A-SOIC
1
5
4
6
7
+12V
S1
GATE4
R39
ANA_GND
10
8
ANA_GND
U4
1
2
3
4
PWM3H
SECY side Components. Require 2250Vdc Isolation.
R34
10K
PWM3L
NC
IN/A
GND
IN/B
R36
8
7
6
5
NC1
OUT/A
VDD
OUT/B
GATE5
GATE6
MCP1404-SO8
10K
C18
2.2uF
+12V
ANA_GND
2.2uF
C17
R28 10
ANA_GND
GATE3
U3
1
2
3
4
PWM1L
R31
Vdd
IN
N/C
GND
Vdd
OUT
OUT
GND
8
7
6
5
C44
TC4422A-SOIC
10K
© 2011 Microchip Technology Inc.
ANA_GND
DT2
.1uF
ANA_GND
1
5
4
6
7
S3
GATE2
+3.3V_ANA
U5
8
TEMP
1
2
3
NC
VSS
VOUT
NC1
5
VDD
4
MCP9700-SC70
C19
2.2uF
ANA_GND
SECY side Components. Require 2250Vdc Isolation.
ANA_GND
FB Quarter Brick DC/DC Converter Schematic (Sheet 2 of 4)
Pin #1
5
C50
.1uF
R7
R3
S1
10K
10.0
D30
S3
GATE3
2.2uF
L2a
C52
10K
8
TX2
2uF
C7
C6
C5
22uF
22uF
22uF
L2b
1
2
3
10.0
10K
BAT54
D31
C10
22uF
C11
22uF
Pin #5
VOR73
0.0
C45
47uF
DIG_GND
ANA_GND
BAT54
R13
GATE4
INPUT VOLTAGE-
22uF
1
R8
3
R4
C9
C8
22uF
VAux
eSMP
4
D32
Pin #6
VO+
.1uF
4
R6
7
5
5
.1uF
10K
HAT2173H
C4
3.5uH
D18
Q4
HAT2173H
Q2
HAT2173H
R11
4
9
11
R2
10.0
5
CT
5
BAT54
C2
C51
GATE6
Q13
1
2
3
2.2uF
R10 4.7
4
3
2
1
D29
BAT54
GATE1
C1
HAT2173H
7
4
3
2
1
R5
10K
R1
10.0
TX1
1
.1uF
4
1
2
3
C49
Q3
HAT2173H
5
Q1
HAT2173H
5
Q5
INPUT VOLTAGE+
1
2
3
© 2011 Microchip Technology Inc.
FIGURE B-7:
3
2
1
3
2
1
GATE2
Q6
Q14
10k
4.7
R12
4
GATE5
4
5
5
Pin #4
HAT2173H
470pF
C46
HAT2173H
R80
Pin #2
150K
CT
Remote ON/OFF
D7
BAS40
3
3
R81
D8
BAS40
+3.3V_ANA
2.2uF
C43
.1uF
47
-
620
R66
ANA_GND
R15
5
6
+3.3V_ANA
R16
620
100
R68
2K
C38
470pF
ANA_GND
ANA_GND
100
R14
11.3
470pF
2K
620
47
+
2
-
C14
.1uF
R20
1
TX CURRENT
R21
4.7K
TX OVER CURRENT
ANA_GND
R17
U6A
MCP6022-TSSOP
3
620
ANA_GND
ANA_GND
R19
R22
4.7K
ANA_GND
2K
ANA_GND
DS01369A-page 73
ANA_GND
ANA_GND
C15
470pF
AN1369
R65
R18
2K
C12
ANA_GND
R64
DIG_GND
ANA_GND
21
8
U6B
MCP6022-TSSOP
+
7
4
R69
LOAD SHARE
R63
2
4
8
1
4.99K
VSecy
C13
FB Quarter Brick DC/DC Converter Schematic (Sheet 3 of 4)
+3.3V_DIG
R33 10
R48 4.7K
VO+
MCLR
1
REMOTE+
2
R44
5.23K
C22
2.2uF
OUTPUT FEEDBACK
R46
1.5K
C48
C21
2200pF
3
C26
.1uF
+3.3V_ANA
4
PGD2
ANA_GND
DIG_GND
2200pF
J1
MCLR
Vdd
Vss
PGD
5
PGC2
PGC
6
N/C
VO-
PWM1L
PWM1H
OUTPUT OVER VOLTAGE
R43
1K
TX OVER CURRENT
EXTSYNCI1
C20
470pF
AN2
AN3
CMP2C
RP10
Vss
CMP4a
RP2
DSPIC33FJ16GS502-QFN28
DIG_GND
PWM2L
PWM2H
PWM3L
PWM3H
Vcap
Vss
SDA1
21
20
19
18
17
16
15
PWM3L
PWM3H
GND
LOAD SHARE
VSecy
OUTPUT OVER VOLTAGE
TEMP
R41
7.5K
C23
2.2uF
29
U1
1
2
3
4
5
6
7
AN1
AN0
MCLR
AVdd
AVss
PWM1L
PWM1H
OUTPUT FEEDBACK
VO+
PGD2
PGC2
DIG_GND
ICSP_6_HDR
28
27
26
25
24
23
22
MCLR
TX CURRENT
10
PGD2
PGC2
Vdd
RB8
RB15
RB5
SCL1
R35
8
9
10
11
12
13
14
REMOTE-
DIG_GND
COM3
COM4
REMOTE ON/OFF
COM2
COM1
+3.3V_DIG
+3.3V_DIG
C24
2.2uF
R49
DIG_GND
R50
4.99K
4.99K
COM3
J4.1
R51
220
COM1
14
15
COM2
EXTSYNCI1
12
13
DIG_GND
10
11
COM4
R52 220
LOAD SHARE
8
9
6
7
N/C
REMOTE ON/OFF-I/P
REMOTE+
4
1
U7
2801
REMOTE ON/OFF
3
2
© 2011 Microchip Technology Inc.
+3.3V_ANA
R62
1.6K
C25
470pF
R47
6.8K
DIG_GND
PRI side Components.
Require 2250Vdc Isolation.
DIG_GND
REMOTE-
AN1369
DS01369A-page 74
FIGURE B-8:
FB Quarter Brick DC/DC Converter Schematic (Sheet 4 of 4)
VAux
+12V
D15
INPUT VOLTAGE +
R56
1K
C33
2200pF
R53
L4
XPL2010
TX3
2
5
1
3
6
7
eSMP
C41
47uF
C30
47uF
ANA_GND
+3.3V_DIG
D14
1Meg
2
4
D17
MURA110
eSMP
1
R57
VIN
6
VEN
D16
47
R58
VDRAIN VSS
VCC
CT
UV
FB
OV
COMP
10
LP3961-LLP6
VOUT
VOUT-SEN
BYPASS
10000pF
1
U9
C34
10uF
XPL2010
C29
15uF
C39
15uF
DIG_GND
1
2
3
4
+3.3V_ANA
L3
1
3
5
C40
R60 1.43K
R59 4.7K
C28
15uF
ANA_GND
+3.3V_ANA
NCP1031-SO8
R55
34K
2
BAT54-XV
R54
45.3K
8
7
6
5
C32
10000pF
C3
15uF
2
C31
10000pF
U8
8
4 GND
7 GND1
© 2011 Microchip Technology Inc.
FIGURE B-9:
C36
C37
680pF
C35
680pF
R40 0.0
R61
C27
2.2uF
10K
10000pF
DIG_GND
ANA_GND
INPUT VOLTAGE -
AN1369
DS01369A-page 75
AN1369
TABLE B-1:
FB Quarter Brick DC/DC Converter Pin Out Details
Pin Number
Pin Designation
Function
1
VIN+
Input Voltage Plus
2
Remote
ON/OFF
Remote ON/OFF
3
VIN-
Input Voltage Minus
4
V0-
Output Voltage Minus
5
V0+
Output Voltage Plus
J4-6
Remote+
Remote Sense Plus
J4-7
Remote-
Remote Sense Minus
J4-8
Load Share
J4-9
NC
J4-10
COM 4
Serial Clock Input/Output
Serial Data Input/Output
J4-11
COM 3
J4-12
EXTSYNCI 1
J4-13
DIG_GND
Single Wire Load Share
Not Connected
External Synchronization Signal
Digital Ground
J4-14
COM 1
PORTB - 8
J4-15
COM 2
PORTB - 15
J1-1
MCLR
Master Clear
J1-2
+3.3V
J1-3
DIG_GND
J1-4
PGD2
Data I/O Pin for Programming/Debugging
J1-5
PGC2
Clock Input Pin for Programming/Debugging
DS01369A-page 76
Supply
Digital Ground
© 2011 Microchip Technology Inc.
BASE BOARD SCHEMATIC
P1
Black
5
4
1
N/C
VO-
5
C14
22 µF
2
TP7
Black
TP8
TP2
White
C13
22 µF
J2
GND
REMOTE-
COM4
COM3
COM2
C12
100 µF
1
20
11
VI-
14
COM1
3
TP3
C11
47 µF
3
ON/OFF
C9
2200 µF
2
9
10
+3.3V
MCLR
6
7
8
TP6
C8
2200 µF
REMOTE+
D1
3.3V
TP1
4
DC-DC
2
LOADSHARE
TP5
VO+
19
C7
13
4
PGC
Orange
C6
17
C5
Red
18
C4
EXTSYNCI1
C3
16
C2
1
3
J1
P2
2
2
C1
180 µF/100V
12
1
2.2 µF/100V
C2-C7
VI+
PGD
U1
1
GND
Red
TP4
15
FIGURE C-1:
BASE BOARD SCHEMATIC AND LAYOUT
5
© 2011 Microchip Technology Inc.
APPENDIX C:
White
White
TP9
White
Fan circuitry
U2
7
8
C17
0.1 µF
ON/OFF
3
FB
GND
R4
139K
5
1
L1
220 µH
D2
50SQ100
SGND
C15
68 µF
LX
6
R3
1M
BST
VIN
VD
4
2
MAX5035
C16
15 µF
J6
1
2
Fan Header
3
C18
0.1 µF
4
J3
2
S1
J7
1
1
3
1
3
4
5
2
2
4
6
J4
MCLR
J5
1
1
2
VDD
2
3
VSS
3
4
PGD
4
PGC
N.C.
RJ-11
5
6
PMBUS
AN1369
DS01369A-page 77
Auxiliary Fan Input
Input Power Selection for Fan
BASE BOARD LAYOUT (TOP VIEW)
AN1369
DS01369A-page 78
FIGURE C-2:
R1
C7
C8 C5
C4 C3 C2
R5
D1
C10
C12
C18
D3
U5
D5
C17
© 2011 Microchip Technology Inc.
R3 C19
R4
C14
BASE BOARD LAYOUT (BOTTOM VIEW)
© 2011 Microchip Technology Inc.
FIGURE C-3:
AN1369
DS01369A-page 79
AN1369
C.1
Efficiency Improvement Proposals
The following proposals can be implemented to
improve the efficiency of the converter.
1.
2.
3.
4.
5.
Improving the rise and fall times of the
MOSFETs.
Investigating the feasibility of using a single gate
drive transformer in the Full-Bridge reference
design.
Investigating the feasibility of using high-side
and low-side drivers.
Using 3+3 synchronous MOSFETs in the
secondary rectifications.
Investigating the feasibility of using fractional
turns in the main transformer.
In the present design, some of the layers were made
using 2 oz. copper. As an improvement, these layers
could be made using 4 oz. copper.
DS01369A-page 80
© 2011 Microchip Technology Inc.
AN1369
APPENDIX D:
FULL-BRIDGE
QUARTER BRICK DC/
DC REFERENCE
DESIGN
DEMONSTRATION
This appendix guides the user through the evaluation
process to test the Quarter Brick DC/DC Converter.
The Full-Bridge Quarter Brick DC/DC Converter
Reference Design is a 200W output isolated converter
with 36V-76V DC input and produces 12V DC output
voltage.
D.1
Tests Performed on the Quarter
Brick DC/DC Converter
• Input characteristics
- Input undervoltage/overvoltage
- No load power
- Input power when remote ON/OFF is active
• Output characteristics
- Line regulation
- Load regulation
- Output voltage ramp-up time
- Start-up time
- Remote ON/OFF start-up time
- Remote ON/OFF shutdown fall time
- Output overcurrent threshold
- Output voltage ripple and noise
- Load transient response
• Efficiency of the converter
D.2
Test Equipment Required
• DC source 30 VDC-100 VDC @ 8A (programmable
DC power supply, 62012P-600-8 from Chroma or
equivalent)
• DC electronic load (DC electronic load 6314/
63103 from Chroma or equivalent)
• Digital multimeters (six and one-half digit multimeter,
34401A from Agilent or equivalent)
• Oscilloscope (mixed-signal oscilloscope,
MSO7054A from Agilent or equivalent)
• Differential probe (high-voltage differential probe,
P5200 from Tektronix or equivalent)
D.3
Test Setup Description
The Quarter Brick DC/DC Converter is assembled on the
base board for evaluation purposes. The location of the
Quarter Brick DC/DC Converter and its associated
components used for testing are illustrated in Figure D-1.
© 2011 Microchip Technology Inc.
DS01369A-page 81
AN1369
FIGURE D-1:
QUARTER BRICK DC/DC CONVERTER CONNECTED TO THE BASE BOARD IN THE
REFERENCE DESIGN ENCLOSURE
Quarter Brick DC/DC Converter
FIGURE D-2:
FRONT VIEW OF THE QUARTER BRICK DC/DC CONVERTER REFERENCE DESIGN
Note: The check mark on the front of the enclosure identifies the reference design model.
FB = Full-Bridge Quarter Brick DC/DC Converter (to be discussed in a future application note)
PSFB = Phase-Shifted Full-Bridge DC/DC Converter
DS01369A-page 82
© 2011 Microchip Technology Inc.
AN1369
Use the following procedure to connect the DC load
and source.
1.
Connect the DC source +ve terminal and -ve
terminals to the + and – input terminals (INPUT
36-76V) of the connector, as illustrated in
Figure D-3.
FIGURE D-3:
LEFT SIDE VIEW OF THE
QUARTER BRICK DC/DC
CONVERTER REFERENCE
DESIGN
© 2011 Microchip Technology Inc.
2.
Connect the DC load +ve terminal and –ve
terminals
to
the
+
and
–
output
terminals (OUTPUT 12V) of the converter, as
illustrated in Figure D-4.
Note:
The PROGRAM/DEBUG socket is used to
program the converter with software.
FIGURE D-4:
RIGHT SIDE VIEW OF THE
QUARTER BRICK DC/DC
CONVERTER REFERENCE
DESIGN
DS01369A-page 83
AN1369
Use the following procedure to prepare the reference
design for testing.
1.
Connect the DMM +ve terminal and –ve
terminals to the +ve and –ve terminals of the
input current measurement resistor, as
illustrated
in
Figure D-5.
The
current
measurement resistor used to measure the
input current is 10 mE. For example, if the
measured voltage across the resistor is 60 mV,
the input current will be 6A.
FIGURE D-5:
2.
INPUT CURRENT MEASUREMENT
Connect the DMM +ve terminal and –ve
terminals to the +ve and –ve terminals of the
output current measurement resistor, as
illustrated
in
Figure D-6.
The
current
measurement resistor used to measure the
output current is 5 mE. For example, if the
measured voltage across the resistor is 85 mV,
then the output current will be 17A.
FIGURE D-6:
DS01369A-page 84
OUTPUT CURRENT MEASUREMENT
© 2011 Microchip Technology Inc.
AN1369
3.
Connect the DMM for input voltage measurement,
as illustrated in Figure D-7.
FIGURE D-7:
4.
INPUT VOLTAGE MEASUREMENT
Connect the DMM for output voltage
measurement, as illustrated in Figure D-8.
FIGURE D-8:
OUTPUT VOLTAGE MEASUREMENT
© 2011 Microchip Technology Inc.
DS01369A-page 85
AN1369
5.
Connect the oscilloscope probe for output
voltage (in DC coupling) and ripple and noise (In
AC coupling) measurement, as illustrated in
Figure D-9.
FIGURE D-9:
6.
OUTPUT VOLTAGE MEASUREMENT
Connect the oscilloscope probe for remote ON/
OFF testing, as illustrated in Figure D-10.
FIGURE D-10: CONNECTING THE OSCILLOSCOPE PROBE FOR REMOTE ON/OFF TESTING
Remote ON/OFF Pin
Note:
Differential probe must be used to monitor
the remote ON/OFF signal.
DS01369A-page 86
© 2011 Microchip Technology Inc.
AN1369
7.
Connect the oscilloscope probe for start-up
time, as illustrated in the Figure D-11.
FIGURE D-11: CONNECTING THE OSCILLOSCOPE PROBE FOR START-UP TIME
Note:
Differential probe must be used to monitor
the input voltage.
Instructions to connect two quarter brick
converters for parallel operation
1.
2.
3.
For N+1 system operations connect COMM2-3
(load share) of converter 1 to converter2
COMM2-3(load share).
Connect a common DC source to the
Converter1 and Converter2 input terminals as
illustrated in Figure D-3.
Connect a Common DC electronic load to the
Converter1 and Converter2 output terminal as
illustrated in Figure D-4.
© 2011 Microchip Technology Inc.
DS01369A-page 87
AN1369
D.4
Forced Air Cooling
a)
The Quarter Brick DC/DC Converter is designed to work
with forced air cooling, which is provided by the fans
illustrated in Figure D-2. Ensure that the fans are
circulating air into the enclosure after providing the DC
input supply at the + and – input terminals (INPUT
36-76V) of the connector, as illustrated in Figure D-3.
D.5
b)
Powering Up the Quarter Brick
DC/DC Converter
c)
Before powering up the converter, ensure that polarity
of the input source and DC load are connected as per
the guidelines described in the section “Test Setup
Description”.
Typically, the unit may enter into the
regulation range at around 35 VDC,
undervoltage lockout at approximately 33.5
VDC,
and
overvoltage
lockout
at
approximately 81 VDC.
Use the following procedure to power up the reference
design.
1.
2.
3.
Turn the DC source ON and measure the input
voltage with DMM, as illustrated in Figure D-7.
This voltage should be in the range of 36 VDC 76 VDC. Check to see that the fans are
circulating air into the enclosure.
Ensure that the connected DC load is in the
range of 0A-17A. The output load current measurement resistor provides a value in the range
of 0 mV-85 mV when measuring with DMM, as
illustrated in Figure D-6.
Ensure that the output voltage read by DMM
(see Figure D-8) is in the range of 11.88 VDC to
12.12 VDC.
D.6
Test Procedure
The following two sections provide detailed procedures
for each test.
D.6.1
1.
INPUT CHARACTERISTICS
Input undervoltage/overvoltage.
The Quarter Brick DC/DC Converter is rated to
operate with regulation between the input
voltage ranges 36 VDC-76 VDC. The converter
features input undervoltage and overvoltage
protection. This feature will not allow the
converter to start-up unless the input voltage
exceeds the turn-on voltage threshold and shuts
down the converter when the input voltage
exceeds the overvoltage threshold.
DS01369A-page 88
Set the DC load at 8.5A and increment the
input voltage from 33 VDC (read the input
voltage with DMM illustrated in Figure D-7)
to the voltage where output voltage is in the
regulation range of 11.88 VDC to 12.12 VDC.
Read the output voltage with DMM
illustrated in Figure D-8.
Start decrementing the input voltage and
observe at what input voltage the converter
shuts OFF. This input voltage point will be
the input undervoltage threshold.
Start incrementing the voltage from 76 VDC
input and observe at what input voltage
converter shuts OFF. This input voltage
point will be the input overvoltage threshold.
2.
No load power.
a) Set the input voltage at 53 VDC and
disconnect or turn OFF the load from the
converter and record the input power.
This value will be the product of input
voltage and input current measured using
the DMM illustrated in Figure D-5 and
Figure D-7.
3.
Input power when remote ON/OFF is active.
Remote ON/OFF will be used to turn OFF the
converter by applying a 3.3 VDC signal on the
pin illustrated in Figure D-10. A high signal (3.3
VDC) will turn OFF the converter and there is no
output. When a high signal is sensed by the
dsPIC DSC, all of the PWM generators are
shutdown. When the dsPIC DSC detects a low
remote ON/OFF signal, the converter will be
turned ON.
a)
b)
Turn ON the converter with 53 VDC input at
8.5A output load. Connect an oscilloscope
voltage probe to measure the output
voltage and a differential voltage probe to
measure the external 3.3 VDC supply, as
illustrated in Figure D-10.
Turn ON the external 3.3 VDC supply and
the system will shut down (there will be no
voltage at the output of the converter).
Record the input voltage and input current
to calculate the input power.
© 2011 Microchip Technology Inc.
AN1369
D.6.2
1.
OUTPUT CHARACTERISTICS
7.
The output overcurrent limit will protect the unit
from excessive loading than the rated load
current. Increment the output load beyond the
rated 17A, the converter enters into Hiccup
mode for a few milliseconds. If overcurrent
persists, the converter enters into Latch mode.
Line regulation.
Change the input DC voltage from 36 VDC to 76
VDC to the converter and record the output
voltage. The output voltage deviation should be
in the range of 11.88 VDC to 12.12 VDC.
2.
Load regulation.
Change the output load from 0A to 17A at
various input voltages in the range of 36 VDC to
76 VDC and record the output voltage variations.
The output voltage deviation should be in the
range of 11.88 VDC to 12.12 VDC.
3.
Set the input voltage at various points in the
specified range 36 VDC to 76 VDC and increment
the load at the output insteps. To monitor the
output voltage, connect the voltage probe, as
illustrated in Figure D-9.
8.
Output voltage ramp-up time.
Start-up time.
This is the time when the input voltage applied to
the converter (in the range of 36 VDC-76 VDC)
when the output voltage reaches 90% of the rated
12V output voltage. Connect the voltage
differential probe at the input voltage terminals
and the voltage probe at the output to the
oscilloscope, as illustrated in Figure D-11.
5.
6.
9.
D.7
Efficiency (%) = Output Power / Input Power * 100
= [(Output voltage * Output current) / (Input Voltage
* Input Current)] * 100
Use the following procedure to measure the efficiency
of the converter.
1.
2.
3.
4.
© 2011 Microchip Technology Inc.
Efficiency of the Quarter Brick DC/
DC Converter
Efficiency is the ratio of output power to the input
power:
Remote ON/OFF shut down fall time.
Removing the 3.3 VDC signal on the remote ON/
OFF pin, turns the converter ON. The remote ON/
OFF fall time is the time duration from when the
remote ON/OFF signal is enabled, to when the
output voltage falls to 10% of the rated output
voltage.
Output voltage ripple and noise.
Measure the AC component on the output voltage
of the converter by connecting the oscilloscope
output voltage probe, as illustrated in Figure D-9.
Read the output voltage by configuring the
oscilloscope in the AC couple mode. The output
ripple is measured in terms of peak-to-peak
voltage.
Remote ON/OFF start-up time.
Remote ON/OFF will be used to disable/enable the
converter by applying or removing a 3.3 VDC signal
on the Remote ON/OFF pin, as illustrated in
Figure D-10. Applying 3.3 VDC on the remote ON/
OFF pin turns the converter OFF. Remote ON/OFF
start-up time is the time duration from when the
remote ON/OFF is disabled, to when the output
voltage rises to 90% of the rated output voltage.
Load transient response.
Observe the variation on the DC output voltage
while step changing the output load from 25% to
the 75% of the rated output load 17A. The
parameters to be measured are peak-to-peak
output voltage variation and load transient
recovery time. Configure the oscilloscope in AC
couple mode and connect the oscilloscope output
voltage probe as illustrated in Figure D-9 to
measure the peak-to-peak output voltage
variation and load transient recovery time.
Turn ON the converter with the specified input
voltage in the range of 36 VDC to 76 VDC and
observe the DC output voltage raise time.
Ramp-up time is the time taken to reach output
voltage from 10% to 90% of the rated output
voltage. Ramp-up time can be measured by
connecting the oscilloscope voltage probe, as
illustrated in Figure D-9.
4.
Output overcurrent threshold.
Connect the DMM +ve terminal and –ve terminals
to the +ve and –ve of the input current
measurement resistor, as illustrated in Figure D-5.
Connect the DMM +ve terminal and –ve
terminals to the +ve and –ve of the output
current measurement resistor, as illustrated in
Figure D-6.
Connect the DMM for input voltage
measurement, as illustrated in Figure D-7.
Connect the DMM for output voltage
measurement, as illustrated in Figure D-8.
DS01369A-page 89
AN1369
D.8
COMM 1 and COMM 2
Connectivity
The COMM 1 and COMM 2 signal connectors, pin
termination, and functionality are described in Table D-1.
The pin sequence is illustrated in Figure D-12.
TABLE D-1:
Pin
PIN, PERIPHERAL AND FUNCTIONALITY TABLE
Peripheral
COMM 1 - 1
RB8
Functionality
Remappable I/O.
COMM 1 - 2
—
COMM 1 - 3
VSS
COMM 1 - 4
SDA1
Synchronous serial data input/output for I2C1.
COMM 1 - 5
SCL1
Synchronous serial clock input/output for I2C1.
COMM 1 - 6
RB15
Remappable I/O.
COMM 2 - 1
—
COMM 2 - 2
—
COMM 2 - 3
AN2
COMM 2 - 4
RP2/SYNCI1
No connect.
DIG_GND
Remote Sense -ve.
Remote Sense +ve.
Load share.
External synchronization signal to PWM master time base.
FIGURE D-12: COMM 1 AND COMM 2 SIGNAL CONNECTORS
Pin 6
Pin 1
Pin 4
Pin 1
Note 1: For N+1 system operations connect
COMM2-3 (load share) of Converter 1 to
Converter2 COMM2-3(load share).
2: Connect a common DC source to the
Converter1 and Converter2 input
terminals as illustrated in Figure D-3.
3: Connect a Common DC electronic load to
the Converter1 and Converter2 output
terminal as illustrated in Figure D-4.
DS01369A-page 90
© 2011 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
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Information contained in this publication regarding device
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The Microchip name and logo, the Microchip logo, dsPIC,
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trademarks of Microchip Technology Incorporated in the
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All other trademarks mentioned herein are property of their
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© 2011, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-60932-823-8
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
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© 2011 Microchip Technology Inc.
DS01369A-page 91
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