YGV638 VC2 en

YGV638
VC2
Video Controller 2
■
Overview
·
YGV638 (hereinafter called “VC2”) is a pattern graphic controller with an on-chip VRAM and
the ample drawing performance enables high-resolution animated GUIs on WVGA display
panels.
·
VC2’s multiple video ports allow direct handling of video signals from various sources: DVD
players, car navigation systems, rear view cameras, etc.
In addition, VC2 is capable of superimposing characters, lines, and even graphic icons or menu
screens (hereinafter called “sprite”) onto these videos.
·
With conventional graphic controllers, complicated display control programs need to be
developed. With VC2, Sprites can be used to simplify the programs as all the controls of a Sprite
is available in its 12-byte attribute: position, scaling factor, transparency, color gradation, etc.
·
VC2 integrates image de-compression engine (Yamaha proprietary algorithm) to dynamically
decompress the Sprite data stored in its external memory (Flash ROM etc.) achieving substantial
memory capacity savings.
VC2, with the features above, allows display systems for in-vehicle AV equipments, audio
equipments with display to be built with low-cost components.
YGV638 CATALOG
CATALOG No. LSI-4GV638A21
2011.03
■ Features
■
YGV638
Features
■
Display Function
●
Video Output
·
Monitor supported: TFT liquid crystal display (digital RGB connection) or compatible display
equipments
·
Digital RGB666, Digital RGB666+FRC, Digital RGB888
·
Supports NTSC, PAL, QVGA, WQVGA, VGA, WVGA, and SVGA
·
Supports interlace and progressive scans
·
Supports display timings in 1 dot and in 1 line resolution
·
Equalizing pulse insertion for composite sync signals
·
Dot clock polarity selection
·
Sync signal polarity selection
·
Gamma correction function (look-up table based)
·
On-chip LCD timing controller
●
■
Display Plane Functions
·
Up to 341 planes (up to 128 planes per scan line) and one external video plane
·
A layer displays either sprites, lines or texts
·
Alpha-blending between layers
·
Alpha-blending between layer and external video
·
Picture attribute controls by layers (contrasts, brightness)
Layer Function
●
Sprite
·
Displaying up to 341 sprites per screen and up to 128 sprites per scan line
·
Specified by horizontal and vertical coordinates
·
Sizes from 8 dot × 8 dot to 1024 dot × 1024 dot. Horizontal and vertical scaling independently
selectable (in 8-dot unit)
·
2, 16, 64, or 256 palette colors from 16M colors, or 64K colors with 16-bit RGB, 256K colors with
18-bit RGB, and 16M colors, life-like picture quality with 24-bit RGB
·
Scaling Function
·
Anti-aliasing of the outline profile
·
On-chip palettes with 1024 colors (combinations of 2 color palettes, 16 color palettes, 64 color
palettes, and 256 color palettes up to 1024 colors in total)
4GV638A21
2
■ Features
●
YGV638
Text
·
Displaying up to 1948 characters per screen and up to 128 characters per scan line
·
Independent font selections for each character strings
·
Supports proportional font
·
Supports half-width font
·
Scaling function
·
Supports 4-bit/pixel anti-aliasing font
·
Font size: 1 dot × 1 dot to 64 dot × 64 dot in increments of 1-dot independently in horizontal and
vertical direction
●
■
Line
·
Line drawn directly from specifications of start/end point coordinates
·
Up to 510 lines per screen
·
32768-color (RGB555) specification or palette index (10 bits) specification
·
Line width: from 1 dot to 16 dots (in one dot increments)
·
Anti-aliasing drawing function
Video Signal Inputs
●
Analog Video Input
·
Compatible with composite video, S video, component video, and RGB signal inputs
·
On-chip three 10bit-ADCs
·
Compatible with NTSC and PAL signal formats
·
On-chip video decoder
·
Supports interlace and progressive scans (RGB)
·
Compatible with composite sync signal inputs (RGB)
●
Digital Video Input
·
Compatible with RGB666, 16bit YCrCb, and 8bit YCrCb (ITU-R BT.656)
·
Compatible with interlace and progressive scans
·
Compatible with composite sync signal inputs
●
Video Image Processing
·
Scaling (the input images scaled to fit the display resolution, not a zooming function)
·
Mirror flipping (through vertical axis)
·
External sync mode (or free-running mode: switchable)
4GV638A21
3
■ Features
■
YGV638
Video Decoder
●
●
●
On-chip High-quality Y/C Separation Circuit (2D adaptive comb filter)
Digital AGC Circuit
Image Color Controls
·
Contrast
·
Brightness
·
Color hue
·
Chroma saturation
●
■
Color Killer Function
Other Features
●
CPU Interface
·
Serial or 8-bit parallel connection
·
Indirect accesses to internal registers and tables through single access port
·
Flexible asynchronous bus interface
·
Macro command function
●
Pattern Memory Interface
·
Bus width of 32 bits, or 16 bits
·
Up to 512 Mbits (64 MB) memory
·
Supports Mask-ROM, NOR-type flash-memory, SRAM, or compatible timing memories
·
Supports Page Mode accesses
·
Access timings in multiples of the system clock cycle
●
Device Specifications
·
Lead-free 208-pin LQFP package (YGV638-VZ)
·
Supply voltages: 3.3V and 1.8V
·
CPU interface power supply 3.3V
·
Operating temperature range from -40℃ to +85℃
4GV638A21
4
■ Pin Attributes
■
YGV638
Pin Attributes
Pin Name
CPU Interface (22)
D7-0
PS2-0
CS_N
RD_N
WR_N
WAIT_N
READY_N
INT_N
SER_N
SCS_N
SDIN
SCLK
SDOUT
Num.
I/O
Function
Attribute
Drive
8
3
1
1
1
1
1
1
1
1
1
1
1
I/O
I
I
I
I
OT
OT
OD
I
I
I
I
OT
CPU data bus
CPU port selection
Chip select (dual-purpose pin)
Read strobe (dual-purpose pin)
Write strobe (dual-purpose pin)
CPU bus wait (dual-purpose pin)
CPU bus ready
Interrupt
CPU interface selection
Serial interface chip select (dual-purpose pin)
Serial interface data input (dual-purpose pin)
Serial interface clocked into (dual-purpose pin)
Serial interface data output (dual-purpose pin)
Tolerant
Tolerant
Tolerant
Tolerant
Tolerant
Tolerant
Tolerant
Tolerant
4mA
4mA
4mA
4mA
Tolerant
Tolerant
Tolerant
Tolerant
4mA
I/O
OT
OT
OT
I
Pattern memory data bus
Pattern memory address bus
Pattern memory output enable
Pattern memory write pulse
Pattern memory high-impedance switching pin
Tolerant
Analog composite video input
Analog composite video input
Analog video R input
Analog video G input
Analog video B input
Test input
ADC reference
Plus reference voltage for ADC
Minus reference voltage for ADC
Analog video clock input
Analog video clock input
Analog video vertical sync signal input
Analog video horizontal sync signal input
Digital video R input (dual-purpose pin)
Digital video G input (dual-purpose pin)
Digital video B input (dual-purpose pin)
Digital video 8bit YCrCb input (dual-purpose pin)
Digital video Y input (dual-purpose pin)
Digital video Cr/Cb input (dual-purpose pin)
Digital video vertical sync signal input
Digital video horizontal sync signal input
Digital video clock input
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Tolerant
Tolerant
Tolerant
Tolerant
Tolerant
Tolerant
Tolerant
Tolerant
Tolerant
Tolerant
Tolerant
Tolerant
Tolerant
Pattern Memory Interface (60)
MD31-0
32
MA25-1
25
MOE_N
1
MWE_N
1
RAHZ_N
1
Video Input (58)
ACIN1
ACIN2
ARIN
AGIN
ABIN
ATESTIN
VREF0
VREFP
VREFN
ADCKIN
ARCKIN
AVSIN_N
AHSIN_N
DRI7-2
DGI7-2
DBI7-2
DIN7-0
YIN7-0
CIN7-0
DVSIN_N
DHSIN_N
DGCKIN
4GV638A21
1
1
1
1
1
1
1
1
1
1
1
1
1
6
6
6
8
8
8
1
1
1
I
I
I
I
I
I
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
5
4mA
4mA
4mA
4mA
■ Pin Attributes
YGV638
Monitor Interface (34)
DRO7-0
DGO7-0
DBO7-0
VSYNC_N
8
8
8
1
O
O
O
OT
HCSYNC_N
1
OT
BLANK_N
STARTH
LOADH
CLKV
STARTV
POL
OUTENV
DOTCLK
1
1
1
1
1
1
1
1
OT
OT
OT
OT
OT
OT
OT
O
Digital video: R output
Digital video: G output
Digital video: B output
Vertical sync signal output (dual-purpose pin)
Horizontal sync signal or composite sync signal output
(dual-purpose pin)
Display timing output (dual-purpose pin)
Horizontal start signal output
Horizontal load signal output
Vertical clock output (dual-purpose pin)
Vertical start signal output (dual-purpose pin)
Polarity reverse output (dual-purpose pin)
Output enable signal for a gate driver output
Dot clock output
Clock & Reset (8)
XIN
XOUT
DTCKIN
PLLCTL3-0
RESET_N
1
1
1
4
1
I
O
I
I
I$
Reference clock input
Crystal connection
Dot clock input
PLL control
Reset
for device (56)
XTEST2-0
VDD33
VSS
PLLVDD
PLLVSS
APLLVDD
APLLVSS
AVDD33
AVDD18
AVSS
VDD18
VSS18
3
17
19
1
1
1
1
1
2
2
4
4
I
－
－
－
－
－
－
－
－
－
－
－
Test pin
Digital I/O power supply
Digital I/O VSS
Power supply for system clock generation PLL
VSS for system clock generation PLL
Power supply for analog RGB clock generation PLL
VSS for analog RGB clock generation PLL
Power supply for Analog Front End
Power supply for Analog Front End
VSS for Analog Front End
Power supply for digital core
VSS for digital core
others (1)
NC
1
－
No connection pin
Tolerant
4mA
4mA
4mA
4mA
Tolerant
4mA
Tolerant
Tolerant
Tolerant
Tolerant
Tolerant
Tolerant
Tolerant
4mA
4mA
4mA
4mA
4mA
4mA
4mA
4mA
Tolerant
Tolerant
Total number of pins: 239 pin - 31 dual-purpose pin = 208 pins
[Description of I/O]
I: Input
O: Output
I$:
OT:
Input with Schmitt trigger
3-state output
I/O:
OD:
Input and Output
Open-drain output
[Description of attribute]
Tolerant: An attribute of an input pin buffer and a bidirectional pin buffer, or the output pin buffer.
During high impedance states, current will not flow into power supply pins from a pin
when some voltage higher than the I/O supply voltage is applied to the pin, if the pin is
“Tolerant.”
Analog:
Attribute which indicates an analog pin. These pins are operated from AVDD33 power
supply.
4GV638A21
6
■ Pin Attributes
YGV638
Sharing Pins
·
On VC2,
- the CPU interface pins change functions depending on which CPU interface, parallel or serial, is used.
- the digital video input pins change functions depending on the digital video input format used.
- the monitor interface pins change functions when the integrated LCD timing controller is used.
i)
Sharing of CPU Interface Pins
The VC2 supports the 8-bit parallel interface or serial interface. The correspondence between CPU
interface and the shared pin is as follows.
Pin Name
D7-0
PS2-0
CS_N
RD_N
WR_N
WAIT_N
READY_N
INT_N
ii)
Parallel Interface
(SER_N=H)
D7-0
PS2-0
CS_N
RD_N
WR_N
WAIT_N
READY_N
INT_N
Serial Interface
(SER_N=L)
Not used (Fixed to “H” or “L”)
Not used (Fixed to “H” or “L”)
SCS_N
SDIN
SCLK
SDOUT
Not used (N.C.)
INT_N
Sharing of Digital Video Input Pins
VC2 supports the digital video input of RGB666, 16bit YCrCb, and 8bit YCrCb format. The
correspondence between the format of digital video and the pins are as follows.
Pin Name
DRI2
DRI3
DRI4
DRI5
DRI6
DRI7
DGI2
DGI3
DGI4
DGI5
DGI6
DGI7
DBI2
DBI3
DBI4
DBI5
DBI6
DBI7
DGCKIN
DVSIN_N
DHSIN_N
RGB666
(DVIF=2’b00)
DRI2
DRI3
DRI4
DRI5
DRI6
DRI7
DGI2
DGI3
DGI4
DGI5
DGI6
DGI7
DBI2
DBI3
DBI4
DBI5
DBI6
DBI7
DGCKIN
DVSIN_N
DHSIN_N
8bit YCrCb
(DVIF=2’b01)
Not used
Not used
Not used
Not used
Not used
Not used
Not used
Not used
Not used
Not used
DIN0
DIN1
DIN2
DIN3
DIN4
DIN5
DIN6
DIN7
DGCKIN
Not used
Not used
Pull up the “Not used” pins to “H” or “L” outside the device.
4GV638A21
7
16bit YCrCb
(DVIF=2’b10)
CIN0
CIN1
CIN2
CIN3
CIN4
CIN5
CIN6
CIN7
Not used
Not used
YIN0
YIN1
YIN2
YIN3
YIN4
YIN5
YIN6
YIN7
DGCKIN
DVSIN_N
DHSIN_N
■ Pin Attributes
iii)
YGV638
Sharing of Monitor Interface Pins
VC2 has an on-chip LCD timing controller. The function of the following pins depends on whether or not
the timing controller is used, as shown below:
Pin Name
DRO7-0
DGO7-0
DBO7-0
DOTCLK
HCSYNC_N
VSYNC_N
BLANK_N
LOADH
STARTH
OUTENV
Timing controller not used
(TCONE=0)
DRO7-0
DGO7-0
DBO7-0
DOTCLK
HCSYNC_N
VSYNC_N
BLANK_N
Not used
Not used
Not used
Timing controller used
(TCONE=1)
DRO7-0
DGO7-0
DBO7-0
DOTCLK
CLKV
POL
STARTV
LOADH
STARTH
OUTENV
● Pin Assignments
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
MA1
MA2
VSS
MA3
MA4
MA5
MA6
VDD33
MA7
MA8
MA9
MA10
VSS
MA11
MA12
MA13
MA14
VDD33
MA15
MA16
MA17
MA18
VSS
MA19
VDD18
MA20
VSS18
MA21
MA22
VDD33
MA23
MA24
MA25
MWE_N
MOE_N
VSS
MD15
MD7
MD14
VDD33
MD6
MD13
MD5
MD12
VSS
MD4
MD11
MD3
MD10
MD2
VDD33
MD9
MD16
MD24
MD17
VDD33
MD25
MD18
MD26
MD19
MD27
VSS
MD20
MD28
MD21
MD29
MD22
VDD33
MD30
MD23
MD31
DBI7
VSS
DBI6
DBI5
VSS18
DBI4
VDD18
DBI3
DBI2
VDD33
DGI7
DGI6
DGI5
DGI4
DGI3
VSS
DGI2
DRI7
DRI6
DRI5
VDD33
DRI4
DRI3
DRI2
DHSIN_N
DVSIN_N
DGCKIN
VSS
AVDD33
AVDD18
AVSS
ATESTIN
ABIN
MD1
MD8
MD0
VSS
RAHZ_N
APLLVDD
NC
APLLVSS
VSS
DRO0
DRO1
DRO2
VDD33
DRO3
DRO4
DRO5
DRO6
VSS
DRO7
DGO0
DGO1
DGO2
VDD33
DGO3
VDD18
DGO4
VSS18
DGO5
DGO6
VSS
DGO7
DBO0
DBO1
DBO2
VDD33
DBO3
DBO4
DBO5
DBO6
DBO7
VSS
DOTCLK
VSYNC_N
HCSYNC_N
BLANK_N
VDD33
LOADH
STARTH
OUTENV
SER_N
VSS
PLLVSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
PLLVDD
DTCKIN
ADCKIN
VSS
XIN
XOUT
VDD33
XTEST0
XTEST1
XTEST2
PLLCTL3
PLLCTL2
PLLCTL1
PLLCTL0
RESET_N
VSS
CS_N
WR_N
RD_N
VDD33
PS2
PS1
PS0
VSS18
D0
VDD18
D1
VDD33
D2
D3
VSS
D4
D5
D6
D7
VDD33
WAIT_N
READY_N
INT_N
ARCKIN
AVSIN_N
AHSIN_N
VSS
AVDD18
AVSS
ACIN1
ACIN2
ARIN
VREFP
VREFN
VREF0
AGIN
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
<208pin LQFP Top View>
4GV638A21
8
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
■ Pin Attributes
■
#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
YGV638
Pin Names
Pin Name
PLLVDD
DTCKIN
ADCKIN
VSS
XIN
XOUT
VDD33
XTEST0
XTEST1
XTEST2
PLLCTL3
PLLCTL2
PLLCTL1
PLLCTL0
RESET_N
VSS
CS_N
WR_N
RD_N
VDD33
PS2
PS1
PS0
VSS18
D0
VDD18
D1
VDD33
D2
D3
VSS
D4
D5
D6
D7
VDD33
WAIT_N
READY_N
INT_N
ARCKIN
AVSIN_N
AHSIN_N
VSS
AVDD18
AVSS
ACIN1
ACIN2
ARIN
VREFP
VREFN
VREF0
AGIN
4GV638A21
#
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
Pin Name
ABIN
ATESTIN
AVSS
AVDD18
AVDD33
VSS
DGCKIN
DVSIN_N
DHSIN_N
DRI2
DRI3
DRI4
VDD33
DRI5
DRI6
DRI7
DGI2
VSS
DGI3
DGI4
DGI5
DGI6
DGI7
VDD33
DBI2
DBI3
VDD18
DBI4
VSS18
DBI5
DBI6
VSS
DBI7
MD31
MD23
MD30
VDD33
MD22
MD29
MD21
MD28
MD20
VSS
MD27
MD19
MD26
MD18
MD25
VDD33
MD17
MD24
MD16
#
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
9
Pin Name
MA1
MA2
VSS
MA3
MA4
MA5
MA6
VDD33
MA7
MA8
MA9
MA10
VSS
MA11
MA12
MA13
MA14
VDD33
MA15
MA16
MA17
MA18
VSS
MA19
VDD18
MA20
VSS18
MA21
MA22
VDD33
MA23
MA24
MA25
MWE_N
MOE_N
VSS
MD15
MD7
MD14
VDD33
MD6
MD13
MD5
MD12
VSS
MD4
MD11
MD3
MD10
MD2
VDD33
MD9
#
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
Pin Name
MD1
MD8
MD0
VSS
RAHZ_N
APLLVDD
NC
APLLVSS
VSS
DRO0
DRO1
DRO2
VDD33
DRO3
DRO4
DRO5
DRO6
VSS
DRO7
DGO0
DGO1
DGO2
VDD33
DGO3
VDD18
DGO4
VSS18
DGO5
DGO6
VSS
DGO7
DBO0
DBO1
DBO2
VDD33
DBO3
DBO4
DBO5
DBO6
DBO7
VSS
DOTCLK
VSYNC_N
HCSYNC_N
BLANK_N
VDD33
LOADH
STARTH
OUTENV
SER_N
VSS
PLLVSS
■ Block Diagram
■
YGV638
Block Diagram
Video Input
Analog
ACIN1
ACIN2
ARIN
AGIN
ABIN
AVSIN_N
AHSIN_N
VREFP
VREFN
VREF0
ADCKIN
ARCKIN
Analog
Front
End
Video
Decoder
Input
Video
Signal
Controller
Analog
Video
Controller
Pixel Data
Digital
DRI7-2
DGI7-2
DBI7-2
DVSIN_N
DHSIN_N
DGCKIN
Monitor I/F
Controller
DRO7-0
DGO7-0
Line Buffer
F
DBO7-0
HCSYNC_N
VSYNC_N
BLANK_N
MD31-0
MA25-1
MOE_N
MWE_N
RAHZ_N
Pattern Memory Interface
Pattern
Memory I/F
Pattern
Data
Decoder
Sprite
Rendering
Processor
DOTCLK
CLKV
STARTH
STARTV
Line
Rendering
Processor
CRTC
CPU I/F
Clock
Sprite & Line Plane Generator
D7-0
PS2-0
CS_N
RD_N
WR_N
WAIT_N
READY_N
INT_N
SDIN
SDOUT
SCS_N
To all
blocks
CPU
Interface
General
Table
Registers
SCLK
SER_N
4GV638A21
XIN
XOUT
Clock
Generator
Color Palette
10
LOADH
POL
OUTENV
To all
blocks
DTCKIN
PLLCTL3-0
■ Block Diagram
YGV638
● Typical Applications
■
VC2 Stand-alone system
Typical display contents: Dashboard instruments or vehicle information and alarms
CPU
LCD
VC2
Pattern memory
(Flash ROM)
■
OSD system for video camera images
Typical display contents: Dashboard instruments or vehicle information and alarms, Blind spot monitor,
Night view
CPU
Camera module
CVBS
VC2
Pattern memory
(Flash ROM)
4GV638A21
11
LCD
■ Block Diagram
■
YGV638
AV + Video camera images
Typical display contents: Dashboard instruments and vehicle information, Blind spot monitor,
HMI (Air-conditioner, Audio), DVD, TV, AUX
Camera module
CVBS
CPU
DVD module
TV module
CVBS
LCD
VC2
CVBS
CVBS
Pattern memory
(Flash ROM)
■
Video camera add-ons for car navigation systems
Typical display contents: Dashboard instruments and vehicles information, Blind spot monitor,
HMI (Air-conditioner, Audio), Car navigation system, Video
CPU
Camera module
CVBS
Navigation module
VC2
Analog RGB
or
Digital RGB
Pattern memory
(Flash ROM)
4GV638A21
12
LCD
■ Electrical Characteristics
■
YGV638
Electrical Characteristics
● Absolute Maximum Ratings
Items
Power supply voltage (VDD33 pin)
Power supply voltage (VDD18 pin)
Analog power supply voltage (AVDD33 pin)
Analog power supply voltage (AVDD18 pin)
PLL power supply voltage
(PLLVDD, APLLVDD pin)
Input pin voltage (Tolerant pin)
Input pin voltage (Analog pin)
Input pin voltage (Other pin)
Output pin voltage (Tolerant pins including I/O pins)
Output pin voltage (Analog pins including I/O pins)
Output pin voltage (Other pins including I/O pins)
Input pin current
Output pin current
Storage temperature
Note 1) Voltage relative to VSS=0V.
Symbol
VDD33
VDD18
VAVD33
VAVD18
Ratings
-0.5 to +4.6
-0.5 to +2.5
-0.5 to +4.6
-0.5 to +2.5
Unit
V
V
V
V
Note
1
1
1
1
VPLVD
-0.5 to +2.5
V
1
VI
VI
VI
VO
VO
VO
II
IO
TSTG
-0.5 to VDD33+4.6 ( ≤ 5.5 Max)
-0.5 to AVDD+0.5 ( ≤ 4.6 Max)
-0.5 to VDD33+0.5 ( ≤ 4.6 Max)
-0.5 to VDD33+4.6 ( ≤ 5.5 Max)
-0.5 to AVDD+0.5 ( ≤ 4.6 Max)
-0.5 to VDD33+0.5 ( ≤ 4.6 Max)
-20 to +20
-20 to +20
-50 to +125
V
V
V
V
V
V
mA
mA
℃
1
1
1
1
1
1
Unit
V
V
V
V
Note
1
1
1
1
V
1
℃
2
● Recommended Operating Condition
Items
Symbol
Min.
Typ.
Max.
Power supply voltage (VDD33 pin)
VDD33
3.0
3.3
3.6
Power supply voltage (VDD18 pin)
VDD18
1.65
1.8
1.95
Analog power supply voltage (AVDD33 pin)
VAVD33
3.0
3.3
3.6
Analog power supply voltage (AVDD18 pin)
VAVD18
1.65
1.8
1.95
PLL power supply voltage
VPLVD
1.65
1.8
1.95
(PLLVDD, APLLVDD pin)
VAPVD
Operating ambient temperature
TOP
-40
85
Note 1) Voltage relative to VSS=0V.
Note 2) The ambient temperature of 85℃ is the value measured under the following conditions:
Four-layer board with over 300% copper trace coverage
● Current Consumption
Items
Conditions
Symbol
Min.
Typ.
Max.
Unit Note
Total power consumption
PD
766
mW
1
Current consumption by supply
voltage
CL=20pF
VDD18
IVD18
VIL=GND
192
mA
1, 2
(including PLLVDD, APLLVDD)
VIH=VDD33
VDD33
IVDD33
40
mA
1
AVDD33
IAVD33
20
mA
1
AVDD18
IAVD18
90
mA
1
Note 1) Current consumption value and power consumption value are the values under the recommended operating
condition.
Note 2) PLLVDD and APLLVDD are internally connected to VDD18.
4GV638A21
13
■ Electrical Characteristics
YGV638
● DC Characteristics
Items
Symbol
Min.
Typ.
Max.
Unit
Low level input voltage (XIN pin)
VIL
-0.3
0.3×VDD33
V
Low level input voltage (except XIN pin)
VIL
-0.3
0.8
V
High level input voltage (XIN pin)
VIH
0.7×VDD33
VDD33+0.3
V
High level input voltage (RESET_N pin)
VIH
2.2
5.5
V
High level input voltage
VIH
2.0
5.5
V
(Tolerant pin other than RESET_N)
High level input voltage (except the above)
VIH
2.0
VDD33+0.3
V
Note 1) Voltage relative to VSS=0V.
Note 2) 5.5V can be applied to the Tolerant pin when the supply voltage is within the range of the recommended
operating voltage; however, up to 3.6V when the power is not applied.
Note
1
1
1
1, 2
Items
Low level output voltage
(except XOUT pin)
Unit
V
V
V
V
μA
μA
Note
1
1
1
1
Items
Symbol
Min.
Typ.
Analog video input voltage (ACIN1, ACIN2 pins)
VACIN
1.25
Analog video input voltage
VARIN
0.7
(ARIN, AGIN, ABIN pins)
Note 1) The above maximum value is for the setting of “R#021h: ADC*GAIN=2’b00.”
Max.
1.4
Unit
Vp-p
Note
1
1.4
Vp-p
1
Items
Input pin capacitance
Output pin capacitance
Input-Output pin capacitance
Max.
10
10
10
Unit
pF
pF
pF
Note
Input leak current
Output leak current
Note 1) Voltage relative to VSS=0V.
4GV638A21
Symbol
VOL
VOL
VOH
VOH
ILI
ILO
Symbol
CI
CO
CIO
14
Min.
0
0
VDD33-0.2
2.4
-10
-25
Min.
Typ.
1
Max.
0.2
0.4
VDD33
VDD33
+10
+25
High level output voltage
(except XOUT pin)
Conditions
IOL=100μA
IOL=2mA
IOH= -100μA
IOH= -2mA
1, 2
Typ.
■ Electrical Characteristics
YGV638
● AC Characteristics
AC characteristic is a value under the following conditions unless otherwise noted.
■
Input signal measurement condition:
Input voltages
0V / VDD33
Input transition time (tr,tf)
1ns (Provide for the transition time between 10% and 90% of
the input voltage.)
Input measurement reference voltage
0.5×VDD33
tr
V DD33
tf
0.9×VDD33
Input
signal
0.1×V DD33
GND
0.9×VDD33
0.1×V DD33
V DD33
Input
signal
0.5×VDD33
0.5×VDD33
GND
Measurement
reference voltage
■
Measurement
reference voltage
Output signal measurement condition
Output measurement reference voltage
0.5×VDD33
(In neither 3-state output pin nor input output pins, even when it
changed to high impedance, an output wave changes; therefore,
I/O cell specifies the transition to high impedance to the timing,
being as a disable state.)
VDD33
Output
signal
0.5×VDD33
0.5×VDD33
GND
Measurement
Measurement
VDD33
3-state output signal
Hi-Z
GND
Measurement point
VDD33
3-state output signal
Hi-Z
GND
Measurement point
4GV638A21
15
■ Electrical Characteristics
YGV638
Output load capacitance
20pF
Output pin
20pF
Clock Input
·
No.
1
2
3
4
5
6
7
8
9
10
11
Items
Symbol
Min.
Typ.
XIN, DTCKIN, DGCKIN: clock frequency
fCK
6
25
XIN, DTCKIN, DGCKIN: clock cycle time
tcCK
XIN, DTCKIN, DGCKIN:
twhCK
7.5
clock high level pulse width
XIN, DTCKIN, DGCKIN:
twlCK
7.5
clock low level pulse width
ADCKIN: clock frequency
fAD
20
35.7
ADCKIN: clock cycle time
tcAD
ADCKIN: clock high level pulse width
twhAD
14.29
ADCKIN: clock low level pulse width
twlAD
14.29
ARCKIN: clock frequency
fAR
6
25
ARCKIN: clock cycle time
tcAR
ARCKIN: clock high level pulse width
twhAR
10
ARCKIN: clock low level pulse width
twlAR
10
SYCLK: clock frequency
fSY
63
11.90
SYCLK: clock cycle time
tcSY
DCLK: clock frequency
fDT
6
25
DCLK: clock cycle time
tcDT
Note 1) The maximum of the oscillation frequency between XIN-XOUT is 30 MHz.
Note 2) SYCLK, DCLK is the internal clock.
Max.
40
166
Unit
MHz
ns
ns
ns
28
50
40
166
84
15.88
40
166
MHz
ns
ns
ns
MHz
ns
ns
ns
MHz
ns
MHz
ns
tcCK
twhCK
XIN
DTCKIN
DGCKIN
VIH
twlCK
VIH
0.5×VDD33
0.5×VDD33
V IL
4GV638A21
16
Note
1
VIL
2
2
2
2
■ Electrical Characteristics
YGV638
tcAD
twhAD
ADCKIN
VIH
twlAD
VIH
0.5×VDD33
0.5×VDD33
V IL
VIL
tcAR
twhAR
ARCKIN
VIH
twlAR
VIH
0.5×VDD33
0.5×VDD33
V IL
VIL
Power Supply and Reset Input
·
No.
1
2
3
4
5
6
Items
Symbol
Min.
Typ.
Max.
Unit Note
RESET_N: input time
twRES
10
μs
1
CPU access stand-by time after RESET_N
twAW
1 to 6.7
ms
2
negation
RESET_N: setup time
tsRES
0
ns
3
Power-on time difference
tVSKWR
1
s
4
Power-off time difference
tVSKWF
1
s
5
Power rise time
tVRISE
200
ms
Note 1) The time from a point where a power supply powered up last VDD33 reaches at 3.0V, and VDD18 reaches at
1.7V, and the input clock to the XIN pin becomes stable.
Note 2) It is necessary to wait to access for 40000 × t_XIN time (cycle of the clock inputted into XIN pin) after
RESET_N negation as PLL lock-up time.
Note 3) The specified value of VDD which is raised up the earliest.
Note 4) It is preferable to turn on VDD33, VDD18, AVDD33, AVDD18, PLLVDD, and APLLVDD at the same time. If 1
second or more time-difference occurs among their power-on, it may affect the LSI’s reliability.
Note 5) It is preferable to turn off VDD33, VDD18, AVDD33, AVDD18, PLLVDD, and APLLVDD at the same time. If 1
second or more time-difference occurs among their power-off, it may affect the LSI’s reliability.
4GV638A21
17
■ Electrical Characteristics
YGV638
tVRISE
3.0V
VDD33
AVDD33
3.0V
1.65V
tVSKWR
tVRISE
VDD18
AVDD18
PLLVDD
APLLVDD
1.7V
twRES
twRES
tsRES
twRES
RESET_N
twAW
twAW
CS_N
XIN
tVSKWF
VDD33
AVDD33
VDD18
AVDD18
PLLVDD
APLLVDD
3.0V
tVSKWF
1.7V
CPU Interface
·
i)
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Parallel Interface
Items
Symbol
Min.
Typ.
Max.
Unit Note
PS2-0: setup time
tsA
4
1
PS2-0: hold time
thA
0
1
CS_N: setup time
tsCS
0
2
CS_N: hold time
thCS
0
2
D7-0: output data turn on time
tonD
0
D7-0: output data turn off time
toffD
30
D7-0: output data valid delay time
tdD
0
D7-0: output data hold time
thD
0
WAIT_N, READY_N: turn on time
tonWAIT
0
ns
WAIT_N: valid delay time
tdWAIT
25
WAIT_N, READY_N: turn off time
toffWAIT
30
D7-0: input data setup time
tsD
tcSY +15
D7-0: input data hold time
thD
0
WR_N: hold time
thWR
0
READY_N: hold time
thREADY
0
30
command pulse active time
taCMD
2 × tcSY
3
command pulse inhibit time
tiCMD
4 × tcSY
3
command cycle time
tcCMD
6 × tcSY
3
Note 1) Specified values for WR_N and RD_N signals; however, in CS_N control, there are specified values for CS_N.
Note 2) Conditions that prove to be WR_N and RD_N controls. If these specified values are not met, these are for CS_N
control.
Note 3) “command pulse” means a low active pulse obtained by performing OR operation between CS_N signal and each
of WR_N and RD_N signals.
4GV638A21
18
■ Electrical Characteristics
●
YGV638
CPU read cycle
PS2-0
tsA
thA
CS_N
thCS
tsCS
RD_N
toffD
tonD
thD
Hi-Z
D7-0
Hi-Z
tdWAIT
tdD
tonWAIT
toffWAIT
Hi-Z
WAIT_N
Hi-Z
toffWAIT
tdD
READY_N
●
thREADY
tonWAIT
Hi-Z
Hi-Z
CPU write cycle
PS2-0
tsA
thA
CS_N
thCS
tsCS
WR_N
tsD
thD
D7-0
tdWAIT
Hi-Z
WAIT_N
thWR
toffWAIT
tonWAIT
Hi-Z
toffWAIT
thREADY
READY_N
●
tonWAIT
thWR
Hi-Z
Hi-Z
Access cycle
CS_N
WR_N
RD_N
taCMD
tiCMD
tcCMD
4GV638A21
taCMD
tiCMD
tcCMD
19
taCMD
tiCMD
tcCMD
taCMD
tiCMD
tcCMD
■ Electrical Characteristics
ii)
YGV638
Serial Interface
No.
Items
Symbol
1
SCLK clock cycle time
twSCLK
2
SCLK clock high level pulse width
twhSCLK
3
SCLK clock low level pulse width
twlSCLK
4
5
6
7
8
9
10
Min.
200
4 × tcXIN
100
2 × tcXIN
100
2 × tcXIN
25
25
25
25
Typ.
Max.
Unit
1, 2
1, 2
1, 2
SCS_N: setup time
tsSCS
SCS_N: hold time
thSCS
SDIN: setup time
tsSDI
SDIN: hold time
thSDI
SDOUT: output data delay time
tdSDO
65
SDOUT: turn off time
tofffSDO
20
SCS_N: pulse inhibit time
tiSCS
400
Note 1) Alternative value during VC2 initialization.
Note 2) tcXIN is the period of a clock that is fed to XIN pin.
Note 3) During VC2 initialization, the maximum of tdSDO becomes 17 ns plus 3 times the XIN input cycle.
ns
3
SCS_N
twSCLK
tsSCS
twlSCLK
thSCS
twhSCLK
SCLK
tsSDI
thSDI
SDIN
tdSDO
SDOUT
tdSDO
Hi-Z
tiSCS
SCS_N
SCLK
4GV638A21
20
Note
toffSDO
■ Electrical Characteristics
YGV638
Pattern Memory Interface
·
No.
1
2
3
4
5
6
7
8
9
10
11
12
●
Items
Symbol
MA25-1: output delay time
tdMA
MOE_N: output delay time
tdOE
MWE_N: output delay time
tdWE
MD31-0: input setup time
tsMD
MD31-0: input hold time
thMD
MD31-0: output delay time
tdMD
MA25-1: output hold time from MOE_N
thMAR
MD31-0:
thMDI
input hold time from MOE_N and MA25-1
MA25-1: output hold time from MWE_N
thMAW
MD31-0: output hold time from MWE_N
thMDO
MD31-0: turn off time from MWE_N
toffMDO
output turn off / on time from RAHZ_N
ton/offRA
Note 1) Specified value for an internal clock (SYCLK)
Min.
Typ.
2
2
4
0
Max.
14
14
14
Unit
24
ns
0
0
0
1
1
10
25
Memory Access Cycle (Random Read Cycle)
SYCLK
tdMA
tdMA
MA25-1
thMAR
tdOE
tdOE
MOE_N
tdWD
MWE_N
thMDI
tsMD
thMD
MD31-0
Note) After the read access, values of MA[25:0] and MOE_N are held until the next access to the pattern memory.
●
Memory Access Cycle (Write Cycle)
SYCLK
tdMA
tdMA
MA25-1
tdOE
tdMAW
MOE_N
tdWE
tdWE
MWE_N
tdMD
toffMDO
thMDO
MD31-0
Note) After the write access, values of MA25–1 and MOE_N are held until the next access to the pattern memory.
4GV638A21
21
Note
1
1
1
1
1
1
■ Electrical Characteristics
●
YGV638
RAHZ_N
MA25-1, MD31-0
MOE_N,MWE_N
ton/offRA
ton/offRA
RAHZ_N
The AC characteristics of an external memory connecting to VC2 must meet the following conditions.
(The following conditions are the values converted from the AC characteristics of the VC2 Pattern Memory;
they do not guarantee the following specifications directly. In addition, the item names below are those mainly
for an externally-connected memory.)
“F”, “R”, and “P” in the below are as follows.
F = (R#008h: FLTIM[1:0] + 1) Number of floating clocks
R = (R#009h: RDM[3:0] + 1)
Number of random access clocks
P = (R#009h: PAG[2:0] + 1)
Number of page mode access clocks
No.
13
14
15
16
17
18
Items
Address access time
Output enable time
Page mode access time
Data turn on time
Data turn off time
Data setup time
Symbol
tACC
tOE
tPACC
tDO
tDF
tDS
Conditions
It should be (F + R) * tcSY – tdMA(max) – tsMD(min) or less
It should be R * tcSY – tdOE(max) – tsMD(min) or less
It should be P * tcSY – tdMA(max) – tsMD(min) or less
It should be 0[ns] or over
It should be F * tcSY - tdOE(max) + tdWE(min) or less
It should be R * tcSY - tdMD(max) + tdWE(min) or less
F
R
P
SYCLK
tdMA(max)
tdOE(max)
tdMA(max)
MA25-(n+1)
t dMA(max)
tdMA(max)
MA(n)-1
tPACC
tACC
thMAR
MOE_N
tdWE (max)
tOE
MWE_N
tDS
thMOD
tDO
tsMD(min)
thMDI
tsMD(min)
t DF
thMDI
MD31-0
F
R
SYCLK
tdMA(max)
t dMA(max)
MA25-(n+1)
MA(n)-1
tdOE(max)
MOE_N
tdWE(max)
tdWE (max)
MWE_N
tdMD(max)
tDS
thMDO
MD31-0
Note) After accesses, values of MA25–1 and MOE_N are held until the next access to the pattern memory.
4GV638A21
22
■ Electrical Characteristics
YGV638
Video Signal Interface
·
No.
1
2
3
4
5
6
7
Items
DOTCLK: delay time
VSYNC_N, HCSYNC_N, BLANK_N,
DRO7-0, DGO7-0, DBO7-0, LOADH,
STARTH, OUTENV: hold time
VSYNC_N, HCSYNC_N, BLANK_N,
DRO7-0, DGO7-0, DBO7-0, LOADH,
STARTH, OUTENV: delay time
DVSIN_N, DHSIN_N, DRI7-2, DGI7-2,
DBI7-2: setup time
DVSIN_N, DHSIN_N, DRI7-2, DGI7-2,
DBI7-2: hold time
AVSIN_N, AHSIN_N: setup time
AVSIN_N, AHSIN_N: hold time
Symbol
tdDOTC
Min.
thDISP
0
Typ.
Max.
26
tdDISP
10
ns
tsDI
4
thDI
1
tsDI
thDI
3
1
DGCKIN or DTCKIN or XIN
tdDOTC
tdDOTC
DOTCLK
tdDISP
thDISP
Outputs
Note) the above figure shows the state that DOTCLK is not reversed.
DGCKIN
ARCKIN
tsDI
thDI
Inputs
4GV638A21
Unit
23
Note
■ Package Information
■
YGV638
Package Information
4GV638A21
24
YGV638
PRECAUTIONS AND INSTRUCTIONS FOR SAFETY
WARNING
Prohibited
Prohibited
Prohibited
Instructions
Do not use the device under stresses beyond those listed in Absolute Maximum Ratings.
Such stresses may become causes of breakdown, damages, or deterioration, causing explosion
or ignition, and this may lead to fire or personal injury.
Do not mount the device reversely or improperly and also do not connect a supply voltage in
wrong polarity. Otherwise, this may cause current and/or power-consumption to exceed the
absolute maximum ratings, causing personal injury due to explosion or ignition as well as causing
breakdown, damages, or deterioration.
And, do not use the device again that has been improperly mounted and powered once.
Do not short between pins.
In particular, when different power supply pins, such as between high-voltage and low-voltage
pins, are shorted, smoke, fire, or explosion may take place.
As to devices capable of generating sound from its speaker outputs, please design with safety of
your products and system in mind, such as the consequences of unusual speaker output due to a
malfunction or failure. A speaker dissipates heat in a voice-coil by air flow accompanying vibration
of a diaphragm. When a DC signal (several Hz or less) is input due to device failure, heat
dissipation characteristics degrade rapidly, thereby leading to voice-coil burnout, smoking or
ignition of the speaker even if it is used within the rated input value.
CAUTION
Prohibited
Instructions
Instructions
Instructions
Instructions
Instructions
Instructions
Instructions
Do not use Yamaha products in close proximity to burning materials, combustible substances, or
inflammable materials, in order to prevent the spread of the fire caused by Yamaha products, and
to prevent the smoke or fire of Yamaha products due to peripheral components.
Generally, semiconductor products may malfunction and break down due to aging, degradation,
etc. It is the responsibility of the designer to take actions such as safety design of products and
the entire system and also fail-safe design according to applications, so as not to cause property
damage and/or bodily injury due to malfunction and/or failure of semiconductor products.
The built-in DSP may output the maximum amplitude waveform suddenly due to malfunction from
disturbances etc. and this may cause damage to headphones, external amplifiers, and human
body (the ear). Please pay attention to safety measures for device malfunction and failure both in
product and system design.
As semiconductor devices are not nonflammable, overcurrent or failure may cause smoke or fire.
Therefore, products should be designed with safety in mind such as using overcurrent protection
circuits to control the amount of current during operation and to shut off on failure.
Products should be designed with fail safe in mind in case of malfunction of the built-in protection
circuits. Note that the built-in protection circuits such as overcurrent protection circuit and
high-temperature protection circuit do not always protect the internal circuits. In some cases,
depending on usage or situations, such protection circuit may not work properly or the device
itself may break down before the protection circuit kicks in.
Use a robust power supply.
The use of an unrobust power supply may lead to malfunctions of the protection circuit, causing
device breakdown, personal injury due to explosion, or smoke or fire.
Product's housing should be designed with the considerations of short-circuiting between pins of
the mounted device due to foreign conductive substances (such as metal pins etc.). Moreover,
the housing should be designed with spatter prevention etc. due to explosion or burning.
Otherwise, the spattered substance may cause bodily injury.
The device may be heated to a high temperature due to internal heat generation during
operation. Therefore, please take care not to touch an operating device directly.
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