Eice DR IV ER ™ Co m pac t High voltage gate driver IC 6E D f a mil y - 2 nd g e nera tion Chip pr od uct 3 phase 600 V gate drive IC 6ED003L06-C2 6EDL04I06PC 6EDL04I06NC 6EDL04N06PC EiceDRIVER™ Compact datash eet <Revision 2.5>, 20.04.2015 Indust rial Po wer C o ntrol Edition 20.04.2015 Published by Infineon Technologies AG 81726 Munich, Germany © 2015 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. 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EiceDRIVER(tm) Compact 6ED family - 2nd generation chip product Revision History Page or Item Subjects (major changes since previous revision) <Revision 2.5>, 20.04.2015 all revised wording of test temperature Trademarks of Infineon Technologies AG AURIX™, BlueMoon™, C166™, CanPAK™, CIPOS™, CIPURSE™, COMNEON™, EconoPACK™, CoolMOS™, CoolSET™, CORECONTROL™, CROSSAVE™, DAVE™, EasyPIM™, EconoBRIDGE™, EconoDUAL™, EconoPIM™, EiceDRIVER™, eupec™, FCOS™, HITFET™, HybridPACK™, I²RF™, ISOFACE™, IsoPACK™, MIPAQ™, ModSTACK™, my-d™, NovalithIC™, OmniTune™, OptiMOS™, ORIGA™, PRIMARION™, PrimePACK™, PrimeSTACK™, PRO-SIL™, PROFET™, RASIC™, ReverSave™, SatRIC™, SIEGET™, SINDRION™, SIPMOS™, SMARTi™, SmartLEWIS™, SOLID FLASH™, TEMPFET™, thinQ!™, TRENCHSTOP™, TriCore™, X-GOLD™, X-PMU™, XMM™, XPOSYS™. Other Trademarks Advance Design System™ (ADS) of Agilent Technologies, AMBA™, ARM™, MULTI-ICE™, KEIL™, PRIMECELL™, REALVIEW™, THUMB™, µVision™ of ARM Limited, UK. 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Last Trademarks Update 2010-10-26 datasheet 3 <Revision 2.5>, 20.04.2015 EiceDRIVER(tm) Compact 6ED family - 2nd generation chip product Table of Contents 1 Overview ............................................................................................................................................. 7 2 Blockdiagram...................................................................................................................................... 9 3 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 Chip size, bondpad configuration and description ...................................................................... 11 Mechanical data ................................................................................................................................. 11 Pad description................................................................................................................................... 12 Low Side and High Side Control Pins (Pin 2, 3, 4, 5, 6, 7) ................................................................ 13 EN (Gate Driver Enable, Pin 10) ........................................................................................................ 13 FAULT (Fault Feedback, Pin 8) ......................................................................................................... 13 ITRIP and RCIN (Over-Current Detection Function, Pin 9, 11) ......................................................... 14 VCC, VSS and COM (Low Side Supply, Pin 1, 12,13) ...................................................................... 14 VB1,2,3 and VS1,2,3 (High Side Supplies, Pin 18, 20, 22, 24, 26, 28) ............................................. 14 LO1,2,3 and HO1,2,3 (Low and High Side Outputs, Pin 14, 15, 16, 19, 23, 27) ............................... 14 4 4.1 4.2 4.3 4.4 4.5 4.6 Electrical Parameters ....................................................................................................................... 15 Absolute Maximum Ratings ............................................................................................................... 15 Required operation conditions ........................................................................................................... 16 Operating Range ................................................................................................................................ 16 Static logic function table ................................................................................................................... 17 Static parameters ............................................................................................................................... 17 Dynamic parameters .......................................................................................................................... 20 5 Quality disclaimer ............................................................................................................................ 21 6 Timing diagrams............................................................................................................................... 22 datasheet 4 <Revision 2.5>, 20.04.2015 EiceDRIVER(tm) Compact 6ED family - 2nd generation chip product List of Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 datasheet Typical Application ............................................................................................................................... 8 Block diagram for 6ED003L06-C2, and 6EDL04I06NC (with ultra fast BS diodes) ............................. 9 Block Diagram for 6EDL04I06PC, and 6EDL04N06PC ..................................................................... 10 Bond pad configuration of 6ED family (signals HIN1,2,3 and LIN1,2,3 according to Table 1) .......... 11 Input pin structure for negative logic (left) and positive logic (right) ................................................... 13 Input filter timing diagram for negative logic (left) and positive logic (right) ....................................... 13 EN pin structures ................................................................................................................................ 13 FAULT pin structures ......................................................................................................................... 14 Timing of short pulse suppression (6EDL04I06NC, 6ED003L06-C2)................................................ 22 Timing of short pulse suppression (6EDL04I06PC, 6EDL04N06PC) ................................................ 22 Timing of of internal deadtime (input logic according to Table 1) ...................................................... 22 Enable delay time definition ............................................................................................................... 23 Input to output propagation delay times and switching times definition (6EDL04I06NC, 6ED003L06C2) ...................................................................................................................................................... 23 Input to output propagation delay times and switching times definition (6EDL04I06PC, 6EDL04N06PC).................................................................................................................................. 23 Operating areas (6EDL04I06NC, 6EDL04I06PC, 6ED003L06-C2)................................................... 23 Operating Areas (6EDL04N06PC) ..................................................................................................... 24 ITRIP-Timing ...................................................................................................................................... 24 5 <Revision 2.5>, 20.04.2015 EiceDRIVER(tm) Compact 6ED family - 2nd generation chip product List of Tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 datasheet nd Members of 6ED family – 2 generation ............................................................................................. 7 Mechanical parameters ...................................................................................................................... 11 Pad position and dimension ............................................................................................................... 11 Pad Description .................................................................................................................................. 12 Abs. maximum ratings ........................................................................................................................ 15 Required Operation Conditions .......................................................................................................... 16 Operating range ................................................................................................................................. 16 Static parameters ............................................................................................................................... 17 Dynamic parameters .......................................................................................................................... 20 6 <Revision 2.5>, 20.04.2015 EiceDRIVER(tm) Compact 6ED family - 2nd generation chip product EiceDRIVER™ Compact 3 phase 600 V gate drive IC Overview 1 Main features Thin-film-SOI-technology Maximum blocking voltage +600V Separate control circuits for all six drivers CMOS and LSTTL compatible input (negative logic) Signal interlocking of every phase to prevent cross-conduction Detection of over current and under voltage supply externally programmable delay for fault clear after over current detection Chip product Product highlights Insensitivity of the bridge output to negative transient voltages up to -50V given by SOI-technology Ultra fast bootstrap diodes (except 6ED003L06-C2) 'shut down' of all switches during error conditions Typical applications Home appliances Fans, pumps General purpose drives Product family Table 1 nd Members of 6ED family – 2 Sales Name generation high side control input HIN1,2,3 and LIN1,2,3 typ. UVLOThresholds Bootstrap diode Package Replacement for st 1 generation 6EDL04I06NC negative logic 11.7 V / 9.8 V Yes sawn on foil No 6EDL04I06PC positive logic 11.7 V / 9.8 V Yes sawn on foil No 6EDL04N06PC positive logic 9 V / 8.1 V Yes sawn on foil No 6ED003L06-C2 negative logic 11.7 V / 9.8 V No sawn on foil Yes Description nd The device 6ED family – 2 generation is a full bridge driver to control power devices like MOS-transistors or IGBTs in 3-phase systems with a maximum blocking voltage of +600 V. Based on the used SOI-technology there is an excellent ruggedness on transient voltages. No parasitic thyristor structures are present in the device. Hence, no parasitic latch-up may occur at all temperatures and voltage conditions. The six independent drivers are controlled at the low-side using CMOS resp. LSTTL compatible signals, down to 3.3 V logic. The device includes an under-voltage detection unit with hysteresis characteristic and an overcurrent detection. The over-current level is adjusted by choosing the resistor value and the threshold level at pin ITRIP. Both error conditions (under-voltage and over-current) lead to a definite shut down off all six switches. An error signal is provided at the FAULT open drain output pin. The blocking time after over-current can be adjusted with an RC-network at pin RCIN. The input RCIN owns an internal current source of 2.8 µA. Therefore, the resistor RRCIN is optional. The typical output current can be given with 165 mA for pull-up and 375 mA for pull down. Because of system safety reasons a 310 ns interlocking time has been realised. The function of input EN datasheet 7 <Revision 2.5>, 20.04.2015 EiceDRIVER(tm) Compact 6ED family - 2nd generation chip product can optionally be extended with an over-temperature detection, using an external NTC-resistor (see Fig.1). The monolithic integrated bootstrap diode structures between pins VCC and VBx can be used for power supply of the high side. DC-Bus VCC VCC HIN1,2,3 LIN1,2,3 EN HIN1,2,3 LIN1,2,3 EN VB1,2,3 HO1,2,3 To Load VS1,2,3 5V FAULT FAULT LO1,2,3 RRCIN CRCIN COM RCIN ITRIP VSS R Sh VSS Signals HIN1,2,3 and LIN1,2,3 according to Table 1 Figure 1 datasheet Typical Application 8 <Revision 2.5>, 20.04.2015 EiceDRIVER(tm) Compact 6ED family - 2nd generation chip product Blockdiagram 2 BOOTSTRAP DIODE-VB1 BIAS NETWORK / VDD2 INPUT NOISE FILTER HIN1 LIN1 INPUT NOISE FILTER HIN2 INPUT NOISE FILTER VB1 BIAS NETWORK - VB1 DEADTIME & SHOOT-THROUGH PREVENTION LATCH HV LEVEL-SHIFTER + REVERSE-DIODE z COMPAR ATOR UVDETECT GateDrive HO1 VS1 BOOTSTRAP DIODE-VB2 LIN2 INPUT NOISE FILTER HIN3 INPUT NOISE FILTER VB2 BIAS NETWORK - VB2 DEADTIME & SHOOT-THROUGH PREVENTION LATCH HV LEVEL-SHIFTER + REVERSE-DIODE COMPAR ATOR UVDETECT GateDrive HO2 VS2 BOOTSTRAP DIODE-VB3 LIN3 INPUT NOISE FILTER EN INPUT NOISE FILTER VB3 BIAS NETWORK / VB3 DEADTIME & SHOOT-THROUGH PREVENTION LATCH HV LEVEL-SHIFTER + REVERSE-DIODE COMPAR ATOR UVDETECT GateDrive HO3 VS3 >1 ITRIP VCC UVDETECT DELAY VSS / COM LEVELSHIFTER GateDrive LO1 DELAY VSS / COM LEVELSHIFTER GateDrive LO2 DELAY VSS / COM LEVELSHIFTER GateDrive LO3 INPUT NOISE FILTER S VDD2 Q SET DOMINANT LATCH R IRCIN RCIN COM FAULT VSS >1 Figure 2 datasheet Block diagram for 6ED003L06-C2, and 6EDL04I06NC (with ultra fast BS diodes) 9 <Revision 2.5>, 20.04.2015 EiceDRIVER(tm) Compact 6ED family - 2nd generation chip product BOOTSTRAP DIODE-VB1 BIAS NETWORK / VDD2 INPUT NOISE FILTER HIN1 LIN1 INPUT NOISE FILTER HIN2 INPUT NOISE FILTER VB1 BIAS NETWORK - VB1 DEADTIME & SHOOT-THROUGH PREVENTION LATCH HV LEVEL-SHIFTER + REVERSE-DIODE z COMPAR ATOR UVDETECT GateDrive HO1 VS1 BOOTSTRAP DIODE-VB2 LIN2 INPUT NOISE FILTER HIN3 INPUT NOISE FILTER VB2 BIAS NETWORK - VB2 DEADTIME & SHOOT-THROUGH PREVENTION LATCH HV LEVEL-SHIFTER + REVERSE-DIODE COMPAR ATOR UVDETECT GateDrive HO2 VS2 BOOTSTRAP DIODE-VB3 VB3 BIAS NETWORK / VB3 DEADTIME & SHOOT-THROUGH PREVENTION LATCH HV LEVEL-SHIFTER + REVERSE-DIODE COMPAR ATOR UVDETECT GateDrive INPUT NOISE FILTER LIN3 HO3 VS3 >1 INPUT NOISE FILTER EN ITRIP VCC UVDETECT DELAY VSS / COM LEVELSHIFTER GateDrive LO1 DELAY VSS / COM LEVELSHIFTER GateDrive LO2 DELAY VSS / COM LEVELSHIFTER GateDrive LO3 INPUT NOISE FILTER S VDD2 Q SET DOMINANT LATCH R IRCIN RCIN COM FAULT VSS >1 Figure 3 datasheet Block Diagram for 6EDL04I06PC, and 6EDL04N06PC 10 <Revision 2.5>, 20.04.2015 EiceDRIVER(tm) Compact 6ED family - 2nd generation chip product 3 Chip size, bondpad configuration and description 3.1 Mechanical data Table 2 Mechanical parameters Raster size of die 2544 x 1706 µm x µm Area total / active 4.34 / 4.65 mm² Thickness 280 µm Wafer size 200 mm Max. possible chips per wafer 5908 pcs Passivation frontside Polyimide Backside (Note 2) Grinded silicon Reject ink dot diameter Min. 0.6 max 1.2 mm Note1: Filler material inside the mould compound with sharp edges may harm the passivation. Note2: Chip must be bonded onto an electrically isolated area All pad openings are designed for gold wire ball bonds and not for aluminum wedge bonds. y x Figure 4 Table 3 Pad Name Bond pad configuration of 6ED family (signals HIN1,2,3 and LIN1,2,3 according to Table 1) Pad position and dimension Pad Number Voltage Domain Pad Center Coordinates /µm Active Pad Dimension /µm X Y X Y VCC 1 1 271 565 80 145 HIN1 2 1 271 423 80 80 HIN2 3 1 271 313 80 80 HIN3 4 1 271 203 80 80 LIN1 5 1 390 185 80 80 LIN2 6 1 669 185 80 80 datasheet 11 <Revision 2.5>, 20.04.2015 EiceDRIVER(tm) Compact 6ED family - 2nd generation chip product Table 3 Pad Name Pad position and dimension Pad Number Voltage Domain Pad Center Coordinates /µm Active Pad Dimension /µm X Y X Y LIN3 7 1 862 185 80 80 FAULT 8 1 1063 185 80 80 ITRIP 9 1 1210 185 80 80 EN 10 1 1488 185 80 80 RCIN 11 1 1637 185 80 80 VSS 12 1 2104 171 160 100 COM 13 1 2305 226 160 80 LO3 14 1 2350 349 80 80 LO2 15 1 2350 469 80 80 LO1 16 1 2350 619 80 140 VS3 18 2 2217 1325 140 80 HO3 19 2 2047 1325 140 80 VB3 20 2 1877 1325 140 80 VS2 22 3 1440 1325 140 80 HO2 23 3 1270 1325 140 80 VB2 24 3 1100 1325 140 80 VS1 26 4 324 1325 140 80 HO1 27 4 294 1185 80 140 VB1 28 4 294 1014 80 140 floating --- --- --- --- Chip back side --- 3.2 Pad description Table 4 Pad Description Symbol Description VCC Low side power supply VSS Logic ground /HIN1,2,3 High side logic input (negative logic) /LIN1,2,3 Low side logic input (negative logic) /FAULT Indicates over-current and under-voltage (negative logic, open-drain output) EN Enable I/O functionality (positive logic) ITRIP Analog input for over-current shutdown, activates FAULT and RCIN to VSS RCIN external RC-network to define FAULT clear delay after FAULT-Signal (TFLTCLR) COM Low side gate driver reference VB1,2,3 High side positive power supply HO1,2,3 High side gate driver output VS1,2,3 High side negative power supply LO1,2,3 Low side gate driver output Chip back side Floating back side (floats towards the highest momentarily active potential) datasheet 12 <Revision 2.5>, 20.04.2015 EiceDRIVER(tm) Compact 6ED family - 2nd generation chip product 3.3 Low Side and High Side Control Pins (Pin 2, 3, 4, 5, 6, 7) The Schmitt trigger input threshold of them are such to guarantee LSTTL and CMOS compatibility down to 3.3 V controller outputs. Input Schmitt trigger and noise filter provide beneficial noise rejection to short input pulses according to Figure 5 and Figure 6. Vcc Schmitt-Trigger HINx LINx Schmitt-Trigger INPUT NOISE FILTER UZ=10.5V HINx LINx SWITCH LEVEL VIH; VIL Figure 5 5k INPUT NOISE FILTER UZ=10.5V SWITCH LEVEL VIH; VIL Input pin structure for negative logic (left) and positive logic (right) An internal pull-up of about 75 k (negative logic) pre-biases the input during supply start-up and a ESD zener clamp is provided for pin protection purposes. The zener diodes are therefore designed for single pulse stress only and not for continuous voltage stress over 10V. For versions with positive, a 5 k pull-down resistor is used for this function. a) tFILIN LIN b) a) tFILIN tFILIN b) tFILIN HIN LIN LIN HIN LIN HO LO LO HO LO high LO Figure 6 high low low Input filter timing diagram for negative logic (left) and positive logic (right) It is anyway recommended for proper work of the driver not to provide input pulse-width lower than 1 µs. nd The 6ED family – 2 generation provides additionally a shoot through prevention capability which avoids the simultaneous on-state of two channels of the same leg (i.e. HO1 and LO1, HO2 and LO2, HO3 and LO3). When two inputs of a same leg are activated, only one leg output is activated, so that the leg is kept steadily in a safe state. Please refer to the application note AN-Gatedrive-6ED2-1 for a detailed description. A minimum dead time insertion of typ. 310 ns is also provided, in order to reduce cross-conduction of the external power switches. 3.4 EN (Gate Driver Enable, Pin 10) The signal applied to pin EN controls directly the output stages. All outputs are set to LOW, if EN is at LOW logic level. The internal structure of the pin is given in Figure 7. The switching levels of the Schmitt-Trigger are here VEN,TH+ = 2.1 V and VEN,TH- = 1.3 V. The typical propagation delay time is tEN = 780 ns. There is an internal pull down resistor (75 k), which keeps the gate outputs off in case of broken PCB connection. EN IEN+, IEN- VZ= 10.5 V INPUT NOISE FILTER VEN,TH+, VEN,TH- 6ED family – 2nd generation Figure 7 3.5 EN pin structures /FAULT (Fault Feedback, Pin 8) /Fault pin is an active low open-drain output indicating the status of the gate driver (see Figure 8). The pin is active (i.e. forces LOW voltage level) when one of the following conditions occur: datasheet 13 <Revision 2.5>, 20.04.2015 EiceDRIVER(tm) Compact 6ED family - 2nd generation chip product Under-voltage condition of VCC supply: In this case the fault condition is released as soon as the supply voltage condition returns in the normal operation range (please refer to VCC pin description for more details). Over-current detection (ITRIP): The fault condition is latched until current trip condition is finished and RCIN input is released (please refer to ITRIP pin). VDD 6ED family – 2nd generation VCC RON,FLT FAULT Figure 8 3.6 >1 from ITRIP-Latch from uv-detection /FAULT pin structures ITRIP and RCIN (Over-Current Detection Function, Pin 9, 11) nd The 6ED family – 2 generation provides an over-current detection function by connecting the ITRIP input with the motor current feedback. The ITRIP comparator threshold (typ 0.44 V) is referenced to VSS ground. A input noise filter (typ. tITRIPMIN = 230 ns) prevents the driver to detect false over-current events. Over-current detection generates a hard shut down of all outputs of the gate driver and provides a latched fault feedback at /FAULT pin. RCIN input/output pin is used to determine the reset time of the fault condition. As soon as ITRIP threshold is exceeded the external capacitor connected to RCIN is fully discharged. The capacitor is then recharged by the RCIN current generator when the over-current condition is finished. As soon as RCIN voltage exceeds the rising threshold of typ VRCIN,TH = 5.2 V, the fault condition releases and the driver returns operational following the ontrol input pins according to section 3.3. Please refer to AN-Gatedrive-6ED2-1 for details on setting RCIN time constant. 3.7 VCC, VSS and COM (Low Side Supply, Pin 1, 12,13) VCC is the low side supply and it provides power both to input logic and to low side output power stage. Input logic is referenced to VSS ground as well as the under-voltage detection circuit. Output power stage is referenced to COM ground. COM ground is floating respect to VSS ground with a maximum range of operation of +/-5.7 V. A back-to-back zener structure protects grounds from noise spikes. The under-voltage circuit enables the device to operate at power on when a typical supply voltage higher than VCCUV+ is present. The IC shuts down all the gate drivers power outputs, when the VCC supply voltage is below VCCUV- = 9.8 V respectively 8.1 V. This prevents the external power switches from critically low gate voltage levels during on-state and therefore from excessive power dissipation. 3.8 VB1,2,3 and VS1,2,3 (High Side Supplies, Pin 18, 20, 22, 24, 26, 28) VB to VS is the high side supply voltage. The high side circuit can float with respect to VSS following the external high side power device emitter/source voltage. Due to the low power consumption, the floating driver stage can be supplied by bootstrap topology connected to VCC. The device operating area as a function of the supply voltage is given in Figure 15 and Figure 16. Details on bootstrap supply section and transient immunity can be found in application note AN-Gatedrive-6ED2-1. 3.9 LO1,2,3 and HO1,2,3 (Low and High Side Outputs, Pin 14, 15, 16, 19, 23, 27) Low side and high side power outputs are specifically designed for pulse operation such as gate drive of IGBT and MOSFET devices. Low side outputs (i.e. LO1,2,3) are state triggered by the respective inputs, while high side outputs (i.e. HO1,2,3) are edge triggered by the respective inputs. In particular, after an under voltage condition of the VBS supply, a new turn-on signal (edge) is necessary to activate the respective high side output, while after a under voltage condition of the VCC supply, the low side outputs switch to the state of their respective inputs. datasheet 14 <Revision 2.5>, 20.04.2015 EiceDRIVER(tm) Compact 6ED family - 2nd generation chip product 4 Electrical Parameters 4.1 Absolute Maximum Ratings All voltages are absolute voltages referenced to VSS -potential unless otherwise specified. All parameters are valid for Ta=25 °C. Table 5 Abs. maximum ratings Parameter Symbol VS High side offset voltage(Note 1) Min. Max. Unit VCC-VBS-6 600 V VCC -VBS – 50 – High side offset voltage (tp<500ns, Note 1) High side offset voltage(Note 1) VB High side offset voltage (tp<500ns, Note 1) Chip back side VBack High side floating supply voltage (VB vs. VS) (internally clamped) VCC – 6 620 VCC – 50 – VCC-VBS-6 620 -1 High side output voltage (VHO vs. VS) VHO -0.5 20 VB + 0.5 Low side supply voltage (internally clamped) Low side supply voltage (VCC vs. VCOM) VCC -1 20 VCCOM -0.5 25 Gate driver ground Low side output voltage (VLO vs. VCOM) VCOM -5.7 VLO -0.5 5.7 VCCOM + 0.5 Input voltage LIN,HIN,EN,ITRIP VIN -1 FAULT output voltage VFLT -0.5 RCIN output voltage VRCIN TJ -0.5 – VCC + 0.5 Junction temperature Storage temperature TS - 40 150 offset voltage slew rate dVS/dt 10 VCC + 0.5 125 50 °C V/ns Note :The minimum value for ESD immunity is 1.0kV (Human Body Model). ESD immunity inside pins connected to the low side (VCC, HINx, LINx, FAULT, EN, RCIN, ITRIP, VSS, COM, LOx) and pins connected inside each high side itself (VBx, HOx, VSx) is guaranteed up to 1.5kV (Human Body Model). Note 1 : In case VCC > VB there is an additional power dissipation in the internal bootstrap diode between pins VCC and VBx. Insensitivity of bridge output to negative transient voltage up to –50V is not subject to production test – verified by design / characterization. datasheet 15 <Revision 2.5>, 20.04.2015 EiceDRIVER(tm) Compact 6ED family - 2nd generation chip product 4.2 Required operation conditions All voltages are absolute voltages referenced to VSS -potential unless otherwise specified. All parameters are valid for Ta=25 °C. Table 6 Required Operation Conditions Parameter Symbol VB Min. Max. Unit High side offset voltage (Note 1) 7 620 V Low side supply voltage (VCC vs. VCOM) VCCOM 10 25 4.3 Operating Range All voltages are absolute voltages referenced to VSS -potential unless otherwise specified. All parameters are valid for Ta=25 °C. Table 7 Operating range Parameter Symbol VS High side floating supply offset voltage 13 17.5 10 VBS 0 VCC 6EDL04I06NC VCC 6EDL04I06PC 6ED003L06-C2 13 17.5 6EDL04N06PC 10 17.5 Low side output voltage (VLO vs. VCOM) VLO Low side supply voltage Unit V -1.0 VBCC 6EDL04I06NC VBS 6EDL04I06PC 6ED003L06-C2 6EDL04N06PC VHO High side output voltage (VHO vs. VS) Max. 550 550 High side floating supply offset voltage (VB vs. VCC, statically) High side floating supply voltage (VB vs. VS, Note 1) Min. VCC VBS -1 Low side ground voltage VCOM -2.5 2.5 Logic input voltages LIN,HIN,EN,ITRIP (Note 2) VIN 0 FAULT output voltage VFLT 0 5 VCC RCIN input voltage VRCIN 0 VCC Pulse width for ON or OFF (Note 3) tIN 1 – µs Ambient temperature Ta -40 95 °C Note 1 : Logic operational for VB (VB vs. VS) > 7,0V Note 2 : All input pins (HINx, LINx) and EN, ITRIP pin are internally clamped (see abs. maximum ratings) Note 3 : In case of input pulse width at LINx and HINx below 1µ the input pulse may not be transmitted properly datasheet 16 <Revision 2.5>, 20.04.2015 EiceDRIVER(tm) Compact 6ED family - 2nd generation chip product 4.4 Static logic function table VCC VBS RCIN ITRIP ENABLE FAULT LO1,2,3 HO1,2,3 <VCCUV– X X X X 0 0 0 15V <VBSUV– X 0 3.3 V High imp LIN1,2,3* 0 15V 15V <3.2 V 0 3.3 V 0 0 0 15V 15V X > VIT,TH+ 3.3 V 0 0 0 15V 15V > VRCIN,TH 0 3.3 V High imp LIN1,2,3* HIN1,2,3* 15V 15V > VRCIN,TH 0 0 High imp 0 0 * according to Table 1 4.5 Static parameters VCC = VBS = 15V unless otherwise specified. All parameters are valid for Ta=25 °C. Table 8 Static parameters Parameter Symbol Values Unit Min. Typ. Max. Test condition High level input voltage VIH 1.7 2.1 2.4 Low level input voltage VIL 0.7 0.9 1.1 EN positive going threshold VEN,TH+ 1.9 2.1 2.3 EN negative going threshold VEN,TH- 1.1 1.3 1.5 ITRIP positive going threshold VIT,TH+ 380 445 510 mV ITRIP input hysteresis VIT,HYS 45 70 RCIN positive going threshold VRCIN,TH - 5.2 6.4 V RCIN input hysteresis VRCIN,HYS - 2.0 - Input clamp voltage (HIN and LIN acc. Table 1, EN, ITRIP) VIN,CLMAP 9 10.3 12 IIN = 4mA Input clamp voltage at high impedance (/HIN, /LIN negative logic only) High level output voltage LO1,2,3 HO1,2,3 VIN,FLOAT - 5.3 5.8 controller output pin floating VOH - VCC -0.7 VCC -1.4 VB -0.7 VB -1.4 IO = 20mA Low level output voltage VOL - VCOM+ 0.6 VS + 0.6 IO = -20mA - VCOM+ 0.2 VS+ 0.2 6EDL04I06NC VCCUV+ 6EDL04I06PC VBSUV+ 6ED003L06-C2 6EDL04N06PC 11 11.7 12.5 8.3 9 9.8 6EDL04I06NC VCCUV– 6EDL04I06PC VBSUV– 6ED003L06-C2 6EDL04N06PC 9.5 9.8 10.8 7.5 8.1 8.8 LO1,2,3 HO1,2,3 VCC and VBS supply undervoltage positive going threshold VCC and VBS supply undervoltage negative going threshold datasheet 17 V V <Revision 2.5>, 20.04.2015 EiceDRIVER(tm) Compact 6ED family - 2nd generation chip product Table 8 Static parameters Parameter Symbol Values Unit Test condition µA VS = 600V TJ = 125°C, VS = 600V Min. Typ. Max. 1.2 1.9 - 0.5 0.9 - - 1 12.5 - 10 - High side leakage current between VSx and ILVS– VSy (x=1,2,3 and y=1,2,3) IQBS1 Quiescent current VBS supply (VB only) IQBS2 Quiescent current VBS supply (VB only) - 10 - - 210 400 - 210 400 Quiescent current VCC supply (VCC only) 6EDL04I06NC IQCC1 6ED003L06-C2 - 1.1 1.8 6EDL04I06PC 6EDL04N06PC 6EDL04I06NC IQCC2 6ED003L06-C2 6EDL04I06PC 6EDL04N06PC 6EDL04I06NC IQCC3 6ED003L06-C2 6EDL04I06PC 6EDL04N06PC 6EDL04I06NC ILIN+ 6ED003L06-C2 - 0.75 1.5 - 1.3 2 VLIN=0, VHIN=3.3 V 0.75 1.5 VLIN=3.3 V, VHIN=0 1.3 2 VLIN=3.3 V, VHIN=0 0.75 1.5 VLIN=3.3 V, VHIN=0 - 70 100 6EDL04I06PC 6EDL04N06PC 6EDL04I06NC ILIN6ED003L06-C2 6EDL04I06PC 6EDL04N06PC 6EDL04I06NC IHIN+ 6ED003L06-C2 400 700 1100 - 110 200 - 70 100 6EDL04I06PC 6EDL04N06PC 400 700 1100 - 110 200 VHIN=0 45 120 VITRIP=3.3 V 45 120 VENABLE=3.3 V VCC and VBS supply undervoltage lockout hysteresis 6EDL04I06NC VCCUVH 6EDL04I06PC VBSUVH 6ED003L06-C2 6EDL04N06PC High side leakage current betw. VS and VSS ILVS+ 1 High side leakage current betw. VS and VSS ILVS+ 1 Quiescent current VCC supply (VCC only) Quiescent current VCC supply (VCC only) Input bias current Input bias current Input bias current Input bias current 6EDL04I06NC IHIN6ED003L06-C2 6EDL04I06PC 6EDL04N06PC IITRIP+ Input bias current (ITRIP=high) IEN+ Input bias current (EN=high) Input bias current RCIN (internal current source) IRCIN Mean output current for load capacity IO+ 1 - TJ = 125°C VSx - VSy = 600V µA HO=low HO=high mA VLIN=float. µA VLIN=3.3 V µA VLIN=0 0 VHIN=3.3 V 0 - VRCIN = 2 V 2.8 120 165 - mA CL=10 nF Not subject of production test, verified by characterisation datasheet 18 <Revision 2.5>, 20.04.2015 EiceDRIVER(tm) Compact 6ED family - 2nd generation chip product Table 8 Static parameters Parameter Symbol Values Min. charging in range from 3 V (20%) to 6 V (40%) Peak output current turn on (single pulse) IOpk+1 Typ. Unit Max. RL = 0 , tp <10 µs 240 IOMean output current for load capacity discharging in range from 12 V (80%) to 9 V (60%) IOpk-1 Peak output current turn off (single pulse) 250 VF,BSD Bootstrap diode forward voltage between VCC and VB (for types with bootstrap diode only) IF,BSD Bootstrap diode forward current between VCC and VB (for types with bootstrap diode only) RBSD Bootstrap diode resistance (for types with bootstrap diode only) Ron,RCIN RCIN low on resistance of the pull down transistor Ron,FLT FAULT low on resistance of the pull down transistor - 1.0 1.3 V IF=0.5 mA 27 51 75 mA VF=4 V 24 40 60 VF1=4 V, VF2=5 V - 40 100 VRCIN=0.5 V - 45 100 VFAULT=0.5 V 1 375 Test condition - CL=10 nF RL = 0 , tp <10 µs 420 Not subject of production test, verified by characterisation datasheet 19 <Revision 2.5>, 20.04.2015 EiceDRIVER(tm) Compact 6ED family - 2nd generation chip product 4.6 Dynamic parameters VCC = VBS = 15 V, VS = VSS = VCOM unless otherwise specified. All parameters are valid for Ta=25 °C. Table 9 Dynamic parameters Parameter Symbol ton Turn-on propagation delay Turn-off propagation delay 6EDL04I06NC toff 6EDL04I06PC 6ED003L06-C2 6EDL04N06PC Values Min. Typ. Max. 400 360 530 490 800 760 Unit Test condition ns VLIN/HIN = 0 or 3.3 V 400 530 800 Turn-on rise time tr - 60 100 Turn-off fall time tf - 26 45 VLIN/HIN = 0 or 3.3 V CL = 1 nF Shutdown propagation delay ENABLE tEN - 780 1100 VEN=0 Shutdown propagation delay ITRIP tITRIP 400 670 1000 VITRIP=1 V Input filter time ITRIP tITRIPMIN 155 230 380 Propagation delay ITRIP to FAULT tFLT - 420 700 Input filter time at LIN/HIN for turn on and off tFILIN tFILEN Input filter time EN 120 300 - 300 600 - Fault clear time at RCIN after ITRIP-fault, (CRCin=1nF) tFLTCLR 1.0 1.9 3.0 ms VLIN/HIN = 0 & 3.3 V VITRIP = 0 Dead time DT 150 310 - ns VLIN/HIN = 0 & 3.3 V Matching delay ON, max(ton)-min(ton), ton are applicable to all 6 driver outputs MTON - 20 100 external dead time > 500 ns Matching delay OFF, max(toff)-min(toff), toff MTOFF are applicable to all 6 driver outputs Output pulse width 6EDL04I06NC PM 6EDL04I06PC matching. Pwin-PW out 6ED003L06-C2 6EDL04N06PC - 40 100 external dead time >500 ns 40 100 PW in > 1 µs 10 100 datasheet 20 VLIN/HIN = 0 & 3.3 V <Revision 2.5>, 20.04.2015 EiceDRIVER(tm) Compact 6ED family - 2nd generation chip product Quality disclaimer 5 The described properties and parameters must be confirmed by specific qualification in the final system. The results of the qualification must be open to Infineon. Otherwise Infineon does not give any design release or warranty. It is the responsibility of the customer to select the suitable set of materials and the manufacturing processes for the final system, which complies to his requirements in respect of life time. We recommend to avoid in particular: during die separation - unwanted mechanical stress on the wafer, wear out of the cutting blade or any other cutter misconfiguration possibly causing cracks, chipping and/or delamination of the passivation; during/after die attachment – die attach delamination causing possibly unwanted high thermal resistance, unwanted mechanical stress, or reduced electrical conductivity; during/after die attachment – die attach voids causing possibly unwanted high thermal resistance, unwanted mechanical stress, or reduced electrical conductivity; during/after die attachment – unwanted ion migration possibly causing unwanted leakage or electrical modification of the device; during/after die attachment – unwanted ion migration causing possibly unwanted leakage or unwanted electrical modification of the device; during/after die attachment – unwanted increase of thermal conductivity possibly causing unwanted overheating of the device; during electrical interconnect, in particular wire bonding – mechanical overstress possibly causing sheared wires and/or damaged pads; during electrical interconnect, in particular wire bonding – lacking bond integrity, in particular non sticking interconnects on pads possibly causing unwanted misfunction of the device and/or unwanted leakages; during encapsulation of the device – unwanted shrink or extension of the mould compound possibly causing corrosion; during encapsulation of the device – unwanted ion migration causing unwanted leakage or unwanted electrical modification of the device; during encapsulation of the device – unsuitable mould, unsuitable moulding processes possibly causing potentially wire sweep of electrical interconnects; during encapsulation of the device – sharp moudl filler components possibly causing penetration of the passivation, hence unwanted environmental influences like corrosion or ion migration etc. during encapsulation of the device – unsuitable mould with unsuitable thermal conductivity possibly causing overheating of the device, resulting in damage of single or multiple transistors/diodes causing non functionality of the device, uncluding unwanted leakages; during encapsulation of the device – unwanted low creepage distances, possibly bringing about the risk of high voltage avalanche breakthroughs; during encapsulation of the device – unsuitable mould and/or mouldling processes possibly causing delamination, resulting in overheating, leackages, shorts, open accessible voltage carrying parts, shortend lifetime etc. during encapsulation of the device – unsuitable thermal behaviour of encapsulation (expansion/shrinking, state change) possibly resulting in overheating, sheared wire, openly accessible voltage carrying parts. datasheet 21 <Revision 2.5>, 20.04.2015 EiceDRIVER(tm) Compact 6ED family - 2nd generation chip product Timing diagrams 6 tFILIN tFILIN tIN HIN/LIN HIN/LIN tIN tIN < tFILIN tIN < tFILIN high HO/LO low HO/LO HIN/LIN tIN HIN/LIN tIN tIN > tFILIN tIN > tFILIN HO/LO Figure 9 HO/LO Timing of short pulse suppression (6EDL04I06NC, 6ED003L06-C2) tFILIN HIN/LIN tFILIN tIN tIN HIN/LIN tIN < tFILIN tIN < tFILIN high HO/LO HIN/LIN HO/LO low tIN HIN/LIN tIN tIN > tFILIN tIN > tFILIN HO/LO HO/LO Figure 10 Timing of short pulse suppression (6EDL04I06PC, 6EDL04N06PC) LIN1,2,3 1.65V 1.65V HIN1,2,3 12V HO1,2,3 3V DT DT 12 V LO1,2,3 3V Figure 11 datasheet Timing of of internal deadtime (input logic according to Table 1) 22 <Revision 2.5>, 20.04.2015 EiceDRIVER(tm) Compact 6ED family - 2nd generation chip product EN tEN HO1,2,3 LO1,2,3 Figure 12 3V Enable delay time definition PWIN LIN1,2,3 1.65V 1.65V HIN1,2,3 ton toff tr 12V tf 12V HO1,2,3 LO1,2,3 3V Figure 13 3V PWOUT Input to output propagation delay times and switching times definition (6EDL04I06NC, 6ED003L06-C2) PWIN LIN1,2,3 1.65V 1.65V HIN1,2,3 ton toff tr 12V tf 12V HO1,2,3 LO1,2,3 3V Figure 14 3V PWOUT Input to output propagation delay times and switching times definition (6EDL04I06PC, 6EDL04N06PC) 20 V 17.5 VCCMAX , VBSMAX vCC vBS 13 VCCUV+, VBSUV+ 11.7 VCCUV-, VBSUV- 9.8 t IC STATE OFF Figure 15 datasheet ON ON Recommended Area ON Forbidden Area ON ON Recommended Area ON OFF Operating areas (6EDL04I06NC, 6EDL04I06PC, 6ED003L06-C2) 23 <Revision 2.5>, 20.04.2015 EiceDRIVER(tm) Compact 6ED family - 2nd generation chip product 20 V 17.5 VCCMAX , VBSMAX vCC vBS 10.0 VCCUV+, VBSUV+ 9.0 VCCUV-, VBSUV- 8.1 t IC STATE OFF Figure 16 ON ON Recommended Area ON Forbidden Area ON ON Recommended Area ON OFF Operating Areas (6EDL04N06PC) VRCIN,TH RCIN ITRIP 0.1V 0.1V FAULT 1V 0.5V tFLT tFLTCLR Any output Figure 17 datasheet 3V tITRIP ITRIP-Timing 24 <Revision 2.5>, 20.04.2015 w w w . i n f i n e o n . c o m Published by Infineon Technologies AG