Qualpack TSS463 / TSS461C TSS463 VAN Van Controller Serial Interface TSS461C VAN Van Controller TSS463/TSS461C VAN Controllers 1999 January TEMIC SEMICONDUCTORS IS AN ATMEL COMPANY Rev. 2 – January 1999 1 Qualpack TS80C31X2/C32X2 1. Contents 1. Contents........................................................................................................................................................ 2 2. General Information ..................................................................................................................................... 3 3. Technology Information .............................................................................................................................. 4 3.1 W AFER PROCESS TECHNOLOGY ..................................................................................................................... 4 3.2 PRODUCT DESIGN .......................................................................................................................................... 5 3.3 PACKAGE TECHNOLOGY ................................................................................................................................. 6 3.3.1 SOIC.300 16 leads............................................................................................................................... 6 3.3.2 Other available packages .................................................................................................................... 7 3.4 TEST ............................................................................................................................................................. 7 3.5 DEVICE CROSS SECTION ................................................................................................................................ 8 3.6 W AFER PROCESS CONTROL ........................................................................................................................... 9 4. Qualification ............................................................................................................................................... 10 4.1 CHANGE PROCEDURE ................................................................................................................................... 11 4.2 QUALIFICATION FLOW ................................................................................................................................... 12 4.3 W AFER PROCESS QUALIFICATION ................................................................................................................. 13 4.4 PACKAGE QUALIFICATION ............................................................................................................................. 14 4.5 DEVICE QUALIFICATION ................................................................................................................................ 16 4.5.1 ESD and Latch-up results .................................................................................................................. 17 4.5.2 Failure Mechanisms and Corrective Actions ..................................................................................... 17 4.5.3 Qualification status............................................................................................................................. 17 4.6 OUTGOING QUALITY AND RELIABILITY ............................................................................................................ 18 4.6.1 AOQ (Average Outgoing Quality) ...................................................................................................... 18 4.6.2 EFR (Early Failure Rate).................................................................................................................... 19 4.6.3 LFR (Latent Failure Rate) .................................................................................................................. 19 5. User Information ........................................................................................................................................ 20 5.1 SOLDERING RECOMMENDATIONS .................................................................................................................. 20 5.2 DRY PACK ORDERING RULES ..................................................................................................................... 20 5.3 ESD CAUTION .............................................................................................................................................. 20 6. Environmental Information ....................................................................................................................... 21 7. Other Data ................................................................................................................................................... 22 7.1 ISO9001 APPROVAL CERTIFICATE................................................................................................................ 22 7.2 DATABOOK REFERENCE................................................................................................................................ 23 7.3 ADDRESS REFERENCE .................................................................................................................................. 23 8. Revision History......................................................................................................................................... 24 2 Rev. 2 – January 1999 Qualpack TSS463 / TSS461C 2. General Information Product Name: Function: Specific features: TSS463 / TSS461C Van Controllers Serial Interface (TSS463) Wafer process: Z86E Available plastic package types: SOIC16 (TSS463), SOIC24 (TSS461C) Locations: Process, product development Wafer plant QC responsability Assembly TEMIC Semiconductors Nantes, France TEMIC Semiconductors Nantes, France TEMIC Semiconductors Nantes, France ANAM, Korea, Philippines Probe test Final test TEMIC Semiconductors Nantes, France GATEWAY Philippines ANAM Korea Quality Assurance Reliability testing Failure analysis TEMIC Semiconductors Nantes, France TEMIC Semiconductors Nantes, France TEMIC Semiconductors Nantes, France Quality Assurance Management Nantes Signed.......................................................... Rev. 2 – January 1999 3 Qualpack TS80C31X2/C32X2 3. Technology Information 3.1 Wafer Process Technology Process type (Name): Base material: Wafer Thickness (final) Wafer diameter Number of masks Gate oxide Material Thickness Polysilicon Number of layers Thickness Metal Number of layers Layer 1 material Layer 1 thickness Layer 2 material Layer 2 thickness Passivation Material Thickness 4 CMOS (SCMOS1/2 - Z86E) Silicon Epi substrate type 475um 150mm 13 Silicon dioxide 195 A 1 3000 A 2 TiN/W 600 + 5000 A Ti/AlCu 7000 A Si3N4 on SiO2 10000 A Rev. 2 – January 1999 Qualpack TSS463 / TSS461C 3.2 Product Design Die size (TSS463) Die size (TSS461C) Logic Effective channel length Gate poly width Gate poly spacing 11.15mm2 (3610µm*3280µm) 8.46mm2 (3480µm*2610µm) 0.8µm 0.8µm 1.2µm Metal 1 width Metal 1 spacing Metal 2 width Metal 2 spacing 1.3um 1.5um 1.6um 1.6um Contact size 1.0µm Via size 1.4µm Rev. 2 – January 1999 5 Qualpack TS80C31X2/C32X2 3.3 Package Technology 3.3.1 SOIC.300 16 leads Package weight Chip separation method Lead frame Material Thickness Size Lead plating Die attach Material Type Wire bonding Material Diameter Method Molding Material Flammability rating Marking Method Coding example Dry packing Tube packed Primary Material Number per unit Secondary Material Number per unit Labelling (minimum) Bar coding 6 0,43 g Sawing Cu 10 mils 270*270 mils2 Electroplated Sn/Pb 85/15 Silver epoxy Ablestick 84-1 LMISR4 Gold 33um Thermosonic Nitto MP8000AN UL94V-0 Printed ink TEMIC optional special customer marking TSS463 YY MM No Tube Antistatic PVC 47 Box Cardboard 1692 Device type, Quantity, Date Code, Prod. code Code 39 to EIA-556-A Rev. 2 – January 1999 Qualpack TSS463 / TSS461C Tape packed Primary Material Number per unit Secondary Material Number per unit Labelling (minimum) Bar coding Tape Antistatic PVC 31 Box Cardboard 1116 Device type, Quantity, Date Code, Prod. code Code 39 to EIA-556-A 3.3.2 Other available packages No other package available Dry packing SOIC 16 SOIC 24 No No 3.4 Test Probe equipement Probe temperature Sentry 15 125°C Test equipement Test temperature Sentry 15 25°C, 125°C(sampling) Rev. 2 – January 1999 7 Qualpack TS80C31X2/C32X2 3.5 Device Cross Section N N N N NMOS P P P P PMOS N- Epi Substrate Thin Oxide Polysilicon 8 Planararization Transversal Isolation Oxide Passivation Metal 1 Metal 2 Rev. 2 – January 1999 Qualpack TSS463 / TSS461C 3.6 Wafer Process Control All the inspections and controls are defined as a process step in the production management software, and are led by using a centralized SPC software. PC system could be summarized as follows: Engineering Database - NANTES : hermetic packages - NANTES : hermetic packages - Subcontractors : plastic packages - S ubcontractors : plastic packages Physical Critical process parameters are identified by using F.M.E.A. and other advanced tools. Those parameters are followed in real time with the SPC methodology and their capability is measured and monthly reported in the Operation Review. For end 1997, the Cpk target is the following : all parameters with Cpk above 1.67 % of all Parameters per Cpk categories 100% 80% >2 60% <2 40% <1.67 20% 0% 1995 Rev. 2 – January 1999 1996 Q1Q2 97 Q3Q4 97 Obj. 98 9 Qualpack TS80C31X2/C32X2 4. Qualification Product Qualification Wafer Process Package Device Type (Design) Qualification Qualification Qualification All product qualifications are split into three distinct steps as shown above. This same procedure is also used to qualify a change. Before a product is released for use, it must have been manufactured using a qualified wafer and package process. Before a device is released for production processing, it must also have successfully completed its required specific qualification. The standard tests which are used for this procedure are shown in the section "Qualification Flow" 10 Rev. 2 – January 1999 Qualpack TSS463 / TSS461C 4.1 Change Procedure All changes are controlled by ECN (Engineering Change Notice). All major changes are notified to those customers using products which are affected by the change. A major change is defined as a change which affects the electrical and/or mechanical specification as defined in the datasheet or which affects the following parameters as defined hereafter: 1 1-1 1-2 1-3 1-4 1-5 1-6 1-7 General Major Changes Manufacturing line Sequence of fabrication process cycle Material Electrical parameter Dimension Pad location Die size 2 2-1 2-2 2-3 2-4 2-5 Changes specific to wafer fabrication area Doping process Gate oxide formation method Equipement change Layer thickness Module dimensions 3 3-1 3-2 3-3 3-4 3-5 Changes specific to to assembly process area Sawing process Die attach process Wire interconnect method Molding process Tinning process 4 4-1 4-2 4-3 4-4 Changes specific to test area Specification limit Test coverage reduction Product identification Final conditioning Rev. 2 – January 1999 11 Qualpack TS80C31X2/C32X2 4.2 Qualification Flow General Requirements for Plastic packaged CMOS IC 12 Standard Test Description Qualification type (acceptance) MIL-STD 883D Method 1005 Electrical Life Test (Early Failure Rate) 12 hours 150°C (Tj) 5.75V Device (1/2000 12h) MIL-STD 883D Method 1005 Electrical Life Test (Latent Failure Rate) 1000 hours 150°C 5.75V Dynamic or Static Device (0/116 500h) MIL-STD 883D Method 3015.7 Electrostatic Discharge HBM +/-2000v 1.5kOhm/100pF/3 pulses Device (0/3 per level) JEDEC 17 Latch up 50mW power injection 125°C Device (0/10) MHS PAQA0046 PROM Dataretention High Temperature Storage 165°C Device (0/45 500h) MIL-STD 883D Method 1010 Temperature Cycling 1000 cycles -65°C/150°C air/air Device and Package (0/45 500c) MHS PAQA0184 Pressure Pot after Mounting Stress 168 hours 130°C/85%RH Device and Package (0/45 168h) EIA JESD22-A101 85/85 Humidity Test 1000 hours 85°C/85%RH Die and Package (0/45 500h) EIA JESD22-A110 HAST 336 hours 130°C/85%RH/5.5V Device and Package (0/45 168h) EIA JESD22-A112 Resistance to Soldering Heat Infra Red Stress 220°C/25s/3 times Package (0/10 per class) MIL-STD 883D Method 2003 Solderability Package (0/3) MIL-STD 883D Method 2015 Marking Permanency Package (0/3) Rev. 2 – January 1999 Qualpack TSS463 / TSS461C 4.3 Wafer Process Qualification This section summarizes the global 1998 reliability results of the products manufactured with the same technology as the VAN TSS463 and TSS461C (Z86 processes). Wafer Process Z86 Z86 Device Types Test Description Microcontrollers and dedicated EFR Dynamic Life Test 12h 3/22888 LFR Dynamic Life Test 500h 1000h 12h 1/1155 Memory, Asic, EFR Dynamic Life Test LFR Dynamic Life Test Z86 TSS463 EFR Dynamic Life Test LFR Dynamic Life Test Z86 TSS461C EFR Dynamic Life Test LFR Dynamic Life Test Failure mechanisms Global All products EFR Dynamic Life Test LFR Life Test Rev. 2 – January 1999 Step 500h 1000h 12h 500h 1000h 12h 500h 1000h All Result Comment 1/5209 1/685 Estimated 65 ppm 3.9 fit Estimated 49 ppm 2.9 fit 50% 17% 17% 17% Poly silicide defect metal resistor shift bonding 12h 4/28097 165 ppm (20mm2) 500h 1000h 2/1840 10 fit (20mm2) 13 Qualpack TS80C31X2/C32X2 4.4 Package Qualification This section presents TSS463 and TSS461C package qualification results, including additional measurements intending to fulfil Q100 Automotive Standard requirements. Lot Number Z21538F Device Type Test Description Step TSS463 in SO 16 (1) Thermal Cycles 1000c 2000c 1000h 2000h Level 1 Level 3 168h 0/45 0/45 0/45 0/45 1/10 0/10 0/45 500c 1000c 500h 1000h 168h SAM 500h 1000h Visual 0/45 0/45 (3) 0/45 0/45 (3) 0/45 (3) 0/10 0/45 0/45 0/5 85/85 Humidity Z21997A TSS463 in SO 16 (2) Resistance to Soldeting Heat HAST after Soldering Stress (with 5.5v bias) Thermal Cycles 85/85 Humidity HAST after Soldering Stress 165c HT Storage Physical Dimensions Bonding Destructive Tests (4) Resistance to Soldeting Heat W28184C 29C461B in SO 24 (1) Thermal Cycles 85/85 Humidity Z04948C TSS461C HAST after Soldering Stress Thermal Cycles 85/85 Humidity HAST after Soldering Stress HAST 5.5V 14 Result Comment 1 die top delamination WP 0/30 (5) AVG=77.3 STD=8.9 CPK=1.8 0/30 MAX=98.9 MIN=61.1 AVG=17.4 STD=1.5 CPK=2.3 BS MAX=21.1 MIN=14.3 0/10 Level 1 0/10 Level 2 0/10 Level 5 500c 0/45 1000c 0/45 500h 0/45 1000h 0/45 168h 0/45 500c 1000c 500h 1000h 168h 0/45 0/45 0/45 0/45 0/45 168h 336h 0/45 0/45 Rev. 2 – January 1999 Qualpack TSS463 / TSS461C Lot Number Z20569K Device Type Test Description Step HMT-65664A in SO 28 (2) Thermal Cycles 500c 1000c 500h 1000h 2000h Level 1 0/45 0/45 0/45 0/45 0/45 0/10 - 0/3 HAST after Soldering Stress (with 5.5v bias) 168h 0/45 Mounting Stress level 1 Elect. 0/255 0 ppm 85/85 Humidity Resistance to Soldeting Heat Marking Permanency Global All products Climatic Tests - Result Comment 0/720 0 % Notes: (1) (2) (3) (4) (5) SUMITOMO 6300 molding compound NITTO MP8000 molding compound Electrical test with Quality program at 25°c, 125°c and -40°c Performed on molded device opened using acid No Lifted Ball Bond, breakdown observed on wires (83%) and over the stich (17%) Rev. 2 – January 1999 15 Qualpack TS80C31X2/C32X2 4.5 Device Qualification This section presents TSS463 and TSS461C device qualification results, including additional measurements intending to fulfil Q100 Automotive Standard requirements. Lot Number Device Type Test Description Z21538F TSS463 in SO 16 EFR Dynamic Life Test Step Resul Comment t 12h LFR Dynamic Life Test Z21997 TSS463 in SO 16 W28184C 29C461B in SO 24 500h 1000h EFR Dynamic Life Test 12h 48h LFR Dynamic Life Test 500h 1000h EFR Dynamic Life Test 12h 0/261 0/116 0/116 0/800 0/304 0/45 0/45 (6) 0/298 LFR Dynamic Life Test Z04948C Global TSS461C in SO 24 All products 500h 0/72 1000h 0/72 EFR Dynamic Life Test 12h 0/296 LFR Dynamic Life Test 500h 1000h EFR Dynamic Life Test 12h LFR Dynamic Life Test 0/78 0/78 0/1655 0 ppm measured 500h 0/311 18 fit measured 1000h 0/311 Notes: (6) 16 Electrical test with Quality program at 25°c, 125°c and -40°c Rev. 2 – January 1999 Qualpack TSS463 / TSS461C 4.5.1 ESD and Latch-up results Lot Number Device Type Test Description Step Resul Comment t Z21538B TSS463 SO 16 3000v 4000v 4500v 5000v 1500v 0/10 1/13 0/4 3/13 0/10 10v 0/10 50mW 0/10 3000v 4000v 1500v 0/5 3/3 0/4 10v 0/10 50mW 0/10 ESD HBM model ESD CDM model Latch up Vcc overstress Z19814 TSS461C DIL 24.3 LU power injection ESD HBM model ESD CDM model TSS461C Latch up Vcc overstress CLASS 2 Leackage pin 6 Leackages pin 2,6,15 CLASS C6 (EOS/ESD of association) CLASS 2 Leakages CLASS C6 LU power injection 4.5.2 Failure Mechanisms and Corrective Actions Failure Mechanism Root Cause Corrective Action Date Effect Check of Efficiency Poly silicide defects Process conditions Nov 97 Robusteness improved EFR monitoring Die top delamination Sumitomo630 0 molding compound Reduce silicide temperature, increase duration Move to Nitto MP8000 Jan 98 No more moitures sensitivity pass level 1 of JESD 22 A112 4.5.3 Qualification status The Wafer Process and the assembly are qualified and controlled by regular monitoring. The TSS461C VAN is full qualified since 1996 July. The TSS463 VAN is full qualified since 1997 October. Additional measurements done in 1998 and generic results demonstrate compliance of the two products to Q100 Automotive Standard. Rev. 2 – January 1999 17 Qualpack TS80C31X2/C32X2 Outgoing Quality and Reliability 4.5.4 AOQ (Average Outgoing Quality) The AOQ is measured following 100% test by sampling outgoing product. The results of this inspection are recorded in ppm (parts per million) using the method defined in JEDEC 16. The figures below cover the last years for both the subject and structurally similar products. 200 ppm 150 100 50 0 1991 1993 1992 1995 1994 1997 1996 1998 (Obj) Year 18 Rev. 2 – January 1999 Qualpack TSS463 / TSS461C 4.5.5 EFR (Early Failure Rate) The EFR is measured on a sample of devices by operating them at an elevated temperature and measuring the number which fails to meet specification after 12 hours at 150°C. The figure is expressed in terms of ppm. 1000 800 ppm 600 400 200 0 1991 1992 1993 1994 1995 1996 1997 1998 (Obj) Year 4.5.6 LFR (Latent Failure Rate) The LFR is measured by operating devices at elevated temperatures for 1000 hours and measuring the failure rate. Using the Arrhenius law, the expected failure rate at a operating temperature of 55°C is calculated using an activation Energy of 0.6 eV with a confidence level of 60%. This is expressed in units per billion hours (FIT). 100 80 FIT 60 40 20 0 1991 1992 1993 1994 1995 1996 1997 1998 (Obj) Year Rev. 2 – January 1999 19 Qualpack TS80C31X2/C32X2 5. User Information 5.1 Soldering Recommendations For DRY PACKED products, TEMIC recommends to strictly follow the procedure described hereunder: - Dry packed products must not be stored more than 1 year at 40°c - 90%rh (worst storage conditions assumed) - A longer storage period is allowed taking into account the following conditions: 5 years max at 25°c (+/-5°c) - 50%rh - From opening of the packs, the product must be assembled within 48 hours. (worst in-process storage condition assumed: 30°c - 60%rh) - If they cannot be soldered within this time period, then the pieces must be dryed at 125°c for 24 hours. Only one drying is allowed. - Max relative humidity allowed in the bag is 20% (readable on the indicator inside the bag). If this value is reached, then the parts must be dryed at 125°C for 24 hours before mounting. - For high sensitive products, the delay between pack opening and assembly is reduced to 6 hours (Level 6 of JEDEC 22-A112). In this case, a warning printed on each pack advises the user of this restriction . 5.2 DRY PACK Ordering rules TEMIC qualification procedure allows to classify products according to JEDEC 22-A112 and to determine the convenient conditioning for safe customer use. Nevertheless, even if the product is not classified as moisture sensitive, it is possible (for example if storage conditions are not properly controlled) to order product with a Dry Pack. In this case the product name suffix will be ":D" or ":xD". 5.3 ESD caution The user must protect components against EOS and ESD damages by grounding personal and workstations. 20 Rev. 2 – January 1999 Qualpack TSS463 / TSS461C 6. Environmental Information The TEMIC Environmental Policy aims at: - Reducing the use of harmful chemicals in its processes - Reducing the content of harmful materials in its products - Using re-cyclable materials wherever possible - Reducing the energy content of its products As part of that plan, Ozone Depleting Chemicals are being replaced either by TEMIC / MHS or its subcontractor's processes. Rev. 2 – January 1999 21 Qualpack TS80C31X2/C32X2 7. Other Data 7.1 ISO9001 Approval Certificate 22 Rev. 2 – January 1999 Qualpack TSS463 / TSS461C 7.2 Databook Reference Direct access on the web to datasheet at: http://www.temic-semi.com Select: Products Automotive ICs Multiplex ICs 7.3 Address Reference All enquiries relating to this document should be addressed to the following: TEMIC Semiconductors BP70602 44306 Nantes Cedex 3 France Telephone (33) 2 40 18 18 18 Telefax (33) 2 40 18 19 20 Or direct contact same address Pascal LECUYER Quality Engineer Telephone (33) 2 40 18 17 73 Telefax (33) 2 40 18 19 00 Rev. 2 – January 1999 23 Qualpack TS80C31X2/C32X2 8. Revision History Issue Modification Notice Application Date 0 TSS463 VAN Qualification Report 1997 October 1 Qualpack TSS463 Van 1998 February 2 Qualpack TSS463 and TSS461C VAN CONTROLLERS 1999 January Remarks: The information given in this document is believed to be accurate and reliable. However, no responsibility is assumed by TEMIC for its use. No specific guarantee or warranty is implied or given by this data unless agreed in writing elsewhere. TEMIC reserve the right to update or modify this information without notification , at any time, in the interest of providing the latest information. Parts of this publication may be reproduced without special permission on the condition that our author and source are quoted and that two copies of such extracts are placed at our disposal after publication. Before use of such reproduced material the user should check that the information is current. Written permission must be obtained from the publisher for complete reprints or translations. 24 Rev. 2 – January 1999