Philips Semiconductors Product specification P-channel enhancement mode MOS transistor FEATURES BSH202 SYMBOL • Low threshold voltage • Fast switching • Logic level compatible • Subminiature surface mount package QUICK REFERENCE DATA VDS = -30 V s ID = -0.52 A g RDS(ON) ≤ 0.9 Ω (VGS = -10 V) d GENERAL DESCRIPTION P-channel, enhancement mode, logic level, field-effect power transistor. This device has low threshold voltage and extremely fast switching making it ideal for battery powered applications and high speed digital interfacing. PINNING SOT23 PIN DESCRIPTION 1 gate 2 source 3 drain 3 Top view The BSH202 is supplied in the SOT23 subminiature surface mounting package. 1 2 LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER CONDITIONS VDS VDGR VGS ID Drain-source voltage Drain-gate voltage Gate-source voltage Drain current (DC) RGS = 20 kΩ IDM Ptot Drain current (pulse peak value) Total power dissipation Tstg, Tj Storage & operating temperature Ta = 25 ˚C Ta = 100 ˚C Ta = 25 ˚C Ta = 25 ˚C Ta = 100 ˚C MIN. MAX. UNIT - 55 -30 -30 ± 20 -0.52 -0.33 -2.1 0.417 0.17 150 V V V A A A W W ˚C THERMAL RESISTANCES SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT Rth j-a Thermal resistance junction to ambient FR4 board, minimum footprint 300 - K/W August 1998 1 Rev 1.000 Philips Semiconductors Product specification P-channel enhancement mode MOS transistor BSH202 ELECTRICAL CHARACTERISTICS Tj= 25˚C unless otherwise specified SYMBOL PARAMETER V(BR)DSS VGS(TO) Drain-source breakdown voltage Gate threshold voltage CONDITIONS MIN. VGS = 0 V; ID = -10 µA VDS = VGS; ID = -1 mA Tj = 150˚C RDS(ON) gfs IGSS IDSS Drain-source on-state resistance VGS = -10 V; ID = -280 mA VGS = -4.5 V; ID = -140 mA VGS = -10 V; ID = -280 mA; Tj = 150˚C Forward transconductance VDS = -24 V; ID = -280 mA Gate source leakage current VGS = ±20 V; VDS = 0 V Zero gate voltage drain VDS = -24 V; VGS = 0 V; current Tj = 150˚C TYP. MAX. UNIT -30 - - V -1 -0.4 0.2 - -1.9 0.63 0.89 0.95 0.7 ±10 -50 -0.4 0.9 1.35 1.35 ±100 -100 -10 V V Ω Ω Ω S nA nA µA Qg(tot) Qgs Qgd Total gate charge Gate-source charge Gate-drain (Miller) charge ID = -0.3 A; VDD = -15 V; VGS = -10 V - 2.9 0.4 0.5 - nC nC nC td on tr td off tf Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time VDD = -15 V; ID = -0.5 A; VGS = -10 V; RG = 6 Ω Resistive load - 2 4.5 45 20 - ns ns ns ns Ciss Coss Crss Input capacitance Output capacitance Feedback capacitance VGS = 0 V; VDS = -24 V; f = 1 MHz - 80 27 9 - pF pF pF MIN. TYP. MAX. UNIT REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS Tj = 25˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS IDR Ta = 25 ˚C - - -0.56 A IDRM VSD Continuous reverse drain current Pulsed reverse drain current Diode forward voltage IF = -0.5 A; VGS = 0 V - -0.87 -2.2 -1.3 A V trr Qrr Reverse recovery time Reverse recovery charge IF = -0.5 A; -dIF/dt = 100 A/µs; VGS = 0 V; VR = -24 V - 30 28 - ns nC August 1998 2 Rev 1.000 Philips Semiconductors Product specification P-channel enhancement mode MOS transistor BSH202 Normalised Power Dissipation, PD (%) Peak Pulsed Drain Current, IDM (A) 120 1000 100 D = 0.5 100 0.2 80 0.1 60 0.05 0.02 single pulse 10 40 P D tp D = tp/T 1 20 T 0 0 25 50 75 100 125 0.1 1E-06 150 1E-05 1E-04 Ambient Temperature, Ta (C) 1E-03 1E-02 1E-01 1E+00 1E+01 Pulse width, tp (s) Fig.1. Normalised power dissipation. PD% = 100⋅PD/PD 25 ˚C = f(Ta) Fig.4. Transient thermal impedance. Zth j-a = f(t); parameter D = tp/T Normalised Drain Current, ID (%) BSH202 Drain current, ID (A) 120 -1.4 100 -1.2 -4.5 V Tj = 25 C VGS = -10 V -3.5 V -1 80 -3.3 V -0.8 60 40 -3.1 V -0.6 -2.9 V -0.4 -2.7 V -2.5 V 20 -0.2 0 0 25 50 75 100 125 0 150 0 Ambient Temperature, Ta (C) Fig.2. Normalised continuous drain current. ID% = 100⋅ID/ID 25 ˚C = f(Ta); conditions: VGS ≤ -10 V -0.5 -1 -1.5 Drain-Source Voltage, VDS (V) Fig.5. Typical output characteristics, Tj = 25 ˚C. ID = f(VDS); parameter VGS Drain-Source On Resistance, RDS(on) (Ohms) 10 Peak Pulsed Drain Current, IDM (A) 3 2.8 2.6 2.4 2.2 2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 BSH202 tp = 10us RDS(on) = VDS/ ID 1 100 us 1 ms 10 ms 0.1 100 ms d.c. 0.01 0.001 0.1 1 10 Drain-Source Voltage, VDS (V) 100 -2.5 V -2.7 V -2.9 V BSH202 Tj = 25 C -3.1 V -3.3 V -3.5 V -4.5 V VGS = -10 V 0 Fig.3. Safe operating area. Ta = 25 ˚C ID & IDM = f(VDS); IDM single pulse; parameter tp August 1998 -2 -0.2 -0.4 -0.6 -0.8 Drain Current, ID (A) -1 -1.2 -1.4 Fig.6. Typical on-state resistance, Tj = 25 ˚C. RDS(ON) = f(ID); parameter VGS 3 Rev 1.000 Philips Semiconductors Product specification P-channel enhancement mode MOS transistor Drain Current, ID (A) BSH202 BSH202 Threshold Voltage, VGS(to), (V) -2 -1.8 1.8 VDS > ID X RDS(on) typical 1.6 -1.6 Tj = 25 C -1.4 1.4 150 C -1.2 1.2 1 -1 minimum 0.8 -0.8 0.6 -0.6 0.4 -0.4 0.2 -0.2 0 0 0 0 -0.5 -1 -1.5 -2 -2.5 -3 -3.5 -4 Gate-Source Voltage, VGS (V) -4.5 -5 50 75 100 125 150 Junction Temperature, Tj (C) Fig.7. Typical transfer characteristics. ID = f(VGS) Transconductance, gfs (S) 25 -5.5 Fig.10. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS BSH202 Drain Current, ID (A) BSH202 1E-01 1.4 VDS > ID X RDS(on) 1.2 1E-02 Tj = 25 C 1 VDS = -5 V Tj = 25 C 150 C 1E-03 0.8 0.6 1E-04 0.4 1E-05 0.2 1E-06 0 1E-07 -2.5 0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 -0.9 -1 -1.1 -1.2 -1.3 -1.4 Drain Current, ID (A) Fig.8. Typical transconductance, Tj = 25 ˚C. gfs = f(ID) -1 Fig.11. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 ˚C Capacitances, Ciss, Coss, Crss (pF) Normalised Drain-Source On Resistance 2 1.9 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1 0.9 0.8 0.7 0.6 0.5 -2 -1.5 Gate-Source Voltage, VGS (V) BSH202 1000 RDS(ON) @ Tj RDS(ON) @ 25C VGS = -10 V 100 -4.5 V Ciss Coss 10 0 25 50 75 100 125 1 -0.1 150 Junction Temperature, Tj (C) Fig.9. Normalised drain-source on-state resistance. RDS(ON)/RDS(ON)25 ˚C = f(Tj) August 1998 Crss -1.0 -10.0 Drain-Source Voltage, VDS (V) -100.0 Fig.12. Typical capacitances, Ciss, Coss, Crss. C = f(VDS); conditions: VGS = 0 V; f = 1 MHz 4 Rev 1.000 Philips Semiconductors Product specification P-channel enhancement mode MOS transistor Gate-source voltage, VGS (V) BSH202 BSH202 -14 -12 -10 BSH202 Source-Drain Diode Current, IF (A) 4 VDD = 15 V RD = 50 Ohms Tj = 25 C 3.5 3 2.5 -8 2 -6 1.5 -4 1 150 C Tj = 25 C 0.5 -2 0 0 0 0 1 2 Gate charge, (nC) 3 4 1 1.5 2 Drain-Source Voltage, VSDS (V) Fig.14. Typical reverse diode current. IF = f(VSDS); conditions: VGS = 0 V; parameter Tj Fig.13. Typical turn-on gate-charge characteristics. VGS = f(QG) August 1998 0.5 5 Rev 1.000 Philips Semiconductors Product specification P-channel enhancement mode MOS transistor BSH202 MECHANICAL DATA Plastic surface mounted package; 3 leads SOT23 D E B A X HE v M A 3 Q A A1 1 2 e1 bp c w M B Lp e detail X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A mm 1.1 0.9 OUTLINE VERSION A1 max. bp c D E 0.1 0.48 0.38 0.15 0.09 3.0 2.8 1.4 1.2 e 1.9 e1 HE Lp Q v w 0.95 2.5 2.1 0.45 0.15 0.55 0.45 0.2 0.1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 97-02-28 SOT23 Fig.15. SOT23 surface mounting package. Notes 1. This product is supplied in anti-static packaging. The gate-source input must be protected against static discharge during transport or handling. 2. Refer to SMD Footprint Design and Soldering Guidelines, Data Handbook SC18. 3. Epoxy meets UL94 V0 at 1/8". August 1998 6 Rev 1.000 Philips Semiconductors Product specification P-channel enhancement mode MOS transistor BSH202 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. Philips Electronics N.V. 1998 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. August 1998 7 Rev 1.000