IRLR110, IRLU110, SiHLR110, SiHLU110 Vishay Siliconix Power MOSFET FEATURES PRODUCT SUMMARY VDS (V) • Dynamic dV/dt Rating 100 RDS(on) (Ω) VGS = 5.0 V Available • Repetitive Avalanche Rated 0.54 Qg (Max.) (nC) 6.1 • Surface Mount (IRLR110/SiHLR110) Qgs (nC) 2.0 • Straight Lead (IRLU110/SiHLU110) 3.3 • Available in Tape and Reel Qgd (nC) Configuration Single RoHS* COMPLIANT • Logic-Level Gate Drive • RDS(on) Specified at VGS = 4 V and 5 V D • Lead (Pb)-free Available DPAK (TO-252) IPAK (TO-251) DESCRIPTION Third generation Power MOSFETs from Vishay provide the designer with the best combination of fast switching, ruggedized device design, low on-resistance and cost-effectiveness. The DPAK is designed for surface mounting using vapor phase, infrared, or wave soldering techniques. The straight lead version (IRLU/SiHLU series) is for through-hole mounting applications. Power dissipation levels up to 1.5 W are possible in typical surface mount applications. G S N-Channel MOSFET ORDERING INFORMATION Package Lead (Pb)-free SnPb DPAK (TO-252) IRLR110PbF SiHLR110-E3 IRLR110 SiHLR110 DPAK (TO-252) IRLR110TRLPbFa SiHLR110TL-E3a IRLR110TRLa SiHLR110TLa DPAK (TO-252) IRLR110TRa SiHLR110Ta IPAK (TO-251) IRLU110PbF SiHLU110-E3 IRLU110 SiHLU110 Note a. See device orientation. ABSOLUTE MAXIMUM RATINGS TC = 25 °C, unless otherwise noted PARAMETER Drain-Source Voltage Gate-Source Voltage Continuous Drain Current Pulsed Drain Currenta Linear Derating Factor Linear Derating Factor (PCB Mount)e Single Pulse Avalanche Energyb Repetitive Avalanche Currenta Repetitive Avalanche Energya Maximum Power Dissipation Maximum Power Dissipation (PCB Mount)e Peak Diode Recovery dV/dtc Operating Junction and Storage Temperature Range Soldering Recommendations (Peak Temperature) SYMBOL VDS VGS VGS at 5.0 V TC = 25 °C TC = 100 °C ID IDM EAS IAR EAR TC = 25 °C TA = 25 °C PD dV/dt TJ, Tstg for 10 s LIMIT 100 ± 10 4.3 2.7 17 0.20 0.020 100 4.3 2.5 25 2.5 5.5 - 55 to + 150 260d UNIT V A W/°C mJ A mJ W V/ns °C Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. VDD = 25 V, starting TJ = 25 °C, L = 8.1 mH, RG = 25 Ω, IAS = 4.3 A (see fig. 12). c. ISD ≤ 5.6 A, dI/dt ≤ 140 A/µs, VDD ≤ VDS, TJ ≤ 150 °C. d. 1.6 mm from case. e. When mounted on 1" square PCB (FR-4 or G-10 material). * Pb containing terminations are not RoHS compliant, exemptions may apply Document Number: 91323 S-81304-Rev. A, 16-Jun-08 www.vishay.com 1 IRLR110, IRLU110, SiHLR110, SiHLU110 Vishay Siliconix THERMAL RESISTANCE RATINGS SYMBOL MIN. TYP. MAX. Maximum Junction-to-Ambient PARAMETER RthJA - - 110 Maximum Junction-to-Ambient (PCB Mount)a RthJA - - 50 Maximum Junction-to-Case (Drain) RthJC - - 5.0 UNIT °C/W Note a. When mounted on 1" square PCB (FR-4 or G-10 material). SPECIFICATIONS TJ = 25 °C, unless otherwise noted PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Static Drain-Source Breakdown Voltage VDS Temperature Coefficient VDS VGS = 0 V, ID = 250 µA 100 - - V ΔVDS/TJ Reference to 25 °C, ID = 1 mA - 0.12 - V/°C VGS(th) VDS = VGS, ID = - 250 µA 1.0 - 2.0 V Gate-Source Leakage IGSS VGS = ± 10 V - - ± 100 nA Zero Gate Voltage Drain Current IDSS VDS = 100 V, VGS = 0 V - - 25 VDS = 80 V, VGS = 0 V, TJ = 125 °C - - 250 Gate-Source Threshold Voltage Drain-Source On-State Resistance Forward Transconductance RDS(on) gfs VGS = 5.0 V ID = 2.6 Ab - - 0.54 VGS = 4.0 V Ab - - 0.76 VDS = 50 V, ID = 2.6 A 2.3 - - VGS = 0 V, VDS = 25 V, f = 1.0 MHz, see fig. 5 - 250 - - 80 - - 15 - - - 6.1 - - 2.0 ID = 2.2 µA Ω S Dynamic Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss Total Gate Charge Qg Gate-Source Charge Qgs VGS = 5.0 V ID = 5.6 A, VDS = 80 V, see fig. 6 and 13b Gate-Drain Charge Qgd - - 3.3 Turn-On Delay Time td(on) - 9.3 - - 47 - - 16 - - 17 - - 4.5 - - 7.5 - - - 4.3 - - 17 - - 2.5 Rise Time Turn-Off Delay Time Fall Time tr td(off) VDD = 50 V, ID = 5.6 A, RG = 12 Ω, RD = 8.4 Ω, see fig. 10b tf Internal Drain Inductance LD Internal Source Inductance LS Between lead, 6 mm (0.25") from package and center of die contactc D pF nC ns nH G S Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current IS Pulsed Diode Forward Currenta ISM Body Diode Voltage VSD Body Diode Reverse Recovery Time trr Body Diode Reverse Recovery Charge Qrr Forward Turn-On Time ton MOSFET symbol showing the integral reverse p - n junction diode D A G S TJ = 25 °C, IS =4.3 A, VGS = 0 Vb TJ = 25 °C, IF = 5.6 A, dI/dt = 100 A/µsb V - 100 130 ns - 0.50 0.65 µC Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD) Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. Pulse width ≤ 300 µs; duty cycle ≤ 2 %. www.vishay.com 2 Document Number: 91323 S-81304-Rev. A, 16-Jun-08 IRLR110, IRLU110, SiHLR110, SiHLU110 Vishay Siliconix TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted Fig. 1 - Typical Output Characteristics, TC = 25 °C Fig. 2 - Typical Output Characteristics, TC = 150 °C Document Number: 91323 S-81304-Rev. A, 16-Jun-08 Fig. 3 - Typical Transfer Characteristics Fig. 4 - Normalized On-Resistance vs. Temperature www.vishay.com 3 IRLR110, IRLU110, SiHLR110, SiHLU110 Vishay Siliconix Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage www.vishay.com 4 Fig. 7 - Typical Source-Drain Diode Forward Voltage Fig. 8 - Maximum Safe Operating Area Document Number: 91323 S-81304-Rev. A, 16-Jun-08 IRLR110, IRLU110, SiHLR110, SiHLU110 Vishay Siliconix VDS VGS RD D.U.T. RG + - VDD 5.0 V Pulse width ≤ 1 µs Duty factor ≤ 0.1 % Fig. 10a - Switching Time Test Circuit VDS 90 % 10 % VGS td(on) Fig. 9 - Maximum Drain Current vs. Case Temperature tr td(off) tf Fig. 10b - Switching Time Waveforms Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case Document Number: 91323 S-81304-Rev. A, 16-Jun-08 www.vishay.com 5 IRLR110, IRLU110, SiHLR110, SiHLU110 Vishay Siliconix L Vary tp to obtain required IAS VDS VDS tp VDD D.U.T RG + - I AS V DD VDS 5.0 V 0.01 Ω tp Fig. 12a - Unclamped Inductive Test Circuit IAS Fig. 12b - Unclamped Inductive Waveforms Fig. 12c - Maximum Avalanche Energy vs. Drain Current Current regulator Same type as D.U.T. 50 kΩ QG VGS 12 V 0.2 µF 0.3 µF QGS QGD + D.U.T. VG - VDS VGS 3 mA Charge IG ID Current sampling resistors Fig. 13a - Basic Gate Charge Waveform www.vishay.com 6 Fig. 13b - Gate Charge Test Circuit Document Number: 91323 S-81304-Rev. A, 16-Jun-08 IRLR110, IRLU110, SiHLR110, SiHLU110 Vishay Siliconix Peak Diode Recovery dV/dt Test Circuit + D.U.T Circuit layout considerations • Low stray inductance • Ground plane • Low leakage inductance current transformer + - - RG • • • • dV/dt controlled by RG Driver same type as D.U.T. ISD controlled by duty factor "D" D.U.T. - device under test Driver gate drive P.W. + Period D= + - VDD P.W. Period VGS = 10 V* D.U.T. ISD waveform Reverse recovery current Body diode forward current dI/dt D.U.T. VDS waveform Diode recovery dV/dt Re-applied voltage VDD Body diode forward drop Inductor current Ripple ≤ 5 % ISD * VGS = 5 V for logic level devices Fig. 14 - For N-Channel Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see http://www.vishay.com/ppg?91323. Document Number: 91323 S-81304-Rev. A, 16-Jun-08 www.vishay.com 7 Legal Disclaimer Notice Vishay Disclaimer All product specifications and data are subject to change without notice. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained herein or in any other disclosure relating to any product. Vishay disclaims any and all liability arising out of the use or application of any product described herein or of any information provided herein to the maximum extent permitted by law. The product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase, including but not limited to the warranty expressed therein, which apply to these products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay. The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications unless otherwise expressly indicated. Customers using or selling Vishay products not expressly indicated for use in such applications do so entirely at their own risk and agree to fully indemnify Vishay for any damages arising or resulting from such use or sale. Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications. Product names and markings noted herein may be trademarks of their respective owners. Document Number: 91000 Revision: 18-Jul-08 www.vishay.com 1