UG-637: ADV7280/ADV7281/ADV7282/ADV7283 Functionality and Features PDF

ADV7280/ADV7281/ADV7282/ADV7283 Hardware
Reference Manual
UG-637
One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com
ADV7280/ADV7281/ADV7282/ADV7283 Functionality and Features
OVERVIEW
This user guide provides a detailed description of the
functionality and features of the ADV7280, ADV7280-M,
ADV7281, ADV7281-M, ADV7281-MA, ADV7282,
ADV7282-M, and ADV7283 video decoders. Table 1 list the
shorthand notations used for these decoders in this user guide.
The ADV7280, ADV7280-M, ADV7281, ADV7281-M,
ADV7281-MA, ADV7282, ADV7282-M, and ADV7283
automatically detect and convert standard composite analog
baseband video signals compatible with worldwide NTSC, PAL,
and SECAM standards. These video recorders accept composite
video signals (CVBS) as well as S-Video (YC) and YPbPr video
signals, supporting a wide range of consumer and automotive video
sources. The ADV7281, ADV7281-M, ADV7281-MA,
ADV7282, ADV7282-M, and ADV7283 models can also accept
pseudo differential and true differential CVBS inputs.
The ADV728x-T models (ADV7280, ADV7281, ADV7282, and
ADV7283) convert the analog video inputs into a YCrCb 4:2:2
component video data stream that is compatible with the 8-bit
ITU-R BT.656 interface standard.
The ADV728x-M models (ADV7280-M, ADV7281-M,
ADV7281-MA, and ADV7282-M) convert the analog video
inputs into an 8-bit YcrCb 4:2:2 video stream, and that is output
over an MIPI CSI-2 interface. This MIPI CSI-2 output interface
connects to a wide range of video processors and FPGAs.
The AGC and clamp-restore circuitry allow an input video signal
peak-to-peak range to 1.0 V at the analog video input pin of the
ADV728x. Alternatively, these can be bypassed for manual
settings.
AC coupling of the input video signals provides STB protection.
On the ADV7281, ADV7281-M, ADV7282, and ADV7282-M
models, short-to-battery (STB) diagnostics can be carried out on
two input video signals.
The ADV728x is programmed via a two-wire, serial,
bidirectional port (I2C® compatible). The ADV728x supports a
number of functions including 8-bit to 6-bit down dither mode
and adaptive contrast enhancement (ACE).
The advanced interlaced-to-progressive (I2P) function allows
the ADV7280, ADV7280-M, ADV7282, ADV7282-M, and
ADV7283 to convert an interlaced video input into a
progressive video output. This function is performed without
the need for external memory. Edge adaptive technology is used
to minimize video defects on low angle lines.
The ADV728x is fabricated in a 1.8 V CMOS process. Its
monolithic CMOS construction ensures greater functionality
with lower power dissipation. The ADV728x are available in
−40°C to +85°C temperature range models. This makes the
ADV728x ideal for automotive applications.
See Table 6 for a descriptive list of these video decoder models.
Rev. A | Page 1 of 104
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ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
TABLE OF CONTENTS
Overview ............................................................................................ 1
Identification ............................................................................... 28
Revision History ............................................................................... 3
Status 1 ......................................................................................... 28
Using this Hardware Reference Guide ........................................... 4
Status 2 ......................................................................................... 28
Generic Shorthand Notations ..................................................... 4
Status 3 ......................................................................................... 28
Number Notations ........................................................................ 4
Autodetection Result ................................................................. 29
Register Access Conventions ...................................................... 4
Video Processor .............................................................................. 30
Acronyms and Abbreviations ..................................................... 4
SD Luma Path ............................................................................. 30
Field Function Descriptions........................................................ 5
SD Chroma Path ......................................................................... 30
Video Decoder Models .................................................................... 6
ACE, I2P, and Dither Processing Blocks ................................. 30
Video Input Pins Column ........................................................... 7
Sync Processing .......................................................................... 31
Differential AFE Column ............................................................ 7
VBI Data Recovery ..................................................................... 31
Output Format Column .............................................................. 7
General Setup .............................................................................. 31
Diagnostic Pins Column ............................................................. 7
Color Controls ............................................................................ 34
GPO Pins Column........................................................................ 7
Free-Run Operation ................................................................... 35
Sync Output Pins Column .......................................................... 7
Clamp Operation ........................................................................ 36
ACE Column ................................................................................. 7
Luma Filter .................................................................................. 37
I2P Column ................................................................................... 7
Chroma Filter.............................................................................. 40
Package Column ........................................................................... 7
Gain Operation ........................................................................... 41
Functional Block Diagrams......................................................... 8
Chroma Transient Improvement (CTI) .................................. 44
General Description ....................................................................... 11
Digital Noise Reduction (DNR) and Luma Peaking Filter ... 45
Overview of Analog Front End ................................................ 11
Comb Filters................................................................................ 46
Overview of Standard Definition Processor ........................... 11
IF Filter Compensation ............................................................. 48
Input Networks ............................................................................... 12
Adaptive Contrast Enhancement (ACE)................................. 49
Single-Ended Input Network .................................................... 12
Dither Function .......................................................................... 50
Differential Input Network ....................................................... 12
I2P Function ............................................................................... 50
Short-to-Battery Protection ...................................................... 13
Output Video Format..................................................................... 51
Short-to-Battery (STB) Diagnostics ............................................. 14
Swap Color output...................................................................... 51
Programming Diagnostic Slice Levels ..................................... 15
Output Format Control ............................................................. 51
Programming Diagnostic Interrupt ......................................... 16
ITU-R BT.656 Output .................................................................... 52
Programming INTRQ Hardware Interrupt ............................ 17
ITU-R BT.656 Output Control Registers ................................ 53
Analog Front End ........................................................................... 18
MIPI CSI-2 Tx Output ................................................................... 55
Input Configuration ................................................................... 18
Ultralow Power State.................................................................. 55
Manual Muxing Mode ............................................................... 21
I C Port Description ....................................................................... 57
Antialiasing Filters.......................................................................... 25
Register Maps .............................................................................. 59
Antialiasing Filter Configuration ............................................. 25
PCB Layout Recommendations.................................................... 61
Global Control Registers ............................................................... 26
Analog Interface Inputs ............................................................. 61
Power Saving Mode and Reset Control ................................... 26
Power Supply Decoupling ......................................................... 61
Global Pin Control ..................................................................... 26
VREFN and VREFP Pins .......................................................... 61
General-Purpose Output Controls .......................................... 27
Digital Outputs ........................................................................... 61
Global Status Register .................................................................... 28
Exposed Metal Pad ..................................................................... 61
2
Rev. A| Page 2 of 104
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
UG-637
Digital Inputs ...............................................................................61
Interrupt/VDP Sub Map Description ...................................... 90
MIPI Outputs (D0P, D0N, CLKP, CLKN) ...............................61
VPP Map Description ................................................................ 99
Power Supply Requirements ..........................................................62
CSI Map Description ................................................................100
I C Register Maps ............................................................................63
References ......................................................................................103
2
User Sub Map Description .........................................................70
User Sub Map 2 Description ......................................................88
REVISION HISTORY
9/14—Rev. 0 to Rev. A
Added ADV7283 (Throughout)...................................................... 1
Changes to Single-Ended Input Network Section and
Differential Input Network Section ..............................................12
Added Short-to-Battery Protection Section ................................13
Changes to Short-to-Battery (STB) Diagnostics Section ...........14
Changes to Table 9 and Table 11 ...................................................15
Added Programming Diagnostic Interrupt Section ...................16
Added Programming INTRQ Hardware Interrupt Section ......17
Changes to Table 27 ........................................................................26
Added Output Format Control Section and Table 75 ................51
Changes to Table 86 and Table 87 .................................................54
Changes to Analog Interface Inputs Section and Digital Outputs
Section ..............................................................................................61
Added Register 0x53 to Register 0x55; Table 106 .......................94
Changes to Register 0x5B; Table 107 ............................................99
5/14—Revision 0: Initial Version
Rev. A | Page 3 of 104
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ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
USING THIS HARDWARE REFERENCE GUIDE
GENERIC SHORTHAND NOTATIONS
REGISTER ACCESS CONVENTIONS
Table 1. Shorthand Notations
Table 3. Register Access Conventions
Notation
ADV728x
Mode
R/W
R
ADV728x-T
ADV728x-M
Description
Refers to the ADV7280, ADV7280-M, ADV7281,
ADV7281-M, ADV7281-MA, ADV7282, ADV7282-M,
and ADV7283 models
Refers to the ADV7280, ADV7281, ADV7282, and
ADV7283 models
Refers to the ADV7280-M, ADV7281-M,
ADV7281-MA, and ADV7282-M models
Table 2. Number Notations
V[X:Y]
0xNN
0bNN
NN
ACRONYMS AND ABBREVIATIONS
Table 4. Acronyms and Abbreviations
NUMBER NOTATIONS
Notation
Bit N
W
Description
Memory location has read and write access.
Memory location is read access only. A read
always returns 0 unless otherwise specified.
Memory location is write access only.
Description
Bits are numbered in little endian format, that is,
the least significant bit of a number is referred to
as Bit 0.
Bit field representation covering Bit X to Bit Y of a
value or a field (V).
Hexadecimal (Base 16) numbers are preceded by
the prefix 0x.
Binary (Base 2) numbers are preceded by the
prefix 0b.
Decimal (Base 10) are represented using no
additional prefixes or suffixes.
Acronym/
Abbreviation
AA
ACE
ADC
AFE
AGC
AIN
CMR
CVBS
AVI
DE
GPO
HS
I2P
IC
I2 C
LLC
LSB
Mbps
ms
MSB
MIPI CSI-2
NC
PLL
Rx
SAV
SFL
SHA
SNR
STB
TTL
Tx
VBI
VS
XTAL
Rev. A | Page 4 of 104
Description
Anti-alias
Adaptive contrast enhancement
Analog-to-digital converter
Analog front end
Automatic gain control
Analog video input pin
Common-mode rejection
Composite video baseband signal
Auxiliary video information
Data enable
General-purpose output
Horizontal synchronization
Interlaced-to-progressive converter (that is,
deinterlacer)
Integrated circuit
Inter integrated circuit
Line locked clock
Least significant bit
Megabits per second
Millisecond
Most significant bit
Mobile industry processor interface camera
serial interface, version 2
No connect
Phase-locked loop
Receiver
Start of active video
Color subcarrier frequency lock
Sample-and-hold
Signal-to-noise ratio
Short-to-battery
Transistor-to-transistor level
Transmitter
Vertical blanking interval
Vertical synchronization
Crystal oscillator
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
UG-637
FIELD FUNCTION DESCRIPTIONS
In this example
Throughout this reference manual, a series of function tables
are provided. The function of a field is described in a table
preceded by the bit name, a short function description, the I2C
map, the register location within the I2C map, and a detailed
description of the field.
•
The name of the field is DIAG1_SLICE_LEVEL and it is
three bits long.
•
User Sub Map indicates which I2C map or sub map the
field is located in.
•
Address 0x5D is the I2C location of the field within the I2C
Map or Sub Map. The address is stated in a big endian
format (MSB first, LSB last).
•
The address is followed by a description of the field.
•
The first column of the table lists values the field can take
or can be set to. These values are in binary format if not
preceded by 0x or in hexadecimal format if preceded by 0x.
•
The second column of the table describes the operation of
the field (such as DIAG1_SLICE_LEVEL) for each value
the field can be set to.
The detailed description consists of:
•
•
the values the field can take (for a readable field)
the values the field can be set to (for a writable field)
Example Field Function Description
This section provides an example of a field function table
followed by a description of each part of the table.
DIAG1_SLICE_LEVEL[2:0], User Sub Map,
Address 0x5D[4:2]
The DIAG1_SLICE_LEVEL[2:0] bits allow the user to set the
diagnostic slice level for the DIAG1 pin.
Table 5. DIAG1_SLICE_LEVEL[2:0] Settings
DIAG1_SLICE_LEVEL[2:0]
000
001
010
011 (default)
100
101
110
111
Diagnostic Slice Level
75 mV
225 mV
375 mV
525 mV
675 mV
825 mV
975 mV
1.125 V
Rev. A | Page 5 of 104
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ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
VIDEO DECODER MODELS
Table 6 lists the Analog Devices, Inc., video decoders described in this reference manual. Select columns are described in full in the
sections that follow.
Table 6. Description of ADV728x Models
Model
Number
ADV7280
Generic
Shorthand
Notation
ADV728x-T
Video
Input
Pins
4
Differential
AFE
No
Output
Format
TTL
Diagnostic
Pins
No
GPO
Pins
No
Sync
Output
Pins
Yes (2)
ACE
Yes
I2P
Yes
ADV7281
ADV728x-T
4
Yes
TTL
Yes (2)
No
No
Yes
No
ADV7282
ADV728x-T
4
Yes
TTL
Yes (2)
No
No
Yes
Yes
ADV7283
ADV728x-T
6
Yes
TTL
No
No
No
Yes
Yes
ADV7280-M
ADV728x-M
8
No
MIPI CSI-2
No
Yes (3)
No
Yes
Yes
ADV7281-M
ADV728x-M
6
Yes
MIPI CSI-2
Yes (2)
Yes (3)
No
Yes
No
ADV7281-MA
ADV728x-M
8
Yes
MIPI CSI-2
No
Yes (3)
No
Yes
No
ADV7282-M
ADV728x-M
6
Yes
MIPI CSI-2
Yes (2)
Yes (3)
No
Yes
Yes
Rev. A | Page 6 of 104
Package
32-lead LFCSP,
5 mm × 5 mm
32-lead LFCSP,
5 mm × 5 mm
32-lead LFCSP,
5 mm × 5 mm
32-lead LFCSP,
5 mm × 5 mm
32-lead LFCSP,
5 mm × 5 mm
32-lead LFCSP,
5 mm × 5 mm
32-lead LFCSP,
5 mm × 5 mm
32-lead LFCSP,
5 mm × 5 mm
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
UG-637
VIDEO INPUT PINS COLUMN
DIAGNOSTIC PINS COLUMN
Indicates how many analog video inputs pins are available on
each ADV728x model.
Indicates if the ADV728x model has diagnostic pins and, if so,
how many. Diagnostic pins are used to monitor analog video
input lines for short-to-battery (STB) events.
•
One analog video input pin is required for single-ended
CVBS inputs.
•
Two analog video input pins are required for pseudo
differential and fully differential CVBS inputs.
•
Two analog video input pins are required for S-Video (YC)
inputs.
•
Three analog video input pins are required for component
(YPbPr) inputs.
DIFFERENTIAL AFE COLUMN
Indicates if the ADV728x model has a differential analog front
end (AFE). A differential AFE is needed to process pseudo
differential and fully differential CVBS inputs.
OUTPUT FORMAT COLUMN
Indicates the digital video output format output from each
ADV728x model.
•
TTL means that the ADV728x model outputs 8-bit YUV
video data over a TTL bus.
•
MIPI CSI-2 indicates that the ADV728x model outputs
8-bit YUV video data over a MIPI CSI-2 bus. This MIPI
CSI-2 bus consists of one differential data channel (D0P,
D0N) and one differential clock channel (CLKP, CLKN).
GPO PINS COLUMN
Indicates if the ADV728x model has general-purpose output
(GPO) pins and, if so, how many. GPO pins are outputs from
the ADV728x that can be used to control other external devices.
SYNC OUTPUT PINS COLUMN
Indicates if the video decoder has synchronization output pins
and, if so, how many. Examples of synchronization output pins
include horizontal synchronization (HS), vertical
synchronization(VS), and subcarrier frequency lock (SFL).
ACE COLUMN
Indicates if the ADV728x model has the ability to perform the
adaptive contrast enhancement (ACE) function.
The ACE function allows dark areas of the video to be
brightened up without saturating bright areas. This is useful for
automotive applications.
I2P COLUMN
Indicates if the ADV728x model has an in-built interlaced-toprogressive converter (I2P). This is also known as a
deinterlacer. The I2P core converts the interlaced video formats
of NTSC (480i) or PAL (576i) into progressive standards (480p,
576p).
PACKAGE COLUMN
Indicates the package in which the video decoder is available.
Rev. A | Page 7 of 104
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ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
FUNCTIONAL BLOCK DIAGRAMS
ADV7280
CLOCK PROCESSING BLOCK
XTALP
PLL
ADLLT PROCESSING
10-BIT ADC
DIGITAL
PROCESSING
BLOCK
LLC
XTALN
+
SHA
AA
FILTER
VBI SLICER
ADC
–
COLOR
DEMOD
AA
FILTER
I2P
FIFO
HS
ACE
DOWN
DITHER
I2C/CONTROL
REFERENCE
8-BIT
PIXEL DATA
P7 TO P0
INTRQ
11935-001
AIN3
AIN4
AA
FILTER
2D COMB
VS/FIELD/SFL
OUTPUT BLOCK
ANALOG VIDEO
INPUTS
MUX BLOCK
AIN1
AIN2
AA
FILTER
SCLK SDATA ALSB RESET PWRDWN
Figure 1. ADV7280 Functional Block Diagram
ADV7280-M
CLKP
CLOCK PROCESSING BLOCK
XTALP
PLL
ADLLT PROCESSING
10-BIT ADC
DIGITAL
PROCESSING
BLOCK
MIPI
Tx
XTALN
CLKN
D0P
2D COMB
+
SHA
AA
FILTER
ADC
–
VBI SLICER
COLOR
DEMOD
AA
FILTER
I2P
ACE
DOWN
DITHER
I2C/CONTROL
REFERENCE
SCLK SDATA ALSB RESET PWRDWN
Figure 2. ADV7280-M Functional Block Diagram
Rev. A | Page 8 of 104
GPO0
GPO1
GPO2
INTRQ
11935-002
AA
FILTER
OUTPUT BLOCK
AA
FILTER
MUX BLOCK
ANALOG VIDEO
INPUTS
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
FIFO
D0N
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
ADV7281
UG-637
CLOCK PROCESSING BLOCK
XTALP
PLL
ADLLT PROCESSING
10-BIT ADC
DIGITAL
PROCESSING
BLOCK
LLC
2D COMB
+
SHA
AA
FILTER
ADC
VBI SLICER
–
COLOR
DEMOD
AA
FILTER
DIAGNOSTICS
DIAG1
ACE
DOWN
DITHER
I2C/CONTROL
REFERENCE
DIAG2
8-BIT
PIXEL DATA
P7 TO P0
INTRQ
11935-003
AA
FILTER
OUTPUT BLOCK
AIN3
AIN4
AA
FILTER
MUX BLOCK
DIFFERENTIAL
OR
SINGLE-ENDED
ANALOG VIDEO
INPUTS
AIN1
AIN2
FIFO
XTALN
SCLK SDATA ALSB RESET PWRDWN
Figure 3. ADV7281 Functional Block Diagram
ADV7281-M
CLKP
CLOCK PROCESSING BLOCK
XTALP
PLL
ADLLT PROCESSING
10-BIT ADC
DIGITAL
PROCESSING
BLOCK
MIPI
Tx
XTALN
CLKN
D0P
2D COMB
+
SHA
AA
FILTER
ADC
VBI SLICER
–
COLOR
DEMOD
AA
FILTER
DIAGNOSTICS
DIAG1
ACE
DOWN
DITHER
GPO0
GPO1
GPO2
I2C/CONTROL
REFERENCE
INTRQ
11935-004
AIN5
AIN6
AA
FILTER
OUTPUT BLOCK
AIN3
AIN4
AA
FILTER
MUX BLOCK
DIFFERENTIAL
OR
SINGLE-ENDED
ANALOG VIDEO
INPUTS
AIN1
AIN2
FIFO
D0N
SCLK SDATA ALSB RESET PWRDWN
DIAG2
Figure 4. ADV7281-M Functional Block Diagram
ADV7281-MA
CLKP
CLOCK PROCESSING BLOCK
XTALP
PLL
MIPI
Tx
ADLLT PROCESSING
XTALN
CLKN
D0P
AA
FILTER
2D COMB
+
SHA
AA
FILTER
DIGITAL
PROCESSING
BLOCK
ADC
–
VBI SLICER
COLOR
DEMOD
AA
FILTER
ACE
DOWN
DITHER
I2C/CONTROL
REFERENCE
SCLK SDATA ALSB RESET PWRDWN
Figure 5. ADV7281-MA Functional Block Diagram
Rev. A | Page 9 of 104
GPO0
GPO1
GPO2
INTRQ
11935-005
MUX BLOCK
DIFFERENTIAL
OR
SINGLE-ENDED
ANALOG VIDEO
INPUTS
AA
FILTER
OUTPUT BLOCK
10-BIT ADC
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
FIFO
D0N
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ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
ADV7282
CLOCK PROCESSING BLOCK
XTALP
PLL
ADLLT PROCESSING
10-BIT ADC
DIGITAL
PROCESSING
BLOCK
LLC
AIN3
AIN4
AA
FILTER
2D COMB
+
AA
FILTER
VBI SLICER
ADC
SHA
–
COLOR
DEMOD
AA
FILTER
DIAGNOSTICS
I2P
DOWN
DITHER
I2C/CONTROL
REFERENCE
DIAG2
DIAG1
ACE
8-BIT
PIXEL DATA
P7 TO P0
INTRQ
11935-006
MUX BLOCK
DIFFERENTIAL
OR
SINGLE-ENDED
ANALOG VIDEO
INPUTS
OUTPUT BLOCK
AA
FILTER
AIN1
AIN2
FIFO
XTALN
SCLK SDATA ALSB RESET PWRDWN
Figure 6. ADV7282 Functional Block Diagram
ADV7282-M
CLKP
CLOCK PROCESSING BLOCK
XTALP
PLL
ADLLT PROCESSING
10-BIT ADC
DIGITAL
PROCESSING
BLOCK
MIPI
Tx
XTALN
CLKN
D0P
AIN5
AIN6
+
SHA
AA
FILTER
ADC
–
VBI SLICER
COLOR
DEMOD
AA
FILTER
DIAGNOSTICS
DIAG1
I2P
ACE
DOWN
DITHER
GPO0
GPO1
GPO2
INTRQ
I2C/CONTROL
REFERENCE
11935-007
AIN3
AIN4
2D COMB
AA
FILTER
OUTPUT BLOCK
MUX BLOCK
DIFFERENTIAL
OR
SINGLE-ENDED
ANALOG VIDEO
INPUTS
AA
FILTER
AIN1
AIN2
FIFO
D0N
SCLK SDATA ALSB RESET PWRDWN
DIAG2
Figure 7. ADV7282-M Functional Block Diagram
ADV7283
CLOCK PROCESSING BLOCK
LLC
XTALP
PLL
ADLLT PROCESSING
10-BIT ADC
DIGITAL
PROCESSING
BLOCK
2D COMB
+
SHA
AA
FILTER
ADC
–
VBI SLICER
COLOR
DEMOD
AA
FILTER
I2P
REFERENCE
ACE
DOWN
DITHER
I2C/CONTROL
SCLK SDATA ALSB RESET PWRDWN
NOTES
1. SHA IS A SAMPLE-AND-HOLD AMPLIFIER CIRCUIT.
Figure 8. ADV7283 Functional Block Diagram
Rev. A | Page 10 of 104
8-BIT
PIXEL DATA
P0 TO P7
INTRQ
11935-108
AIN5
AIN6
AA
FILTER
OUTPUT BLOCK
AIN3
AIN4
AA
FILTER
MUX BLOCK
DIFFERENTIAL
OR
SINGLE-ENDED
ANALOG VIDEO
INPUTS
AIN1
AIN2
FIFO
XTALN
UG-637
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
GENERAL DESCRIPTION
4.43, and SECAM B/D/G/K/L. The ADV728x can automatically
detect the video standard and process it accordingly.
OVERVIEW OF ANALOG FRONT END
The ADV728x has a five-line, adaptive, 2D comb filter that gives
superior chrominance and luminance separation when decoding
a composite video signal. This highly adaptive filter automatically
adjusts its processing mode according to the video standard and
signal quality without requiring user intervention. Video user
controls, such as brightness, contrast, saturation, and hue, are
also available with these video decoders.
The ADV728x AFE consists of a single high speed, 10-bit
analog-to-digital converter (ADC) that digitizes the analog
video signal before applying it to the standard definition
processor.
The front end also includes a four-channel input mux that
enables multiple composite video signals to be applied to the
ADV728x. Clamp restore circuitry is positioned in front of the
ADC to ensure that the video signal remains within the range of
the converter. An external resistor and capacitor circuit is
required before each analog input channel to ensure that the
input signal is kept within the range of the ADC (see the Input
Networks section). Fine clamping of the video signal is performed
downstream by digital fine clamping within the ADV728x.
The ADV728x implements a patented ADLLT™ algorithm to
track varying video line lengths from sources such as a VCR.
ADLLT enables the ADV728x to track and decode poor quality
video sources, such as VCRs and noisy sources, from tuner outputs
and camcorders. The ADV728x contains a chroma transient
improvement (CTI) processor that sharpens the edge rate of
chroma transitions, resulting in sharper vertical transitions.
Table 7 shows the three ADC clocking rates that are determined
by the video input format to be processed—that is, INSEL[4:0].
These clock rates ensure 4× oversampling per channel for
CVBS, Y/C, and YPbPr modes.
ACE offers improved visual detail using an algorithm to
automatically vary contrast levels in order to enhance picture
detail. This increases the brightness of dark regions of an image
without saturating bright areas of the image.
Table 7. ADC Clock Rates
Down dithering converts the output of the ADV728x from an
8-bit output to a 6-bit output.
Input Format
CVBS
Y/C (S-Video)
YPbPr
1
ADC Clock Rate (MHz)1
57.27
114
172
Oversampling
Rate per Channel
4×
4×
4×
Based on a 28.63636 MHz crystal between the XTAL and XTAL1 pins.
OVERVIEW OF STANDARD DEFINITION
PROCESSOR
The ADV728x is capable of decoding a large selection of baseband
video signals in composite, S-Video, and component formats.
The ADV7281, ADV7281-M, ADV7281-MA, ADV7282,
ADV7282-M, and ADV7283 are also capable of receiving
pseudo-differential and fully differential CVBS inputs. The
video standards supported by the video processor include PAL
B/D/I/G/H, PAL 60, PAL M, PAL N, PAL Nc, NTSC M/J, NTSC
The I2P block on the ADV7280, ADV7280-M, ADV7282,
ADV7282-M, and ADV7283 converts the interlaced video input
into a progressive video output. This is done without a need for
external memory.
The ADV728x can process a variety of vertical blanking interval
(VBI) data services, such as closed captioning (CCAP),
widescreen signaling (WSS), and copy generation management
systems (CGMS). VBI data is transmitted as ancillary data
packets.
The ADV728x is fully Rovi (previously Macrovision) compliant;
detection circuitry enables Type I, Type II, and Type III protection
levels to be identified and reported to the user. The decoder is
also fully robust to all Rovi signal inputs.
Rev. A | Page 11 of 104
UG-637
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
INPUT NETWORKS
An input network (external resistor and capacitor circuit)
is required on the AINx input pins of the ADV728x. The
components of the input network depend on the video format
selected for the analog input.
POSITIVE
INPUT
CONNECTOR
1.3kΩ
SINGLE-ENDED INPUT NETWORK
24Ω
100nF
EXT
ESD
R1
1.3kΩ
430Ω
100nF
AIN2
NEGATIVE
INPUT
CONNECTOR
Figure 10. Differential Input Network
Fully differential video transmission involves transmitting
two complementary CVBS signals. Pseudo differential video
transmission involves transmitting a CVBS signal and a source
ground signal.
Differential video transmission has several key advantages over
single-ended transmission, including the following:
AIN3
51Ω
11935-008
EXT
ESD
VIDEO INPUT
FROM SOURCE
11935-009
• Single-ended CVBS
• YC (S-Video)
• YPrPb
It is recommended that the input network circuit shown in
Figure 9 be placed as close as possible to the AINx pins of the
ADV728x.
VIDEO INPUT
FROM SOURCE
AIN1
430Ω
Figure 9 shows the input network to use on each AINx input pin
of the ADV728x when any of the following video input formats
are used:
INPUT
CONNECTOR
100nF
Figure 9. Single-Ended Input Network
The 24 Ω and 51 Ω resistors supply the 75 Ω end termination
required for the analog video input. These resistors also create a
resistor divider with a gain of 0.68. The resistor divider attenuates
the amplitude of the input analog video and scales the input to the
ADC range of the ADV728x. This allows an input range to the
ADV728x of up to 1.47 V peak-to-peak. Note that amplifiers
within the ADC restore the amplitude of the input signal so that
signal-to-noise ratio (SNR) performance is maintained.
The 100 nF ac coupling capacitor removes the dc bias of the
analog input video before it is fed into the AINx pin of the
ADV728x. The clamping circuitry within the ADV728x restores
the dc bias of the input signal to the optimal level before it is fed
into the ADC of the ADV728x.
The 100 nF ac coupling capacitor limits the current flow into
the ADV728x during short-to-battery (STB) events. Note that
the 24 Ω and 51 Ω resistors can be damaged during STB events
unless high power resistors are used. To avoid the need for high
power resistors, use the differential input network described in
the Differential Input Network section.
DIFFERENTIAL INPUT NETWORK
•
•
•
Inherent small signal and large signal noise rejection
Improved EMI performance
Ability to absorb ground bounce
Resistor R1 provides the RF end termination for the differential
CVBS input lines. For a pseudo differential CVBS input, R1
should have a value of 75 Ω. For a fully differential CVBS input,
R1 should have a value of 150 Ω.
The 1.3 kΩ and 430 Ω resistors create a resistor divider with a
gain of 0.25. The resistor divider attenuates the amplitude of the
input analog video, but increases the input common-mode range
to 4 V peak-to-peak. Note that amplifiers within the ADC
restore the amplitude of the input signal so that SNR
performance is maintained.
The 100 nF ac coupling capacitor removes the dc bias of the analog
input video before it is fed into the AINx pin. The clamping
circuitry within the part restores the dc bias of the input signal
to the optimal level before it is fed into the ADC of the part.
The 100 nF ac coupling capacitors limit the current flow into
the ADV7281, ADV7281-M, ADV7281-MA, ADV7282,
ADV7282-M, and ADV7283 during STB events. See the Shortto-Battery Protection section.
To achieve optimal performance, the 1.3 kΩ and 430 Ω resistors
should be closely matched; that is, all 1.3 kΩ and 430 Ω resistors
should have the same resistance tolerance, and this tolerance
should be as low as possible.
This section applies to the ADV7281, ADV7281-M,
ADV7281-MA, ADV7282, ADV7282-M, and ADV7283
models only.
Figure 10 shows the input network to use when pseudo
differential or fully differential CVBS video is input on the AINx
input pins. It is recommended that the input network circuit
shown in Figure 10 be placed as close as possible to the AINx
pins of the ADV728x.
Rev. A | Page 12 of 104
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
SHORT-TO-BATTERY PROTECTION
In differential mode, the ADV7281, ADV7281-M,
ADV7281-MA, ADV7282, ADV7282-M, and ADV7283 are
protected against short-to-battery (STB) events by the external
100 nF ac-coupling capacitors (see Figure 10). The external input
network resistors are sized to be large enough to reduce the
current flow during a STB event, but to be small enough not to
effect the operation of the ADV7281, ADV7281-M,
ADV7281-MA, ADV7282, ADV7282-M, and ADV7283.
UG-637
Choose the power rating of the input network resistors to
withstand the high voltages of STB events. Similarly, choose the
breakdown voltage of the ac-coupling capacitors to be robust to
STB events.
The R1 resistor is protected because no current or limited
current flows through it during an STB event.
In single-ended CVBS, YC, and YPbPr modes, the inputs
network resistors need to have high power ratings to be robust
to STB events
Rev. A | Page 13 of 104
UG-637
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
SHORT-TO-BATTERY (STB) DIAGNOSTICS
Short-to-battery (STB) diagnostic pins are only available on the
ADV7281, ADV7281-M, ADV7282, and ADV7282-M models.
R5
DIAG1
INPUT
CONNECTOR
R4
1.3kΩ
100nF
Resistors R4 and R5 divide down the voltage at the input
connector to protect the DIAGx pin from an STB event. The
DIAGx pin circuitry compares this voltage to a programmable
reference voltage, known as the diagnostic slice level. When the
diagnostic slice level is exceeded, an STB event has occurred.
AIN1
430Ω
EXT
ESD
R1
1.3kΩ
430Ω
100nF
INPUT
CONNECTOR
Figure 11. Diagnostic Connections
AIN2
11935-010
VIDEO INPUT
FROM SOURCE
The ADV7281/ADV7281-M/ADV7282/ADV7282-M senses
an STB event via the DIAG1 and DIAG2 pins. The DIAG1 and
DIAG2 pins can sense an STB event on either the positive or
negative differential input because of the negligible voltage drop
across Resistor R1.
When the DIAGx pin voltage exceeds the diagnostic slice level
voltage, a hardware interrupt is triggered and indicated by the
INTRQ pin. A readback register is also provided, which allows
the user to determine the DIAGx pin on which the STB event
occurred (see the Programming Diagnostic Interrupt section
for more information).
Use Equation 1 to find the trigger voltage for a selected
diagnostic slice level.
VSTB _ TRIGGER 
R5  R4
 DIAGNOSTIC _SLICE_LEV EL
R5
where:
VSTB_TRIGGER is the minimum voltage required at the input
connector to trigger the STB interrupt on the
ADV7281/ADV7281-M/ADV7282/ADV7282-M.
DIAGNOSTIC_SLICE_LEVEL is the programmable
reference voltage.
Rev. A | Page 14 of 104
(1)
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
DIAG2 Pin
DIAG2_SLICER_PWRDN, User Sub Map,
Address 0x5E[6]
PROGRAMMING DIAGNOSTIC SLICE LEVELS
DIAG1 Pin
DIAG1_SLICER_PWRDN, User Sub Map,
Address 0x5D[6]
This bit powers up or powers down the diagnostic circuitry for
the DIAG1 pin.
Table 8. DIAG1_SLICER_PWRDN Function
DIAG1_SLICER_PWRDN
0
1 (default)
Diagnostic Slice Level
Power up the diagnostic circuitry
for the DIAG1 pin.
Power down the diagnostic
circuitry for the DIAG1 pin.
DIAG1_SLICE_LEVEL[2:0], User Sub Map,
Address 0x5D[4:2]
The DIAG1_SLICE_LEVEL[2:0] bits allow the user to set the
diagnostic slice level for the DIAG1 pin. When a voltage greater
than the diagnostic slice level is seen on the DIAG1 pin, an STB
interrupt is triggered.
For the diagnostic slice level to be set correctly, the diagnostic
circuitry for the DIAG1 pin must be powered up (see Table 8).
Table 9. DIAG1_SLICE_LEVEL[2:0] Settings
DIAG1_SLICE_LEVEL[2:0]
000
001
010
011 (default)
100
101
110
111
1
Diagnostic Slice Level
75 mV1
225 mV1
375 mV1
525 mV
675 mV
825 mV
975 mV
1.125 V
UG-637
This bit powers up or powers down the diagnostic circuitry for
the DIAG2 pin.
Table 10. DIAG2_SLICER_PWRDN Function
DIAG2_SLICER_PWRDN
0
1 (default)
Diagnostic Slice Level
Power up the diagnostic circuitry
for the DIAG2 pin.
Power down the diagnostic
circuitry for the DIAG2 pin.
DIAG2_SLICE_LEVEL[2:0], User Sub Map,
Address 0x5E[4:2]
The DIAG2_SLICE_LEVEL[2:0] bits allow the user to set the
diagnostic slice level for the DIAG2 pin. When a voltage greater
than the diagnostic slice level is seen on the DIAG2 pin, an STB
interrupt is triggered.
For the diagnostic slice level to be set correctly, the diagnostic
circuitry for the DIAG2 pin must be powered up (see Table 10).
Table 11. DIAG2_SLICE_LEVEL[2:0] Settings
DIAG2_SLICE_LEVEL[2:0]
000
001
010
011 (default)
100
101
110
111
1
Diagnostic Slice Level
75 mV1
225 mV1
375 mV1
525 mV
675 mV
825 mV
975 mV
1.125 V
This setting is not recommended for the optimal performance of the
ADV728x.
This setting is not recommended for the optimal performance of the
ADV728x.
Rev. A | Page 15 of 104
UG-637
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
PROGRAMMING DIAGNOSTIC INTERRUPT
This section describes how to program software interrupt bits
to toggle when STB events are detected on the diagnostic pins.
A hardware interrupt indicated by the INTRQ pin will also
trigger when a software interrupt activates. Details on how to
control the INTRQ pin hardware interrupt are given in the
Programming INTRQ Hardwar Interrupt section.
Before programming the software diagnostic interrupts, the
diagnostic circuitry must first be activated and the diagnostic
slice level must be programmed (see Programming Diagnostic
Slice Levels section).
The diagnostic interrupts also need to be unmasked
(that is, activated) using the DIAG_TRI1_L1_MSK and
DIAG_TRI2_L1_MSK bits.
DIAG_TRI1_L1, Diagnostic Interrupt 1 Status,
Interrupt/VDP Sub Map, Address 0x53[1]
This read-only register, shows the status of the interrupt for
Diagnostic Pin 1, that is, if a STB event has occurred on the
DIAG1 pin. An STB event is deemed to have occurred when the
voltage on the DIAG1 pin exceeds the diagnostic slice level (see
the Programming Diagnostic Slice Levels section). When
triggered the DIAG_TRI1_L1 bit will remain high until cleared
(see the Clearing Diagnostic Interrupts).
Table 14. DIAG_TRI1_L1
DIAG_TRI1_L1
0
1
Description
Voltage higher than DIAG1_Slice_Level not
detected on DIAG1 pin
Voltage higher than DIAG1_Slice_Level
detected on DIAG1 pin
When a STB event is detected, the interrupt status bits
DIAG_TRI1_L1 and DIAG_TRI2_L1 will toggle from 0 to 1.
DIAG_TRI2_L1, Diagnostic Interrupt 2 Status,
Interrupt/VDP Sub Map, Address 0x53[3]
The DIAG_TRI1_L1 and DIAG_TRI2_L1 interrupts will
remain at 1 until they are cleared.
This read-only register, shows the status of the interrupt for
Diagnostic Pin 2, that is, if a STB event has occurred on the
DIAG2 pin. An STB event is deemed to have occurred when the
voltage on the DIAG2 pin exceeds the diagnostic slice level (see
the Programming Diagnostic Slice Levels section). When
triggered the DIAG_TRI2_L1 bit will remain high until cleared
(see the Clearing Diagnostic Interrupts).
DIAG_TRI1_L1 and DIAG_TRI2_L1 interrupts are
cleared by writing 1 to the DIAG_TRI1_L1_CLR and
DIAG_TRI2_L1_CLR bits.
Unmasking Diagnostic Interrupts
The DIAG_TRI1_L1_MSK and DIAG_TRI2_L1_MSK bits are
used to unmask (that is, to activate) the diagnostic interrupts.
Table 15. DIAG_TRI2_L1 Function
DIAG_TRI2_L1
0
DIAG_TRI1_L1_MSK, Unmask Diagnostic Interrupt 1,
Interrupt/VDP Sub Map, Address 0x55[1]
Description
Voltage higher than DIAG2_SLICE_LEVEL not
detected on the DIAG2 pin
Voltage higher than DIAG2_SLICE_LEVEL
detected on the DIAG2 pin
This unmasks (that is, activates) the STB interrupt for
Diagnostic Pin 1.
1
Table 12. DIAG_TRI1_L1_MSK Function
Clearing Diagnostic Interrupts
DIAG_TRI1_L1_MSK
Description
0 (default)
1
Mask DIAG_TRI1_L1 interrupt
Unmask DIAG_TRI1_L1 interrupt
The DIAG_TRI1_L1_CLR and DIAG_TRI2_L1_CLR bits are
used to clear the diagnostic interrupts.
DIAG_TRI1_L1_CLR, Clear Diagnostic Interrupt 1,
Interrupt/VDP Sub Map, Address 0x54[1]
DIAG_TRI2_L1_MSK, Unmask Diagnostic Interrupt 2,
Interrupt/VDP Sub Map, Address 0x55[3]
This bit clears the interrupt for Diagnostic Pin 1.
This unmasks (that is, activates) the STB interrupt for
Diagnostic Pin 2.
The DIAG_TRI1_L1_CLR is a self-clearing, write only bit.
Table 16. DIAG_TRI1_L1_CLR Function
Table 13. DIAG_TRI2_L1_MSK Function
DIAG_TRI2_L1_MSK
Description
0 (default)
1
Mask DIAG_TRI2_L1 interrupt
Unmask (that is, activate) DIAG_TRI2_L1
interrupt
Diagnostic Interrupt Status
The DIAG_TRI1_L1 and DIAG_TRI2_L1 bits give the status of
the diagnostic interrupt (that is, if a STB event has occurred or
not).
DIAG_TRI1_L1_CLR
0 (default)
1
Description
Do not clear DIAG_TRI1_L1
Clear DIAG_TRI1_L1
DIAG_TRI2_L1_CLR , Clear Diagnostic Interrupt 2,
Interrupt/VDP Sub Map, Address 0x54[3]
This bit clears the interrupt for Diagnostic Pin 2.
The DIAG_TRI2_L1_CLR is a self-clearing, write only bit.
Table 17. DIAG_TRI2_L1_CLR Function
DIAG_TRI2_L1_CLR
0 (default)
1
Rev. A | Page 16 of 104
Description
Do not clear DIAG_TRI2_L1
Clear DIAG_TRI2_L1
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
PROGRAMMING INTRQ HARDWARE INTERRUPT
When a software interrupt is unmasked and triggered, a
hardware interrupt indicated by the INTRQ pin will also
automatically trigger.
INTRQ_DUR_SEL[1:0], Interrupt/VDP Sub Map,
Address 0x40[7:6]
The INTRQ_DUR_SEL[1:0] bits are used to set the duration of
the INTRQ interrupt output.
An example on how to program a software interrupt is given in
the Programming Diagnostic Interrupt section. Other software
interrupts can be programmed in a similar manner. See
Table 106 for other software interrupts available on the
ADV728x.
The INTRQ_OP_SEL[1:0] bits are used to program the INTRQ
hardware interrupt to drive out in a number of different ways
(for example, drive the INTRQ pin high, drive the INTRQ pin
low, or make the INTRQ pin open drain).
The INTRQ_DUR_SEL[1:0] bits are used to set the duration of
the INTRQ interrupt output.
The duration of the INTRQ interrupt output is given in terms
of crystal clock periods. Because a 28.63636 MHz crystal is used
a clock period corresponds to approximately 35 ns.
The INTRQ interrupt output can also be set to be active until
cleared. In this mode of operation, the INTRQ pin will be active
until every active software interrupt has been cleared.
Table 19. INTRQ_DUR_SEL[1:0] Settings
INTRQ_DUR_SEL[1:0]
00 (default)
01
INTRQ_OP_SEL[1:0], Interrupt/VDP Sub Map,
Address 0x40[1:0]
10
The INTRQ_OP_SEL[1:0] bits are used to program the INTRQ
hardware interrupt to drive out in a number of different ways
when active.
11
In open-drain mode, the INTRQ is at DVDDIO voltage when
not active and drives low when active. In open-drain mode,
the INTRQ pin requires a pull-up resistor to DVDDIO in order
for the INTRQ interrupt to work correctly.
In drive low when active mode, the INTRQ is at DVDDIO
voltage when not active and drives low when active. In drive
low when active mode, the INTRQ pin does not require a pullup resistor to DVDDIO.
In drive high when active mode, the INTRQ is at GND when
not active and drives high to DVDDIO when active. In drive
high when active mode, the INTRQ pin does not require a pullup resistor to DVDDIO.
Table 18. INTRQ_OP_SEL[1:0] Settings
INTRQ_OP_SEL[1:0]
00 (default)
01
10
11
UG-637
Description
Open drain
Drive low when active
Drive high when active
Reserved
Rev. A | Page 17 of 104
Description
3 crystal periods ( approximately
0.105 µs)
15 crystal periods (approximately
0.525 µs)
63 crystal periods (approximately
2.205 µs)
Active until cleared
UG-637
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
ANALOG FRONT END
INPUT CONFIGURATION
INSEL[4:0], Input Control, Address 0x00[4:0]
The following two steps are key for configuring the ADV728x to
correctly decode the input video.
The INSEL bits allow the user to select the input format. They also
configure the standard definition processor core to process CVBS,
differential CVBS, S-Video (Y/C), or component (YPrPb) format.
1.
2.
Use INSEL[4:0] to configure the routing and format decoding
(CVBS, Y/C, or YPrPb).
If the input requirements are not met using the INSEL[4:0]
options, the analog input muxing section must be configured
manually to correctly route the video from the analog
input pins to the ADC. The standard definition processor
block, which decodes the digital data, should be configured
to process the CVBS, Y/C, or YPrPb format. This is performed
by the INSEL[4:0] selection.
INSEL[4:0] has predefined analog input routing schemes that
do not require manual mux programming (see Table 20). This
allows the user to route the various video signal types to the
decoder and select them using INSEL[4:0] only. The added
benefit is that if, for example, the CVBS input is selected, the
remaining channels are powered down.
Rev. A | Page 18 of 104
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
UG-637
Table 20. INSEL[4:0]
Analog Input for
ADV7281 and
ADV7282
CVBS input on AIN1
CVBS input on AIN2
Reserved
Reserved
Reserved
Reserved
CVBS input on AIN3
CVBS input on AIN4
Y input on AIN1,
C input on AIN2
Reserved
Analog Input for
ADV7281-M,
ADV7282-M, and
ADV7283
CVBS input on AIN1
CVBS input on AIN2
CVBS input on AIN3
CVBS input on AIN4
Reserved
Reserved
CVBS input on AIN5
CVBS input on AIN6
Y input on AIN1,
C input on AIN2
Y input on AIN3,
C input on AIN4
Reserved
INSEL
[4:0]
00000
00001
00010
00011
00100
00101
00110
00111
01000
Video
Format
CVBS
CVBS
CVBS
CVBS
CVBS
CVBS
CVBS
CVBS
Y/C (S-Video)
01001
Y/C (S-Video)
01010
Y/C (S-Video)
Analog Input for
ADV7280
CVBS input on AIN1
CVBS input on AIN2
CVBS input on AIN3
CVBS input on AIN4
Reserved
Reserved
Reserved
Reserved
Y input on AIN1,
C input on AIN2
Y input on AIN3,
C input on AIN4
Reserved
01011
Y/C (S-Video)
Reserved
01100
YPrPb
01101
YPrPb
Y input on AIN1,
Pb input on AIN2,
Pr input on AIN3
Reserved
01110
Differential
CVBS
Differential
CVBS
Differential
CVBS
Differential
CVBS
Reserved
Analog Input for
ADV7280-M
CVBS input on AIN1
CVBS input on AIN2
CVBS input on AIN3
CVBS input on AIN4
CVBS input on AIN5
CVBS input on AIN6
CVBS input on AIN7
CVBS input on AIN8
Y input on AIN1,
C input on AIN2
Y input on AIN3,
C input on AIN4
Y input on AIN5,
C input on AIN6
Y input on AIN7,
C input on AIN8
Y input on AIN1,
Pb input on AIN2,
Pr input on AIN3
Y input on AIN4,
Pb input on AIN5,
Pr input on AIN6
Reserved
Reserved
Reserved
Positive on AIN1,
Negative on AIN2
Reserved
Reserved
Reserved
Reserved
Positive on AIN1,
Negative on AIN2
Positive on AIN3,
Negative on AIN4
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Positive on AIN3,
Negative on AIN4
Reserved
Positive on AIN5,
Negative on AIN6
Reserved
01111
10000
10001
10010
to
11111
1
Reserved
Y input on AIN3,
C input on AIN4
Reserved1
Reserved1
Y input on AIN5,
C input on AIN6
Y input on AIN1,
Pb input on AIN2,
Pr input on AIN3
Reserved
Analog Input for
ADV7281-MA
CVBS input on AIN1
CVBS input on AIN2
CVBS input on AIN3
CVBS input on AIN4
CVBS input on AIN5
CVBS input on AIN6
CVBS input on AIN7
CVBS input on AIN8
Y input on AIN1,
C input on AIN2
Y input on AIN3,
C input on AIN4
Y input on AIN5,
C input on AIN6
Y input on AIN7,
C input on AIN8
Y input on AIN1,
Pb input on AIN2,
Pr input on AIN3
Y input on AIN4,
Pb input on AIN5,
Pr input on AIN6
Positive on AIN1,
Negative on AIN2
Positive on AIN3,
Negative on AIN4
Positive on AIN5,
Negative on AIN6
Positive on AIN7,
Negative on AIN8
Reserved
Note that it is possible for the ADV7281/ADV7282 to receive YPbPr formats; however, a manual muxing scheme is required. In this case luma(Y) is fed in on AIN1 or AIN3,
blue chroma (Pb) is fed in on AIN4 and red chroma (Pr) is fed in on AIN2. See the Manual Muxing Mode section for more information.
Rev. A | Page 19 of 104
UG-637
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
MAN_MUX_EN
MAN_MUX_EN
AIN1
AIN2
AIN3
AIN4
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
MUX_0[3:0]
AIN2
AIN4
AIN6
AIN2
AIN4
MUX_0[3:0]
MUX_0N[3:0]
MUX_1[3:0]
ADC
ADC
AIN2
AIN4
AIN6
MUX_1[3:0]
AIN2
AIN3
MUX_2[3:0]
MUX_2[3:0]
11935-011
AIN2
AIN3
11935-014
Figure 12. Manual Muxing Scheme for ADV7280
MAN_MUX_EN
AIN2
AIN3
AIN6
MAN_MUX_EN
MUX_0[3:0]
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
MUX_1[3:0]
ADC
AIN2
AIN4
AIN6
AIN8
MUX_2[3:0]
MUX_0[3:0]
MUX_0N[3:0]
Figure 13. Manual Muxing Scheme for ADV7280-M
MAN_MUX_EN
AIN1
AIN2
AIN3
AIN4
AIN2
AIN4
AIN2
AIN4
MUX_0[3:0]
ADC
AIN2
AIN4
AIN5
AIN6
AIN8
MUX_1[3:0]
AIN2
AIN3
AIN6
MUX_2[3:0]
Figure 16. Manual Muxing Scheme for ADV7281-MA
MUX_ON[3:0]
ADC
MUX_1[3:0]
AIN2
11935-013
MUX_2[3:0]
Figure 14. Manual Muxing Scheme for ADV7281 and ADV7282
Rev. A | Page 20 of 104
11935-015
AIN2
AIN4
AIN5
AIN6
AIN8
Figure 15. Manual Muxing Scheme for ADV7281-M, ADV7282-M, and ADV7283
11935-012
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
MANUAL MUXING MODE
UG-637
Note that MUX0N cannot be powered down independently.
MUX0N can only be powered down when MUX0, MUX1, and
MUX2 are all powered down.
In manual muxing mode, the user selects the analog input pin
(for example, AIN1, AIN2, and so on) that is to be processed by
the ADC of the ADV728x. MAN_MUX_EN (User Map,
Register 0xC4, Bit 7) must be set to 1 to enable the following
muxing blocks:
Manual Muxing of the ADV7280



MAN_MUX_EN must be set to 1 (User Map,
Register 0xC4, Bit 7).

CVBS can only be processed by MUX0.

Y/C can only be processed by MUX0 and MUX1. MUX0
processes the luma (Y) and MUX1 processes the chroma
(C).

Component (YPbPr) signals can only be processed by
MUX0(Y), MUX1(Pb), and MUX2(Pr).


MUX0[3:0], ADC mux configuration, Address 0xC3[3:0]
MUX0N[3:0], ADC mux configuration, Address 0x60[3:0]
(MUX0N[3:0] applies only to the ADV7281, ADV7281-M,
ADV7281-MA, ADV7282, and ADV7282-M models)
MUX1[3:0], ADC mux configuration, Address 0xC3[7:4]
MUX2[3:0], ADC mux configuration, Address 0xC4[3:0]
The four mux sections are controlled by the signal buses,
MUX0/MUX0N/MUX2/MUX3[2:0].
The tables in this section explain the control words used.
The input signal that contains the timing information (HS and VS)
must be processed by MUX0. For example, in a Y/C input
configuration, connect MUX0 to the Y channel and MUX1 to
the C channel.
MUX0N is only used to process the negative input for fully
differential or pseudo differential CVBS inputs.
When one or more muxes are not used to process video, such as
the CVBS input, the idle mux and associated channel clamps and
buffers should be powered down (see the description of
Register 0x3A in the User Map in Table 104).
Table 21 shows the settings for manual muxing of the
ADV7280.
Manual Muxing of the ADV7280-M
Table 22 shows the settings for manual muxing of the
ADV7280-M.



MAN_MUX_EN must be set to 1 (User Map, Register 0xC4,
Bit 7).
CVBS can only be processed by MUX0.
Y/C can only be processed by MUX0 and MUX1. MUX0
processes the luma (Y) and MUX1 processes the chroma
(C).
Component (YPbPr) signals can only be processed by
MUX0(Y), MUX1(Pb), and MUX2(Pr).
Table 21. Manual Mux Settings for ADC of ADV7280
MUX0[3:0]
0000
0001
0010
0011
0100
0101 to 1111
ADC Connection
No connect
AIN1
AIN2
AIN3
AIN4
No connect
MUX1[3:0]
0000
0001
0010
0011
0100
0101 to 1111
ADC Connected To
No connect
No connect
AIN2
No connect
AIN4
No connect
MUX2[3:0]
0000
0001
0010
0011
0100
0101 to 1111
ADC Connection
No connect
No connect
AIN2
AIN3
No connect
No connect
ADC Connection
No connect
No connect
AIN2
No connect
AIN4
AIN5
AIN6
No connect
AIN8
No connect
MUX2[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001-1111
ADC Connection
No connect
No connect
AIN2
AIN3
No connect
No connect
AIN6
No connect
No connect
No connect
Table 22. Manual Mux Settings for ADC of ADV7280-M
MUX0[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001-1111
ADC Connection
No connect
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
No connect
MUX1[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001-1111
Rev. A | Page 21 of 104
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
Manual Muxing of the ADV7281 and ADV7282
•
Table 24 shows the settings for manual muxing of the ADV7281
and ADV7282.
•
•
•
•
MAN_MUX_EN must be set to 1 (User Map, Register
0xC4, Bit 7)
CVBS can only be processed by MUX0.
Differential CVBS can only be processed by MUX0
(positive channel) and MUX0N (negative channel).
UG-637
Y/C can only be processed by MUX0 and MUX1. MUX0
processes the luma (Y) and MUX1 processes the chroma
(C).
Component (YPbPr) signals can only be processed by
MUX0(Y), MUX1(Pb), and MUX2(Pr). For example, Y
can be fed in on AIN1 or AIN3 for MUX0. Pb can be fed in
on AIN4 for MUX1. Pr can be fed in on AIN2 for MUX2.
Table 23 gives an example of how to program the
ADV7281/ADV7282 to accept YPrPb inputs.
Table 23. Register Writes to Program the ADV7281 or ADV7282 to Accept YPbPr Input
Register Map
User Map (0x40 or 0x42)
Register Address
0x00
0xC3
Register Write
0x0C
0x87
0xC4
0x82
Description
Program INSEL for YPbPr input.
Program manual muxing. Y is fed in on AIN3 for MUX0. Pb is fed in
on AIN4 for MUX1.
Enable manual muxing. Pr is fed in on AIN2 for MUX2.
Table 24. Manual Mux Settings for ADC of ADV7281 and ADV7282
MUX0[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001 to
1111
ADC Connection
No connect
AIN1
AIN2
No connect
No connect
No connect
No connect
AIN3
AIN4
No connect
MUX0N[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001 to
1111
ADC Connection
No connect
No connect
AIN2
No connect
No connect
No connect
No connect
No connect
AIN4
No connect
MUX1[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001 to
1111
Rev. A | Page 22 of 104
ADC Connection
No connect
No connect
AIN2
No connect
No connect
No connect
No connect
No connect
AIN4
No connect
MUX2[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001 to
1111
ADC Connection
No connect
No connect
AIN2
No connect
No connect
No connect
No connect
No connect
No connect
No connect
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
UG-637
Manual Muxing of the ADV7281-M, ADV7282-M, and ADV7283
Table 25 shows the settings for manual muxing of the ADV7281-M, ADV7282-M, and ADV7283.
•
•
•
•
•
MAN_MUX_EN must be set to 1 (User Map, Register 0xC4, Bit 7)
CVBS can only be processed by MUX0.
Differential CVBS can only be processed by MUX0 (positive channel) and MUX0N (negative channel).
Y/C can only be processed by MUX0 and MUX1. MUX0 processes the luma (Y) and MUX1 processes the chroma (C).
Component (YPbPr) signals can only be processed by MUX0(Y), MUX1(Pb), and MUX2(Pr).
Table 25. Manual Mux Settings for ADC of ADV7281-M, ADV7282-M, and ADV7283
MUX0[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001 to 1111
ADC Connection
No connect
AIN1
AIN2
AIN3
AIN4
No connect
No connect
AIN5
AIN6
No connect
MUX0N[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001 to 1111
ADC Connection
No connect
No connect
AIN2
No connect
AIN4
No connect
No connect
No connect
AIN6
No connect
MUX1[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001 to 1111
Rev. A | Page 23 of 104
ADC Connection
No connect
No connect
AIN2
No connect
AIN4
No connect
No connect
No connect
AIN6
No connect
MUX2[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001 to 1111
ADC Connection
No connect
No connect
AIN2
AIN3
No connect
No connect
No connect
No connect
No connect
No connect
UG-637
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
Manual Muxing of the ADV7281-MA
Table 26 shows the settings for manual muxing of the ADV7281-MA.
•
•
•
•
•
MAN_MUX_EN must be set to 1 (User Map, Register 0xC4, Bit 7).
CVBS can only be processed by MUX0.
Differential CVBS can only be processed by MUX0 (positive channel) and MUX0N (negative channel).
Y/C can only be processed by MUX0 and MUX1. MUX0 processes the luma (Y) and MUX1 processes the chroma (C).
Component (YPbPr) signals can only be processed by MUX0(Y), MUX1(Pb), and MUX2(Pr).
Table 26. Manual Mux Settings for ADC of ADV7281-MA
MUX0[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001 to 1111
ADC
Connection
No connect
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
No connect
MUX0N[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001 to 1111
ADC
Connection
No connect
No connect
AIN2
No connect
AIN4
No connect
AIN6
No connect
AIN8
No connect
MUX1[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001 to 1111
Rev. A | Page 24 of 104
ADC
Connection
No connect
No connect
AIN2
No connect
AIN4
AIN5
AIN6
No connect
AIN8
No connect
MUX2[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001 to 1111
ADC
Connection
No connect
No connect
AIN2
AIN3
No connect
No connect
AIN6
No connect
No connect
No connect
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
UG-637
ANTIALIASING FILTERS
The ADV728x has optional on-chip antialiasing (AA) filters
on each of the four channels that are multiplexed to the ADC
(see Figure 17).
AA_FILT_EN[1], Antialiasing Filter Enable,
Address 0xF3[1]
The filters are designed for standard definition video up to
10 MHz bandwidth. Figure 18 and Figure 19 show the filter
magnitude and phase characteristics.
When AA_FILT_EN[1] is set to 1, AA Filter 2 is enabled.
AA_FILT_EN[2], Antialiasing Filter Enable,
Address 0xF3[2]
The antialiasing filters are enabled by default and the selection
of INSEL[4:0] determines which filters are powered up at any
given time. For example, if CVBS mode is selected, the filter
circuits for the remaining input channels are powered down to
conserve power. However, the antialiasing filters can be disabled
or bypassed using the AA_FILT_MAN_OVR control.
AA
FILTER 1
MUX BLOCK
AA
FILTER 2
AA
FILTER 3
When AA_FILT_EN[2] is set to 0, AA Filter 3 is disabled.
When AA_FILT_EN[2] is set to 1, AA Filter 3 is enabled.
AA_FILT_EN[3], Antialiasing Filter Enable,
Address 0xF3[3]
When AA_FILT_EN[3] is set to 0, AA Filter 4 is disabled.
When AA_FILT_EN[3] is set to 1, AA Filter 4 is enabled.
10-BIT, 86MHz
ADC
0
+
SHA
–
–4
ADC
–8
NOTES
1. EIGHT ANALOG INPUTS ARE ONLY AVAILABLE ON THE
ADV7280-M AND ADV7281-MA MODELS.
SIX ANALOG INPUTS ARE AVAILABLE ON ADV7281-M,
ADV7282-M, AND ADV7283.
FOUR ANALOG INPUTS ARE AVAILABLE ON ADV7280,
ADV7281, AND ADV7282.
MAGNITUDE (dB)
AA
FILTER 4
11935-016
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
When AA_FILT_EN[1] is set to 0, AA Filter 2 is disabled.
–12
–16
–20
–24
–28
Figure 17. Antialias Filter Configuration
–36
1k
AA_FILT_MAN_OVR, Antialiasing Filter Override,
Address 0xF3[4]
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 18. Antialiasing Filter Magnitude Response
This feature allows the user to override the antialiasing filters
on/off settings, which are automatically selected by INSEL[4:0].
0
–10
AA_FILT_EN[3:0], Antialiasing Filter Enable,
Address 0xF3[3:0]
–20
–30
–40
PHASE (Degrees)
These bits allow the user to enable or disable the antialiasing
filters on each of the three input channels multiplexed to the
ADC. When disabled, the analog signal bypasses the AA filters
and is routed directly to the ADC.
–50
–60
–70
–80
–90
–100
–110
–120
When AA_FILT_EN[0] is set to 0, AA Filter 1 is disabled.
–130
–140
When AA_FILT_EN[0] is set to 1, AA Filter 1 is enabled.
–150
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 19. Antialiasing Filter Phase Response
Rev. A | Page 25 of 104
100M
11935-018
AA_FILT_EN[0], Antialiasing Filter Enable,
Address 0xF3[0]
10k
11935-017
–32
ANTIALIASING FILTER CONFIGURATION
UG-637
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
GLOBAL CONTROL REGISTERS
The register control bits listed in this section affect the entire
chip.
POWER SAVING MODE AND RESET CONTROL
Power Down
PWRDWN, Address 0x0F[5]
The ADV728x can be placed into a chip-wide, power-down mode
by setting the PWRDWN bit or by using the PWRDWN pin.
The power-down mode stops the clock from entering the digital
section of the chip, thereby freezing its operation. No I2C bits are
lost during power-down mode. The PWRDWN bit also affects
the analog blocks and switches them into low current modes.
The I2C interface is unaffected and remains operational in
power-down mode.
When PWRDWN is set to 0, the chip is operational. When
PWRDWN is set to 1 (default), the ADV728x is in a chip-wide,
power-down mode.
Reset, Chip Reset, Address 0x0F[7]
Setting this bit, which is equivalent to controlling the RESET
pin on the ADV728x, issues a full chip reset. All I2C registers
are reset to their default/power-up values. Note that some register
bits do not have a reset value specified; they keep their last
written value. Those bits are marked as having a reset value of
x in the register tables (see Table 104 and Table 106). After the
reset sequence, the part immediately starts to acquire the
incoming video signal.
After setting the reset bit (or initiating a reset via the RESET pin),
the part returns to the default for its primary mode of operation.
All I2C bits are loaded with their default values, making this bit
self-clearing. Executing a software reset takes approximately 2 ms.
However, it is recommended to wait 5 ms before any further I2C
writes are performed.
The I2C master controller receives a no acknowledge condition
on the ninth clock cycle when chip reset is implemented.
When the reset bit is set to 0 (default), operation is normal.
When the reset bit is set to 1, the reset sequence starts.
GLOBAL PIN CONTROL
Drive Strength Selection (I2C)
DR_STR_S[1:0], Address 0xF4[1:0]
The DR_STR_S[1:0] bits allow the user to select the strength of
the I2C signal output drivers. This affects the drive strength for
the SDA and SCL pins.
Table 27. DR_STR_S Function
DR_STR_S[1:0]
00
01 (default)
10
11
1
Description
Low drive strength (1×)1
Medium low drive strength (2×)
Medium high drive strength (3×)
High drive strength (4×)
The low drive strength setting is not recommended for the optimal
performance of the ADV728x.
Rev. A | Page 26 of 104
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
UG-637
GENERAL-PURPOSE OUTPUT CONTROLS
When GPO[0] is set to 1, Logic 1 is output from the GPO0 pin.
The ADV7280-M, ADV7281-M, ADV7281-MA, and
ADV7282-M have three general-purpose outputs (GPO).
GPO[1]
When GPO[1] is set to 0 (default), Logic 0 is output from the
GPO1 pin.
Three GPOs
These outputs allow the user to control other devices in a
system via the I2C port of the device.
When GPO[1] is set to 1, Logic 1 is output from the GPO1 pin.
GPO[2]
GPO_ENABLE, General-Purpose Output Enable,
User Sub Map, Address 0x59[4]
When GPO[2] is set to 0 (default), Logic 0 is output from the
GPO2 pin.
When GPO_ENABLE is set to 0 (default), all GPO pins are
tristated.
When GPO[2] is set to 1, Logic 1 is output from the GPO2 pin.
When GPO_ENABLE is set to 1, all GPO pins are in a driven
state. The polarity output from each GPO is controlled by
GPO[3:0].
GPO[2:0], General-Purpose Outputs, User Sub Map,
Address 0x59[2:0]
Individual control of the four GPO ports is achieved using
GPO[2:0].
GPO_ENABLE must be set to 1 for the GPO pins to become active.
GPO[0]
When GPO[0] is set to 0 (default), Logic 0 is output from the
GPO0 pin.
Table 28. General-Purpose Output Truth Table
GPO_ENABLE
0
1
1
1
1
1
1
1
1
1
2
GPO[2:0]
XXX1
000
001
010
011
100
101
110
111
X indicates any value.
Z indicates high impedance.
Rev. A | Page 27 of 104
GPO2
Z2
0
0
0
0
1
1
1
1
GPO1
Z2
0
0
1
1
0
0
1
1
GPO0
Z2
0
1
0
1
0
1
0
1
UG-637
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
GLOBAL STATUS REGISTER
Four registers provide summary information about the video
decoder. The IDENT register allows the user to identify the
revision code of the ADV728x. The other three registers
(Address 0x10, Address 0x12, and Address 0x13) contain
status bits from the ADV728x.
IDENTIFICATION
IDENT[7:0], Address 0x11[7:0]
This is the register identification of the ADV728x revision. Table 29
describes the various versions of the ADV728x.
Table 29. IDENT CODE
IDENT[7:0]
0x40
0x41
0x42
Description
Pre-release Silicon
Pre-release Silicon
Released Silicon
STATUS 2
Status 2[7:0], Address 0x12[7:0]
Table 31. Status 2 Function
Status 2[7:0]
0
Bit Name
MVCS DET
1
MVCS T3
2
MV PS DET
3
4
5
6
7
MV AGC DET
LL NSTD
FSC NSTD
Reserved
Reserved
Description
Detected Rovi (previously
Macrovision) color striping
Rovi color striping protection;
conforms to Type 3 if high, Type
2 if low
Detected Rovi pseudo sync
pulses
Detected Rovi AGC pulses
Line length is nonstandard
fSC frequency is nonstandard
STATUS 1
STATUS 3
Status 1[7:0], Address 0x10[7:0]
Status 3[7:0], Address 0x13[7:0]
Table 32. Status 3 Function
This read-only register provides information about the internal
status of the ADV728x.
See the CIL[2:0], Count into Lock, Address 0x51[2:0] section
and the COL[2:0], Count Out of Lock, Address 0x51[5:3] section
for details on timing.
Depending on the setting of the FSCLE bit, the status registers are
based solely on horizontal timing information or on the horizontal
timing and lock status of the color subcarrier. See the FSCLE,
fSC Lock Enable, Address 0x51[7] section.
Table 30. Status 1 Function
Status 1[7:0]
0
1
2
3
4
5
6
7
Bit Name
IN_LOCK
LOST_LOCK
FSC_LOCK
FOLLOW_PW
AD_RESULT[0]
AD_RESULT[1]
AD_RESULT[2]
COL_KILL
Description
In lock (now)
Lost lock (since last read)
fSC locked (now)
AGC follows peak white algorithm
Result of autodetection
Result of autodetection
Result of autodetection
Color kill active
Status 3[7:0]
0
Bit Name
INST_HLOCK
1
2
Reserved
SD_OP_50Hz
3
4
Reserved
FREE_RUN_ACT
5
STD FLD LEN
6
Interlaced
7
PAL_SW_LOCK
Rev. A | Page 28 of 104
Description
Horizontal lock indicator
(instantaneous)
Flags whether 50 Hz or 60 Hz is
present at output
Reserved
Flags if ADV728x has entered
free-run mode (see Free-Run
Operation section)
Field length is correct for
currently selected video
standard
Interlaced video detected
(field sequence found)
Reliable sequence of
swinging bursts detected
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
UG-637
Table 33. AD_RESULT Function
AUTODETECTION RESULT
AD_RESULT[2:0], Address 0x10[6:4]
The AD_RESULT[2:0] bits report back on the findings from the
ADV728x autodetection block. See the General Setup section for
more information on enabling the autodetection block and the
Autodetection of SD Modes section for more information on
how to configure it.
AD_RESULT[2:0]
000
001
010
011
100
101
110
111
Rev. A | Page 29 of 104
Description
NTSC M/NTSC J
NTSC 4.43
PAL M
PAL 60
PAL B/PAL G/PAL H/PAL I/PAL D
SECAM
PAL Combination N
SECAM 525
UG-637
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
VIDEO PROCESSOR
STANDARD DEFINITION PROCESSOR
DIGITIZED CVBS
DIGITIZED Y (YC)
DIGITIZED CVBS
DIGITIZED C (YC)
VBI DATA
RECOVERY
LUMA
DIGITAL
FINE
CLAMP
CHROMA
DIGITAL
FINE
CLAMP
CHROMA
DEMOD
STANDARD
AUTODETECTION
SLLC
CONTROL
LUMA
FILTER
LUMA
GAIN
CONTROL
LUMA
RESAMPLE
SYNC
EXTRACT
LINE
LENGTH
PREDICTOR
RESAMPLE
CONTROL
CHROMA
FILTER
CHROMA
GAIN
CONTROL
CHROMA
RESAMPLE
LUMA
2D COMB
AV
CODE
INSERTION
ACE
DITHER
I2P
SD PROCESSOR
OUTPUT
MEASUREMENT
BLOCK (≥ I2C)
CHROMA
2D COMB
VIDEO DATA
PROCESSING
BLOCK
INTERLACED TO
PROGRESSIVE
CONVERTER BLOCK,
ADV7280, ADV7280-M
ADV7282 AND
ADV7282-M ONLY
fSC
RECOVERY
11935-019
MACROVISION
DETECTION
Figure 20. Block Diagram of Video Processor
Figure 20 shows a block diagram of the video processor within the
ADV728x. The ADV728x can handle standard definition video
in CVBS, Y/C, and YPrPb formats. It can be divided into a
luminance and chrominance path. If the input video is of a
composite type (CVBS), both processing paths are fed with the
CVBS input. The output from the video processor is fed into
a MIPI CSI-2 Tx block in the ADV728x-M models. In the
ADV728x-T models, the output of the video processor is output
from the part in an ITU-R BT.656 video stream.



SD LUMA PATH
The input signal is processed by the following blocks:






Luma digital fine clamp. This block uses a high precision
algorithm to clamp the video signal.
Luma filter. This block contains a luma decimation filter
(YAA) with a fixed response and some shaping filters
(YSH) that have selectable responses.
Luma gain control. The AGC can operate on a variety of
different modes, including gain based on the depth of the
horizontal sync pulse, peak white mode, and fixed manual
gain.
Luma resample. To correct for line length errors as well as
dynamic line length changes, the data is digitally resampled.
Luma 2D comb. The 2D comb filter provides Y/C separation.
AV code insertion. At this point, the decoded luma (Y) signal
is merged with the retrieved chroma values. AV codes can
be inserted (as per ITU-R BT.656).
SD CHROMA PATH



ACE, I2P, AND DITHER PROCESSING BLOCKS


The input signal is processed by the following blocks:

Chroma demodulation. This block employs a color subcarrier
(fSC) recovery unit to regenerate the color subcarrier for
any modulated chroma scheme. The demodulation block
then performs an AM demodulation for PAL and NTSC,
and an FM demodulation for SECAM.
Chroma filter. This block contains a chroma decimation filter
(CAA) with a fixed response and some shaping filters (CSH)
that have selectable responses.
Chroma gain control. AGC can operate on several different
modes, including gain based on the color subcarrier
amplitude, gain based on the depth of the horizontal sync
pulse on the luma channel, or fixed manual gain.
Chroma resample. The chroma data is digitally resampled
to keep it perfectly aligned with the luma data. The
resampling is done to correct for static and dynamic line
length errors of the incoming video signal.
Chroma 2D comb. The 2D, five line, super adaptive comb
filter provides high quality Y/C separation if the input
signal is CVBS.
AV code insertion. At this point, the demodulated chroma
(Cr and Cb) signal is merged with the retrieved luma values.
AV codes can be inserted (as per ITU-R BT.656).
Chroma digital fine clamp. This block uses a high precision
algorithm to clamp the video signal.
Rev. A | Page 30 of 104
Adaptive contrast enhancement (ACE). This block offers
improved visual detail by using an algorithm to automatically vary the contrast levels to enhance picture detail.
See the Adaptive Contrast Enhancement section.
Dither. When enabled, this block converts the digital output
of the ADV728x from 8-bit pixel data down to 6-bit pixel
data. This function makes it easier for the ADV728x to
communicate with some LCD panels. See the Dither
Function section.
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
•
Interlaced-to-progressive converter (I2P). This block is
only available in the ADV7280, ADV7280-M, ADV7282,
ADV7282-M, and ADV7283 models. This block converts
interlaced video formats (480i and 576i) into progressive
video formats (480p and 576p).
SYNC PROCESSING
The ADV728x extracts syncs embedded in the analog input
video signal. The sync extraction is optimized to support
imperfect video sources, such as VCRs with head switches.
The actual algorithm used employs a coarse detection based on
a threshold crossing, followed by a more detailed detection using
an adaptive interpolation algorithm. The raw sync information
is sent to a line length measurement and prediction block. The
output of this is then used to drive the digital resampling
section to ensure that the ADV728x outputs 720 active pixels
per line.
The sync processing on the ADV728x also includes the following
specialized postprocessing blocks that filter and condition the
raw sync information retrieved from the digitized analog video:
•
•
VSYNC processor. This block provides extra filtering of the
detected VSYNCs to improve vertical lock.
HSYNC processor. The HSYNC processor is designed to
filter incoming HSYNCs that were corrupted by noise,
providing much improved performance for video signals
with a stable time base, but poor SNR.
VBI DATA RECOVERY
The ADV728x can retrieve the following information from the
input video:
•
•
•
•
•
Wide screen signaling (WSS)
Copy generation management system (CGMS)
Closed captioning (CCAP)
Rovi protection presence
Teletext
Autodetection of SD Modes
To guide the autodetect system of the ADV728x, individual
enable bits are provided for each of the supported video standards.
Setting the relevant bit to 0 inhibits the standard from being
detected automatically. Instead, the system chooses the closest of
the remaining enabled standards. The results of the autodetection
block can be read back via the status registers (see the Global
Status Register section for more information).
VID_SEL[3:0], Address 0x02[7:4]
Table 34. VID_SEL Function
VID_SEL[3:0]
0000 (default)
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Description
Autodetect PAL B/PAL G/PAL H/PAL I/PAL D,
NTSC J (no pedestal), SECAM
Autodetect PAL B/PAL G/PAL H/PAL I/PAL D,
NTSC M (pedestal), SECAM
Autodetect PAL N (pedestal), NTSC J
(no pedestal), SECAM
Autodetect PAL N (pedestal), NTSC M
(pedestal), SECAM
NTSC J
NTSC M
PAL 60
NTSC 4.43
PAL B/PAL G/PAL H/PAL I/PAL D
PAL N = PAL B/PAL G/PAL H/PAL I/PAL D (with
pedestal)
PAL M (without pedestal)
PAL M
PAL Combination N
PAL Combination N (with pedestal)
SECAM
SECAM
AD_SEC525_EN, SECAM 525 Autodetect Enable,
Address 0x07[7]
Setting AD_SEC525_EN to 0 (default) disables the autodetection
of a 525-line system with a SECAM style, FM-modulated color
component.
The ADV728x is also capable of automatically detecting the
incoming video standard with respect to the following:
•
•
•
UG-637
Setting AD_SEC525_EN to 1 enables the detection of a SECAM
style, FM-modulated color component.
Color subcarrier frequency
Field rate
Line rate
The ADV728x can configure itself to support PAL B/PAL D/
PAL I/PAL G/PAL H, PAL M, PAL N, PAL Combination N,
NTSC M/NTSC J, SECAM 50 Hz/60 Hz, NTSC 4.43, and PAL 60.
GENERAL SETUP
Video Standard Selection
The VID_SEL[3:0] bits (Address 0x02[7:4]) allow the user to
force the digital core into a specific video standard. This is not
necessary under normal circumstances. The VID_SEL[3:0] bits
default to an autodetection mode that supports PAL, NTSC,
SECAM, and variants thereof.
AD_SECAM_EN, SECAM Autodetect Enable,
Address 0x07[6]
Setting AD_SECAM_EN to 0 (default) disables the autodetection
of SECAM.
Setting AD_SECAM_EN to 1 enables the detection of SECAM.
AD_N443_EN, NTSC 4.43 Autodetect Enable,
Address 0x07[5]
Setting AD_N443_EN to 0 disables the autodetection of NTSC
style systems with a 4.43 MHz color subcarrier.
Setting AD_N443_EN to 1 (default) enables the detection of
NTSC style systems with a 4.43 MHz color subcarrier.
Rev. A | Page 31 of 104
UG-637
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
AD_P60_EN, PAL 60 Autodetect Enable, Address 0x07[4]
Setting AD_P60_EN to 0 disables the autodetection of PAL
systems with a 60 Hz field rate.
Setting AD_P60_EN to 1 (default) enables the detection of PAL
systems with a 60 Hz field rate.
AD_PALN_EN, PAL N Autodetect Enable,
Address 0x07[3]
Setting AD_PALN_EN to 0 (default) disables the detection of
the PAL N standard.
Setting AD_PALN_EN to 1 enables the detection of the PAL N
standard.
AD_PALM_EN, PAL M Autodetect Enable,
Address 0x07[2]
Setting AD_PALM_EN to 0 (default) disables the autodetection
of PAL M.
SFL_INV, Subcarrier Frequency Lock Inversion,
Address 0x41[6] (ADV7280 Only)
This bit controls the behavior of the PAL switch bit in the
SFL (genlock telegram) data stream. Implemented to solve
compatibility issues with video encoders, it solves two
problems.
First, the PAL switch bit is meaningful only in PAL. Some encoders
(including Analog Devices encoders) also look at the state of
this bit in NTSC.
Second, there was a design change in Analog Devices encoders
from ADV717x to ADV719x. The older versions used the SFL
(genlock telegram) bit directly, whereas the newer ones invert
the bit prior to using it. The reason for this is that the inversion
compensated for the one line delay of an SFL (genlock telegram)
transmission.
AD_NTSC_EN, NTSC Autodetect Enable,
Address 0x07[1]
As a result, for the ADV717x and ADV73xx encoders, the PAL
switch bit in the SFL (genlock telegram) must be set to 0 for NTSC
to work. For the older video encoders, the PAL switch bit in the
SFL must be set to 1 to work in NTSC. If the state of the PAL switch
bit is wrong, a 180° phase shift occurs.
Setting AD_NTSC_EN to 0 (default) disables the detection of
standard NTSC.
In a decoder/encoder back-to-back system in which SFL is used,
this bit must be set up properly for the specific encoder used.
Setting AD_NTSC_EN to 1 enables the detection of standard NTSC.
Setting SFL_INV to 0 (default) makes the part SFL compatible
with the ADV717x and ADV73xx video encoders.
Setting AD_PALM_EN to 1 enables the detection of PAL M.
AD_PAL_EN, PAL B/PAL D/PAL I/PAL G/PAL H
Autodetect Enable, Address 0x07[0]
Setting SFL_INV to 1 makes the part SFL compatible with the
older video encoders.
Setting AD_PAL_EN to 0 (default) disables the detection of
standard PAL.
Setting AD_PAL_EN to 1 enables the detection of standard PAL.
Rev. A | Page 32 of 104
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
SELECT THE RAW LOCK SIGNAL
SRLS
1
0
FILTER THE RAW LOCK SIGNAL
CIL[2:0], COL[2:0]
0
1
fSC LOCK
COUNTER INTO LOCK
COUNTER OUT OF LOCK
STATUS 1[0]
MEMORY
STATUS 1[1]
11935-020
TIME_WIN
FREE_RUN
UG-637
TAKE fSC LOCK INTO ACCOUNT
FSCLE
Figure 21. Lock Related Signal Path
Lock Related Controls
CIL[2:0], Count into Lock, Address 0x51[2:0]
Lock information is presented to the user through Bits[2:0] of the
Status 1 register (see the Status 1[7:0], Address 0x10[7:0] section).
Figure 21 outlines the signal flow and the controls that are available
to influence the way the lock status information is generated.
CIL[2:0] determines the number of consecutive lines for which
the lock condition must be true before the system switches into
the locked state and reports this via Status 1[1:0]. The bit counts
the value in lines of video.
SRLS, Select Raw Lock Signal, Address 0x51[6]
Table 35. CIL Function
Using the SRLS bit, the user can choose between two sources for
determining the lock status (per Bits[1:0] in the Status 1 register).
See Figure 21.
CIL[2:0]
000
001
010
011
100 (default)
101
110
111
•
•
The TIME_WIN signal is based on a line-to-line evaluation
of the horizontal synchronization pulse of the incoming
video. It reacts quickly.
The FREE_RUN signal evaluates the properties of the
incoming video over several fields, taking vertical
synchronization information into account.
Number of Video Lines
1
2
5
10
100
500
1000
100,000
COL[2:0], Count Out of Lock, Address 0x51[5:3]
Setting SRLS to 0 (default) selects the FREE_RUN signal (to
evaluate over several fields).
Setting SRLS to 1 selects the TIME_WIN signal (to evaluate on a
line-to-line basis).
FSCLE, fSC Lock Enable, Address 0x51[7]
The FSCLE bit allows the user to choose whether the status of
the color subcarrier loop is taken into account when the overall
lock status is determined and presented via Bits[1:0] in the
Status 1 register. This bit must be set to 0 when operating the
ADV728x in YPrPb component mode to generate a reliable
HLOCK status bit.
When FSCLE is set to 0 (default), the overall lock status is
dependent only on horizontal sync lock.
When FSCLE is set to 1, the overall lock status is dependent on
horizontal sync lock and fSC lock.
COL[2:0] determines the number of consecutive lines for which
the out-of-lock condition must be true before the system switches
into the unlocked state and reports this via Status 1[1:0]. It counts
the value in lines of video.
Table 36. COL Function
COL[2:0]
000
001
010
011
100 (default)
101
110
111
Rev. A | Page 33 of 104
Number of Video Lines
1
2
5
10
100
500
1000
100,000
UG-637
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
COLOR CONTROLS
SD_OFF_Cr[7:0], SD Offset Cr Channel, Address 0xE2[7:0]
These registers allow the user to control picture appearance,
including control of active data in the event of video being lost.
These controls are independent of any other controls. For instance,
brightness control is independent of picture clamping, although
both controls affect the dc level of the signal.
This register allows the user to select an offset for the Cr channel
only and to adjust the hue of the picture. There is a functional
overlap with the HUE[7:0] register.
Table 41. SD_OFF_Cr Function
This register allows the user to control contrast adjustment of
the picture.
SD_OFF_Cr[7:0]
0x80 (default)
0x00
0xFF
Table 37. CON Function
BRI[7:0], Brightness Adjust, Address 0x0A[7:0]
CON[7:0], Contrast Adjust, Address 0x08[7:0]
CON[7:0]
0x80 (default)
0x00
0xFF
Description
Gain on luma channel = 1
Gain on luma channel = 0
Gain on luma channel = 2
This register controls the brightness of the video signal. It allows
the user to adjust the brightness of the picture.
Table 42. BRI Function
SD_SAT_Cb[7:0], SD Saturation Cb Channel,
Address 0xE3[7:0]
This register allows the user to control the gain of the Cb channel
only, which in turn adjusts the saturation of the picture.
Table 38. SD_SAT_Cb Function
SD_SAT_Cb[7:0]
0x80 (default)
0x00
0xFF
BRI[7:0]
0x00 (default)
0x7F
0x80
HUE[7:0], Hue Adjust, Address 0x0B[7:0]
HUE[7:0] has a range of ±90°, with 0x00 equivalent to an
adjustment of 0°. The resolution of HUE[7:0] is 1 bit = 0.7°.
This register allows the user to control the gain of the Cr channel
only, which in turn adjusts the saturation of the picture.
Table 39. SD_SAT_Cr Function
The hue adjustment value is fed into the AM color demodulation
block. Therefore, it applies only to video signals that contain
chroma information in the form of an AM-modulated carrier
(CVBS or Y/C in PAL or NTSC). It does not affect SECAM
and does not work on component video inputs (YPrPb).
Table 43. HUE Function
Description
Gain on Cr channel = 0 dB
Gain on Cr channel = −42 dB
Gain on Cr channel = +6 dB
HUE[7:0]
0x00 (default)
0x7F
0x80
SD_OFF_Cb[7:0], SD Offset Cb Channel, Address 0xE1[7:0]
This register allows the user to select an offset for the Cb channel
only and to adjust the hue of the picture. There is a functional
overlap with the HUE[7:0] register (Address 0x0B).
Table 40. SD_OFF_Cb Function
SD_OFF_Cb[7:0]
0x80 (default)
0x00
0xFF
Description
Offset of the luma channel = 0 IRE
Offset of the luma channel = +30 IRE
Offset of the luma channel = −30 IRE
This register contains the value for the color hue adjustment. It
allows the user to adjust the hue of the picture.
Description
Gain on Cb channel = 0 dB
Gain on Cb channel = −42 dB
Gain on Cb channel = +6 dB
SD_SAT_Cr[7:0], SD Saturation Cr Channel,
Address 0xE4[7:0]
SD_SAT_Cr[7:0]
0x80 (default)
0x00
0xFF
Description
0 mV offset applied to the Cr channel
−312 mV offset applied to the Cr channel
+312 mV offset applied to the Cr channel
Description
0 mV offset applied to the Cb channel
−312 mV offset applied to the Cb channel
+312 mV offset applied to the Cb channel
Rev. A | Page 34 of 104
Description (Adjust Hue of the Picture)
Phase of the chroma signal = 0°
Phase of the chroma signal = −90°
Phase of the chroma signal = +90°
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
UG-637
DEF_Y[5:0], Default Value Y, Address 0x0C[7:2]
Single Color Test Pattern
When the ADV728x loses lock on the incoming video signal or
when there is no input signal, the DEF_Y[5:0] register allows
the user to specify a default luma value to be output. This value
is used under the following conditions:
In this mode, the ADV728x device can be set to output the
default luma and chroma data stored in DEF_Y and DEF_C
(see the Color Controls section).

In this mode, the ADV728x device outputs the 100% color bars
pattern.

If the DEF_VAL_AUTO_EN bit is set to 1 and the
ADV728x has lost lock to the input video signal, this is the
intended mode of operation (automatic mode).
If the DEF_VAL_EN bit is set to 1, regardless of the lock
status of the video decoder, this is a forced mode that may
be useful during configuration.
The DEF_Y[5:0] values define the six MSBs of the output video.
The remaining LSBs are padded with 0s. For example, in 8-bit
mode, the output is Y[7:0] = (DEF_Y[5:0], 0, 0).
For DEF_Y[5:0], 0x0D (blue) is the default value for Y.
Color Bars Test Pattern
Luma Ramp Test Pattern
In this mode, the ADV728x device outputs a series of vertical
bars. Each vertical bar is progressively brighter than the vertical
bar to its left.
Boundary Box Test Pattern
In this mode, the ADV728x device outputs a black screen with
a 1-pixel depth white border (see Figure 22).
Register 0x0C has a default value of 0x36.
DEF_C[7:0], Default Value C, Address 0x0D[7:0]
The DEF_C[7:0] register complements the DEF_Y[5:0] value. It
defines the four MSBs of Cr and Cb values to be output if:

The DEF_VAL_AUTO_EN bit is set to high and the
ADV728x cannot lock to the input video (automatic mode).
The DEF_VAL_EN bit is set to high (forced output).
11935-021

Figure 22. Boundary Box Free-Run Test Pattern
The data that is finally output from the ADV728x for the chroma
side is Cr[4:0] = (DEF_C[7:4]) and Cb[4:0] = (DEF_C[3:0]).
DEF_VAL_AUTO_EN, Default Value Automatic Enable,
User Map, Address 0x0C[1]
For DEF_C[7:0], 0x7C (blue) is the default value for Cr and Cb.
This bit enables the ADV728x to enter free-run mode if it
cannot decode the video signal that has been input.
FREE-RUN OPERATION
Table 44. DEF_VAL_AUTO_EN Function
Free-run mode provides the user with a stable clock and
predictable data if the input signal cannot be decoded, for
example, if input video is not present.
DEF_VAL_AUTO_EN
0
The ADV728x automatically enters free-run mode if the input
signal cannot be decoded. The user can prevent this operation
by setting the DEF_VAL_AUTO_EN to 0. When the DEF_VAL_
AUTO_EN bit is set to 0, the ADV728x outputs noise if it
cannot decode the input video. It is recommended that the user
keep DEF_VAL_AUTO_EN set to 1.
The user can force free-run mode by setting the DEF_VAL_EN
bit to 1. This can be a useful tool in debugging system level issues.
The VID_SEL[3:0] bits can be used to force the video standard
output in free-run mode (see the Video Standard Selection
section).
1 (default)
DEF_VAL_EN, Default Value Enable, User Map,
Address 0x0C[0]
This bit forces free-run mode.
Table 45. DEF_VAL_EN Function
DEF_VAL_EN
0 (default)
1
The user can also specify which data is output in free-run mode
with the FREE_RUN_PAT_SEL bits. The following test patterns
can be set using this function:




Description
The ADV728x outputs noise if it loses
lock with the inputted video signal.
The ADV728x enters free-run mode if it
loses lock with the inputted video signal.
Single color
Color bars
Luma ramp
Boundary box
Rev. A | Page 35 of 104
Description
Do not force free-run mode (that is, free-run
mode dependent on DEF_VAL_AUTO_EN)
Force free-run mode
UG-637
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
The clamping can be divided into two sections.
FREE_RUN_PAT_SEL[2:0], Free Run Pattern Select, User
Map, Address 0x14[2:0]

This function selects what data is output in free-run mode.

Table 46. FREE_FUN_PAT_SEL Function
001
010
101
Description
Single color set by DEF_C and DEF_Y
controls; see the Color Controls section
100% color bars
Luma ramp. Note that to display
properly, the DEF_C register should be
set to 0x88; see the Color Controls
section
Boundary box
The primary task of the analog clamping circuits is to ensure that
the video signal stays within the valid 1.0 V ADC input window
so that the analog-to-digital conversion can take place. The current
sources in the AFE correct the dc level of the ac-coupled input
video signal before it is fed into the ADC. The digitized data from
the ADC is then fed into the video processor. The digital fine
clamp block within the video processor corrects for any remaining
variation in the dc level. The video processor also sends clamp
control signals to the current sources. This feedback loop fine
tunes the current clamp operation and compensates for any noise
on the input video signal. This maintains the dc level of the
video signal during normal operation.
CLAMP OPERATION
The input video is ac-coupled into the ADV728x. This has the
advantage of protecting the ADV728x from STB events. However,
the dc value of the input video needs to be restored. This process
is referred to as clamping the video. This section explains the
general process of clamping on the ADV728x in both singleended and differential modes. This section also shows the different
ways in which a user can configure clamp operation behavior.
Differential CVBS Clamping Operation
This section applies to the ADV7281, ADV7281-M,
ADV7281-MA, ADV7282, ADV7282-M, and ADV7283
models only.
Single-Ended CVBS Clamp Operation
The ADV728x uses a combination of current sources and a digital
processing block for clamping as shown in Figure 23.
The analog processing channel shown is replicated three times
inside the IC. While only a single channel is needed for a singleended CVBS signal, two independent channels are needed for
Y/C (SVHS) type signals, and three independent channels are
needed to allow component signals (YPrPb) to be processed.
The differential clamping operation works in a similar manner
to the single-ended clamping operation (see the Single-Ended
CVBS Clamp Operation section). In differential mode, a coarse
clamp pulls the positive and negative video input to a commonmode voltage VCML (see Figure 24). The feedback loop
between the current clamps and the video processor fine tunes
this coarse dc offset and makes the clamping robust to noise on the
video input. Note that the current clamps are controlled within
a feedback loop between the AFE and the video processor; the
coarse clamps are not.
ADV728x
ANALOG FRONT END (AFE)
EXTERNAL AC
COUPLING
CAPACITOR
CLAMP CONTROL
ADC
CURRENT
SOURCE
CLAMPS
DATA PREPROCESSOR
VIDEO PROCESSOR
WITH DIGITAL
FINE CLAMP
11935-022
SINGLE-ENDED
ANALOG
VIDEO INPUT
DIGITAL CORE
Figure 23. Single-Ended Clamping Overview
ADV728x
ANALOG FRONT END (AFE)
EXTERNAL AC
COUPLING
CAPACITOR
CLAMP CONTROL
COARSE
CLAMP
ADC
POSITIVE
DIFFERENTIAL ANALOG
VIDEO INPUT
NEGATIVE
DIFFERENTIAL ANALOG
VIDEO INPUT
EXTERNAL AC
COUPLING
CAPACITOR
VCML
DIGITAL CORE
DATA PREPROCESSOR
CURRENT
SOURCE
CLAMPS
VIDEO PROCESSOR
WITH DIGITAL
FINE CLAMP
CURRENT
SOURCE
CLAMPS
COARSE
CLAMP
CLAMP CONTROL
Figure 24. Differential Clamping Overview
Rev. A | Page 36 of 104
11935-023
FREE_RUN_PAT_SEL
000 (default)
Clamping before the ADC (analog domain): current sources
and voltage sources.
Clamping after the ADC (digital domain): digital processing
block.
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
Clamp Operation Controls
•
The following sections describe the I2C signals that can be used
to influence the behavior of the clamping block.
CCLEN, Current Clamp Enable, Address 0x14[4]
The current clamp enable bit allows the user to switch off all the
current sources in the AFE simultaneously. This may be useful
if the incoming analog video signal is clamped externally.
When CCLEN is set to 0, the current sources are switched off.
When CCLEN is set to 1 (default), the current sources are
enabled.
DCT[1:0], Digital Clamp Timing, Address 0x15[6:5]
The clamp timing register determines the time constant of the
digital fine clamp circuitry. Note that the digital fine clamp reacts
quickly because it immediately corrects any residual dc level error
for the active line. The time constant from the digital fine clamp
must be much quicker than the one from the analog blocks.
By default, the time constant of the digital fine clamp is adjusted
dynamically to suit the currently connected input signal.
Table 47. DCT Function
DCT[1:0]
00 (default)
01
10
11
Description
Slow (TC = 1 sec)
Medium (TC = 0.5 sec)
Fast (TC = 0.1 sec)
Determined by ADV728x, depending on the
input video parameters
Luma shaping filters (YSH). The shaping filter block is a
programmable low-pass filter with a wide variety of responses.
It can be used to reduce selectively the luma video signal
bandwidth (needed prior to scaling, for example). For some
video sources that contain high frequency noise, reducing
the bandwidth of the luma signal improves visual picture
quality. If the video is low-pass filtered, a follow-on video
compression stage can work more efficiently.
The ADV728x has two responses for the shaping filter: one
that is used for good quality composite, component, and SVHS
type sources; and a second for nonstandard CVBS signals.
The YSH filter responses also include a set of notches for
PAL and NTSC. However, using the comb filters for Y/C
separation is recommended.
Digital resampling filter. This block allows dynamic
resampling of the video signal to alter parameters such as
the time base of a line of video. Fundamentally, the resampler
is a set of low-pass filters. The actual response is chosen by the
system with no requirement for user intervention.
Figure 26 through Figure 29 show the overall response of all filters
together. Unless otherwise noted, the filters are set into a typical
wideband mode.
Y Shaping Filter
DCFE, Digital Clamp Freeze Enable, Address 0x15[4]
This register bit allows users to freeze the digital clamp loop at
any time (do their own clamping). Users can disable the current
sources for analog clamping via the appropriate register bits,
wait until the digital clamp loop settles, and then freeze it via
the DCFE bit.
When DCFE is set to 0 (default), the digital clamp is operational.
When DCFE is set to1, the digital clamp loop is frozen.
LUMA FILTER
Data from the digital fine clamp block is processed by the three
sets of filters that follow. The data format at this point is CVBS
for CVBS input or luma only for Y/C and YPrPb input formats.
•
•
UG-637
Luma antialias filter (YAA). The ADV728x receives video at
a rate of 28.6363 MHz. (In the case of 4× oversampled video,
the ADC samples at 57.27 MHz, and the first decimation is
performed inside the DPP filters. Therefore, the data rate
into the ADV728x is always 28.6363 MHz.) The ITU-R
BT.601 recommends a sampling frequency of 13.5 MHz.
The luma antialias filter decimates the oversampled video
using a high quality linear phase, low-pass filter that preserves
the luma signal while, at the same time, attenuating out-ofband components. The luma antialias filter (YAA) has a
fixed response.
For input signals in CVBS format, the luma shaping filters play
an essential role in removing the chroma component from a
composite signal. Y/C separation must aim for the best possible
crosstalk reduction while still retaining as much bandwidth
(especially on the luma component) as possible. High quality
Y/C separation can be achieved by using the internal comb
filters of the ADV728x. Comb filtering, however, relies on the
frequency relationship of the luma component (multiples of the
video line rate) and the color subcarrier (fSC). For good quality
CVBS signals, this relationship is known; the comb filter algorithms
can be used to separate luma and chroma with high accuracy.
In the case of nonstandard video signals, the frequency relationship
may be disturbed, and the comb filters may not be able to remove
all crosstalk artifacts in the best fashion without the assistance
of the shaping filter block.
An automatic mode is provided that allows the ADV728x to
evaluate the quality of the incoming video signal and select the
filter responses in accordance with the signal quality and video
standard. YFSM, WYSFMOVR, and WYSFM allow the user to
manually override the automatic decisions in part or in full.
The luma shaping filter has the following control bits.
•
•
Rev. A | Page 37 of 104
YSFM[4:0] allows the user to manually select a shaping
filter mode (applied to all video signals) or to enable an
automatic selection (depending on video quality and video
standard).
WYSFMOVR allows the user to manually override the
WYSFM decision.

ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
The Y-shaping filter mode operates as follows:
WYSFM[4:0] allows the user to select a different shaping
filter mode for good quality composite (CVBS), component
(YPrPb), and SVHS (Y/C) input signals.

In automatic mode, the system preserves the maximum possible
bandwidth for good CVBS sources (because they can be successfully
combed) as well as for luma components of YPrPb and Y/C
sources (because they need not be combed). For poor quality
signals, the system selects from a set of proprietary shaping
filter responses that complements comb filter operation to
reduce visual artifacts.

If the YSFM settings specify a filter (that is, YSFM is set
to values other than 00000 or 00001), the chosen filter is
applied to all video, regardless of its quality.
In automatic selection mode, the notch filters are only used
for bad quality video signals. For all other video signals,
wideband filters are used.
WYSFMOVR, Wideband Y Shaping Filter Override,
Address 0x18[7]
Setting the WYSFMOVR bit enables the use of the WYSFM[4:0]
settings for good quality video signals. For more information on
luma shaping filters, see the Y Shaping Filter section and the
flowchart shown in Figure 25.
The decisions of the control logic are shown in Figure 25.
YSFM[4:0], Y Shaping Filter Mode, Address 0x17[4:0]
The Y shaping filter mode bits allow the user to select from
a wide range of low-pass and notch filters. When switched in
automatic mode, the filter selection is based on other register
selections, such as detected video standard, as well as properties
extracted from the incoming video itself, such as quality and time
base stability. The automatic selection always selects the widest
possible bandwidth for the video input encountered (see Table 48).
When WYSFMOVR is set to 0, the shaping filter for good quality
video signals is selected automatically.
When WYSFMOVR is set to 1 (default), it enables manual
override via WYSFM[4:0].
SET YSFM
YES
YSFM IN AUTO MODE?
00000 OR 00001
NO
VIDEO
QUALITY
BAD
GOOD
AUTO SELECT LUMA
SHAPING FILTER TO
COMPLEMENT COMB
USE YSFM SELECTED
FILTER REGARDLESS OF
VIDEO QUALITY
WYSFMOVR
1
0
SELECT WIDEBAND
FILTER AS PER
WYSFM[4:0]
SELECT AUTOMATIC
WIDEBAND FILTER
Figure 25. YSFM and WYSFM Control Flowchart
Rev. A | Page 38 of 104
11935-024
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ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
Table 48. YSFM Function
YSFM[4:0]
00000
00001 (default)
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
Description
Automatic selection including a wide notch
response (PAL/NTSC/SECAM)
Automatic selection including a narrow notch
response (PAL/NTSC/SECAM)
SVHS 1
SVHS 2
SVHS 3
SVHS 4
SVHS 5
SVHS 6
SVHS 7
SVHS 8
SVHS 9
SVHS 10
SVHS 11
SVHS 12
SVHS 13
SVHS 14
SVHS 15
SVHS 16
SVHS 17
SVHS 18 (CCIR 601)
PAL NN1
PAL NN2
PAL NN3
PAL WN1
PAL WN2
NTSC NN1
NTSC NN2
NTSC NN3
NTSC WN1
NTSC WN2
NTSC WN3
Reserved
UG-637
WYSFM[4:0], Wideband Y Shaping Filter Mode,
Address 0x18[4:0]
The WYSFM[4:0] bits allow the user to manually select a shaping
filter for good quality video signals, such as CVBS with stable
time base, luma component of YPrPb, and luma component of
Y/C. The WYSFM bits are active only if the WYSFMOVR bit is
set to 1. See the general discussion of the shaping filter settings in
the Y Shaping Filter section.
Table 49. WYSFM Function
WYSFM[4:0]
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011 (default)
10100 to 11111
Rev. A | Page 39 of 104
Description
Reserved, do not use
Reserved, do not use
SVHS 1
SVHS 2
SVHS 3
SVHS 4
SVHS 5
SVHS 6
SVHS 7
SVHS 8
SVHS 9
SVHS 10
SVHS 11
SVHS 12
SVHS 13
SVHS 14
SVHS 15
SVHS 16
SVHS 17
SVHS 18 (CCIR 601)
Reserved, do not use
UG-637
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
The filter plots in Figure 26 show the SVHS 1 (narrowest) to
SVHS 18 (widest) shaping filter settings. Figure 28 shows the PAL
notch filter responses. The NTSC notch filter responses are shown
in Figure 29.
0
–10
–20
–20
–30
–40
–60
–80
–100
–40
–120
0
2
4
–50
6
8
10
12
FREQUENCY (MHz)
11935-026
AMPLITUDE (dB)
0
AMPLITUDE (dB)
COMBINED Y ANTIALIAS, SVHS LOW-PASS FILTERS,
Y RESAMPLE
COMBINED Y ANTIALIAS, CCIR MODE SHAPING FILTER,
Y RESAMPLE
Figure 27. Combined Y Antialias, CCIR Mode Shaping Filter
–60
0
2
4
6
8
10
12
FREQUENCY (MHz)
COMBINED Y ANTIALIAS, PAL NOTCH FILTERS,
Y RESAMPLE
11935-025
–70
0
Figure 26. Y SVHS Combined Responses
–10
•
Figure 30 shows the overall response of all filters together.
–30
–40
–50
–60
–70
0
2
4
6
8
10
12
FREQUENCY (MHz)
11935-027
•
Chroma antialias filter (CAA). The ADV728x oversamples the
CVBS by a factor of 4 and the chroma/YPrPb by a factor of 2.
A decimating filter (CAA) is used to preserve the active video
band and to remove any out-of-band components. The
CAA filter has a fixed response.
Chroma shaping filters (CSH). The shaping filter block
(CSH) can be programmed to perform a variety of low-pass
responses. It can be used to selectively reduce the bandwidth
of the chroma signal for scaling or compression.
Digital resampling filter. This block allows dynamic
resampling of the video signal to alter parameters,0 such as
the time base of a line of video. Fundamentally, the resampler
is a set of low-pass filters. The actual response is chosen by
the system without user intervention.
–20
Figure 28. Combined Y Antialias, PAL Notch Filters
COMBINED Y ANTIALIAS, NTSC NOTCH FILTERS,
Y RESAMPLE
0
–10
–20
–30
–40
–50
–60
–70
0
2
4
6
8
10
12
FREQUENCY (MHz)
Figure 29. Combined Y Antialias Filter, NTSC Notch Filters
Rev. A | Page 40 of 104
11935-028
•
AMPLITUDE (dB)
Data from the digital fine clamp block is processed by the three
sets of filters that follow. The data format at this point is CVBS for
CVBS (or differential CVBS) inputs, chroma only for Y/C, or U/V
interleaved for YPrPb input formats.
AMPLITUDE (dB)
CHROMA FILTER
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
As shown in Figure 33, the ADV728x can decode a video signal
as long as it fits into the ADC window. The components for this
are the amplitude of the input signal and the dc level it resides on.
The dc level is set by the clamping circuitry (see the Clamp
Operation section).
COMBINED C ANTIALIAS, C SHAPING FILTER,
C RESAMPLER
0
–10
–20
If the amplitude of the analog video signal is too high, clipping
may occur, resulting in visual artifacts. The analog input range
of the ADC, together with the clamp level, determines the
maximum supported amplitude of the video signal.
–40
–60
0
1
2
3
4
5
6
FREQUENCY (MHz)
11935-029
–50
Figure 30. Chroma Shaping Filter Responses
CSFM[2:0], C Shaping Filter Mode, Address 0x17[7:5]
The C shaping filter mode bits allow the user to select from a
range of low-pass filters for the chrominance signal. When
switched in automatic mode, the widest filter is selected based
on the video standard/format and user choice (see the 000 and
001 settings in Table 50).
Figure 31 and Figure 32 show the typical voltage divider networks
required to keep the input video signal within the allowed range of
the ADC, 0 V to 1 V. The circuit in Figure 31 should be placed
before all the single-ended analog inputs to the ADV728x, and
place the circuit in Figure 32 before all the differential inputs to
the ADV728x.
Note differential inputs can only be applied directly to the
ADV7281, ADV7281-M, ADV7281-MA, ADV7282, ADV7282-M,
and ADV7283 models.
ANALOG VIDEO
INPUT
AIN
24Ω
Table 50. CSFM Function
CSFM[2:0]
000 (default)
001
010
011
100
101
110
111
100nF
11935-030
–30
51Ω
Figure 31. Single-Ended Input Voltage Divider Network
Description
Autoselection 1.5 MHz bandwidth
Autoselection 2.17 MHz bandwidth
SH1
SH2
SH3
SH4
SH5
Wideband mode
ANALOG_INPUT
CVBS_1P
1.3kΩ
0.1µF
AINx
430Ω
75Ω
ANALOG_INPUT
CVBS_1N
1.3kΩ
430Ω
0.1µF
AINx
11935-031
ATTENUATION (dB)
UG-637
Figure 32. Differential Input Voltage Divider Network
Figure 30 shows the responses of SH1 (narrowest) to SH5
(widest) in addition to the wideband mode (shown in red).
The minimum supported amplitude of the input video is
determined by the ability of the ADV728x to retrieve horizontal
and vertical timing and to lock to the color burst, if present.
GAIN OPERATION
The gain control within the ADV728x is done on a purely digital
basis. The input ADC supports a 10-bit range mapped into a 1.0 V
analog voltage range. Gain correction takes place after the
digitization in the form of a digital multiplier.
There are separate gain control units for luma and chroma data.
Both can operate independently of each other. The chroma unit,
however, can also take its gain value from the luma path.
Advantages of this architecture over the commonly used
programmable gain amplifier (PGA) before the ADC include
the fact that the gain is now completely independent of supply,
temperature, and process variations.
Rev. A | Page 41 of 104
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
The possible AGC modes are shown in Table 51.
Table 51. AGC Modes
Input Video Type
Any
CVBS
Luma Gain
Manual gain luma
Dependent on
horizontal sync depth
Peak white
Y/C
Dependent on
horizontal sync depth
Peak white
YPrPb
Dependent on
horizontal sync depth
Chroma Gain
Manual gain chroma
Dependent on colorburst amplitude
taken from luma path
Dependent on colorburst amplitude
taken from luma path
Dependent on colorburst amplitude
taken from luma path
Dependent on colorburst amplitude
Taken from luma path
It is possible to freeze the automatic gain control loops. This causes
the loops to stop updating and the AGC determined gain at the
time of the freeze to stay active until the loop is either unfrozen
or the gain mode of operation is changed.
The currently active gain from any of the modes can be read
back. Refer to the description of the dual-function manual gain
registers, LG[11:0] luma gain and CG[11:0] chroma gain, in the
Luma Gain section and Chroma Gain section, respectively.
ANALOG VOLTAGE RANGE SUPPORTED BY ADC
(1V RANGE FOR ADV7182)
MAXIMUM
VOLTAGE
VIDEO PROCESSOR
(GAIN SELECTION ONLY)
ADC
DATA PREPROCESSOR
(DPP)
GAIN
CONTROL
MINIMUM
VOLTAGE
CLAMP
LEVEL
Figure 33. Gain Control Overview
Rev. A | Page 42 of 104
11935-032
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ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
UG-637
Luma Gain
LAGC[2:0], Luma Automatic Gain Control,
Address 0x2C[6:4]
LG[11:0], Luma Gain, Address 0x2F[3:0], Address 0x30[7:0]
The luma automatic gain control mode bits select the operating
mode for the gain control in the luma path.
Luma gain[11:0] is a dual-function register. If all of these bits
are written to, a desired manual luma gain can be programmed.
This gain becomes active if the LAGC[2:0] mode is switched to
manual fixed gain. Equation 1 shows how to calculate a desired
gain.
LMG[11:0], Luma Manual Gain, Address 0x2F[3:0],
Address 0x30[7:0]
The peak white algorithm is used to detect if the input video
amplitude exceeds the ADC input range of the ADV728x. If this
is so, then the ADV728x reduces its internal luma gain to
prevent the signal from becoming saturated.
Table 52. LAGC Function
LAGC[2:0]
000
001
010 (default)
011
100
101
110
111
Description
Manual fixed gain (use LMG[11:0])
AGC (blank level to sync tip), peak white algorithm off
AGC (blank level to sync tip), peak white algorithm on
Reserved
Reserved
Reserved
Reserved
Freeze gain
LAGT[1:0], Luma Automatic Gain Timing,
Address 0x2F[7:6]
•
•
Luma manual gain value (LAGC[2:0] set to luma manual
gain mode)
Luma automatic gain value (LAGC[2:0] set to either of the
automatic modes)
Table 54. LG/LMG Function
LG[11:0]/LMG[11:0]
LMG[11:0] = x
LG[11:0] = x
Luma Gain ≅
The luma automatic gain timing register allows the user to
influence the tracking speed of the luminance automatic gain
control. This register has an effect only if the LAGC[2:0] register
is set to 001 or 010 (automatic gain control modes).
If peak white AGC is enabled and active (see the Status 1[7:0],
Address 0x10[7:0] section), the actual gain update speed is dictated
by the peak white AGC loop and, as a result, the LAGT settings
have no effect. As soon as the part leaves peak white AGC, LAGT
becomes relevant again.
The update speed for the peak white algorithm can be customized
by the use of internal parameters.
Description
Slow (time constant = 2 sec)
Medium (time constant = 1 sec)
Fast (time constant = 0.2 sec)
Adaptive
Read/Write
Write
Read
Description
Manual gain for luma path
Actual used gain
LMG[11 : 0]
Luma Calibration Factor
(1)
where LMG[11:0] is a decimal value between 1024 and 4095.
Calculation of the Luma Calibration Factor
1.
2.
3.
4.
Table 53. LAGT Function
LAGT[1:0]
00
01
10
11 (default)
If read back, this register returns the current gain value.
Depending on the setting in the LAGC[2:0] bits, the value is
one of the following:
Using a video source, set the content to a gray field and
apply a standard CVBS signal to the CVBS input of
the board.
Using an oscilloscope, measure the signal at the CVBS input
to ensure that its sync depth, color burst, and luma are at
the standard levels.
Connect the output of the ADV728x to a backend system
that has unity gain and monitor the output voltage.
Measure the luma level correctly from the black level. Turn
off the luma AGC and manually change the value of the luma
manual gain control register, LMG[11:0], until the output
luma level matches the input measured in Step 2.
This value, in decimal, is the luma calibration factor.
PW_UPD, Peak White Update, Address 0x2B[0]
The peak white and average video algorithms determine the
gain based on measurements taken from the active video. The
PW_UPD bit determines the rate of gain change. LAGC[2:0] must
be set to the appropriate mode to enable the peak white or average
video mode in the first place. For more information, see the
LAGC[2:0], Luma Automatic Gain Control, Address 0x2C[6:4]
section.
Setting PW_UPD to 0 updates the gain once per video line.
Setting PW_UPD to 1 (default) updates the gain once per field.
Chroma Gain
CAGC[1:0], Chroma Automatic Gain Control,
Address 0x2C[1:0]
The two bits of the color automatic gain control mode select the
basic mode of operation for the automatic gain control in the
chroma path.
Table 55. CAGC Function
CAGC[1:0]
00
01
10 (default)
11
Rev. A | Page 43 of 104
Description
Manual fixed gain (use CMG[11:0])
Use luma gain for chroma
Automatic gain (based on color burst)
Freeze chroma gain
UG-637
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
CAGT[1:0], Chroma Automatic Gain Timing,
Address 0x2D[7:6]
CKE, Color Kill Enable, Address 0x2B[6]
The color kill enable bit allows the optional color kill function
to be switched on or off.
The chroma automatic gain timing register allows the user to
influence the tracking speed of the chroma automatic gain
control. This register has an effect only if the CAGC[1:0] bits
are set to 10 (automatic gain).
For QAM-based video standards (PAL and NTSC), as well as
FM-based systems (SECAM), the threshold for the color kill
decision is selectable via the CKILLTHR[2:0] bits.
If color kill is enabled and the color carrier of the incoming
video signal is less than the threshold for 128 consecutive video
lines, color processing is switched off (black and white output).
To switch the color processing back on, another 128 consecutive
lines with a color burst greater than the threshold are required.
Table 56. CAGT Function
CAGT[1:0]
00
01
10
11 (default)
Description
Slow (time constant = 2 sec)
Medium (time constant = 1 sec)
Reserved
Adaptive
The color kill option works only for input signals with a modulated
chroma part. For component input (YPrPb), there is no color kill.
CG[11:0], Chroma Gain, Address 0x2D[3:0],
Address 0x2E[7:0];
CMG[11:0], Chroma Manual Gain, Address 0x2D[3:0],
Address 0x2E[7:0]
Set CKE to 0 to disable color kill.
Set CKE to 1 (default) to enable color kill.
CKILLTHR[2:0], Color Kill Threshold, Address 0x3D[6:4]
Chroma gain[11:0] is a dual-function register. If written to, a
desired manual chroma gain can be programmed. This gain
becomes active if the CAGC[1:0] function is switched to manual
fixed gain. See Equation 2 for calculating a desired gain.
The CKILLTHR[2:0] bits allow the user to select a threshold for
the color kill function. The threshold applies only to QAM-based
(NTSC and PAL) or FM-modulated (SECAM) video standards.
If read back, this register returns the current gain value. Depending
on the setting in the CAGC[1:0] bits, this is either:
•
•
The chroma manual gain value (CAGC[1:0] set to chroma
manual gain mode).
The chroma automatic gain value (CAGC[1:0] set to either
of the automatic modes).
Table 57. CG/CMG Function
CG[11:0]/CMG[11:0]
CMG[11:0]
CG[11:0]
Chroma_Gain ≅
Read/Write
Write
Read
Description
Manual gain for chroma path
Currently active gain
CMG[11 : 0]decimal
ChromaCalibrationFactor
(2)
where ChromaCalibrationFactor is a decimal value between 0
and 4095.
To enable the color kill function, the CKE bit must be set. For the
000, 001, 010, and 011 settings, chroma demodulation inside
the ADV728x may not work satisfactorily for poor input video
signals.
Table 58. CKILLTHR Function
CKILLTHR[2:0]
000
001
010 (default)
011
100
101
110
111
Description
NTSC, PAL
SECAM
Kill at <0.5%
No color kill
Kill at <1.5%
Kill at <5%
Kill at <2.5%
Kill at <7%
Kill at <4%
Kill at <8%
Kill at <8.5%
Kill at <9.5%
Kill at <16%
Kill at <15%
Kill at <32%
Kill at <32%
Reserved for Analog Devices internal use only;
do not select
Calculation of Chroma Calibration Factor
CHROMA TRANSIENT IMPROVEMENT (CTI)
Take the following steps to calculate the chroma calibration factor:
The signal bandwidth allocated for chroma is typically much
smaller than that for luminance. In the past, this was a valid way
to fit a color video signal into a given overall bandwidth because
the human eye is less sensitive to chrominance than to luminance.
1.
2.
3.
4.
Apply a CVBS signal with the color bars/SMPTE bars test
pattern content directly to the measurement equipment.
Ensure correct termination of 75 Ω on the measurement
equipment. Measure chroma output levels.
Reconnect the source to the CVBS input of the ADV728x
system that has a back end gain of 1. Repeat the measurement
of chroma levels.
Turn off the chroma AGC and manually change the
chroma gain control register, CMG[11:0], until the chroma
level matches that measured directly from the source.
The uneven bandwidth, however, may lead to visual artifacts in
sharp color transitions. At the border of two bars of color, both
components (luma and chroma) change at the same time (see
Figure 34). Due to the higher bandwidth, the signal transition
of the luma component is usually much sharper than that of the
chroma component. The color edge is not sharp, and in the
worst case, it can be blurred over several pixels.
This value, in decimal, is the chroma calibration factor.
Rev. A | Page 44 of 104
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
UG-637
Table 59. CTI_AB Function
DEMODULATED
CHROMA SIGNAL
ORIGINAL, SLOW CHROMA
TRANSITION PRIOR TO CTI
SHARPENED CHROMA
TRANSITION AT THE
OUTPUT OF CTI
01
10
11 (default)
11935-033
LUMA SIGNAL
CTI_AB[1:0]
00
LUMA SIGNAL WITH A
TRANSITION, ACCOMPANIED
BY A CHROMA TRANSITION
Figure 34. CTI Luma/Chroma Transition
The chroma transient improvement block examines the input video
data. It detects transitions of chroma and can be programmed to
create steeper chroma edges in an attempt to artificially restore lost
color bandwidth. The CTI block, however, operates only on edges
above a certain threshold to ensure that noise is not emphasized.
Care was taken to ensure that edge ringing and undesirable
saturation or hue distortion are avoided.
Chroma transient improvements are needed primarily for signals
that have severe chroma bandwidth limitations. For those types
of signals, it is strongly recommended to enable the CTI block
via CTI_EN.
CTI_EN, Chroma Transient Improvement (CTI) Enable,
Address 0x4D[0]
Set CTI_EN to 0 to disable the CTI block.
Description
Sharpest mixing between sharpened and
original chroma signal
Sharp mixing
Smooth mixing
Smoothest mixing between sharpened and
original chroma signal
CTI_C_TH[7:0], CTI Chroma Threshold, Address 0x4E[7:0]
The CTI_C_TH[7:0] value is an unsigned, 8-bit number specifying
how big the amplitude step in a chroma transition must be if it
is going to be steepened by the CTI block. Programming a small
value into this register causes even smaller edges to be steepened by
the CTI block. Making CTI_C_TH[7:0] a large value causes the
block to improve large transitions only.
The default value for CTI_C_TH[7:0] is 0x08.
DIGITAL NOISE REDUCTION (DNR) AND LUMA
PEAKING FILTER
Digital noise reduction is based on the assumption that high
frequency signals with low amplitude are probably noise and that
their removal, therefore, improves picture quality. The two DNR
blocks in the ADV728x are the DNR1 block before the luma
peaking filter and the DNR2 block after the luma peaking filter,
as shown in Figure 35.
Set CTI_EN to 1 (default) to enable the CTI block.
The CTI_AB_EN bit enables an alpha blend function within
the CTI block. If set to 1, the alpha blender mixes the transient
improved chroma with the original signal. The sharpness of the
alpha blending can be configured via the CTI_AB[1:0] bits.
For the alpha blender to be active, the CTI block must be enabled
via the CTI_EN bit.
Set CTI_AB_EN to 0 to disable the CTI alpha blender.
LUMA
SIGNAL
DNR1
LUMA
PEAKING
FILTER
DNR2
LUMA
OUTPUT
11935-034
CTI_AB_EN, Chroma Transient Improvement Alpha
Blend Enable, Address 0x4D[1]
Figure 35. DNR and Peaking Block Diagram
DNR and Peaking
DNR_EN, Digital Noise Reduction Enable, Address 0x4D[5]
Set CTI_AB_EN to 1 (default) to enable the CTI alpha-blend
mixing function.
The DNR_EN bit enables the DNR block or bypasses it.
CTI_AB[1:0], Chroma Transient Improvement Alpha
Blend, Address 0x4D[3:2]
Table 60. DNR_EN Function
The CTI_AB[1:0] controls the behavior of alpha blend circuitry
that mixes the sharpened chroma signal with the original one. It
thereby controls the visual impact of CTI on the output data.
For CTI_AB[1:0] to become active, the CTI block must be
enabled via the CTI_EN bit, and the alpha blender must be
switched on via CTI_AB_EN.
Sharp blending maximizes the effect of CTI on the picture;
however, it may also increase the visual impact of small amplitude,
high frequency chroma noise.
Setting
0
1 (default)
Description
Bypasses the DNR block (disable)
Enables the DNR block
DNR_TH[7:0], DNR Noise Threshold 1, Address 0x50[7:0]
The DNR1 block is positioned before the luma peaking block.
The DNR_TH[7:0] value is an unsigned, 8-bit number used to
determine the maximum edge that is interpreted as noise and,
therefore, blanked from the luma data. Programming a large value
into DNR_TH[7:0] causes the DNR block to interpret even large
transients as noise and remove them. As a result, the effect on
the video data is more visible. Programming a small value causes
only small transients to be seen as noise and to be removed.
Rev. A | Page 45 of 104
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ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
Table 61. DNR_TH[7:0] Function
DNR_TH2[7:0], DNR Noise Threshold 2, Address 0xFC[7:0]
Setting
0x08 (default)
The DNR2 block is positioned after the luma peaking block
and, therefore, affects the gained luma signal. It operates in the
same way as the DNR1 block; however, there is an independent
threshold control, DNR_TH2[7:0], for this block. This value is
an unsigned, 8-bit number used to determine the maximum
edge that is interpreted as noise and, therefore, blanked from
the luma data. Programming a large value into DNR_TH2[7:0]
causes the DNR block to interpret even large transients as noise
and remove them. As a result, the effect on the video data is more
visible. Programming a small value causes only small transients
to be seen as noise and to be removed.
Description
Threshold for maximum luma edges to be
interpreted as noise
PEAKING_GAIN[7:0], Luma Peaking Gain,
Address 0xFB[7:0]
This filter can be manually enabled. The user can select to boost
or to attenuate the midregion of the Y spectrum around 3 MHz.
The peaking filter can visually improve the picture by showing
more definition on the picture details that contain frequency
components around 3 MHz. The default value on this register
passes through the luma data unaltered. A lower value attenuates
the signal, and a higher value gains the luma signal. A plot of
the responses of the filter is shown in Figure 36.
Table 62. PEAKING_GAIN[7:0] Function
Setting
0x40 (default)
Description
0 dB response
Description
Threshold for maximum luma edges to be
interpreted as noise
The comb filters of the ADV728x can automatically handle
video of all types, standards, and levels of quality. The NTSC
and PAL configuration registers allow the user to customize the
comb filter operation depending on which video standard is
detected (by autodetection) or selected (by manual programming).
10
5
NTSC Comb Filter Settings
0
These settings are used for NTSC M/NTSC J CVBS inputs.
–5
NSFSEL[1:0], Split Filter Selection, NTSC, Address 0x19[3:2]
–10
–15
–20
0
1
2
3
4
FREQUENCY (MHz)
5
Figure 36. Peaking Filter Responses
6
7
11935-035
FILTER RESPONSE (dB)
Setting
0x04 (default)
COMB FILTERS
PEAKING GAIN USING BP FILTER
15
Table 63. DNR_TH2[7:0] Function
The NSFSEL[1:0] control selects how much of the overall signal
bandwidth is fed to the combs. A narrow split filter selection
results in better performance on diagonal lines but more dot
crawl in the final output image. The opposite is true for selecting
a wide bandwidth split filter.
Table 64. NSFSEL Function
NSFSEL[1:0]
00 (default)
01
10
11
Rev. A | Page 46 of 104
Description
Narrow
Medium
Medium
Wide
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
UG-637
CTAPSN[1:0], Chroma Comb Taps, NTSC,
Address 0x38[7:6]
YCMN[2:0], Luma Comb Mode, NTSC, Address 0x38[2:0]
Table 65. CTAPSN Function
YCMN[2:0]
000 (default)
Description
Adaptive comb mode
100
Disable luma comb
101
Fixed luma comb (top
lines of line memory)
Fixed luma comb (all
lines of line memory)
Fixed luma comb
(bottom lines of line
memory)
CTAPSN[1:0]
00
01
10 (default)
11
Table 67. YCMN Function
Description
Do not use
NTSC chroma comb adapts three lines to two lines
NTSC chroma comb adapts five lines to three lines
NTSC chroma comb adapts five lines to four lines
CCMN[2:0], Chroma Comb Mode, NTSC, Address 0x38[5:3]
Table 66. CCMN Function
CCMN[2:0]
000
(default)
100
101
Description
Adaptive comb mode
Disable chroma comb
Fixed chroma comb
(top lines of line
memory)
110
Fixed chroma comb (all
lines of line memory)
111
Fixed chroma comb
(bottom lines of line
memory)
Configuration
Three-line adaptive
chroma comb for
CTAPSN = 01
Four-line adaptive
chroma comb for
CTAPSN = 10
Five-line adaptive
chroma comb for
CTAPSN = 11
110
111
Configuration
Adaptive three-lines
(three taps) luma comb
Use low-pass/notch
filter; see the Y Shaping
Filter section
Fixed luma comb twoline (two taps)
Fixed luma comb threeline (three taps)
Fixed luma comb twoline (two taps)
PAL Comb Filter Settings
These settings are used for PAL B/PAL G/PAL H/PAL I/PAL D,
PAL M, PAL Combinational N, PAL 60, and NTSC 4.43 CVBS
inputs.
PSFSEL[1:0], Split Filter Selection, PAL, Address 0x19[1:0]
Fixed two-line chroma
comb for CTAPSN = 01
Fixed three-line chroma
comb for CTAPSN = 10
Fixed four-line chroma
comb for CTAPSN = 11
Fixed three-line chroma
comb for CTAPSN = 01
Fixed four-line chroma
comb for CTAPSN = 10
Fixed five-line chroma
comb for CTAPSN = 11
Fixed two-line chroma
comb for CTAPSN = 01
Fixed three-line chroma
comb for CTAPSN = 10
Fixed four-line chroma
comb for CTAPSN = 11
The PSFSEL[1:0] control selects how much of the overall signal
bandwidth is fed to the combs. A wide split filter selection
eliminates dot crawl but shows imperfections on diagonal lines.
The opposite is true for selecting a narrow bandwidth split filter.
Table 68. PSFSEL Function
PSFSEL[1:0]
00
01 (default)
10
11
Description
Narrow
Medium
Wide
Widest
CTAPSP[1:0], Chroma Comb Taps, PAL, Address 0x39[7:6]
Table 69. CTAPSP Function
CTAPSP[1:0]
00
01
10
11 (default)
Rev. A | Page 47 of 104
Description
Do not use
PAL chroma comb adapts five lines (three taps)
to three lines (two taps); cancels cross luma only
PAL chroma comb adapts five lines (five taps) to
three lines (three taps); cancels cross luma and
hue error less well
PAL chroma comb adapts five lines (five taps) to
four lines (four taps); cancels cross luma and hue
error well
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
CCMP[2:0], Chroma Comb Mode, PAL, Address 0x39[5:3]
IF FILTER COMPENSATION
Table 70. CCMP Function
IFFILTSEL[2:0], IF Filter Select, Address 0xF8[2:0]
110
111
Disable chroma comb
Fixed chroma comb
(top lines of line
memory)
Fixed chroma comb (all
lines of line memory)
Fixed chroma comb
(bottom lines of line
memory)
The IFFILTSEL[2:0] register allows the user to compensate for
SAW filter characteristics on a composite input, as would be
observed on tuner outputs. Figure 37 and Figure 38 show IF
filter compensation for NTSC and PAL, respectively.
Configuration
Adaptive three-line
chroma comb for
CTAPSN = 01
Adaptive four-line
chroma comb for
CTAPSN = 10
Adaptive five-line
chroma comb for
CTAPSN = 11
The options for this feature are as follows:
•
•
•
Fixed two-line chroma
comb for CTAPSN = 01
Fixed three-line chroma
comb for CTAPSN = 10
Fixed four-line chroma
comb for CTAPSN = 11
Fixed three-line chroma
comb for CTAPSN = 01
Fixed four-line chroma
comb for CTAPSN = 10
Fixed five-line chroma
comb for CTAPSN = 11
Fixed two-line chroma
comb for CTAPSN = 01
Fixed three-line chroma
comb for CTAPSN = 10
Fixed four-line chroma
comb for CTAPSN = 11
Bypass mode
NTSC, consisting of three filter characteristics
PAL, consisting of three filter characteristics
See Table 104 for programming details.
6
4
2
0
–2
–4
–6
–8
–10
–12
2.0
6
Table 71. YCMP Function
4
101
110
111
Disable luma comb
Fixed luma comb (top
lines of line memory)
Fixed luma comb (all
lines of line memory)
Fixed luma comb
(bottom lines of line
memory)
Configuration
Adaptive five lines (three
taps) luma comb
Use low-pass/notch filter;
see the Y Shaping Filter
section
Fixed three lines (two
taps) luma comb
Fixed five lines (three taps)
luma comb
Fixed three lines (two
taps) luma comb
3.0
3.5
4.0
FREQUENCY (MHz)
4.5
5.0
6.0
IF COMP FILTERS PAL ZOOMED AROUND fSC
2
AMPLITUDE (dB)
100
Description
Adaptive comb mode
2.5
Figure 37. NTSC IF Filter Compensation
YCMP[2:0], Luma Comb Mode, PAL, Address 0x39[2:0]
YCMP[2:0]
000 (default)
IF COMP FILTERS NTSC ZOOMED AROUND FSC
11935-036
100
101
Description
Adaptive comb mode
AMPLITUDE (dB)
CCMP[2:0]
000 (default)
11935-037
UG-637
0
–2
–4
–6
–8
3.0
3.5
4.0
4.5
5.0
FREQUENCY (MHz)
Figure 38. PAL IF Filter Compensation
Rev. A | Page 48 of 104
5.5
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
UG-637
ADAPTIVE CONTRAST ENHANCEMENT (ACE)
Table 73. Register Writes to Disable the ACE Function
The ADV728x can increase the contrast of an image depending
on the content of the picture, allowing bright areas to be made
brighter and dark areas to be made darker. The optional ACE
feature allows for the contrast within dark areas to be increased
without significantly affecting the bright areas. The ACE feature
is particularly useful in automotive applications, where it can be
important to be able to discern objects in shaded areas.
Register
Map
User Sub
Map (0x40 or
0x42)
User Sub
Map 2 (0x40
or 0x42)
User Sub
Map 2 (0x40
or 0x42)
The ACE function is disabled by default. To enable the ACE
function, execute the register writes shown in Table 72. To
disable the ACE function, execute the register writes shown in
Table 73.
The ACE feature works by sampling the chroma and luma levels
in the input image. This information is then histogrammed, and
the resulting correction is applied to the entire image. This
correction is done in a nonlinear fashion so that more correction
can be applied to dark areas, if required.
For normal use, the luma and chroma gain controls can be
used; however, in automotive applications, where dark areas
may need to be further enhanced, the gamma gain controls are
also used.
The reaction time of the ACE function can be set using the
ACE_RESPONSE_SPEED[7:4] bits (see Table 105). The corrected
image is faded over the original image using alpha blending,
giving a gradual change in contrast with scene changes. The ACE_
RESPONSE_SPEED[7:4] bits determine the duration of the
transition from the original to the corrected image. A larger value
for these bits results in a faster transition time; however, a smaller
value gives more stability to rapid scene changes.
The ACE_CHROMA_MAX[7:4] bits are used to set a
maximum value that clips the chroma gain regardless of
the ACE_CHROMA_GAIN[3:0] settings.
Register Map
User Sub Map
(0x40 or 0x42)
User Sub Map 2
(0x40 or 0x42)
User Sub Map 2
(0x40 or 0x42)
Register
Address
0x0E
Register
Write
0x40
0x80
0x80
0x0E
0x00
Description
Enter User Sub Map
2
Enable ACE
Description
Enter User Sub Map 2
0x80
0x00
Disable ACE
0x0E
0x00
Reenter User Sub Map
ACE_ENABLE, User Sub Map 2, Address 0x80[7]
This control enables ACE.
Table 74. ACE_ENABLE Function
ACE_ENABLE
0 (default)
1
Description
Disable ACE
Enable ACE
ACE_LUMA_GAIN[4:0], User Sub Map 2, Address 0x83[4:0]
This is a control to set the auto-contrast level for the luma channel
when ACE_ENABLE is set to 1.
Table 75. ACE_LUMA_GAIN Function
ACE_LUMA_GAIN[4:0]
00000
11111
Table 72. Register Writes to Enable the ACE Function
Register
Write
0x40
Note that the I2C registers that control the ACE operation of the
ADV728x are contained in the User Sub Map 2. See the Power
Supply Requirements section for information on how to
program the ADV728x into User Sub Map 2.)
01101 (default)
The ACE_GAMMA_GAIN[3:0] bits are particularly useful in
automotive applications because they allow dramatic image
enhancement in dark regions by stretching the contrast of pixels
at the low (dark) values of the image histogram. The luma
and chroma gain controls are normally used; however, the
ACE_GAMMA_GAIN[3:0] bits should be used when further
stretching of the contrast in the dark areas of an image is needed.
Register
Address
0x0E
Description
Set ACE luma auto-contrast level to
minimum value
Set ACE luma auto-contrast level to
default value
Set ACE luma auto-contrast level to
maximum value
ACE_RESPONSE_SPEED[3:0], User Sub Map 2,
Address 0x85[7:4]
This control sets the reaction time of the ACE function.
Table 76. ACE_RESPONSE_SPEED Function
ACE_ RESPONSE_SPEED[3:0]
0000
1111 (default)
Reenter User Sub
Map
Rev. A | Page 49 of 104
Description
Set speed of ACE response to
slowest value
Set speed of ACE response to
fastest value
UG-637
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
ACE_CHROMA_GAIN[3:0], User Sub Map 2,
Address 0x84[3:0]
BR_DITHER_MODE, User Sub Map 2, Address 0x92[0]
This control sets the color saturation level for the color channels
when ACE_ENABLE is set to 1.
BR_DITHER_MODE is contained in the I2C map User Sub
Map 2. See the Register Maps section for a description of how to
enter User Sub Map 2.
Table 77. ACE_CHROMA_GAIN Function
Table 80. BR_DITHER_MODE Function
ACE_CHROMA_GAIN[3:0]
0000
BR_DITHER_MODE
0 (default)
1
1000 (default)
1111
Description
Set ACE color auto-saturation level
to minimum value
Set ACE color auto-saturation level
to default value
Set ACE color auto-saturation level
to maximum value
ACE_CHROMA_MAX[3:0], User Sub Map 2,
Address 0x84[7:4]
This control sets a maximum threshold value that clips the
chroma gain regardless of the ACE_CHROMA_GAIN[3:0]
settings.
Table 78. ACE_CHROMA_MAX Function
ACE_CHROMA_MAX[3:0]
0000
1000 (default)
Description
Set maximum threshold for ACE
color auto-saturation level to
minimum value
Set maximum threshold for ACE
color auto-saturation level to
default value
Set maximum threshold for ACE
color auto-saturation level to
maximum value
The script described in Table 81 and Table 82 explains how to
enable and disable the 8-bit to 6-bit down dither function.
Table 81. Register Writes to Enable the Dither Function
Register
Map
User Sub
Map (0x40 or
0x42)
User Sub
Map 2 (0x40
or 0x42)
User Sub
Map 2 (0x40
or 0x42)
Register
Address
0x0E
Register
Write
0x40
0x92
0x07
Enable 8-bit to 6-bit
down dither
0x0E
0x00
Reenter User Sub Map
This control provides further contrast enhancement to the luma
and chroma gain controls and is particularly effective in the darker
areas of an image.
Table 79. ACE_GAMMA_GAIN[3:0] Function
I2P FUNCTION
ACE_GAMMA_GAIN[3:0], User Sub Map 2,
Address 0x85[3:0]
ACE_GAMMA_GAIN[3:0]
0000
1000 (default)
1111
Description
Set further contrast enhancement
to minimum value
Set further contrast enhancements
to default value
Set further contrast enhancement
to maximum value
DITHER FUNCTION
The dither function converts the digital output of the ADV728x
from 8-bit pixel data down to 6-bit pixel data. This function makes
it easier for the ADV728x to communicate with some LCD panels.
The dither function is turned off by default. It is activated by the
BR_DITHER_MODE bit.
Description
Enter User Sub Map 2
Table 82. Register Writes to Disable the Dither Function
Register
Map
User Sub
Map (0x40 or
0x42)
User Sub
Map 2 (0x40
or 0x42)
User Sub
Map 2 (0x40
or 0x42)
1111
Description
8-bit to 6-bit down dither disabled
8-bit to 6-bit down dither enabled
Register
Address
0x0E
Register
Write
0x40
0x92
0x06
Disable 8-bit to 6-bit
down dither
0x0E
0x00
Reenter User Sub Map
Description
Enter User Sub Map 2
This section applies only to the ADV7280, ADV7280-M,
ADV7282, ADV7282-M, and ADV7283 models.
The interlaced-to-progressive (I2P) function converts an
interlaced video input into a progressive video output. This
function is performed without the need for external memory.
Edge adaptive technology is used to minimize video defects on
low angle lines.
The I2P function is disabled by default. To enable the I2P
function, see the Analog Devices’ recommended scripts
available online.
Rev. A | Page 50 of 104
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
UG-637
OUTPUT VIDEO FORMAT
All ADV728x devices (MIPI CSI-2 or TTL output models)
output video data in YCbCr 4:2:2 format. The video timing is
compliant with the ITU-R BT.656-3 or ITU-R BT.656-4
standards.
The following bits modify the video output of all ADV728x
models. More output controls can be found in the ITU-R
BT.656 Output section and MIPI CSI-2 Tx Output section.
OUTPUT FORMAT CONTROL
BT.656-4, User Map, Address 0x04[7]
The BT.656-4 bit allows the user to select an output mode
compatible with the ITU-R BT.656-3 or ITU-R BT.656-4
standard.
When the BT.656-4 bit equals 0 (default), the ADV728x-T
outputs video that is compatible with the ITU-R BT.656-3
standard.
SWAP COLOR OUTPUT
SWPC, Swap Pixel Cr/Cb, Address 0x27[7]
This bit allows Cr and Cb output samples to be swapped. This
bit affects ADV728x-T and ADV728x-M models.
When SWPC is 0 (default), no swapping is allowed.
When SWPC is 1, the Cr and Cb output values are swapped.
When the BT.656-4 bit equals 1, the ADV728x-T outputs video
that is compatible with the ITU-R BT.656-4 standard.
Note the BT.656-4 bit also affects the MIPI CSI-2 active video
output resolution from ADV728x-M parts. Table 83 shows all
the possible active video output resolutions from the
ADV728x-T and ADV728x-M parts.
Note that events such as video source disconnection/
reconnection can cause the ADV728x to output nonstandard
line lengths during the event.
Table 83. Output Resolution from the ADV728x
Digital
Format
480i
Even/Odd
Frames
Even frames
Odd frames
Active Video Output Resolution in BT.656-3 Mode
(BT.656-4 bit equal to 0)
720 × 253
720 × 254
Active Video Output Resolution in BT.656-4 Mode
(BT.656-4 bit equal to 1)
720 × 243
720 × 244
480p
Even frames
Odd frames
720 × 507
720 × 507
720 × 487
720 × 487
576i
Even frames
Odd frames
720 × 288
720 × 288
720 × 288
720 × 288
576p
Even frames
Odd frames
720 × 576
720 × 576
720 × 576
720 × 576
Rev. A | Page 51 of 104
UG-637
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
ITU-R BT.656 OUTPUT
This section applies to the ADV728x-T models only (ADV7280,
ADV7281, ADV7282, and ADV7283 models).
The ADV728x-T receives analog video and outputs digital
video according to the ITU-R BT.656 specification. The
ADV728x-T outputs the ITU-R BT.656 video data stream over
the P0 to P7 data pins and has a line-locked clock (LLC) pin.
Video data is output over the P0 to P7 pins in YCrCb 4:2:2 format.
Synchronization signals are automatically embedded in the video
data signal in accordance with the ITU-R BT.656 specification.
Two synchronization pins (HS and VS/FIELD/SFL) are available
on the ADV7280 model. The two synchronization pins are not
available on the ADV7281, ADV7282, and ADV7283 models.
The two synchronization pins (HS and VS/FIELD/SFL) output a
variety of synchronization signals such as horizontal sync, vertical
sync, field sync, and color subcarrier frequency lock (SFL) sync.
The majority of these synchronization signals are already
embedded in the video data. Therefore, the use of the
synchronization pins is optional.
The LLC output is used to clock the output data on the P0 to P7
pins at a nominal frequency of 27 MHz.
VIDEO
DECODER
P0
P1
P2
P3
ANALOG
FRONT
END
STANDARD
DEFINITION
PROCESSOR
P4
P5
P6
P7
LLC
HS
(ADV7280 ONLY)
VS/FIELD/SFL
(ADV7280 ONLY)
Figure 39. ITU-R BT.656 Output Stage of the ADV728x-T
Rev. A | Page 52 of 104
11935-038
ANALOG
VIDEO
INPUT
ITU-R BT.656
DATA
STREAM
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
ITU-R BT.656 OUTPUT CONTROL REGISTERS
VS/FIELD/SFL Sync Mux Selection
The following are controls for the ITU-R BT.656 output for the
ADV728x-T models. See the Global Control Registers for
further control registers.
FLD_OUT_SEL[2:0], Address 0x6B[2:0]
Tristate Output Drivers
This section applies only to the ADV728x-T models (ADV7280,
ADV7281, ADV7282, and ADV7283 models).
TOD, Address 0x03[6]
This bit allows the user to tristate the output drivers of the
ADV7280.
UG-637
This section applies only to the ADV7280 model.
The FLD_OUT_SEL[2:0] bits select whether the VS/FIELD/
SFL pin outputs vertical sync, horizontal sync, field sync, data
enable (DE), or subcarrier frequency lock (SFL) signals.
Note that the VS/FIELD/SFL pin must be active for this
selection to occur. See the ITU-R BT.656 Output Control
Registers section for more information.
Table 84. FLD_OUT_SEL Function
Upon setting the TOD bit, the P7 to P0, HS, and VS/FIELD/SFL
pins are tristated.
The timing pins (HS and VS/FIELD/SFL pins) can be forced
active via the TIM_OE bit. Note the HS and VS/FIELD/SFL
pins are only available on the ADV7280 model.
When TOD is set to 0, the output drivers are enabled.
When TOD is set to 1(default), the output drivers are tristated.
FLD_OUT_SEL[2:0]
000
001
010 (default)
011
Description
The VS/FIELD/SFL pin outputs horizontal
sync information.
The VS/FIELD/SFL pin outputs vertical sync
information.
The VS/FIELD/SFL pin outputs field sync
information.
The VS/FIELD/SFL pin outputs data enable
(DE) information.
The VS/FIELD/SFL pin outputs subcarrier
frequency lock information.
Tristate LLC Driver
100
This section applies only to the ADV728x-T models (ADV7280,
ADV7281, ADV7282, and ADV7283 models).
HS Sync Mux Selection
TRI_LLC, Address 0x1D[7]
This section applies only to the ADV7280 model.
This bit allows the output drivers for the LLC pin of the
ADV728x-T to be tristated.
HS_OUT_SEL[2:0], Address 0x6A[2:0]
When TRI_LLC is set to 0, the LLC pin drivers work according to
the DR_STR_C[1:0] setting (pin enabled).
When TRI_LLC is set to 1 (default), the LLC pin drivers are
tristated.
The HS_OUT_SEL[2:0] bits allow the user to change the operation
of the HS pin. The HS pin is set to output horizontal sync signals as
the default. The user can also set the HS pin to output vertical
sync, field sync, data enable (DE), or subcarrier frequency lock
(SFL) information.
Note that the HS pin must be active for this selection to occur.
See the ITU-R BT.656 Output Control Registers section for
more information.
Timing Signals Output Enable
This section applies only to the ADV7280 model.
TIM_OE, Address 0x04[3]
The TIM_OE bit should be regarded as an addition to the TOD bit.
Setting it high forces the output drivers for HS, VS/FIELD/SFL into
the active state (that is, driving state) even if the TOD bit is set. If
TIM_OE is set to low, the HS and VS/FIELD/SFL pins are tristated
depending on the TOD bit. This functionality is beneficial if the
decoder is used only as a timing generator. This may be the case
if only the timing signals are extracted from an incoming signal or
if the part is in free-run mode, where a separate chip can output
a company logo, for example.
Table 85. HS_OUT_SEL Function
HS_OUT_SEL[2:0]
000 (default)
001
010
011
100
When TIM_OE is set to 0 (default), HS and VS/FIELD/SFL are
tristated according to the TOD bit.
When TIM_OE is set to 1, HS and VS/FIELD/SFL are forced
active all the time.
Rev. A | Page 53 of 104
Description
The HS pin output horizontal sync information.
The HS pin outputs vertical sync information.
The HS pin outputs field sync information.
The HS pin outputs data enable (DE)
information.
The HS pin outputs subcarrier frequency
lock (SFL) information.
UG-637
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
Drive Strength Selection (Data)
Enable Subcarrier Frequency Lock Pin
This section applies only to the ADV728x-T models (ADV7280,
ADV7281, ADV7282, and ADV7283 models).
This section applies only to the ADV7280 model.
DR_STR[1:0], Address 0xF4[5:4]
The EN_SFL_PIN bit enables the output of subcarrier lock
information (also known as genlock) from the ADV7280 core
to an encoder in a decoder/encoder back-to-back arrangement.
For EMC and crosstalk reasons, it may be desirable to strengthen or
weaken the drive strength of the output drivers. The DR_STR[1:0]
bits affect the drive strength for the pixel output pins (P[7:0])
and the timing pins (HS and VS/FIELD/SFL). Note the HS and
VS/FIELD/SFL pins are only available on the ADV7280 model.
Table 86. DR_STR Function
DR_STR[1:0]
00
01 (default)
10
11
1
Description
Low drive strength (1×)1
Medium low drive strength (2×)
Medium high drive strength (3×)
High drive strength (4×)
EN_SFL_PIN, Address 0x04[1]
When the EN_SFL_PIN is set to 0 (default), the subcarrier
frequency lock output is disabled.
When EN_SFL_PIN is set to 1, the subcarrier frequency lock
information is presented on the SFL pin.
Polarity LLC Pin
This section applies only to the ADV728x-T models (ADV7280,
ADV7281, ADV7282, and ADV7283 models).
PCLK, Address 0x37[0]
The low drive strength setting is not recommended for the optimal
performance of the ADV728x.
Drive Strength Selection (Clock)
This section applies only to the ADV728x-T models (ADV7280,
ADV7281, ADV7282, and ADV7283 models).
DR_STR_C[1:0], Address 0xF4[3:2]
The DR_STR_C[1:0] bits can be used to select the strength of
the clock signal output driver (LLC pin).
The polarity of the clock that leaves the ADV728x-T via the
LLC pin can be inverted using the PCLK bit. Changing the
polarity of the LLC clock output may be necessary to meet the
setup-and-hold time expectations of follow-on chips.
When PCLK is set to 0, the LLC output polarity is inverted.
When PCLK is set to 1 (default), the LLC output polarity is
normal.
Table 87. DR_STR_C Function
DR_STR_C[1:0]
00
01 (default)
10
11
1
Description
Low drive strength (1×)1
Medium low drive strength (2×)
Medium high drive strength (3×)
High drive strength (4×)
The low drive strength setting is not recommended for the optimal
performance of the ADV728x.
Rev. A | Page 54 of 104
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
UG-637
MIPI CSI-2 Tx OUTPUT
The ADV728x-M outputs video data in an 8-bit YCrCb 4:2:2
format. When the I2P core is disabled, the video data is output
in an interlaced format at a nominal data rate of 216 Mbps. When
the I2P core is enabled, the video data is output in a progressive
format at a nominal data rate of 432 Mbps. Note the progressive
MIPI output is only available on the ADV7280-M and
ADV7282-M models.
This section applies to the ADV728x-M models only
(ADV7280-M, ADV7281-M, ADV7281-MA, and ADV7282-M
models).
The decoder in the ADV728x-M outputs an ITU-R BT.656
data stream. The ITU-R BT.656 data stream is connected into a
CSI-2 Tx module. Data from the CSI-2 Tx module is fed into a
D-PHY physical layer and output serially from the device.
ULTRALOW POWER STATE
The output of the ADV728x-M consists of a single data channel
on the D0P and D0N lanes and a clock channel on the CLKP
and CLKN lanes.
The ADV728x-M MIPI Tx can be programmed to enter the
ultralow power state (ULPS) by the CSITX_PWRDN bit (CSI
MAP, Address 0x00[7]). In this mode, the MIPI clock and data
lanes transition to VOL and do not oscillate.
Video data and ancillary data is output over the data lanes in
high speed mode. The data lanes enter a low power mode
during the horizontal and vertical blanking periods.
Alternatively, the MIPI clock and data lanes can be
programmed to enter the ULPS state separately using the
ESC_MODE_EN_CLK, ESC_XSHUTDOWN_CLK,
ESC_MODE_EN_D0, and ESC_XSHUTDOWN_D0 bits.
D0P
(1 BIT)
CSI Tx DATA
OUTPUT (8 BITS)
ANALOG
VIDEO
INPUT
VIDEO
DECODER
ITU-R BT.656
DATA
STREAM
CSI-2
Tx
DATA LANE LP
SIGNALS (2 BITS)
D0N
(1 BIT)
D-PHY
Tx
CLOCK LANE LP
SIGNALS (2 BITS)
CLKP
(1 BIT)
CLKN
(1 BIT)
11935-039
The clock lanes are used to clock the output video. After the
ADV728x-M is programmed, the clock lanes exit low power
mode and remain in high speed mode until the part is reset
or powered down.
Figure 40. MIPI CSI-2 Output Stage of ADV728x-M
Table 88. CSITX_PWRDN Function
CSITX_PWRDN (CSI MAP, Address 0x00[7])
0
1 (default)
Description
Power up CSI output block. The clock and data lanes output the ultralow power state
exit sequence, and then exit the ultralow power state.
Power down CSI output block.
The clock and data lanes output the ultralow power state entry sequence and then
enter ultralow power state.
ESC_MODE_EN_D0, User Sub Map, Address 0x26[7] and ESC_XSHUTDOWN_D0, User Sub Map, Address 0x26[6]
The MIPI CSI-2 Data lanes (D0P and D0N) can be programmed to enter and exit the ultralow power state (ULPS) using the
ESC_MODE_EN_D0 and ESC_XSHUTDOWN_D0 bits.
To make the data lanes enter the ULPS state, the writes listed in Table 89 are needed.
Table 89. Writes to Force MIPI Data Lanes (D0Pand D0N) to Enter Ultralow Power State
Order of
Reads/Writes
1st Write
2nd Write
ESC_MODE_EN_D0
(User Sub Map, Address 0x26[7])
0
1
ESC_XSHUTDOWN_D0
(User Sub Map, Address 0x26[7])
0
0
To make the data lanes exit the ULPS state, the writes listed in Table 90 are needed.
Rev. A | Page 55 of 104
Description
Normal operation.
The ULPS entry sequence is transmitted and
then DOP and D0N enter ULPS state. DOP and
D0N go to VOL.
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ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
Table 90. Writes to Force MIPI Data Lanes (D0P and D0N) to Exit Ultralow Power State
Order of
Reads/Writes
Read
1st Write
ESC_MODE_EN_D0
(User Sub Map, Address 0x26[7])
1
1
ESC_XSHUTDOWN_D0
(User Sub Map, Address 0x26[7])
0
1
2nd Write
3rd Write
0
0
1
0
Description
Data lanes in ULPS state.
The ULPS exit sequence is transmitted and
then DOP and D0N exit ULPS state. DOP and
D0N go to VOH.
Data lanes enter normal operation.
No change. Data lanes remain in normal
operation.
ESC_MODE_EN_CLK, User Sub Map, Address 0x26[5] and ESC_XSHUTDOWN_CLK, User Sub Map, Address 0x26[4]
The MIPI CSI-2 clock lanes (CLKP and CLKN) can be programmed to enter and exit the ultralow power state using the
ESC_MODE_EN_D0 and ESC_XSHUTDOWN_D0 bits.
To make the data lanes enter the ULPS state, the writes listed in Table 91 are needed.
Table 91. Writes to Force MIPI Clock Lanes (CLKP and CLKN) to Enter Ultralow Power State
Order of
Reads/Writes
1st Write
2nd Write
ESC_MODE_EN_CLK
(User Sub Map, Address 0x26[5])
0
1
ESC_XSHUTDOWN_CLK
(User Sub Map, Address 0x26[4])
0
0
Description
Normal operation.
The ULPS entry sequence is transmitted and
then CLKP and CLKN enter ULPS state. CLKP
and CLKN go to VOL..
To make the data lanes exit the ULPS state, the writes listed in Table 92 are needed.
Table 92. Writes to Force MIPI Clock Lanes (CLKP and CLKN) to Exit Ultralow Power State
Order of
Reads/Writes
Read
1st Write
ESC_MODE_EN_CLK
(User Sub Map, Address 0x26[5] )
1
1
ESC_XSHUTDOWN_D0
(User Sub Map, Address 0x26[4])
0
1
2nd Write
3rd Write
0
0
1
0
Rev. A | Page 56 of 104
Description
Clock lanes in ULPS state.
The ULPS exit sequence is transmitted and
then CLKP and CLKN exit ULPS state. CLKP
and CLKN go to VOH.
Clock lanes enter normal operation.
No change. Clock lanes remain in normal
operation.
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
UG-637
I2C PORT DESCRIPTION
The ADV728x supports a 2-wire (I2C compatible) serial
interface. Two inputs, serial data (SDATA) and serial clock
(SCLK), carry information between the ADV728x and the
system I2C master controller. The ADV728x I2C port allows
the user to set up and configure the decoder and to read back
captured VBI data.
The ADV728x has a number of possible I2C slave addresses and
subaddresses (see the Register Maps section). The ADV728x Main
Map has four possible slave addresses for read and write operations
depending on the logic level of the ALSB pin (see Table 93).
Table 93. Main I2C Address for ADV728x
ALSB Pin
0
0
1
1
R/W Bit
0
1
0
1
Slave Address
0x40 (write)
0x41 (read)
0x42 (write)
0x43 (read)
The ADV728x ALSB pin controls Bit 1 of the slave address. By
changing the logic level of the ALSB pin, it is possible to control
two ADV728x devices in an application without using the same I2C
slave address. The LSB (Bit 0) specifies either a read or write
operation: Logic 1 corresponds to a read operation and Logic 0
corresponds to a write operation.
To control the device on the bus, a specific protocol is followed:



The master initiates a data transfer by establishing a start
condition, which is defined as a high-to-low transition on
SDATA while SCLK remains high, and indicates that an
address/data stream follows.
All peripherals respond to the start condition and shift the
next eight bits (the 7-bit address plus the R/W bit).
The bits are transferred from MSB to LSB.
The peripheral that recognizes the transmitted address
responds by pulling the data line low during the ninth clock
pulse; this is known as an acknowledge (ACK) bit.

All other devices withdraw from the bus and maintain an
idle condition. In the idle condition, the device monitors the
SDATA and SCLK lines for the start condition and the
correct transmitted address.
The R/W bit determines the direction of the data. Logic 0 on the
LSB of the first byte means that the master writes information
to the peripheral. Logic 1 on the LSB of the first byte means that
the master reads information from the peripheral.
The ADV728x acts as a standard I2C slave device on the bus.
The data on the SDATA pin is eight bits long, supporting the 7-bit
address plus the R/W bit. The device has subaddresses to enable
access to the internal registers; therefore, it interprets the first
byte as the device address and the second byte as the starting
subaddress. The subaddresses auto-increment, allowing data to
be written to or read from the starting subaddress. A data transfer
is always terminated by a stop condition. The user can also
access any unique subaddress register individually without
updating all the registers.
Stop and start conditions can be detected at any stage during the
data transfer. If these conditions are asserted out of sequence with
normal read and write operations, they cause an immediate jump
to the idle condition. During a given SCLK high period, the user
should issue only one start condition, one stop condition, or a
single stop condition followed by a single start condition. If an
invalid subaddress is issued by the user, the ADV728x does not
issue an acknowledge and returns to the idle condition.
If the highest subaddress is exceeded in auto-increment mode,
the following action is taken:


In read mode, the highest subaddress register contents
continue to be output until the master device issues a no
acknowledge, which indicates the end of a read. A no
acknowledge condition occurs when the SDATA line is not
pulled low on the ninth pulse.
In write mode, the data for the invalid byte is not loaded
into a subaddress register. A no acknowledge is issued by the
ADV728x, and the part returns to the idle condition.
Rev. A | Page 57 of 104
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ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
SCLK
S
1–7
8
9
1–7
8
9
START ADDR R/W ACK SUBADDRESS ACK
1–7
DATA
8
9
P
ACK
STOP
11935-040
SDATA
Figure 41. Bus Data Transfer
S SLAVE ADDR A(S) SUBADDRESS A(S)
DATA
LSB = 0
READ
SEQUENCE
DATA
A(S) P
LSB = 1
S SLAVE ADDR A(S) SUBADDRESS A(S) S
S = START BIT
P = STOP BIT
A(S)
SLAVE ADDR A(S)
A(S) = ACKNOWLEDGE BY SLAVE
A(M) = ACKNOWLEDGE BY MASTER
DATA
A(M)
A(S) = NO ACKNOWLEDGE BY SLAVE
A(M) = NO ACKNOWLEDGE BY MASTER
Figure 42. Read and Write Sequence
Rev. A | Page 58 of 104
DATA
A(M) P
11935-041
WRITE
SEQUENCE
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
UG-637
REGISTER MAPS
Interrupt/VDP Sub Map
The ADV728x contains three register maps: the main register
map, the VPP register map, and the CSI register map. The Main
Map contains three sub maps: the User Sub Map, the Interrupt/
VDP Sub Map, and User Sub Map 2 (see Figure 43).
The Interrupt/VDP Sub Map contains registers that can be used
to program internal interrupts, control the INTRQ pin, and
decode vertical blanking interval (VBI) data.
Main Map
The I2C slave address of the Main Map of the ADV728x is set
by the ALSB pin (see Table 93). The Main Map allows the user to
program the I2C slave addresses of the VPP and CSI Maps. The
Main Map contains three sub maps: the User Sub Map, the
Interrupt/VDP Sub Map, and User Sub Map 2. These three sub
maps are accessed by writing to the SUB_USR_EN bits
(Address 0x0E[6:5]) within the Main Map (see Figure 43).
User Sub Map
The User Sub Map contains registers that program the analog
front end and digital core of the ADV728x. The User Sub Map
has the same I2C slave address as the Main Map. To access the
User Sub Map, set the SUB_USR_EN bits in the Main Map
(Address 0x0E[6:5]) to 00.
User Sub Map 2
User Sub Map 2 contains registers that control the ACE, down
dither, and fast lock functions. It also contains controls that set the
acceptable input luma and chroma limits before the ADV728x
enters free run and color kill modes.
User Sub Map 2 has the same I2C slave address as the Main
Map. To access User Sub Map 2, set the SUB_USR_EN bits in the
Main Map (Address 0x0E[6:5]) to 10.
VPP MAP
MAIN MAP
DEVICE ADDRESS
ALSB PIN HIGH
WRITE: 0x42
READ: 0x43
0x0E[6:5] = 00
0x0E[6:5] = 01
0x0E[6:5] = 10
USER
SUB MAP
INTERRUPT/VDP
SUB MAP
USER SUB
MAP 2
WRITE: 0x84 (RECOMMENDED
READ: 0x85 SETTINGS)
VPP MAP DEVICE ADDRESS IS
PROGRAMMABLE AND SET BY
REGISTER 0xFD IN THE USER
SUB MAP
CSI MAP
DEVICE ADDRESS
WRITE: 0x88 (RECOMMENDED
READ: 0x89 SETTINGS)
CSI MAP ADDRESS IS
PROGRAMMABLE AND SET BY
REGISTER 0xFE IN THE USER
SUB MAP
11935-042
DEVICE ADDRESS
ALSB PIN LOW
WRITE: 0x40
READ: 0x41
The Interrupt/VDP Sub Map has the same I2C slave address
as the Main Map. To access the Interrupt/VDP Sub Map, set the
SUB_USR_EN bits in the Main Map (Address 0x0E[6:5]) to 01.
NOTES
1. CSI MAP ONLY APPLIES TO THE ADV7282-M MODEL.
Figure 43. Register Map and Sub Map Access
Rev. A | Page 59 of 104
UG-637
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
Table 94. I2C Register Map and Sub Map Addresses
R/W Bit
ALSB Pin
0
0
0
0
0
0
1
1
1
1
1
1
N/A
N/A
N/A
N/A
0 (write)
1 (read)
0 (write)
1 (read)
0 (write)
1 (read)
0 (write)
1 (read)
0 (write)
1 (read)
0 (write)
1 (read)
0 (write)
1 (read)
0 (write)
1 (read)
SUB_USR_EN Bits
(Address 0x0E[6:5])
00
00
01
01
10
10
00
00
01
01
10
10
N/A
N/A
N/A
N/A
Slave Address
0x40
0x41
0x40
0x41
0x40
0x41
0x42
0x43
0x42
0x43
0x42
0x43
0x88
0x89
0x84
0x85
Register Map or Sub Map
User Sub Map
User Sub Map
Interrupt/VDP Sub Map
Interrupt/VDP Sub Map
User Sub Map 2
User Sub Map 2
User Sub Map
User Sub Map
Interrupt/VDP Sub Map
Interrupt/VDP Sub Map
User Sub Map 2
User Sub Map 2
CSI Map
CSI Map
VPP Map
VPP Map
VPP Map
SUB_USR_EN Bits, Address 0x0E[6:5]
Note that the VPP Map applies only to the ADV7280,
ADV7280-M, ADV7282-M, and ADV7283 models.
The ADV728x Main Map contains three sub maps: the User
Sub Map, the Interrupt/VDP Sub Map, and the User Sub Map 2
(see Figure 43). The User Sub Map is available by default. The
other two sub maps are accessed using the SUB_USR_EN bits.
When programming of the interrupt/VDP map or User Sub
Map 2 is completed, it is necessary to write to the
SUB_USR_EN bits to return to the User Sub Map.
The video postprocessor (VPP) map contains registers that
control the I2P core (interlaced-to-progressive converter).
The VPP map has a programmable I2C slave address, which is
programmed using Register 0xFD in the User Sub Map of the
Main Map. The default value for the VPP map address is 0x00;
however, the VPP map cannot be accessed until the I2C slave
address is set. The recommended I2C slave address for the VPP
map is 0x84.
To reset the I2C slave address of the VPP map, write to the
VPP_SLAVE_ADDRESS[7:1] bits in the main register map
(Address 0xFD[7:1]). Set these bits to a value of 0x84 (I2C write
address; I2C read address is 0x85).
CSI Map
VPP_SLAVE_ADDRESS, Program VPP Register Map
Address, User Map, Address 0xFD[7:1]
Table 95. Program VPP Register Map Address
VPP_SLAVE_ADDRESS [7:1]
0000000 (default)
10000100 (recommended)
This section applies only to the ADV7280-M, ADV7281-M,
ADV7281-MA, and ADV7282-M models.
Description
When set to this value, the VPP
register map cannot be written
to or read from.
This sets the VPP register map
to a write address of 0x84 and a
read address of 0x85. This is the
recommended setting.
The camera serial interface (CSI) map contains registers that
control the MIPI CSI-2 output stream from the ADV728x-M.
CSI_TX_SLAVE_ADDRESS, Program CSI Register Map
address, User Map, Address 0xFE[7:1]
The CSI map has a programmable I2C slave address, which is
programmed using Register 0xFE in the User Sub Map of the
Main Map. The default value for the CSI map address is 0x00;
however, the CSI map cannot be accessed until the I2C slave
address is reset. The recommended I2C slave address for the
CSI map is 0x88.
Table 96. Program CSI_Tx Register Map address
CSI_TX_SLAVE_ADDRESS[7:1]
0000000 (default)
10001000 (recommended)
To reset the I C slave address of the CSI map, write to the
CSI_TX_SLAVE_ADDRESS[7:1] bits in the main register map
(Address 0xFE[7:1]). Set these bits to a value of 0x88 (I2C write
address; I2C read address is 0x89).
2
Rev. A | Page 60 of 104
Description
When set to this value, the
CSI_Tx register map cannot be
written to or read from.
This sets the CSI_Tx register
map to a write address of
0x88 and a read address of
0x89. This is the
recommended setting.
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
UG-637
PCB LAYOUT RECOMMENDATIONS
The ADV728x is a high precision, high speed, mixed-signal
device. To achieve the maximum performance from the part, it
is important to use a well-designed PCB. This section provides
guidelines for designing a PCB for use with the ADV728x.
ANALOG INTERFACE INPUTS
When routing the analog interface inputs on the PCB, keep
track lengths to a minimum. Use 75 Ω trace impedances when
possible; trace impedances other than 75 Ω increase the chance
of reflections.
Place the resistor divider and ac-coupling capacitor circuit
described in the Input Networks section as close as possible to
the AINx pins of the ADV728x.
POWER SUPPLY DECOUPLING
It is recommended that each power supply pin be decoupled with
0.1 µF and 10 nF capacitors. The basic principle is to place a
decoupling capacitor within approximately 0.5 cm of each power
pin. Avoid placing the decoupling capacitors on the opposite side
of the PCB from the ADV728x because doing so introduces
inductive vias in the path.
Locate the decoupling capacitors between the power plane and
the power pin. Current should flow from the power plane to the
capacitor and then to the power pin. Do not apply the power
connection between the capacitor and the power pin. The best
approach is to place a via beneath the 100 nF capacitor pads down
to the power plane (see Figure 44).
VIA TO SUPPLY
SUPPLY
10nF
VREFN AND VREFP PINS
The capacitor between the VREFN and VREFP pins should be
placed as close as possible to the ADV728x and on the same
side of the PCB as the part.
DIGITAL OUTPUTS
The digital output pins are: INTRQ, GPO0, GPO1, GPO2, LLC,
P0:P7, HS, and VS/FIELD/SFL.
Try to minimize the trace length that the digital outputs must
drive. Longer traces have higher capacitance, requiring more
current and, in turn, causing more internal digital noise. Shorter
traces reduce the possibility of reflections.
Adding a 30 Ω to 50 Ω series resistor can suppress reflections,
reduce EMI, and reduce current spikes inside the ADV728x. If
series resistors are used, place them as close as possible to the
ADV728x pins. However, try not to add vias or extra length to
the output trace in an attempt to place the resistors closer.
If possible, limit the capacitance that each digital output must
drive to less than 15 pF. This recommendation can be easily
accomplished by keeping traces short and by connecting the
outputs to only one device. Loading the outputs with excessive
capacitance increases the current transients inside the ADV728x,
creating more digital noise on the power supplies.
EXPOSED METAL PAD
The ADV728x has an exposed metal pad on the bottom of the
package. This pad must be soldered to ground. The exposed
pad is used for proper heat dissipation, noise suppression and
mechanical strength.
100nF
VIA TO GND
11935-043
GROUND
separate ground plane is smaller, and long ground loops can
result.
Figure 44. Recommended Power Supply Decoupling
DIGITAL INPUTS
It is especially important to maintain low noise and good
stability for the PVDD pin. Careful attention must be paid to
regulation, filtering, and decoupling. It is highly desirable to
provide separate regulated supplies for each circuit group
(AVDD, DVDD, DVDDIO, and PVDD).
Some graphic controllers use substantially different levels of
power when active (during active picture time) and when idle
(during horizontal and vertical sync periods). This disparity can
result in a measurable change in the voltage supplied to the analog
supply regulator, which can, in turn, produce changes in the
regulated analog supply voltage. This problem can be mitigated
by regulating the analog supply, or at least the PVDD supply,
from a different, cleaner power source, for example, from a 12 V
supply.
Using a single ground plane for the entire board is also
recommended. Experience has shown that the noise
performance is the same or better with a single ground plane.
Using multiple ground planes can be detrimental because each
The digital inputs of the ADV728x are designed to work with
1.8 V signals (3.3 V for DVDDIO) and are not tolerant of 5 V signals.
Extra components are required if 5 V logic signals must be applied
to the decoder.
MIPI OUTPUTS (D0P, D0N, CLKP, CLKN)
It is recommended that the MIPI output traces be kept as short
as possible and on the same side of the PCB as the ADV728x-M
device. It is also recommended that a solid plane—preferably a
ground plane—be placed on the layer adjacent to the MIPI traces
to provide a solid reference plane.
MIPI transmission operates in both differential and singleended modes. During high speed transmission, the pair of
outputs operates in differential mode; in low power mode,
the pair operates as two independent single-ended traces.
Therefore, it is recommended that each output pair be routed
as two loosely coupled 50 Ω single-ended traces to reduce the
risk of crosstalk between the two traces.
Rev. A | Page 61 of 104
UG-637
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
POWER SUPPLY REQUIREMENTS
Table 97 and Table 98 show the current rating recommendations for power supply design. These values should be used
when designing a power supply section to ensure that an
adequate current can be supplied to the ADV7280, ADV7281,
ADV7282, or ADV7283 models.
Table 97. Current Supply Design Recommendations for the
ADV7280, ADV7281, ADV7282, and ADV7283 Models
Parameter
IDVDDIO
IDVDD
IAVDD
IPVDD
Rating
20 mA
110 mA
100 mA
20 mA
Table 98. Current Supply Design Recommendations for the
ADV7280-M, ADV7281-M, ADV7281-MA, andADV7282-M
Parameter
IDVDDIO
IDVDD
IAVDD
IPVDD
IMVDD
Rev. A | Page 62 of 104
Rating
5 mA
110 mA
100 mA
20 mA
20 mA
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
UG-637
I2C REGISTER MAPS
To access all the registers listed in Table 99, SUB_USR_EN in Register Address 0x0E must be programmed to 00. All read only registers
are left blank.
Table 99. User Sub Map Register Map Details
Address
7
6
5
4
3
2
1
0
Reset
Value
INSEL[4]
INSEL[3]
INSEL[2]
INSEL[1]
INSEL[0]
00001110 0E
Dec
Hex Register Name
RW
0
00
Input control
RW
1
01
Video Selection 1
RW
ENHSPLL
BETACAM
2
02
Video Selection 2
RW
VID_SEL[3]
VID_SEL[2]
VID_SEL[1]
3
03
Output control
RW
VBI_EN
TOD
4
04
Extended output control RW
5
05
Reserved
6
06
Reserved
7
07
Autodetect enable
RW
AD_SEC525_EN AD_SECAM_EN
AD_N443_EN
8
08
Contrast
RW
CON[7]
CON[6]
9
09
Reserved
10
0A
Brightness adjust
RW
BRI[7]
11
0B
Hue adjust
RW
HUE[7]
12
0C
Default Value Y
RW
13
0D
Default Value C
RW
14
0E
ADI Control 1
RW
15
0F
Power management
RW
Reset
16
10
Status 1
R
COL_KILL
AD_RESULT[2]
17
11
IDENT
R
IDENT[7]
IDENT[6]
18
12
Status 2
R
19
13
Status 3
R
20
14
Analog clamp control
RW
21
15
Digital Clamp Control 1
RW
22
16
Reserved
23
17
Shaping Filter Control 1
RW
CSFM[2]
24
18
Shaping Filter Control 2
RW
WYSFMOVR
25
19
Comb filter control
RW
29
1D
ADI Control 2
RW
TRI_LLC
39
27
Pixel delay control
RW
SWPC
43
2B
Misc gain control
RW
CKE
44
2C
AGC mode control
RW
LAGC[2]
45
2D
Chroma Gain Control 1
W
45
2D
Chroma Gain 1
R
46
2E
Chroma Gain Control 2
W
CMG[7]
CMG[6]
CMG[5]
CMG[4]
CMG[3]
CMG[2]
CMG[1]
CMG[0]
46
2E
Chroma Gain 2
R
CG[7]
CG[6]
CG[5]
CG[4]
CG[3]
CG[2]
CG[1]
CG[0]
47
2F
Luma Gain Control 1
W
LAGT[1]
LAGT[0]
LMG[11]
LMG[10]
LMG[9]
LMG[8]
47
2F
Luma Gain 1
R
LG[11]
LG[10]
LG[9]
LG[8]
48
30
Luma Gain Control 2
W
LMG[7]
LMG[6]
LMG[5]
LMG[4]
LMG[3]
LMG[2]
LMG[1]
LMG[0]
48
30
Luma Gain 2
R
LG[7]
LG[6]
LG[5]
LG[4]
LG[3]
LG[2]
LG[1]
LG[0]
49
31
VS/FIELD Control 1
RW
NEWAVMODE
HVSTIM
50
32
VS/FIELD Control 2
RW
VSBHO
VSBHE
51
33
VS/FIELD Control 3
RW
VSEHO
VSEHE
52
34
HS Position Control 1
RW
53
35
HS Position Control 2
RW
54
36
HS Position Control 3
RW
55
37
Polarity
RW
PHS
56
38
NTSC comb control
RW
CTAPSN[1]
CTAPSN[0]
CCMN[2]
CCMN[1]
CCMN[0]
YCMN[2]
YCMN[1]
YCMN[0]
10000000 80
57
39
PAL comb control
RW
CTAPSP[1]
CTAPSP[0]
CCMP[2]
CCMP[1]
CCMP[0]
YCMP[2]
YCMP[1]
YCMP[0]
11000000 C0
58
3A
ADC control
RW
PWRDWN_
MUX_2
MUX PDN override
00000000 00
61
3D
Manual window control RW
CKILLTHR[2]
65
41
Resample control
RW
SFL_INV
77
4D
CTI DNR Control 1
RW
78
4E
CTI DNR Control 2
RW
CTI_C_TH[7]
CTI_C_TH[6]
80
50
DNR Noise Threshold 1
RW
DNR_TH[7]
DNR_TH[6]
81
51
Lock count
RW
FSCLE
SRLS
96
60
ADC Switch 3
106
6A
107
143
ENVSPROC
(Hex)
11001000 C8
VID_SEL[0]
00000100 04
01001100 4C
BT.656-4
TIM_OE
BL_C_VBI
EN_SFL_PIN Range
00110101 35
AD_P60_EN
AD_PALN_EN
AD_PALM_EN
AD_NTSC
_EN
AD_PAL_EN
01111111 7F
CON[5]
CON[4]
CON[3]
CON[2]
CON[1]
CON[0]
10000000 80
BRI[6]
BRI[5]
BRI[4]
BRI[3]
BRI[2]
BRI[1]
BRI[0]
00000000 00
HUE[6]
HUE[5]
HUE[4]
HUE[3]
HUE[2]
HUE[1]
HUE[0]
00000000 00
DEF_Y[5]
DEF_Y[4]
DEF_Y[3]
DEF_Y[2]
DEF_Y[1]
DEF_Y[0]
DEF_VAL_
AUTO_EN
DEF_VAL_EN
00110110 36
DEF_C[7]
DEF_C[6]
DEF_C[5]
DEF_C[4]
DEF_C[3]
DEF_C[2]
DEF_C[1]
DEF_C[0]
SUB_USR_EN[1]
SUB_USR_EN[0]
PAL_SW_LOCK
PWRDWN
Interlaced
00100000 20
AD_RESULT[1]
AD_RESULT[0]
FOLLOW_PW
FSC_LOCK
LOST_LOCK
IN_LOCK
IDENT[5]
IDENT[4]
IDENT[3]
IDENT[2]
IDENT[1]
IDENT[0]
FSC NSTD
LL NSTD
MV AGC DET
MV PS DET
MVCS T3
MVCS DET
STD FLD LEN
FREE_RUN_ACT
Reserved
SD_OP_50Hz
Reserved
INST_HLOCK
FREE_RUN_
PAT_SEL.2
FREE_RUN_
PAT_SEL.1
FREE_RUN_
PAT_SEL.0
CCLEN
CAGT[1]
01111100 7C
00000000 00
01000010 42
00010000 10
DCT[1]
DCT[0]
DCFE
0000xxxx 00
CSFM[1]
CSFM[0]
YSFM[4]
YSFM[3]
YSFM[2]
YSFM[1]
YSFM[0]
00000001 01
WYSFM[4]
WYSFM[3]
WYSFM[2]
WYSFM[1]
WYSFM[0]
10010011 93
NSFSEL[1]
NSFSEL[0]
PSFSEL[1]
PSFSEL[0]
11110001 F1
11000xxx C0
AUTO_PDC_EN
CTA[2]
CTA[1]
LAGC[1]
CTA[0]
LTA[1]
LAGC[0]
CAGT[0]
CAGC[1]
LTA[0]
01011000 58
PW_UPD
11100001 E1
CAGC[0]
10101110 AE
11110100 F4
CMG[11]
CMG[10]
CMG[9]
CMG[8]
CG[11]
CG[10]
CG[9]
CG[8]
00000000 00
1111xxxx F0
xxxxxxxx
00
00000010 02
01000001 41
10000100 84
HSB[10]
HSB[9]
HSB[8]
HSB[7]
HSB[6]
HSB[5]
HSB[4]
HSB[3]
HSB[2]
HSE[7]
HSE[6]
HSE[5]
HSE[4]
HSE[3]
HSE[2]
PVS
HSE[10]
HSE[9]
HSE[8]
00000000 00
HSB[1]
HSB[0]
00000010 02
HSE[1]
HSE[0]
00000000 00
PCLK
00010001 09
PF
PWRDWN_MUX_0 PWRDWN_
MUX_1
CKILLTHR[1]
CKILLTHR[0]
00100010 22
00000001 01
DNR_EN
CTI_AB[1]
CTI_AB[0]
CTI_AB_EN
CTI_C_TH[4]
CTI_C_TH[3]
CTI_C_TH[2]
CTI_C_TH[1] CTI_C_TH[0]
00001000 08
DNR_TH[5]
DNR_TH[4]
DNR_TH[3]
DNR_TH[2]
DNR_TH[1]
DNR_TH[0]
00001000 08
COL[2]
COL[1]
COL[0]
CIL[2]
CIL[1]
CIL[0]
00100100 24
RW
MUX3[2]
MUX3[1]
MUX3[0]
00010000 10
Output Sync Select 1
RW
HS_OUT_SEL[2] HS_OUT
_SEL[1]
HS_OUT_SEL[0]
00000000 00
6B
Output Sync Select 2
RW
FLD_OUT_SEL[2]
FLD_OUT_SEL[1] FLD_OUT_SEL[0]
00010010 12
8F
Free-Run Line Length 1
W
LLC_PAD_SEL[2]
LLC_PAD_
SEL[1]
00000000 00
CTI_C_TH[5]
LLC_PAD_
SEL[0]
Rev. A | Page 63 of 104
CTI_EN
11101111 EF
UG-637
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
Address
Dec
Hex Register Name
RW
7
6
5
4
3
2
1
0
153
99
CCAP1
R
CCAP1[7]
CCAP1[6]
CCAP1[5]
CCAP1[4]
CCAP1[3]
CCAP1[2]
CCAP1[1]
CCAP1[0]
154
9A
CCAP2
R
CCAP2[7]
CCAP2[6]
CCAP2[5]
CCAP2[4]
CCAP2[3]
CCAP2[2]
CCAP2[1]
CCAP2[0]
155
9B
Letterbox 1
R
LB_LCT[7]
LB_LCT[6]
LB_LCT[5]
LB_LCT[4]
LB_LCT[3]
LB_LCT[2]
LB_LCT[1]
LB_LCT[0]
156
9C
Letterbox 2
R
LB_LCM[7]
LB_LCM[6]
LB_LCM[5]
LB_LCM[4]
LB_LCM[3]
LB_LCM[2]
LB_LCM[1]
LB_LCM[0]
157
9D
Letterbox 3
R
LB_LCB[7]
LB_LCB[6]
LB_LCB[5]
LB_LCB[4]
LB_LCB[3]
LB_LCB[2]
LB_LCB[1]
LB_LCB[0]
178
B2
CRC enable
W
195
C3
ADC Switch 1
RW
Reserved
196
C4
ADC Switch 2
RW
MAN_MUX_EN
220
DC
Letterbox Control 1
RW
221
DD
Letterbox Control 2
RW
222
DE
ST Noise Readback 1
R
223
DF
ST Noise Readback 2
R
ST_NOISE[7]
ST_NOISE[6]
ST_NOISE[5]
225
E1
SD offset Cb channel
RW
SD_OFF_Cb[7]
SD_OFF_Cb[6]
SD_OFF_Cb[5]
CRC_ENABLE
LB_SL[3]
MUX1[2]
LB_SL[2]
MUX1[1]
MUX1[0]
LB_SL[1]
Reset
Value
(Hex)
00011100 1C
Reserved
MUX0[2]
MUX0[1]
MUX0[0]
xxxxxxxx
00
Reserved
MUX2[2]
MUX2[1]
MUX2[0]
0xxxxxxx
00
LB_TH[4]
LB_TH[3]
LB_TH[2]
LB_TH[1]
LB_TH[0]
10101100 AC
LB_SL[0]
LB_EL[3]
LB_EL[2]
LB_EL[1]
LB_EL[0]
01001100 4C
ST_NOISE_VLD
ST_NOISE[10]
ST_NOISE[9] ST_NOISE[8]
ST_NOISE[4]
ST_NOISE[3]
ST_NOISE[2]
ST_NOISE[1] ST_NOISE[0]
SD_OFF_Cb[4]
SD_OFF_Cb[3]
SD_OFF_Cb[2]
SD_OFF_Cb[ SD_OFF_Cb[0]
1]
10000000 80
10000000 80
226
E2
SD offset Cr channel
RW
SD_OFF_Cr[7]
SD_OFF_Cr[6]
SD_OFF_Cr[5]
SD_OFF_Cr[4]
SD_OFF_Cr[3]
SD_OFF_Cr[2]
SD_OFF_Cr[ SD_OFF_Cr[0]
1]
227
E3
SD saturation Cb channel RW
SD_SAT_Cb[7]
SD_SAT_Cb[6]
SD_SAT_Cb[5]
SD_SAT_Cb[4]
SD_SAT_Cb[3]
SD_SAT_Cb[2]
SD_SAT_Cb[ SD_SAT_Cb[0]
1]
10000000 80
228
E4
SD saturation Cr channel RW
SD_SAT_Cr[7]
SD_SAT_Cr[6]
SD_SAT_Cr[5]
SD_SAT_Cr[4]
SD_SAT_Cr[3]
SD_SAT_Cr[2]
SD_SAT_Cr[1 SD_SAT_Cr[0]
]
10000000 80
229
E5
NTSC V bit begin
RW
NVBEGDELO
NVBEGDELE
NVBEGSIGN
NVBEG[4]
NVBEG[3]
NVBEG[2]
NVBEG[1]
NVBEG[0]
00100101 25
230
E6
NTSC V bit end
RW
NVENDDELO
NVENDDELE
NVENDSIGN
NVEND[4]
NVEND[3]
NVEND[2]
NVEND[1]
NVEND[0]
00000100 04
231
E7
NTSC F bit toggle
RW
NFTOGDELO
NFTOGDELE
NFTOGSIGN
NFTOG[4]
NFTOG[3]
NFTOG[2]
NFTOG[1]
NFTOG[0]
01100011 63
232
E8
PAL V bit begin
RW
PVBEGDELO
PVBEGDELE
PVBEGSIGN
PVBEG[4]
PVBEG[3]
PVBEG[2]
PVBEG[1]
PVBEG[0]
01100101 65
233
E9
PAL V bit end
RW
PVENDDELO
PVENDDELE
PVENDSIGN
PVEND[4]
PVEND[3]
PVEND[2]
PVEND[1]
PVEND[0]
00010100 14
234
EA
PAL F bit toggle
RW
PFTOGDELO
PFTOGDELE
PFTOGSIGN
PFTOG[4]
PFTOG[3]
PFTOG[2]
PFTOG[1]
PFTOG[0]
01100011 63
235
EB
Vblank Control 1
RW
NVBIOLCM[1]
NVBIOLCM[0]
NVBIELCM[1]
NVBIELCM[0]
PVBIOLCM[1]
PVBIOLCM[0]
PVBIELCM[1] PVBIELCM[0]
01010101 55
236
EC
Vblank Control 2
RW
NVBIOCCM[1]
NVBIOCCM[0]
NVBIECCM[1]
NVBIECCM[0]
PVBIOCCM[1]
PVBIOCCM[0]
PVBIECCM[1] PVBIECCM[0]
01010101 55
243
F3
AFE_CONTROL 1
RW
AA_FILT_MAN_
OVR
AA_FILT_EN[3]
AA_FILT_EN[2]
AA_FILT_EN[ AA_FILT_EN[0]
1]
00000000 00
244
F4
Drive strength
RW
DR_STR[0]
DR_STR_C[1]
DR_STR_C[0]
DR_STR_S[1] DR_STR_S[0]
0x010101 15
248
F8
IF comp control
RW
IFFILTSEL[2]
IFFILTSEL[1]
249
F9
VS mode control
RW
VS_COAST_
MODE[1]
VS_COAST_
MODE[0]
EXTEND_VS_ EXTEND_VS_
MAX_FREQ
MIN_FREQ
00000011 03
251
FB
Peaking gain
RW
PEAKING_
GAIN[7]
PEAKING_
GAIN[6]
PEAKING_
GAIN[5]
PEAKING_
GAIN[4]
PEAKING_
GAIN[3]
PEAKING_
GAIN[2]
PEAKING_
GAIN[1]
01000000 40
252
FC
DNR Noise Threshold 2
RW
DNR_TH2[7]
DNR_TH2[6]
DNR_TH2[5]
DNR_TH2[4]
DNR_TH2[3]
DNR_TH2[2]
DNR_TH2[1] DNR_TH2[0]
253
FD
VPP slave address
RW
VPP_SLAVE_
ADDR[6]
VPP_SLAVE_
ADDR[5]
VPP_SLAVE_
ADDR[4]
VPP_SLAVE_
ADDR[3]
VPP_SLAVE_
ADDR[2]
VPP_SLAVE_
ADDR[1]
VPP_SLAVE_
ADDR[0]
254
FE
CSI Tx slave address
RW
CSI_TX_SLAVE_ CSI_TX_SLAVE_
ADDR[6]
ADDR[5]
CSI_TX_SLAVE_
ADDR[2]
CSI_TX_SLAVE_ CSI_TX_SLA
ADDR[1]
VE_ADDR[0]
GLITCH_FILT_
BYP
DR_STR[1]
CSI_TX_SLAVE_ CSI_TX_SLAVE_
ADDR[4]
ADDR[3]
Rev. A | Page 64 of 104
IFFILTSEL[0]
PEAKING_
GAIN[0]
00000000 00
00000100 04
00000000 00
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
UG-637
To access the registers listed in Table 100, SUB_USR_EN in Register Address 0x0E must be programmed to 10. All read only registers are
left blank.
Table 100. User Sub Map 2 Register Map Details
Address
6
5
4
Hex Register Name
RW 7
128
80
ACE Control 1
RW ACE_ENABLE
131
83
ACE Control 4
RW
2
1
0
(Hex)
132
84
ACE Control 5
RW ACE_CHROMA_
MAX[3]
ACE_CHROMA_
MAX[2]
ACE_CHROMA_
MAX[1]
133
85
ACE Control 6
RW ACE_RESPONSE_
SPEED[3]
ACE_RESPONSE_
SPEED[2]
ACE_RESPONSE_
SPEED[2]
146
92
Dither control
RW
217
D9
Min Max 0
RW MIN_THRESH_Y[7] MIN_THRESH_Y[6] MIN_THRESH_Y[5] MIN_THRESH_
Y[4]
218
DA
Min Max 1
RW MAX_THRESH_Y[7] MAX_THRESH_Y[6] MAX_THRESH_Y[5] MAX_THRESH_ MAX_THRESH_Y[3] MAX_THRESH_Y[2] MAX_THRESH_ MAX_THRESH_ 11111111 FF
Y[4]
Y[1]
Y[0]
219
DB
Min Max 2
RW MIN_THRESH_C[7] MIN_THRESH_C[6] MIN_THRESH_C[5] MIN_THRESH_
C[4]
220
DC
Min Max 3
RW MAX_THRESH_C[7] MAX_THRESH_C[6] MAX_THRESH_C[5] MAX_THRESH_ MAX_THRESH_C[3] MAX_THRESH_C[2] MAX_THRESH_ MAX_THRESH_ 11111111 FF
C[4]
C[1]
C[0]
221
DD
Min Max 4
RW MIN_SAMPLES_
ALLOWED_Y[3]
MIN_SAMPLES_
ALLOWED_Y[2]
MIN_SAMPLES_
ALLOWED_Y[1]
MIN_SAMPLES_ MAX_SAMPLES_
ALLOWED_Y[0] ALLOWED_Y[3]
MAX_SAMPLES_
ALLOWED_Y[2]
MAX_SAMPLES MAX_SAMPLES 11001100 CC
_ALLOWED_Y[1] _ALLOWED_Y[0]
222
DE
Min Max 5
RW MIN_SAMPLES_
ALLOWED_C[3]
MIN_SAMPLES_
ALLOWED_C[2]
MIN_SAMPLES_
ALLOWED_C[1]
MIN_SAMPLES_ MAX_SAMPLES_
ALLOWED_C[0] ALLOWED_C[3]
MAX_SAMPLES_
ALLOWED_C[2]
MAX_SAMPLES_ MAX_SAMPLES_ 11001100 CC
ALLOWED_C[1] ALLOWED_C[0]
224
E0
FL control
RW
FL_ENABLE
00000000 00
225
E1
Y Average 0
RW LINE_START[8]
LINE_START[7]
LINE_START[6]
LINE_START[5]
LINE_START[4]
LINE_START[3]
LINE_START[2]
LINE_START[1]
0001001
226
E2
Y Average 1
RW LINE_END[8]
LINE_END[7]
LINE_END[6]
LINE_END[5]
LINE_END[4]
LINE_END[3]
LINE_END[2]
LINE_END[1]
10001000 88
227
E3
Y Average 2
RW SAMPLE_START[9] SAMPLE_START[8] SAMPLE_START[7] SAMPLE_
START[6]
SAMPLE_
START[3]
SAMPLE_
START[2]
00010111 1B
228
E4
Y Average 3
RW SAMPLE_END[9]
SAMPLE_END[8]
SAMPLE_END[7]
229
E5
Y Average 4
RW SAMPLE_END[1]
SAMPLE_END[0]
SAMPLE_START[1] SAMPLE_
START[0]
230
E6
Y Average 5
RW
231
E7
Y average data MSB
R
232
E8
Y average data LSB
R
00000000 00
ACE_LUMA_
GAIN[4]
Y_AVERAGE[9]
3
Reset
Value
Dec
Y_AVERAGE[8]
Y_AVERAGE[7]
ACE_LUMA_
GAIN[3]
ACE_LUMA_
GAIN[2]
ACE_LUMA_
GAIN[1]
ACE_CHROMA_ ACE_CHROMA_
MAX[0]
GAIN[3]
ACE_CHROMA_
GAIN[2]
ACE_CHROMA_ ACE_CHROMA_ 10001000 88
GAIN[1]
GAIN[0]
ACE_RESPONSE ACE_GAMMA_
_SPEED[1]
GAIN[3]
ACE_GAMMA_
GAIN[2]
ACE_GAMMA_
GAIN[1]
MIN_THRESH_Y[3] MIN_THRESH_Y[2] MIN_THRESH_
Y[1]
MIN_THRESH_C[3] MIN_THRESH_C[2] MIN_THRESH_
C[1]
SAMPLE_START[5] SAMPLE_
START[4]
SAMPLE_END[6] SAMPLE_END[5]
SAMPLE_END[4]
Y_AVG_TIME_
CONST[1]
Y_AVG_TIME_
CONST[0]
Y_AVERAGE[6]
Y_AVERAGE[5]
Y_AVERAGE[4]
Rev. A | Page 65 of 104
00001101 0D
ACE_GAMMA_
GAIN[0]
11111000 F8
BR_DITHER_
MODE
00000000 00
MIN_THRESH_
Y[0]
00000000 00
MIN_THRESH_
C[0]
00000000 00
11
SAMPLE_END[3] SAMPLE_END[2] 11010111 D7
LINE_END[0]
Y_AVG_TIME_
CONST[2]
ACE_LUMA_
GAIN[0]
LINE_START[0]
Y_AVG_FILT_EN CAPTURE_
VALUE
Y_AVERAGE[3]
Y_AVERAGE[2]
Y_AVERAGE[1]
Y_AVERAGE[0]
00100011 23
00010000 10
UG-637
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
To access the registers listed in Table 101, SUB_USR_EN in Register Address 0x0E must be programmed to 01. All read only registers are
left blank.
Table 101. Interrupt/VDP Sub Map Details
Address
2
1
0
Reset Value1 (Hex)
MPU_STIM_
INTRQ
INTRQ_OP_
SEL[1]
INTRQ_OP_
SEL[0]
0001x000
10
SD_FR_CHNG_Q
SD_UNLOCK_Q
SD_LOCK_Q
SD_FR_CHNG_
CLR
SD_UNLOCK_
CLR
SD_LOCK_CLR
x0000000
00
SD_FR_CHNG_
MSKB2
SD_UNLOCK_
MSKB2
SD_LOCK_
MSKB2
x0000000
00
CCAPD_CLR
0xx00000
00
CCAPD_MSKB2
0xx00000
00
Dec
Hex
Register Name
RW
7
6
5
4
64
40
Interrupt
Configuration 1
RW
INTRQ_DUR_
SEL[1]
INTRQ_DUR_
SEL[0]
MV_INTRQ_
SEL[1]
MV_INTRQ_
SEL[0]
66
42
Interrupt Status 1
R
MV_PS_CS_Q
67
43
Interrupt Clear 1
W
MV_PS_CS_CLR
68
44
Interrupt Mask 1
RW
MV_PS_CS_
MSKB2
69
45
Raw Status 2
R
MPU_STIM_
INTRQ
CHX_MIN_MAX_ EVEN_FIELD
INTRQ
70
46
Interrupt Status 2
R
MPU_STIM_
INTRQ_Q
SD_FIELD_
CHNGD_Q
71
47
Interrupt Clear 2
W
MPU_STIM_
INTRQ_CLR
CHX_MIN_MAX_ SD_FIELD_
INTRQ_CLR
CHNGD_CLR
72
48
Interrupt Mask 2
RW
MPU_STIM_
INTRQ_MSKB2
CHX_MIN_MAX_ SD_FIELD_
INTRQ_MSKB2
CHNGD_MSKB2
73
49
Raw Status 3
R
74
4A
Interrupt Status 3
R
PAL_SW_LK_
CHNG_Q
SCM_LOCK_
CHNG_Q
75
4B
Interrupt Clear 3
W
PAL_SW_LK_
CHNG_CLR
76
4C
Interrupt Mask 3
RW
PAL_SW_LK_
CHNG_MSKB2
78
4E
Interrupt Status 4
R
79
4F
Interrupt Clear 4
80
50
81
3
CCAPD
CCAPD_Q
SCM_LOCK
SD_H_LOCK
SD_V_LOCK
SD_OP_50Hz
SD_AD_CHNG_Q SD_H_LOCK_
CHNG_Q
SD_V_LOCK_
CHNG_Q
SD_OP_CHNG_Q
SCM_LOCK_
CHNG_CLR
SD_AD_CHNG_
CLR
SD_H_LOCK_
CHNG_CLR
SD_V_LOCK_
CHNG_CLR
SD_OP_CHNG_
CLR
xx000000
00
SCM_LOCK_
CHNG_MSKB2
SD_AD_CHNG_
MSKB2
SD_H_LOCK_
CHNG_MSKB2
SD_V_LOCK_
CHNG_MSKB2
SD_OP_CHNG_
MSKB2
xx000000
00
VDP_CGMS_
WSS_CHNGD_Q
VDP_CCAPD_Q
W
VDP_CGMS_
WSS_CHNGD_
CLR
VDP_CCAPD_CLR 00x0x0x0
00
Interrupt Mask 4
RW
VDP_CGMS_
WSS_CHNGD_
MSKB2
VDP_CCAPD_
MSKB2
00x0x0x0
00
51
Interrupt Latch 0
R
96
60
VDP_CONFIG_1
RW
98
62
VDP_ADF_
CONFIG_1
RW
ADF_ENABLE
99
63
VDP_ADF_
CONFIG_2
RW
DUPLICATE_ADF
100
64
VDP_LINE_00E
RW
MAN_LINE_PGM
101
65
VDP_LINE_00F
RW
VBI_DATA_
P6_N23[3]
VBI_DATA_
P6_N23[2]
VBI_DATA_
P6_N23[1]
102
66
VDP_LINE_010
RW
VBI_DATA_
P7_N24[3]
VBI_DATA_
P7_N24[2]
103
67
VDP_LINE_011
RW
VBI_DATA_
P8_N25[3]
104
68
VDP_LINE_012
RW
105
69
VDP_LINE_013
106
6A
107
Y_CHANNEL_
Y_CHANNEL_
CB_CHANNEL_ CB_CHANNEL_ CR_CHANNEL_ CR_CHANNEL_
MIN_VIOLATION MAX_VIOLATION MIN_VIOLATION MAX_VIOLATION MIN_VIOLATION MAX_VIOLATION
ADF_MODE[1]
WST_PKT_
DECODE_
DISABLE
VDP_TTXT_
TYPE_MAN_
ENABLE
VDP_TTXT_
TYPE_MAN[1]
VDP_TTXT_
TYPE_MAN[0]
10001000
88
ADF_MODE[0]
ADF_DID[4]
ADF_DID[3]
ADF_DID[2]
ADF_DID[1]
ADF_DID[0]
00010101
15
ADF_SDID[5]
ADF_SDID[4]
ADF_SDID[3]
ADF_SDID[2]
ADF_SDID[1]
ADF_SDID[0]
0x101010
2A
VBI_DATA_
P318[3]
VBI_DATA_
P318[2]
VBI_DATA_
P318[1]
VBI_DATA_
P318[0]
0xxx0000
00
VBI_DATA_
P6_N23[0]
VBI_DATA_
P319_N286[3]
VBI_DATA_
P319_N286[2]
VBI_DATA_
P319_N286[1]
VBI_DATA_
P319_N286[0]
00000000
00
VBI_DATA_
P7_N24[1]
VBI_DATA_
P7_N24[0]
VBI_DATA_
P320_N287[3]
VBI_DATA_
P320_N287[2]
VBI_DATA_
P320_N287[1]
VBI_DATA_
P320_N287[0]
00000000
00
VBI_DATA_
P8_N25[2]
VBI_DATA_
P8_N25[1]
VBI_DATA_
P8_N25[0]
VBI_DATA_
P321_N288[3]
VBI_DATA_
P321_N288[2]
VBI_DATA_
P321_N288[1]
VBI_DATA_
P321_N288[0]
00000000
00
VBI_DATA_
P9[3]
VBI_DATA_
P9[2]
VBI_DATA_
P9[1]
VBI_DATA_
P9[0]
VBI_DATA_
P322[3]
VBI_DATA_
P322[2]
VBI_DATA_
P322[1]
VBI_DATA_
P322[0]
00000000
00
RW
VBI_DATA_
P10[3]
VBI_DATA_
P10[2]
VBI_DATA_
P10[1]
VBI_DATA_
P10[0]
VBI_DATA_
P323[3]
VBI_DATA_
P323[2]
VBI_DATA_
P323[1]
VBI_DATA_
P323[0]
00000000
00
VDP_LINE_014
RW
VBI_DATA_
P11[3]
VBI_DATA_
P11[2]
VBI_DATA_
P11[1]
VBI_DATA_
P11[0]
VBI_DATA_
P324_N272[3]
VBI_DATA_
P324_N272[2]
VBI_DATA_
P324_N272[1]
VBI_DATA_
P324_N272[0]
00000000
00
6B
VDP_LINE_015
RW
VBI_DATA_
P12_N10[3]
VBI_DATA_
P12_N10[2]
VBI_DATA_
P12_N10[1]
VBI_DATA_
P12_N10[0]
VBI_DATA_
P325_N273[3]
VBI_DATA_
P325_N273[2]
VBI_DATA_
P325_N273[1]
VBI_DATA_
P325_N273[0]
00000000
00
108
6C
VDP_LINE_016
RW
VBI_DATA_
P13_N11[3]
VBI_DATA_
P13_N11[2]
VBI_DATA_
P13_N11[1]
VBI_DATA_
P13_N11[0]
VBI_DATA_
P326_N274[3]
VBI_DATA_
P326_N274[2]
VBI_DATA_
P326_N274[1]
VBI_DATA_
P326_N274[0]
00000000
00
109
6D
VDP_LINE_017
RW
VBI_DATA_
P14_N12[3]
VBI_DATA_
P14_N12[2]
VBI_DATA_
P14_N12[1]
VBI_DATA_
P14_N12[0]
VBI_DATA_
P327_N275[3]
VBI_DATA_
P327_N275[2]
VBI_DATA_
P327_N275[1]
VBI_DATA_
P327_N275[0]
00000000
00
110
6E
VDP_LINE_018
RW
VBI_DATA_
P15_N13[3]
VBI_DATA_
P15_N13[2]
VBI_DATA_
P15_N13[1]
VBI_DATA_
P15_N13[0]
VBI_DATA_
P328_N276[3]
VBI_DATA_
P328_N276[2]
VBI_DATA_
P328_N276[1]
VBI_DATA_
P328_N276[0]
00000000
00
111
6F
VDP_LINE_019
RW
VBI_DATA_
P16_N14[3]
VBI_DATA_
P16_N14[2]
VBI_DATA_
P16_N14[1]
VBI_DATA_
P16_N14[0]
VBI_DATA_
P329_N277[3]
VBI_DATA_
P329_N277[2]
VBI_DATA_
P329_N277[1]
VBI_DATA_
P329_N277[0]
00000000
00
112
70
VDP_LINE_01A
RW
VBI_DATA_
P17_N15[3]
VBI_DATA_
P17_N15[2]
VBI_DATA_
P17_N15[1]
VBI_DATA_
P17_N15[0]
VBI_DATA_
P330_N278[3]
VBI_DATA_
P330_N278[2]
VBI_DATA_
P330_N278[1]
VBI_DATA_
P330_N278[0]
00000000
00
113
71
VDP_LINE_01B
RW
VBI_DATA_
P18_N16[3]
VBI_DATA_
P18_N16[2]
VBI_DATA_
P18_N16[1]
VBI_DATA_
P18_N16[0]
VBI_DATA_
P331_N279[3]
VBI_DATA_
P331_N279[2]
VBI_DATA_
P331_N279[1]
VBI_DATA_
P331_N279[0]
00000000
00
114
72
VDP_LINE_01C
RW
VBI_DATA_
P19_N17[3]
VBI_DATA_
P19_N17[2]
VBI_DATA_
P19_N17[1]
VBI_DATA_
P19_N17[0]
VBI_DATA_
P332_N280[3]
VBI_DATA_
P332_N280[2]
VBI_DATA_
P332_N280[1]
VBI_DATA_
P332_N280[0]
00000000
00
115
73
VDP_LINE_01D
RW
VBI_DATA_
P20_N18[3]
VBI_DATA_
P20_N18[2]
VBI_DATA_
P20_N18[1]
VBI_DATA_
P20_N18[0]
VBI_DATA_
P333_N281[3]
VBI_DATA_
P333_N281[2]
VBI_DATA_
P333_N281[1]
VBI_DATA_
P333_N281[0]
00000000
00
116
74
VDP_LINE_01E
RW
VBI_DATA_
P21_N19[3]
VBI_DATA_
P21_N19[2]
VBI_DATA_
P21_N19[1]
VBI_DATA_
P21_N19[0]
VBI_DATA_
P334_N282[3]
VBI_DATA_
P334_N282[2]
VBI_DATA_
P334_N282[1]
VBI_DATA_
P334_N282[0]
00000000
00
Rev. A | Page 66 of 104
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
UG-637
Address
Dec
Hex
Register Name
RW
7
6
5
4
3
2
1
0
Reset Value1 (Hex)
117
75
VDP_LINE_01F
RW
VBI_DATA_
P22_N20[3]
VBI_DATA_
P22_N20[2]
VBI_DATA_
P22_N20[1]
VBI_DATA_
P22_N20[0]
VBI_DATA_
P335_N283[3]
VBI_DATA_
P335_N283[2]
VBI_DATA_
P335_N283[1]
VBI_DATA_
P335_N283[0]
00000000
00
118
76
VDP_LINE_020
RW
VBI_DATA_
P23_N21[3]
VBI_DATA_
P23_N21[2]
VBI_DATA_
P23_N21[1]
VBI_DATA_
P23_N21[0]
VBI_DATA_
P336_N284[3]
VBI_DATA_
P336_N284[2]
VBI_DATA_
P336_N284[1]
VBI_DATA_
P336_N284[0]
00000000
00
119
77
VDP_LINE_021
RW
VBI_DATA_
P24_N22[3]
VBI_DATA_
P24_N22[2]
VBI_DATA_
P24_N22[1]
VBI_DATA_
P24_N22[0]
VBI_DATA_
P337_N285[3]
VBI_DATA_
P337_N285[2]
VBI_DATA_
P337_N285[1]
VBI_DATA_
P337_N285[0]
00000000
00
120
78
VDP_STATUS
R
TTXT_AVL
120
78
VDP_STATUS_
CLEAR
W
00000000
00
121
79
VDP_CCAP_
DATA_0
R
CCAP_BYTE_1[7] CCAP_BYTE_1[6] CCAP_BYTE_1[5] CCAP_BYTE_1[4] CCAP_BYTE_1[3] CCAP_BYTE_1[2] CCAP_BYTE_1[1] CCAP_BYTE_1[0]
122
7A
VDP_CCAP_
DATA_1
R
CCAP_BYTE_2[7] CCAP_BYTE_2[6] CCAP_BYTE_2[5] CCAP_BYTE_2[4] CCAP_BYTE_2[3] CCAP_BYTE_2[2] CCAP_BYTE_2[1] CCAP_BYTE_2[0]
125
7D
VDP_CGMS_
WSS_DATA_0
R
126
7E
VDP_CGMS_
WSS_DATA_1
R
CGMS_CRC[1]
CGMS_CRC[0]
CGMS_WSS[13]
127
7F
VDP_CGMS_
WSS_DATA_2
R
CGMS_WSS[7]
CGMS_WSS[6]
CGMS_WSS[5]
156
9C
VDP_OUTPUT_SEL RW
00110000
30
1
2
CGMS_WSS_AVL CC_EVEN_FIELD
CC_AVL
CGMS_WSS_
CLEAR
CC_CLEAR
CGMS_CRC[5]
CGMS_CRC[4]
CGMS_CRC[3]
CGMS_CRC[2]
CGMS_WSS[12]
CGMS_WSS[11]
CGMS_WSS[10]
CGMS_WSS[9]
CGMS_WSS[8]
CGMS_WSS[4]
CGMS_WSS[3]
CGMS_WSS[2]
CGMS_WSS[1]
CGMS_WSS[0]
WSS_CGMS_CB_
CHANGE
x in a reset value indicates do not care.
B at the end of the bit name equals an overbar for the whole bit name.
Rev. A | Page 67 of 104
UG-637
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
To access the registers listed in Table 102 the VPP I2C slave address needs to be set. The VPP Map address is set by writing to register
0xFD in the User Map. See the I2C Port Description section. All read only registers are left blank.
Table 102. VPP Map Details
Address
Dec
Hex
Register Name
RW
65
41
DEINT_RESET
RW
7
85
55
I2C_DEINT_
ENABLE
RW
I2C_DEINT_
ENABLE
91
5B
ADV_TIMING_
MODE_EN
RW
ADV_TIMING_
MODE_EN
6
5
4
Rev. A | Page 68 of 104
3
2
1
0
Reset Value (Hex)
DEINT_RESET
00000000
00
00000000
00
10000000
00
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
UG-637
To access the registers listed in Table 103, the CSI I2C slave address needs to be set. The CSI Map address is set by writing to register 0xFE
in the User Map. See the I2C Port Description section. All read only registers are left blank.
Table 103. CSI Map Details
Address
6
5
Reset
Value
(Hex)
10000000
0x80
TLPX[0]
00011000
0x18
THSPREP[0]
00011000
0x18
THSZEROS[0]
00110000
0x30
THSTRAIL[1]
THSTRAIL[0]
00100000
0x20
THSEXIT[1]
THSEXIT[0]
00101000
0x28
01000000
0x40
01011000
0x58
00110000
0x30
ANCILLARY_
DI[0]
11000000
0xC0
VBIVIDEO_
DI[1]
VBIVIDEO_
DI[0]
11000100
0xC4
LSPKT_DI[2]
LSPKT_DI[1]
LSPKT_DI[0]
00001000
0x08
LEPKT_DI[2]
LEPKT_DI[1]
LEPKT_DI[0]
00001100
0x0C
00000000
0x00
10000000
0x80
01000000
0x40
00000000
0x00
LINENUMBER1
_F1_
INTERLACED[0]
00000011
0x03
LINENUMBER1
_F2_
INTERLACED[0]
00000010
0x02
01010000
0x50
00000001
0x01
Dec
Hex
Register Name
RW
7
4
3
2
1
00
0x00
CSITX_PWRDN
RW
CSITX_PWRDN
01
0x01
TLPX
RW
TLPX[4]
TLPX[3]
TLPX[2]
TLPX[1]
02
0x02
THSPREP
RW
THSPREP[4]
THSPREP[3]
THSPREP[2]
THSPREP[1]
03
0x03
THSZEROS
RW
THSZEROS[4]
THSZEROS[3]
THSZEROS[2]
THSZEROS[1]
04
0x04
THSTRAIL
RW
THSTRAIL[4]
THSTRAIL[3]
THSTRAIL[2]
05
0x05
THSEXIT
RW
THSEXIT[4]
THSEXIT[3]
THSEXIT[2]
06
0x06
TCLK_PREP
RW
TCLK_PREP[2]
TCLK_PREP[1]
TCLK_
PREP[0]
07
0x07
TCLK_ZEROS
RW
TCLK_ZEROS[4]
TCLK_ZEROS[3]
TCLK_
ZEROS[2]
TCLK_ZEROS[1]
08
0x08
TCLK_TRAIL
RW
TCLK_TRAIL[3]
TCLK_TRAIL[2]
TCLK_
TRAIL[1]
TCLK_TRAIL[0]
09
0x09
ANCILLARY_DI
RW
ANCILLARY_DI[5]
ANCILLARY_
DI[4]
ANCILLARY_
DI[3]
ANCILLARY_
DI[2]
ANCILLARY_
DI[1]
10
0x0A
VBIVIDEO_DI
RW
VBIVIDEO_DI[5]
VBIVIDEO_DI[4]
VBIVIDEO_
DI[3]
VBIVIDEO_DI[2]
11
0x0B
LSPKT_DI
RW
LSPKT_DI[5]
LSPKT_DI[4]
LSPKT_DI[3]
12
0x0C
LEPKT_DI
RW
LEPKT_DI[5]
LEPKT_DI[4]
LEPKT_DI[3]
13
0x0D
VC_REF
RW
VC_REF[1]
VC_REF[0]
14
0x0E
CKSUM_EN
RW
CKSUM_EN
31
0x1F
CSI_FRAME_NUM_
CTL
RW
FRAMENUMBER_
INTERLACED
32
0x20
CSI_LINENUM_
INCR_INTERLACED
RW
LINENUMBER_
INCR_
INTERLACED
33
0x21
LINENUMBER1_F1_
INTERLACED
RW
LINENUMBER1
_F1_
INTERLACED[7]
LINENUMBER1
_F1_
INTERLACED[6]
LINENUMBER1
_F1_
INTERLACED[5]
LINENUMBER1
_F1_
INTERLACED[4]
LINENUMBER1
_FF1_
INTERLACED[3]
LINENUMBER1
_F1_
INTERLACED[2]
LINENUMBER1
_F1_
INTERLACED[1]
34
0x22
LINENUMBER1_F2_
INTERLACED
RW
LINENUMBER1
_F2_
INTERLACED[7]
LINENUMBER1
_F2_
INTERLACED[6]
LINENUMBER1
_F2_
INTERLACED[5]
LINENUMBER1
_F2_
INTERLACED[4]
LINENUMBER1
_FF2_
INTERLACED[3]
LINENUMBER1
_F2_
INTERLACED[2]
LINENUMBER1
_F2_
INTERLACED[1]
38
0x26
ESC_MODE_CTL
RW
ESC_MODE_EN_
D0
ESC_
XSHUTDOWN_
D0
ESC_MODE_
EN_CLK
ESC_
XSHUTDOWN_
CLK
EN_ESC_CMD
_CLK_LANE
222
0xDE
DPHY_PWDN_CTL
RW
0
TCLK_
ZEROS[0]
FBIT_VAL_AT_
FIELD1START_
INTERLACED
DPHY_PWDN_
OVERRIDE
Rev. A | Page 69 of 104
DPHY_PWDN
UG-637
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
USER SUB MAP DESCRIPTION
To access all the registers listed in Table 104, SUB_USR_EN in Register Address 0x0E must be programmed to 00. The gray shading is the
default.
Table 104. User Sub Map Register Descriptions
User Sub Map
Address
0x00
0x01
Register
Input control
Video
Selection 1
Bits (Shading Indicates Default)
Bit Description
INSEL[4:0]; the INSEL bits allow
the user to select an input
channel and the input format
7
6
0x03
Output control
3
0
0
0
0
1
1
1
2
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
0
0
1
0
1
0
1
0
0
1
1
1
0
0
1
1
1
1
0
0
0
0
1
0
0
1
1
0
0
0
1
Output drivers tristated
Reserved
ENVSPROC
0
1
0
0
1
ENHSPLL
Video
Selection 2
4
0
0
0
0
0
0
0
Comments
CVBS input on AIN1
CVBS input on AIN2
CVBS input on AIN3
CVBS input on AIN4
Y input on AIN1, C input on AIN2
Y input on AIN3, C input on AIN4
Y input on AIN1, Pb input on AIN2, Pr
input on AIN3
Differential positive on AIN1,
differential negative on AIN2
Differential positive on AIN3,
differential negative on AIN4
Sets to default
Disables VSYNC processor
Enables VSYNC processor
Sets to default
Standard video input
Betacam input enable
Disables HSYNC processor
Enables HSYNC processor
Sets to default
Set to default
Autodetects PAL B/PAL G/PAL H/
PAL I/PAL D, NTSC J (no pedestal),
SECAM
Autodetects PAL B/PAL G/PAL H/
PAL I/PAL D, NTSC M (pedestal),
SECAM
Autodetects PAL N (pedestal),
NTSC J (no pedestal), SECAM
Autodetects PAL N (pedestal),
NTSC M (pedestal) SECAM
NTSC J
NTSC M
PAL 60
NTSC 4.43
PAL B/G/H/I/D
PAL N = PAL B/PAL G/PAL H/ PAL
I/PAL D (with pedestal)
PAL M (without pedestal)
PAL M
PAL Combination N
PAL Combination N (with
pedestal)
SECAM
SECAM
Reserved
Output drivers enabled
Reserved
BETACAM; enables BETACAM
levels
0x02
5
Reserved
Reserved
VID_SEL[3:0]; the VID_SEL bits
allow the user to select the input
video standard
Reserved
TOD; tristate output drivers; this
bit allows the user to tristate the
output drivers; pixel outputs, HS
and VS/FIELD/SFL
VBI_EN; vertical blanking interval
data enable; allows VBI data
(Line 1 to Line 21) to be passed
through with only a minimum
amount of filtering performed
0
1
1
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
0
0
0
1
1
1
1
1
1
0
0
0
0
1
1
0
0
0
1
0
1
0
1
1
1
1
1
0
0
1
1
1
1
0
0
0
1
0
1
1
1
1
1
1
1
0
0
1
0
0
1
All lines filtered and scaled
Only active video region filtered
Rev. A | Page 70 of 104
Notes
See also TIM_OE
and TRI_LLC
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
User Sub Map
Address
0x04
Register
Extended
output control
Bits (Shading Indicates Default)
Bit Description
Range; allows the user to select
the range of output values; can
be ITU-R BT.656 compliant or can
fill the whole accessible number
range
EN_SFL_PIN
7
6
5
4
Autodetect
enable
Reserved
BT.656-4; allows the user to select
an output mode compatible with
ITU-R BT.656-3/-4
AD_PAL_EN; PAL B/PAL D/PAL I/
PAL G/PAL H autodetect enable
3
2
0
1
0
1
0
1
0
1
0
1
0
1
0
1
AD_N443_EN; NTSC 4.43
autodetect enable
0x0A
Brightness
adjust
0x0B
Hue adjust
0x0C
Default Value Y
HUE[7:0]; this register contains
the value for the color hue
adjustment
DEF_VAL_EN; default value
enable
0
1
0
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
DEF_VAL_AUTO_EN; default
value automatic enable
0x0D
Default
Value C
SFL output enables
encoder and decoder
to be connected
directly
during VBI
Controlled by TOD
ITU-R BT.656-3 compatible
ITU-R BT.656-4 compatible
AD_P60_EN; PAL 60 autodetect
enable
CON[7:0]; contrast adjust; this is
the user control for contrast
adjustment
BRI[7:0]; this register controls the
brightness of the video signal
Disables SFL output
Outputs SFL information on the
SFL pin
1
AD_PALN_EN; PAL N autodetect
enable
Contrast
Notes
ITU-R BT.656
Extended range
HS, VS, FIELD tristated
HS, VS, FIELD forced active
0
1
AD_SECAM_EN; SECAM
autodetect enable
Comments
16 ≤ Y ≤ 235, 16 ≤ C/P ≤ 240
1 ≤ Y ≤ 254, 1 ≤ C/P ≤ 254
Decode and output color during
VBI
Blank Cr and Cb values during VBI
1
AD_PALM_EN; PAL M autodetect
enable
0x08
0
0
1
0
AD_NTSC_EN; NTSC autodetect
enable
AD_SEC525_EN; SECAM 525
autodetect enable
1
0
1
BL_C_VBI; blank chroma during
VBI; if set, it enables data in the VBI
region to be passed through the
decoder undistorted
TIM_OE; enables timing signals
output
0x07
UG-637
0
1
DEF_Y[5:0]; default value is Y; this
register holds the Y default value
0
0
1
1
0
1
DEF_C[7:0]; default value is C; the
Cr and Cb default values are
defined in this register
0
1
1
1
1
1
Rev. A | Page 71 of 104
Disables
Enables
Disables
Enables
Disables
Enables
Disables
Enables
Disables
Enables
Disables
Enables
Disables
Enables
Disables
Enables
Luma gain = 1
Free-run mode dependent
on DEF_VAL_AUTO_EN
Forces free-run mode on
Disables free-run mode
Enables automatic free-run mode
Y[7:0] = {DEF_Y[5:0], 0, 0}
0
0
Cr[3:0] = {DEF_C[7:4]},
Cb[3:0] = {DEF_C[3:0]}
0x00 gain = 0,
0x80 gain = 1,
0xFF gain = 2
0x00 = 0 IRE,
0x7F = +30 IRE,
0x80 = −30 IRE
Hue range = −90° to
+90°
When lock is lost,
free-run mode can
be enabled to
output stable
timing, clock, and a
set color
Default Y value
output in free-run
mode
Default Cb/Cr value
output in free-run
mode; default
values give blue
screen output
UG-637
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
User Sub Map
Address
0x0E
0x0F
0x10
0x11
0x12
Register
ADI Control 1
Power
management
Status 1
(read only)
IDENT
(read only)
Status 2
(read only)
Bits (Shading Indicates Default)
Bit Description
Reserved
SUB_USR_EN[1:0]; enables user to
access the interrupt/VDP map and
User Sub Map 2
7
Reserved
Reserved
Reserved
PWRDWN; power-down places
the decoder into a full powerdown mode
Reserved
Reset; chip reset, loads all I2C bits
with default values
0
5
0
0
0
1
1
0
4
0
3
0
2
0
1
0
0
0
0
0
0
0
0
1
0
x
x
x
x
x
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
0
0
0
0
1
x
x
x
x
x
Rev. A | Page 72 of 104
1 = in lock (now)
1 = lost lock (since last read)
1 = fSC lock (now)
1 = peak white AGC mode active
NTSC M/NTSC J
NTSC 4.43
PAL M
PAL 60
PAL B/PAL G/PAL H/PAL I/PAL D
SECAM
PAL Combination N
SECAM 525
1 = color kill is active
0
x
x
x
Comments
Sets as default
Accesses main register space
Accesses interrupt/VDP register
space
Accesses User Sub Map 2
Sets as default
Sets to default
Sets to default
System functional
Powered down
Sets to default
Normal operation
Starts reset sequence
0
1
IN_LOCK
LOST_LOCK
FSC_LOCK
FOLLOW_PW
AD_RESULT[2:0]; autodetection
result reports the standard of the
input video
COL_KILL
IDENT[7:0]; provides ID on the
revision of the part
MVCS DET
MVCS T3
MV PS DET
MV AGC DET
LL NSTD
FSC NSTD
Reserved
6
MV color striping detected
MV color striping type
MV pseudosync detected
MV AGC pulses detected
Nonstandard line length
fSC frequency nonstandard
Notes
See Figure 43
Executing reset takes
approximately 2 ms;
this bit is self-clearing
Provides info about
the internal status
of the decoder
Detected standard
Color kill
Power-up value =
0x42
1 = detected
0 = Type 2, 1 = Type 3
1 = detected
1 = detected
1 = detected
1 = detected
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
User Sub Map
Address
0x13
Register
Status 3
(read only)
Bits (Shading Indicates Default)
Bit Description
INST_HLOCK
Reserved
SD_OP_50Hz
7
6
0x15
Analog clamp
control
Digital Clamp
Control 1
4
3
0
x
Comments
1 = horizontal lock achieved
Reserved
SD 60 Hz detected
SD 50 Hz detected
Notes
Unfiltered
SD field rate detect
x
1 = free-run mode active
1 = field length standard
x
x
1 = interlaced video detected
x
1 = swinging burst detected
0
0
0
0
0
1
0
1
0
1
0
1
x
x
x
0
0
1
0
0
0
x
0
1
DCT[1:0]; digital clamp timing
determines the time constant of
the digital fine clamp circuitry
Reserved
1
x
FREE_RUN_PAT_SEL[2:0]
Reserved
CCLEN; current clamp enable
allows the user to switch off the
current sources in the analog
front
Reserved
Reserved
DCFE; digital clamp freeze enable
2
x
Interlaced
PAL_SW_LOCK
5
0
1
Reserved
FREE_RUN_ACT
STD FLD LEN
0x14
UG-637
0
0
1
1
0
1
0
1
0
Rev. A | Page 73 of 104
Single color set by DEF_C and
DEF_Y; see the Color Controls
section
100% color bars
Luma ramp
Boundary box
Sets to default
Current sources switched off
Current sources enabled
Sets to default
Sets to default
Digital clamp on
Digital clamp off
Slow (TC = 1 sec)
Medium (TC = 0.5 sec)
Fast (TC = 0.1 sec)
TC dependent on video
Set to default
Correct field length
found
Field sequence
found
Reliable swinging
burst sequence
UG-637
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
User Sub Map
Address
0x17
Register
Shaping Filter
Control 1
Bits (Shading Indicates Default)
Bit Description
YSFM[4:0]; selects Y shaping filter
mode in CVBS-only mode; allows
the user to select a wide range of
low-pass/notch filters; if either
auto mode is selected, the decoder
selects the optimum Y filter
depending on the CVBS video
source quality (good vs. poor)
7
6
5
4
0
3
0
2
0
1
0
0
0
CSFM[2:0]: C shaping filter mode
allows selection from a range of
low-pass chrominance filters; if
either auto mode is selected, the
decoder selects the optimum C
filter depending on the CVBS
video source quality (good vs.
bad); nonauto settings force a C
filter for all standards and quality of
CVBS video
0
0
0
0
0
1
Comments
Autowide notch for poor quality
sources or wideband filter with
comb for good quality input
Autonarrow notch for poor quality
sources or wideband filter with
comb for good quality input
SVHS 1
SVHS 2
SVHS 3
SVHS 4
SVHS 5
SVHS 6
SVHS 7
SVHS 8
SVHS 9
SVHS 10
SVHS 11
SVHS 12
SVHS 13
SVHS 14
SVHS 15
SVHS 16
SVHS 17
SVHS 18 (CCIR 601)
PAL NN1
PAL NN2
PAL NN3
PAL WN1
PAL WN2
NTSC NN1
NTSC NN2
NTSC NN3
NTSC WN1
NTSC WN2
NTSC WN3
Reserved
Autoselection 1.5 MHz
Autoselection 2.17 MHz
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
SH1
SH2
SH3
SH4
SH5
Wideband mode
Rev. A | Page 74 of 104
Notes
Decoder selects
optimum Y shaping
filter depending on
CVBS quality
If one of these
modes is selected,
the decoder does
not change filter
modes; depending
on video quality, a
fixed filter response
(the one selected) is
used for good and
bad quality video
Automatically
selects a C filter
based on video
standard and
quality
Selects a C filter for
all video standards
and for good and
bad video
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
User Sub Map
Address
0x18
Register
Shaping Filter
Control 2
Bits (Shading Indicates Default)
Bit Description
WYSFM[4:0]; wideband Y shaping
filter mode allows the user to
select which Y shaping filter is
used for the Y component of Y/C,
YPrPb, B/W input signals; it is also
used when a good quality input
CVBS signal is detected; for all
other inputs, the Y shaping filter
chosen is controlled by YSFM[4:0]
Reserved
WYSFMOVR; enables use of the
automatic WYSFM filter
0x19
Comb filter
control
7
6
5
0
0
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
~
1
ADI Control 2
3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
~
1
2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
~
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
~
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
~
1
0
0
1
1
0
1
0
1
x
x
0
1
PSFSEL[1:0]; controls the signal
bandwidth that is fed to the
comb filters (PAL)
NSFSEL[1:0]; controls the signal
bandwidth that is fed to the
comb filters (NTSC)
0x1D
UG-637
Reserved
Reserved
Reserved
1
TRI_LLC; tristate LLC driver
0
1
1
1
0
1
0
0
0
1
1
0
1
0
1
0
x
Comments
Reserved, do not use
Reserved, do not use
SVHS 1
SVHS 2
SVHS 3
SVHS 4
SVHS 5
SVHS 6
SVHS 7
SVHS 8
SVHS 9
SVHS 10
SVHS 11
SVHS 12
SVHS 13
SVHS 14
SVHS 15
SVHS 16
SVHS 17
SVHS 18 (CCIR 601)
Reserved, do not use
Reserved, do not use
Reserved, do not use
Set to default
Autoselection of best filter
Manual select filter using
WYSFM[4:0]
Narrow
Medium
Wide
Widest
Narrow
Medium
Medium
Wide
1
LLC pin active
LLC pin tristated
Rev. A | Page 75 of 104
Notes
UG-637
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
User Sub Map
Address
0x27
Register
Pixel delay
control
Bits (Shading Indicates Default)
Bit Description
LTA[1:0]; luma timing adjust
allows the user to specify a timing
difference between chroma and
luma samples
7
6
Reserved
CTA[2:0]; chroma timing adjust
allows a specified timing
difference between the luma and
chroma samples
AUTO_PDC_EN; automatic
programmed delay control.
automatically programs the
LTA/CTA values so that luma and
chroma are aligned at the output
for all modes of operation
SWPC; allows the Cr and Cb
samples to be swapped
0x2B
Misc gain
control
AGC mode
control
4
3
2
1
0
0
0
0
1
Comments
No delay
Luma one clock (37 ns) late
1
1
0
1
Luma two clocks (74 ns) early
Luma one clock (37 ns) early
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
Sets to 0
Reserved
Chroma + two pixels (early)
Chroma + one pixel (early)
No delay
Chroma − one pixel (late)
Chroma − two pixels (late)
Chroma − three pixels (late)
Reserved
Use values in LTA[1:0] and
CTA[2:0] for delaying
luma/chroma
0
1
0
1
0
1
0
1
0
1
PW_UPD; peak white update
determines the rate of gain
Reserved
CAGC[1:0]; chroma automatic
gain control selects the basic
mode of operation for the AGC in
the chroma path
0
1
1
Reserved
0
0
0
0
No swapping
Swaps the Cr and Cb output
samples
Updates once per video line
Updates once per field
Sets to default
Color kill disabled
Color kill enabled
0
1
1
0
0
0
0
0
1
Sets to default
Manual fixed gain
Uses luma gain for chroma
Automatic gain
Freeze chroma gain
Sets to 1
Manual fixed gain
AGC peak white algorithm off
0
1
0
AGC peak white algorithm on
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
Reserved
Reserved
Reserved
Reserved
Freeze gain
Sets to 1
0
0
1
1
Reserved
LAGC[2:0]; luma automatic gain
control selects the mode of
operation for the gain control in
the luma path
Notes
CVBS mode,
LTA[1:0] = 00b,
Y/C mode,
LTA[1:0] = 01b,
YPrPb mode,
LTA[1:0] = 01b
CVBS mode
CTA[2:0] = 011b,
Y/C mode,
CTA[2:0] = 101b,
YPrPb mode,
CTA[2:0] = 110b
LTA and CTA values determined
automatically
0
1
Reserved
CKE; color kill enable allows the
color kill function to be switched on
and off
0x2C
5
1
1
1
Rev. A | Page 76 of 104
0
1
0
1
Peak white must be
enabled; see
LAGC[2:0]
For SECAM color
kill, the threshold is
set at 8%; see
CKILLTHR[2:0]
Use CMG[11:0]
Based on color burst
Uses LMG[11:0]
Blank level to sync
tip
Blank level to sync
tip
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
User Sub Map
Address
0x2D
0x2E
0x2F
Register
Chroma Gain
Control 1,
Chroma Gain 1
(CG)
Chroma Gain
Control 2,
Chroma Gain 2
(CG)
Luma Gain
Control 1, Luma
Gain 1 (LG)
0x30
Luma Gain
Control 2, Luma
Gain 2 (LG)
0x31
VS/FIELD
Control 1
Bits (Shading Indicates Default)
Bit Description
CMG[11:8]/CG[11:8]; in manual
mode, the chroma gain control can
be used to program a desired
manual chroma gain; in auto mode,
it can be used to read back the
current gain value
Reserved
CAGT[1:0]; chroma automatic
gain timing allows adjustment of
the chroma AGC tracking speed
CMG[7:0]/CG[7:0]; chroma manual
gain lower eight bits; see
CMG[11:8]/CG[11:8] for
description
LMG[11:8]/LG[11:8]; in manual
mode, luma gain control can be
used to program a desired
manual luma gain; in auto mode, it
can be used to read back the
actual gain value used
Reserved
LAGT[1:0]; luma automatic gain
timing allows adjustment of the
luma AGC tracking speed
LMG[7:0]/LG[7:0]; luma manual
gain/ luma gain lower eight bits;
see LMG[11:8]/LG[11:8] for
description
Reserved
HVSTIM; horizontal VSYNC timing;
selects where within a line of
video the VSYNC signal is asserted
NEWAVMODE; sets the EAV/SAV
mode
7
6
0
0
1
1
0
0
1
0
1
0
5
4
1
1
0
0
1
0
0
1
1
x
0
1
0
1
x
x
3
0
2
1
1
0
0
0
0
0
0
0
x
x
x
x
1
x
x
x
x
x
0
1
0
0
1
0
1
0x32
VS/FIELD
Control 2
Reserved
Reserved
VSBHE
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
1
VSBHO
0
1
0x33
VS/FIELD
Control 3
UG-637
Reserved
VSEHE
0
1
VSEHO
0
1
Rev. A | Page 77 of 104
Comments
Notes
CAGC[1:0] settings
decide in which
mode CMG[11:0]
operates
Set to 1
Slow (TC = 2 sec)
Medium (TC = 1 sec)
Reserved
Adaptive
CMG[11:0] = see the CMG section
Has an effect only if
CAGC[1:0] is set to
autogain (10)
Minimum value =
0d,
maximum value =
4095d
LAGC[1:0] settings decide in which
mode LMG[11:0] operates
Sets to 1
Slow (TC = 2 sec)
Medium (TC = 1 sec)
Fast (TC = 0.2 sec)
Adaptive
LMG[7:0]/LG[7:0]; luma manual
gain/luma gain lower eight bits; see
LMG[11:8]/LG[11:8] for description
Sets to default
Start of line relative to HSE
Start of line relative to HSB
EAV/SAV codes generated to suit
Analog Devices encoders
Manual VS/FIELD position
controlled by the Register 0x32,
Register 0x33, and Register 0xE5 to
Register 0xEA
Sets to default
Sets to default
VSYNC signal goes high in the
middle of the line (even field)
VSYNC signal changes state at the
start of the line (even field)
VSYNC signal goes high in the
middle of the line (odd field)
VSYNC signal changes state at the
start of the line (odd field)
Sets to default
VSYNC signal goes low in the
middle of the line (even field)
VSYNC signal changes state at the
start of the line (even field)
VSYNC signal goes low in the
middle of the line (odd field)
VSYNC signal changes state at the
start of the line odd field
Has an effect only if
LAGC[1:0] is set to
autogain (001, 010)
Minimum value =
1024d,
Maximum value =
4095d
HSE = HSYNC end
HSB = HSYNC begin
NEWAVMODE bit
must be set high
NEWAVMODE bit
must be set high
UG-637
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
User Sub Map
Address
0x34
Register
HS Position
Control 1
0x35
HS Position
Control 2
0x36
HS Position
Control 3
Polarity
0x37
Bits (Shading Indicates Default)
Bit Description
HSE[10:8]; HSYNC end allows
positioning of the HSYNC output
within the video line
Reserved
HSB[10:8]; HSYNC begin allows
positioning of the HSYNC output
within the video line
Reserved
HSB[7:0]; see Address 0x34, using
HSB[10:0] and HSE[10:0], users can
program the position and length of
the HSYNC output signal
HSE[7:0]; see Address 0x35
description
PCLK; sets polarity of LLC
7
6
5
4
0
0
0
0
0
0
0
0
0
0
1
0
NTSC comb
control
0
0
0
0
0
0
0
0
0
0
Comments
HSYNC output ends HSE[10:0]
pixels after the falling edge of
HSYNC
Sets to 0
HS output starts HSB[10:0] pixels
after the falling edge of HSYNC
0
1
Notes
Using HSB and HSE,
the position/length
of the output HSYNC
can be
programmed
0
0
Inverts polarity
Normal polarity as per the timing
diagrams
Set to 0
0
1
0
0
1
0
0
1
0
1
YCMN[2:0]; luma comb mode,
NTSC
CCMN[2:0]; chroma comb mode,
NTSC
CTAPSN[1:0]; chroma comb taps,
NTSC
1
0
Sets to 0
Reserved
PVS; sets the VSYNC polarity
0x38
2
0
0
Reserved
PF; sets the FIELD polarity
Reserved
PHS; sets HSYNC polarity
3
0
0
1
1
0
0
0
1
1
0
0
0
1
1
1
0
1
1
1
0
0
0
1
1
0
0
0
1
1
1
0
1
1
1
0
1
0
1
Rev. A | Page 78 of 104
Active high
Active low
Sets to 0
Active high
Active low
Adaptive three-line, three-tap luma
comb
Uses low-pass/notch filter
Fixed luma comb two-line (two
taps)
Fixed luma comb three-line (three
taps)
Fixed luma comb two-line (two
taps)
Three-line adaptive for CTAPSN = 01,
four-line adaptive for CTAPSN = 10,
five-line adaptive for CTAPSN = 11
Disables chroma comb
Fixed two-line for CTAPSN = 01,
fixed three-line for CTAPSN = 10,
fixed four-line for CTAPSN = 11
Fixed three-line for CTAPSN = 01,
fixed four-line for CTAPSN = 10,
fixed five-line for CTAPSN = 11
Fixed two-line for CTAPSN = 01,
fixed three-line for CTAPSN = 10,
fixed four-line for CTAPSN = 11
Not used
Adapts three lines to two lines
Adapts five lines to three lines
Adapts five lines to four lines
Top lines of memory
All lines of memory
Bottom lines of
memory
Top lines of memory
All lines of memory
Bottom lines of
memory
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
User Sub Map
Address
0x39
Register
PAL comb
control
Bits (Shading Indicates Default)
Bit Description
YCMP[2:0]; luma comb mode,
PAL
7
6
CCMP[2:0]; chroma comb mode,
PAL
CTAPSP[1:0]; chroma comb taps,
PAL
0x3A
ADC control
UG-637
0
0
0
1
1
0
1
1
5
4
3
0
0
0
1
1
0
0
0
1
1
1
0
1
1
1
2
0
1
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
Comments
Adaptive five-line, three-tap luma
comb
Use low-pass notch filter
Fixed luma comb (three-line)
Fixed luma comb (five-line)
Fixed luma comb (three-line)
Three-line adaptive for CTAPSN = 01,
four-line adaptive for CTAPSN = 10,
five-line adaptive for CTAPSN = 11
Disable chroma comb
Fixed two-line for CTAPSN = 01,
fixed three-line for CTAPSN = 10,
fixed four-line for CTAPSN = 11
Fixed three-line for CTAPSN = 01,
fixed four-line for CTAPSN = 10,
fixed five-line for CTAPSN = 11
Fixed two-line for CTAPSN = 01,
fixed three-line for CTAPSN = 10,
fixed four-line for CTAPSN = 11
Not used
Adapts five lines to three lines
(two taps)
Adapts five lines to three lines
(three taps)
Adapts five lines to four lines (four
taps)
MUX PDN override; mux powerdown override
0
0
1
PWRDWN_MUX_1; enables
power-down of MUX1 and
associated channel clamp and
buffer
0
1
PWRDWN_MUX_0; enables
power-down of MUX0 and
associated channel clamp and
buffer
Reserved
0
1
0
0
0
0
Rev. A | Page 79 of 104
Top lines of memory
All lines of memory
Bottom lines of
memory
Top lines of memory
All lines of memory
Bottom lines of
memory
No control over
power-down for
muxes and
associated channel
circuit
Allows power-down
of MUX0/MUX1/
MUX2 and
associated channel
circuit; when
INSEL[4:0] is used,
unused channels are
automatically
powered down
1
PWRDWN_MUX_2; enables
power-down of MUX2 and
associated channel clamp and
buffer
Notes
MUX2 and associated channel in
normal operation
Power down MUX2 and associated
channel operation
MUX1 and associated channel in
normal operation
Power down MUX1 and associated
channel operation
MUX0 and associated channel in
normal operation
Power down MUX0 and associated
channel operation
Sets as default
MUX PDN override =
1
MUX PDN override =
1
MUX PDN override =
1
UG-637
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
User Sub Map
Address
0x3D
0x41
Register
Manual
window
control
Resample
control
Bits (Shading Indicates Default)
Bit Description
Reserved
CKILLTHR[2:0]; color kill threshold
Reserved
Reserved
SFL_INV; controls the behavior of
the PAL switch bit
7
6
5
4
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
0
0
3
0
2
0
1
1
0
0
0
0
0
0
1
0
1
0x4D
CTI DNR
Control 1
Reserved
CTI_EN; CTI enable
0
0
1
CTI_AB_EN; enables the mixing of
the transient improved chroma
with the original signal
CTI_AB[1:0]; controls the
behavior of the alpha-blend
circuitry
0
1
Reserved
DNR_EN; enables or bypasses the
DNR block
0x4E
CTI DNR
Control 2
0x50
DNR Noise
Threshold 1
Reserved
CTI_C_TH[7:0]; specifies how big
the amplitude step must be to be
steepened by the CTI block
DNR_TH[7:0]; specifies the
maximum luma edge that is
interpreted as noise and is
therefore blanked
0
0
0
1
1
0
1
1
Sharpest mixing between
sharpened/original chroma signal
Sharp mixing between sharpened
and original chroma signal
Smooth mixing between
sharpened/original chroma signal
Smoothest mixing between
sharpened and original chroma
signal
Sets to default
Bypasses the DNR block
Enables the DNR block
Sets to default
0
0
1
1
0
1
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
Rev. A | Page 80 of 104
Comments
Sets to default
NTSC, PAL color kill at <0.5%,
SECAM no color kill
NTSC, PAL color kill at <1.5%,
SECAM color kill at <5%
NTSC, PAL color kill at <2.5%,
SECAM color kill at <7%
NTSC, PAL color kill at <4%,
SECAM color kill at <8%
NTSC, PAL color kill at <8.5%,
SECAM color kill at <9.5%
NTSC, PAL color kill at <16%,
SECAM color kill at <15%
NTSC, PAL color kill at <32%,
SECAM color kill at <32%
Reserved
Sets to default
Sets to default
SFL-compatible with the ADV717x
and ADV73xx video encoders
SFL-compatible with older video
encoders such as the ADV7194.
Set to default
Disables CTI
Enables CTI
Disables CTI alpha blender
Enables CTI alpha blender
Notes
CKE = 1 enables the
color kill function
and must be
enabled for
CKILLTHR[2:0] to
take effect
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
User Sub Map
Address
0x51
Register
Lock count
Bits (Shading Indicates Default)
Bit Description
CIL[2:0]; count into lock
determines the number of lines
the system must remain in lock
before showing a locked status
7
6
COL[2:0]; count out of lock
determines the number of lines
the system must remain out-oflock before showing a lost-locked
status
SRLS; select raw lock signal and
selects the determination of the
lock status
FSCLE; fSC lock enable
5
4
3
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
DIAG1 Control
Reserved
DIAG1_SLICE_LEVEL[2:0]
0
Reserved
DIAG1_SLICER_PWRDN
0x5E
DIAG2 Control
Reserved
Reserved
DIAG2_SLICE_LEVEL[2:0]
0x59
GPO
Reserved
GPO[0]
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Set the DIAG1 slice level to 75 mV
Set the DIAG1 slice level to 225 mV
Set the DIAG1 slice level to 375 mV
Set the DIAG1 slice level to 525 mV
Set the DIAG1 slice level to 675 mV
Set the DIAG1 slice level to 825 mV
Set the DIAG1 slice level to 975 mV
Set the DIAG1 slice level to 1.125 V
Reserved
Power up the DIAG1 slicer
Power down the DIAG1 slicer
Reserved
1
0
0
1
1
0
1
0
0
1
GPO[1]
0
1
GPO[2]
0
1
Reserved
GPO_ENABLE
Reserved
1
0
1
Reserved
DIAG1_SLICER_PWRDN
0
0
1
0
Comments
One line of video
Two lines of video
Five lines of video
10 lines of video
100 lines of video
500 lines of video
1000 lines of video
100,000 lines of video
One line of video
Two lines of video
Five lines of video
10 lines of video
100 lines of video
500 lines of video
1000 lines of video
100,000 lines of video
Over field with vertical info
Line-to-line evaluation
Notes
Lock status set only by horizontal
lock
Lock status set by horizontal lock
and subcarrier lock
0
1
0x5D
UG-637
0
0
Rev. A | Page 81 of 104
Set the DIAG2 slice level to 75 mV
Set the DIAG2 slice level to 225 mV
Set the DIAG2 slice level to 375 mV
Set the DIAG2 slice level to 525 mV
Set the DIAG2 slice level to 675 mV
Set the DIAG2 slice level to 825 mV
Set the DIAG2 slice level to 975 mV
Set the DIAG2 slice level to 1.125 V
Reserved
Power up the DIAG1 slicer
Power down the DIAG1 slicer
Reserved
Logic 0 output from GPO0 pin
Logic 1 output from GPO0 pin
Logic 0 output from GPO1 pin
Logic 1 output from GPO1 pin
Logic 0 output from GPO2 pin
Logic 1 output from GPO2 pin
Reserved
GPO pins are tristated
GPO pins are enabled
Note that it
recommended that
the DIAG1 slice
level not be set to
75 mV, 225 mV, or
375 mV to achieve
optimal performance of the
ADV728x.
Note that it
recommended that
the DIAG2 slice
level not be set to
75 mV, 225 mV, or
375 mV to achieve
optimal performance of the
ADV728x.
GPO_ENABLE must
be set to 1 in order
for GPO outputs to
be enabled.
GPO outputs only
available on
ADV728x-M models.
UG-637
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
User Sub Map
Bits (Shading Indicates Default)
Address
0x60
Register
ADC Switch 3
Bit Description
MUX3[2:0]
7
6
5
4
0
0
1
Output Sync
Select 1
Reserved
HS_OUT_SEL[2:0] selects which
sync comes out on the HS pin
0
0x6A
Output Sync
Select 2
Reserved
FLD_OUT_SEL[2:0] selects which
sync comes out on the
VS/FIELD/SFL pin
0
0x6B
Free-Run Line
Length 1
Reserved
Reserved
0
0x8F
Reserved
CCAP1[7:0]; closed caption data
register
CCAP2[7:0]; closed caption data
register
LB_LCT[7:0]; letterbox data
register
LB_LCM[7:0]; letterbox data
register
0x9D
Letterbox 3
(read only)
LB_LCB[7:0]; letterbox data
register
0xB2
CRC enable
(write only)
Reserved
CRC_ENABLE; enable CRC
checksum decoded from FMS
packet to validate CGMSD
0x9A
0x9B
0x9C
0xC3
ADC Switch 1
Reserved
MUX0[2:0]; manual muxing
control for MUX0; this setting
controls which input is routed to
the ADC for processing
0
1
0
0
1
1
0
0
0
1
0
1
0
Comments
No connect
No connect
AIN2
No connect
AIN4
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
HSYNC
VSYNC
FIELD
DE
SFL
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
0
0
0
HSYNC
VSYNC
FIELD
DE
SFL
Set as default
Set as default
1
0
0
0
1
0
1
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
0
0
0
0
0
1
1
0
0
1
0
1
0
0
1
0
0
0
1
1
0
0
0
0
1
LLC (nominal 27 MHz) selected out
on LLC pin
LLC (nominal 13.5 MHz) selected
out on LLC pin
Sets to default
CCAP1[7] contains parity bit for
Byte 0
CCAP2[7] contains parity bit for
Byte 0
Reports the number of black lines
detected at the top of active video
Reports the number of black lines
detected in the middle half of
active video if subtitles are
detected
Reports the number of black lines
detected at the bottom of active
video
Sets as default
Turns off CRC check
CGMSD goes high with valid
checksum
Sets as default
No connect
AIN1
AIN2
AIN3
AIN4
0
0
0
0
0
1
0
0
1
1
0
Notes
0
0
Reserved
MUX1[2:0]; manual muxing
control for MUX1; this setting
controls which input is routed to
the ADC for processing
Reserved
0
2
0
0
0
0
1
0
LLC_PAD_SEL[2:0]; enables manual
selection of the clock for the LLC
pin
CCAP1
(read only)
CCAP2
(read only)
Letterbox 1
(read only)
Letterbox 2
(read only)
0x99
0
3
0
0
0
0
0
0
0
1
0
1
0
0
Rev. A | Page 82 of 104
No connect
No connect
AIN2
No connect
AIN4
This feature
examines the active
video at the start
and end of each
field; it enables
format detection
even if the video is
not accompanied
by a CGMS or WSS
sequence
MAN_MUX_EN = 1
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
User Sub Map
Address
0xC4
Register
ADC Switch 2
Bits (Shading Indicates Default)
Bit Description
MUX2[2:0]; manual muxing
control for MUX2; this setting
controls which input is routed to
the ADC for processing
Reserved
MAN_MUX_EN; enable manual
setting of input signal muxing
0xDC
Letterbox
Control 1
0xDD
Letterbox
Control 2
0xDE
0xDF
0xE1
0xE2
ST Noise
Readback 1
(read only)
ST Noise
Readback 2
(read only)
SD offset Cb
channel
SD offset Cr
channel
UG-637
7
6
5
4
3
0
0
0
0
2
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
0
1
LB_TH[4:0]; sets the threshold
value that determines if a line is
black
0
1
0
0
1
1
0
0
x
x
x
Reserved
LB_EL[3:0]; programs the end line
of the activity window for LB
detection (end of field)
LB_SL[3:0]; programs the start
line of the activity window for LB
detection (start of field)
ST_NOISE[10:8]
ST_NOISE_VLD
1
ST_NOISE[7:0]
x
x
x
x
x
x
x
x
SD_OFF_Cb[7:0]; adjusts the hue
by selecting the offset for the Cb
channel
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
1
1
0
1
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
0
1
0
0
1
0
0
0
1
0
0
1
1
0
0
1
0
0
1
0
0
0
1
0
0
1
1
SD_OFF_Cr[7:0]; adjusts the hue
by selecting the offset for the Cr
channel
0xE3
SD saturation
Cb channel
SD_SAT_Cb[7:0]; adjusts the
saturation by affecting gain on
the Cb channel
0xE4
SD saturation
Cr channel
SD_SAT_Cr[7:0]; adjusts the
saturation by affecting gain on
the Cr channel
0xE5
NTSC VSYNC
begin
NVBEG[4:0]; number of lines after
lCOUNT rollover to set V high
NVBEGSIGN
1
0
1
1
1
0
0
x
Notes
MAN_MUX_EN = 1
Disables
Enables
This bit must be set
to 1 for manual
muxing
Default threshold for the
detection of black lines
01101 to 10000—increase
threshold,
00000 to 01011—decrease
threshold
Sets as default
LB detection ends with the last
line of active video on a field,
1100b: 262/525
Letterbox detection aligned with
the start of active video, 0100b:
23/286 NTSC
When = 1, ST_NOISE[10:0] is valid
0
1
NVBEGDELE; delay V bit going
high by one line relative to
NVBEG (even field)
NVBEGDELO; delay V bit going
high by one line relative to
NVBEG (odd field)
Comments
No connect
No connect
AIN2
AIN3
No connect
0
1
0
1
−312 mV offset applied to the Cb
channel
0 mV offset applied to the Cb
channel
+312 mV offset applied to the Cb
channel
−312 mV offset applied to the Cr
channel
0 mV offset applied to the Cr
channel
+312 mV offset applied to the Cr
channel
Gain on Cb channel = −42 dB
Gain on Cb channel = 0 dB
Gain on Cb channel = +6 dB
Gain on Cr channel = −42 dB
Gain on Cr channel = 0 dB
Gain on Cr channel = +6 dB
NTSC default (ITU-R BT.656)
Sets to low when manual
programming
Not suitable for user programming
No delay
Additional delay by one line
No delay
Additional delay by one line
Rev. A | Page 83 of 104
ST noise[10:0]
measures the noise
on the horizontal
sync tip of video
source
UG-637
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
User Sub Map
Address
0xE6
Register
NTSC VSYNC
end
Bits (Shading Indicates Default)
Bit Description
NVEND[4:0]; number of lines after
lCOUNT rollover to set V low
NVENDSIGN
7
6
5
4
0
3
0
2
1
1
0
0
0
0
Sets to low when manual
programming
Not suitable for user programming
No delay
Additional delay by one line
1
0xE7
NTSC FIELD
toggle
NVENDDELE; delay V bit going
low by one line relative to NVEND
(even field)
NVENDDELO; delay V bit going
low by one line relative to NVEND
(odd field)
NFTOG[4:0]; number of lines after
lCOUNT rollover to toggle F signal
NFTOGSIGN
0
1
0
1
No delay
Additional delay by one line
0
0
0
1
1
0
0xE8
PAL VSYNC
begin
0
1
0
1
No delay
Additional delay by one line
0
0
1
0
1
0
0xE9
PAL VSYNC
end
0
1
0
1
No delay
Additional delay by one line
1
0
1
0
0
0
0xEA
PAL FIELD
toggle
0
1
0
1
No delay
Additional delay by one line
0
0
0
0
1
PFTOGDELE; delay F transition by
one line relative to PFTOG (even
field)
PFTOGDELO; delay F transition by
one line relative to PFTOG (odd
field)
PAL default (ITU-R BT.656)
Sets to low when manual
programming
Not suitable for user programming
No delay
Additional delay by one line
1
PVENDDELE; delay V bit going low
by one line relative to PVEND
(even field)
PVENDDELO; delay V bit going
low by one line relative to PVEND
(odd field)
PFTOG[4:0]; number of lines after
lCOUNT rollover to toggle F signal
PFTOGSIGN
PAL default (ITU-R BT.656)
Sets to low when manual
programming
Not suitable for user programming
No delay
Additional delay by one line
1
PVBEGDELE; delay V bit going
high by one line relative to
PVBEG (even field)
PVBEGDELO; delay V bit going
high by one line relative to
PVBEG (odd field)
PVEND[4:0]; number of lines after
lCOUNT rollover to set V low.
PVENDSIGN
NTSC default
Sets to low when manual
programming
Not suitable for user programming
No delay
Additional delay by one line
1
NFTOGDELE; delay F transition by
one line relative to NFTOG (even
field)
NFTOGDELO; delay F transition
by one line relative to NFTOG
(odd field)
PVBEG[4:0]; number of lines after
lCOUNT rollover to set V high
PVBEGSIGN
Comments
NTSC default (ITU-R BT.656)
0
1
0
1
1
1
PAL default (ITU-R BT.656)
Sets to low when manual
programming
Not suitable for user programming
No delay
Additional delay by one line
No delay
Additional delay by one line
Rev. A | Page 84 of 104
Notes
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
User Sub Map
Address
0xEB
Register
Vblank
Control 1
Bits (Shading Indicates Default)
Bit Description
PVBIELCM[1:0]; PAL VBI even field
line control
7
6
5
4
PVBIOLCM[1:0]; PAL VBI odd field
line control
NVBIOLCM[1:0]; NTSC VBI odd field
line control
Vblank
Control 2
0
0
1
1
0
0
1
1
0
0
Comments
VBI ends one line earlier (Line 335)
0
1
1
1
0
1
ITU-R BT.470 compliant (Line 336)
VBI ends one line later (Line 337)
VBI ends two lines later (Line 338)
VBI ends one line earlier (Line 22)
ITU-R BT.470 compliant (Line 23)
VBI ends one line later (Line 24)
VBI ends two lines later (Line 25)
VBI ends one line earlier (Line 282)
ITU-R BT.470 compliant (Line 283)
VBI ends one line later (Line 284)
VBI ends two lines later (Line 285)
VBI ends one line earlier (Line 20)
ITU-R BT.470 compliant (Line 21)
VBI ends one line later (Line 22)
VBI ends two lines later (Line 23)
Color output beginning Line 335
ITU-R BT.470 compliant color
output beginning Line 336
Color output beginning Line 337
Color output beginning Line 338
Color output beginning Line 22
ITU-R BT.470-compliant color
output beginning Line 23
Color output beginning Line 24
Color output beginning Line 25
Color output beginning Line 282
ITU-R BT.470-compliant color
output beginning Line 283
VBI ends one line later (Line 284)
Color output beginning Line 285
Color output beginning Line 20
ITU-R BT.470 compliant color
output beginning Line 21
Color output beginning Line 22
Color output beginning Line 23
Antialiasing Filter 1 disabled
0
1
0
1
PVBIECCM[1:0]; PAL VBI even field
color control
NVBIOCCM[1:0]; NTSC VBI odd
field color control
1
0
0
1
0
1
NVBIECCM[1:0]; NTSC VBI even
field color control
AFE_
CONTROL 1
2
0
1
0
1
PVBIOCCM[1:0]; PAL VBI odd field
color control
0xF3
3
0
0
1
1
NVBIELCM[1:0]; NTSC VBI even
field line control
0xEC
UG-637
0
0
0
1
1
1
0
1
0
0
0
1
1
1
0
1
0
0
0
1
1
1
0
1
0
0
0
1
1
1
0
1
AA_FILT_EN[3:0] antialiasing filter
enable
0
1
0
1
0
1
0
1
AA_FILT_MAN_OVR; antialiasing
filter override
Reserved
0
1
0
0
0
Rev. A | Page 85 of 104
Antialiasing Filter 1 enabled
Antialiasing Filter 2 disabled
Antialiasing Filter 2 enabled
Antialiasing Filter 3 disabled
Antialiasing Filter 3 enabled
Antialiasing Filter 4 enabled
Antialiasing Filter 4 enabled
Override disabled
Override enabled
Notes
Controls position of
first active (comb
filtered) line after VBI
on even field in PAL
Controls position of
first active (comb
filtered) line after VBI
on odd field in PAL
Controls position of
first active (comb
filtered) line after VBI
on even field in NTSC
Controls position of
first active (comb
filtered) line after VBI
on odd field in NTSC
Controls the
position of first line
that outputs color
after VBI on even
field in PAL
Controls the
position of first line
that outputs color
after VBI on odd field
in PAL
Controls the
position of first line
that outputs color
after VBI on even
field in NTSC
Controls the
position of first line
that outputs color
after VBI on odd field
in NTSC
AA_FILT_MAN_OVR
must be enabled to
change settings
defined by
INSEL[4:0]
UG-637
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
User Sub Map
Address
0xF4
Register
Drive strength
Bits (Shading Indicates Default)
Bit Description
DR_STR_S[1:0]; selects the drive
strength for the sync output
signals
7
6
5
4
DR_STR_C[1:0]; selects the drive
strength for the clock output
signal
DR_STR[1:0]; selects the drive
strength for the data output signals;
can be increased or decreased for
EMC or crosstalk reasons
Reserved
GLITCH_FILT_BYP
0xF8
0xF9
IF comp
control
VS mode
control
0
0
1
1
3
2
0
0
1
1
0
1
0
1
0
0
1
0
1
Comments
Low drive strength (1×)
Medium low drive strength (2×)
Medium drive strength (3×)
High drive strength (4×)
Low drive strength (1×)
Medium low drive strength (2×)
Medium drive strength (3×)
High drive strength (4×)
Low drive strength (1×)
Medium low drive strength (2×)
Medium drive strength (3×)
High drive strength (4×)
Notes
Note the low drive
strength settings for
DR_STR, DR_STR_C
and DR_STR_S are
not recommended
for the optimal
performance of the
ADV728x.
0
0
0
Bypass mode
0 dB
0
0
0
1
0
1
1
0
1
0
1
0
1
1
1
0
1
1
1
0
1
0
1
0
1
x
0
1
IFFILTSEL[2:0]; IF filter selection
for PAL and NTSC
Reserved
EXTEND_VS_MAX_FREQ
1
0
0
1
1
0
0
0
0
0
0
1
EXTEND_VS_MIN_FREQ
0
1
VS_COAST_MODE[1:0]
0
0
1
1
0
1
0
1
Reserved
PEAKING_GAIN[7:0]
0
0
0
1
0
0
0
0
0
0
0
0
DNR Noise
Threshold 2
DNR_TH2[7:0]
0
0
0
0
0
1
0
0
VPP slave
address
Reserved
VPP_SLAVE_ADDR[6:0]
0
0
0
0
0
0
0
0xFB
Peaking gain
0xFC
0xFD
2 MHz NTSC filters
−3 dB
−6 dB
−10 dB
Reserved
3 MHz PAL filters
−2 dB
−5 dB
−7 dB
0
Rev. A | Page 86 of 104
Limits maximum VSYNC frequency
to 66.25 Hz (475 lines/frame)
Limits maximum VSYNC frequency
to 70.09 Hz (449 lines/frame)
Limits minimum VSYNC frequency
to 42.75 Hz (731 lines/frame)
Limits minimum VSYNC frequency
to 39.51 Hz (791 lines/frame)
Autocoast mode
576i 50 Hz coast mode
480i 60 Hz coast mode
Reserved
Increases/decreases the gain for
high frequency portions of the
video signal
Specifies the maximum luma edge
that is interpreted as noise and
therefore blanked
Reserved
Programs the I2C address of the
Video Post Processor (VPP) Map
This value forces
the video standard
output during freerun mode
Applies only to the
ADV7280,
ADV7280-M, and
ADV7282-M models.
VPP map cannot be
accessed when this
register is set to 0x00.
Analog Devices
recommended
scripts set this
register to 0x84.
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
User Sub Map
Address
0xFE
Register
CSI Tx slave
address
UG-637
Bits (Shading Indicates Default)
Bit Description
Reserved
CSI_TX_SLAVE_ADDR(6:0)
7
6
5
4
3
2
1
0
0
0
0
0
0
0
Rev. A | Page 87 of 104
0
0
Comments
Reserved
Programs the I2C address of the CSI
Map
Notes
Applies only to the
ADV7280-M,
ADV7281-M,
ADV7281-MA, and
ADV7282-M models.
CSI Map cannot be
accessed when this
register is set to 0x00.
Analog Devices
recommended script
sets this register to
0x88.
UG-637
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
USER SUB MAP 2 DESCRIPTION
To access the registers listed in Table 105, SUB_USR_EN in Register Address 0x0E must be programmed to 10. The gray shading is the
default.
Table 105. User Sub Map 2 Register Map Descriptions
User Sub Map 2
Address
Register
0x80
ACE Control 1
Bit Description
Reserved
ACE_ENABLE
Bits (Shading Indicates Default)
7 6 5 4 3 2 1 0
0 0 0
0
0
0
0
0
1
0
1
1
0
1
0x83
ACE Control 4
ACE_LUMA_GAIN[4:0]
ACE Control 5
Reserved
ACE_CHROMA_GAIN[3:0]
0
0x84
ACE_CHROMA_MAX[3:0]
1
0x85
ACE Control 6
0
0
1
1
1
1
0
0
0
0
ACE_GAMMA_GAIN[3:0]
ACE_RESPONSE_SPEED[3:0]
0
0
0
1
0x92
Dither control
BR_DITHER_MODE
0xD9
Min Max 0
Reserved
MIN_THRESH_Y[7:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0xDA
Min Max 1
MAX_THRESH_Y[7:0]
1
1
1
1
1
1
1
1
0xDB
Min Max 2
MIN_THRESH_C[7:0]
0
0
0
0
0
0
0
0
0xDC
Min Max 3
MAX_THRESH_C[7:0]
1
1
1
1
1
1
1
1
0xDD
Min Max 4
MAX_SAMPLES_ALLOWED_
Y[3:0]
1
1
0
0
1
1
0
0
MIN_SAMPLES_ALLOWED_
Y[3:0]
0xDE
Min Max 5
FL Control
1
0
0
MAX_SAMPLES_ALLOWED_
C[3:0]
MIN_SAMPLES_ALLOWED_
C[3:0]
0xE0
0
1
1
1
1
0
0
FL_ENABLE
Reserved
0
1
0
0
Notes
When ACE_
ENABLE is set to 1
0
1
0
Comments
Reserved.
Disable ACE.
Enable ACE.
Set ACE luma auto-contrast level to
default value.
5b’00000 minimum value
…
5b’11111 maximum value
0
0
0
0
Rev. A | Page 88 of 104
0
Set ACE color auto-saturation level.
4b’0000 minimum value
…
4b’1111 maximum value
Set maximum threshold for ACE color
color-saturation level.
4b’0000 = minimum value
…
4b’1111 = maximum value
Set further contrast enhancement.
4b’0000 = minimum value
…
4b’1111 = maximum value
Set speed of ACE response.
4b’0000 slowest value
…
4b’1111 fastest value
8-bit to 6-bit down dither disabled
8-bit to 6-bit down dither enabled
Selects the minimum threshold for the
incoming luma video signal.
Selects the maximum threshold for the
incoming luma video signal.
Selects the minimum threshold for the
incoming chroma video signal.
Selects the maximum threshold for the
incoming chroma video signal.
Selects the number of maximum luma
samples allowed in a given window
before an interrupt is triggered.
Selects the number of minimum luma
samples allowed in a given window
before an interrupt is triggered.
Selects the number of maximum
chroma samples allowed in a given
window before an interrupt is
triggered.
Selects the number of minimum
chroma samples allowed in a given
window before an interrupt is
triggered.
Fast lock mode not enabled
Enables fast lock mode
See Subaddress
0xE5 for least
significant bits
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
User Sub Map 2
Address
Register
0xE1
Y Average 0
0xE2
Y Average 1
0xE3
Y Average 2
0xE4
0xE5
0xE6
Y Average 3
Y Average 4
Y Average 5
Bit Description
LINE_START[8:1]
LINE_END[8:1]
SAMPLE_START[9:2]
SAMPLE_END[9:2]
LINE_START[0]
LINE_END[0]
Reserved
SAMPLE_START[1:0]
SAMPLE_END[1:0]
CAPTURE_VALUE
Bits (Shading Indicates Default)
7 6 5 4 3 2 1 0
0 0 0 1
0
0
0
1
1 0 0
0
1
0
0
0
0 0 0
1
0
1
1
1
1
1
0
1
0
1
0
0
1
0
0
0
0
0
Y_AVG_TIME_CONST[2:0]
0xE8
Y Average Data
MSB
Y Average Data
LSB
1
1
Notes
See Subaddress
0xE5 for least
significant bits
1
Y_AVG_FILT_EN
0xE7
1
Comments
Selects starting line for field averaging.
Selects end line for field averaging.
Selects starting sample for line
averaging.
Selects end sample for line averaging.
UG-637
1
Reserved
0
0
0
Y_AVERAGE[9:2]
x
x
x
0
0
Trigger used to store the readback
value.
Enable low pass filtering of the
y_averaged signal.
Selects the filter cutoff to be used for
filtering the y averaged data.
3’b1xx = least filtered.
3’b000 = next least.
…
3’b011 = heavily filtered.
Note these are read
only registers
x
x
x
Y_AVERAGE[1:0]
Rev. A | Page 89 of 104
x
x
x
x
Contains the averaged video data.
UG-637
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
INTERRUPT/VDP SUB MAP DESCRIPTION
To access the registers listed in Table 106, SUB_USR_EN in Register Address 0x0E must be programmed to 01. The gray shading is the default.
Table 106. Interrupt/VDP Sub Map Register Descriptions
Interrupt/VDP Sub Map
Address Register
0x40
Interrupt
Configuration 1
Bits (Shading Indicates Default)
Bit Description
7 6 5 4 3 2 1 0
INTRQ_OP_SEL[1:0]; interrupt drive
0 0
level select
0 1
1
1
MPU_STIM_INTRQ; manual
interrupt set mode
0
1
Reserved
MV_INTRQ_SEL[1:0]; Rovi interrupt
select
INTRQ_DUR_SEL[1:0]; interrupt
duration select
0x42
x
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Interrupt Status 1 SD_LOCK_Q
(read only)
0
1
SD_UNLOCK_Q
0
1
Reserved
SD_FR_CHNG_Q
x
Interrupt Clear 1
(write only)
Reserved
SD_LOCK_CLR
x
x
0
1
MV_PS_CS_Q
0x43
No change
Denotes a change in the free-run
status
No change
Pseudo sync/color striping
detected; see Register 0x40
MV_INTRQ_SEL[1:0] for selection
0
1
x
0
1
SD_UNLOCK_CLR
0
1
Reserved
SD_FR_CHNG_CLR
0
0
0
0
1
MV_PS_CS_CLR
Reserved
0
1
Comments
Open drain
Drive low when active
Drive high when active
Reserved
Manual interrupt mode disabled
Manual interrupt mode enabled
Not used
Reserved
Pseudo sync only
Color stripe only
Pseudo sync or color stripe
3 XTAL periods
15 XTAL periods
63 XTAL periods
Active until cleared
No change
SD input has caused the decoder
to go from an unlocked state to a
locked state
No change
SD input has caused the decoder
to go from a locked state to an
unlocked state
0
1
x
Rev. A | Page 90 of 104
Do not clear
Clears SD_LOCK_Q bit
Do not clear
Clears SD_UNLOCK_Q bit
Not used
Do not clear
Clears SD_FR_CHNG_Q bit
Do not clear
Clears MV_PS_CS_Q bit
Not used
Notes
These bits can be cleared or
masked in Register 0x43 and
Register 0x44, respectively
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
Interrupt/VDP Sub Map
Address Register
0x44
Interrupt Mask 1
(read/write)
Bit Description
SD_LOCK_MSK
SD_UNLOCK_MSK
Reserved
SD_FR_CHNG_MSK
MV_PS_CS_MSK
0x45
Raw Status 2
(read only)
Reserved
CCAPD
Bits (Shading Indicates Default)
7 6 5 4 3 2 1 0
0
1
0
1
0 0 0
0
1
0
1
x
0
1
Reserved
EVEN_FIELD
x
x
0
1
Reserved
MPU_STIM_INTRQ
0x46
x
0
1
Interrupt Status 2 CCAPD_Q
(read only)
0
1
Reserved
Reserved
SD_FIELD_CHNGD_Q
x
x
x
0
1
Reserved
MPU_STIM_INTRQ_Q
0x47
Interrupt Clear 2
(write only)
x
x
0
1
CCAPD_CLR
0
1
Reserved
Reserved
SD_FIELD_CHNGD_CLR
x
x
Reserved
MPU_STIM_INTRQ_CLR
Current SD field is odd numbered
Current SD field is even
numbered
If the input to the ADC is within
the correct range this is 0
If the input to the ADC is outside
the range this is set to 1. The
range is set by User Sub Map 2
Not used
MPU_STIM_INTRQ = 0
MPU_STIM_INTRQ = 1
Closed captioning not detected
in the input video signal—VBI
System 2
Closed captioning data detected
in the video input signal—VBI
System 2
Not used
Not used
SD signal has not changed field
from odd to even or vice versa
SD signal has changed Field from
odd to even or vice versa
Not used
Manual interrupt not set
Manual interrupt set
Do not clear—VBI System 2
Clears CCAPD_Q bit—
VBI System 2
Not used
x
0
1
CHX_MIN_MAX_INTRQ_CLR
Notes
These bits are status bits
only; they cannot be cleared
or masked; Register 0x46 is
used for this purpose
x
0
1
CHX_MIN_MAX_INTRQ
Comments
Masks SD_LOCK_Q bit
Unmasks SD_LOCK_Q bit
Masks SD_UNLOCK_Q bit
Unmasks SD_UNLOCK_Q bit
Not used
Masks SD_FR_CHNG_Q bit
Unmasks SD_FR_CHNG_Q bit
Masks MV_PS_CS_Q bit
Unmasks MV_PS_CS_Q bit
Not used
No CCAPD data detected— VBI
System 2
CCAPD data detected—VBI
System 2
UG-637
0
1
x
0
1
Rev. A | Page 91 of 104
Do not clear
Clears SD_FIELD_CHNGD_Q bit
Do not clear
Clears CHX_MIN_MAX_INTRQ bit
Not used
Do not clear
Clears MPU_STIM_INTRQ_Q bit
These bits can be cleared or
masked by Register 0x47 and
Register 0x48, respectively;
note that the interrupt in
Register 0x46 for the CCAP,
CGMS, and WSS data uses the
Mode 1 data slicer
Note that interrupt in
Register 0x46 for the CCAP,
CGMS, and WSS data uses the
Mode 1 data slicer
UG-637
Interrupt/VDP Sub Map
Address Register
0x48
Interrupt Mask 2
(read/write)
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
Bit Description
CCAPD_MSK
Bits (Shading Indicates Default)
7 6 5 4 3 2 1 0
0
1
Reserved
0
Reserved
SD_FIELD_CHNGD_MSK
0
0
1
0
1
CHX_MIN_MAX_INTRQ_MSKB
Reserved
MPU_STIM_INTRQ_MSK
0x49
Raw Status 3
(read only)
0
0
0
1
SD_OP_50Hz; SD 60 Hz/50 Hz
frame rate at output
0
1
SD_V_LOCK
0
1
SD_H_LOCK
0
1
Reserved
SCM_LOCK
0x4A
Reserved
Interrupt Status 3 SD_OP_CHNG_Q; SD 60 Hz/50 Hz
(read only)
frame rate at output
x
0
1
x
x
x
0
1
SD_V_LOCK_CHNG_Q
0
1
SD_H_LOCK_CHNG_Q
0
1
SD_AD_CHNG_Q; SD autodetect
changed
0
1
SCM_LOCK_CHNG_Q; SECAM lock
0
1
PAL_SW_LK_CHNG_Q
0
1
Reserved
x
x
Rev. A | Page 92 of 104
Comments
Masks CCAPD_Q bit—
VBI System 2
Unmasks CCAPD_Q bit—
VBI System 2
Not used
Not used
Masks SD_FIELD_CHNGD_Q bit
Unmasks SD_FIELD_CHNGD_Q
bit
Masks CHX_MIN_MAX_INTRQ bit
Unmasks CHX_MIN_MAX_INTRQ
bit
Not used
Masks MPU_STIM_INTRQ_Q bit
Unmasks MPU_STIM_INTRQ_Q
bit
SD 60 Hz signal output
SD 50 Hz signal output
SD vertical sync lock is not
established
SD vertical sync lock established
SD horizontal sync lock is not
established
SD horizontal sync lock
established
Not used
SECAM lock is not established
SECAM lock established
Not used
No change in SD signal standard
detected at the output
A change in SD signal standard is
detected at the output
No change in SD VSYNC lock
status
SD VSYNC lock status has
changed
No change in HSYNC lock status
SD HSYNC lock status has
changed
No change in AD_RESULT[2:0]
bits in Status 1 register
AD_RESULT[2:0] bits in Status 1
register have changed
No change in SECAM lock status
SECAM lock status has changed
No change in PAL swinging burst
lock status
PAL swinging burst lock status
has changed
Not used
Notes
Note that interrupt in
Register 0x46 for the CCAP,
CGMS, and WSS data uses the
Mode 1 data slicer
These bits are status bits
only; they cannot be cleared
or masked; Register 0x4A is
used for this purpose
These bits can be cleared
and masked by Register 0x4B
and Register 0x4C, respectively
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
Interrupt/VDP Sub Map
Address Register
0x4B
Interrupt Clear 3
(write only)
Bit Description
SD_OP_CHNG_CLR
SD_V_LOCK_CHNG_CLR
SD_H_LOCK_CHNG_CLR
SD_AD_CHNG_CLR
SCM_LOCK_CHNG_CLR
PAL_SW_LK_CHNG_CLR
0x4C
Interrupt Mask 3
(read/write)
Reserved
SD_OP_CHNG_MSK
SD_V_LOCK_CHNG_MSK
Bits (Shading Indicates Default)
7 6 5 4 3 2 1 0
0
1
0
1
0
1
0
1
0
1
0
1
x x
0
1
0
1
0
1
PAL_SW_LK_CHNG_MSK
0x4F
Interrupt Clear 4
(write only)
x
x
x
0
CGMS/WSS data is not
changed/not available
CGMS/WSS data is
changed/available
1
Notes
These bits can be cleared
and masked by Register 0x4F
and Register 0x50,
respectively; note that an
interrupt in Register 0x4E for
the CCAP, CGMS, and WSS
data uses the VDP data slicer
x
x
x
x
x
0
1
Reserved
VDP_CGMS_WSS_CHNGD_CLR
Reserved
Reserved
Reserved
Reserved
Reserved
VDP_CCAPD_CLR
Closed captioning detected
0
1
SCM_LOCK_CHNG_MSK
Reserved
VDP_CGMS_WSS_CHNGD_Q;
see Address 0x9C, Bit 4, of User Sub
Map to determine whether
interrupt is issued for a change in
detected data or for when data is
detected, regardless of content
Reserved
Reserved
Reserved
Reserved
Reserved
VDP_CCAPD_CLR
1
0
1
SD_AD_CHNG_MSK
Reserved
Interrupt Status 4 VDP_CCAPD_Q
(read only)
0
0
1
SD_H_LOCK_CHNG_MSK
0x4E
Comments
Do not clear
Clears SD_OP_CHNG_Q bit
Do not clear
Clears SD_V_LOCK_CHNG_Q bit
Do not clear
Clears SD_H_LOCK_CHNG_Q bit
Do not clear
Clears SD_AD_CHNG_Q bit
Do not clear
Clears SCM_LOCK_CHNG_Q bit
Do not clear
Clears PAL_SW_LK_CHNG_Q bit
Not used
Masks SD_OP_CHNG_Q bit
Unmasks SD_OP_CHNG_Q bit
Masks SD_V_LOCK_CHNG_Q bit
Unmasks SD_V_LOCK_CHNG_Q
bit
Masks SD_H_LOCK_CHNG_Q bit
Unmasks SD_H_LOCK_CHNG_Q
bit
Masks SD_AD_CHNG_Q bit
Unmasks SD_AD_CHNG_Q bit
Masks SCM_LOCK_CHNG_Q bit
Unmasks SCM_LOCK_CHNG_Q
bit
Masks PAL_SW_LK_CHNG_Q bit
Unmasks PAL_SW_LK_CHNG_Q
bit
Not used
Closed captioning not detected
UG-637
Do not clear
Clears VDP_CCAPD_Q
0
0
1
Do not clear
Clears
VDP_CGMS_WSS_CHNGD_Q
0
0
0
0
Do not clear
0
0
Rev. A | Page 93 of 104
Do not clear
In Register 0x4E,
CCAP/CGMS/ WSS data uses
VDP data slicer
UG-637
Interrupt/VDP Sub Map
Address Register
0x50
Interrupt Mask 4
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
Bit Description
VDP_CCAPD_MSK
Reserved
VDP_CGMS_WSS_CHNGD_MSK
Bits (Shading Indicates Default)
7 6 5 4 3 2 1 0
0
1
0
0
1
0x51
Reserved
Reserved
Reserved
Reserved
Reserved
Interrupt Latch 0 CR_CHANNEL_MAX_VIOLATION
(read only)
0
0
0
0
0
CR_CHANNEL_MIN_VIOLATION
0
1
CB_CHANNEL_MAX_VIOLATION
0
1
CB_CHANNEL_MIN_VIOLATION
0
1
Y_CHANNEL_MAX_VIOLATION
0
1
Y_CHANNEL_MIN_VIOLATION
0
1
Interrupt Status 5
(read only)
Reserved
Reserved
DIAG_TRI1_L1
0
x
x
x
See DIAG1_SLICE_LEVEL
(User Map Register 0x5D
[4:2]) and
DIAG2_SLICE_LEVEL (User
Map Register 0x5E [4:2])
x
0
0
1
Reserved
DIAG_TRI2_L1_CLR
Reserved
Voltage higher than
DIAG1_SLICE_LEVEL not detected
on DIAG1 pin
Voltage higher than
DIAG1_SLICE_LEVEL detected on
DIAG1 pin.
These bits can be cleared or
masked in Register 0x54 and
Voltage higher than
Register 0x55, respectively
DIAG2_SLICE_LEVEL not detected
on DIAG2 pin
Voltage higher than
DIAG2_SLICE_LEVEL detected on
DIAG2 pin.
x
0
1
Reserved
Reserved
DIAG_TRI1_L1_CLR
This register is cleared by
CHX_MIN_MAX_INTRQ_CLR
x
0
Reserved
DIAG_TRI2_L1
Interrupt Clear 5
(write only)
Cr value is below programmed
maximum value
Cr value is above programmed
maximum value
Cr value is above programmed
minimum value
Cr value is below programmed
minimum value
Cb value is below programmed
maximum value
Cb value is above programmed
maximum value
Cb value is above programmed
minimum value
Cb value is below programmed
minimum value
Y value is below programmed
maximum value
Y value is above programmed
maximum value
Y value is above programmed
minimum value
Y value is below programmed
minimum value
0
1
0x54
Masks
VDP_CGMS_WSS_CHNGD_Q
Unmasks
VDP_CGMS_WSS_CHNGD_Q
Notes
Note that an interrupt in
Register 0x4E for the CCAP,
CGMS, and WSS data uses
the VDP data slicer
0
1
0x53
Comments
Masks VDP_CCAPD_Q
Unmasks VDP_CCAPD_Q
Do not clear DIAG_TRI1_L1
Clear DIAG_TRI1_L1
0
0
1
0
0
0
0
Rev. A | Page 94 of 104
Do not clear DIAG_TRI2_L1
Clear DIAG_TRI2_L1
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
Interrupt/VDP Sub Map
Address Register
0x55
Interrupt Mask 5
Bit Description
Reserved
DIAG_TRI1_L1_MSK
Reserved
DIAG_TRI2_L1_MSK
0x60
VDP_CONFIG_1
Reserved
VDP_TTXT_TYPE_MAN[1:0]
Bits (Shading Indicates Default)
7 6 5 4 3 2 1 0
0
0
1
0
0
1
0 0 0 0
0 0
VDP_TTXT_TYPE_MAN_ENABLE
0
1
1
0
1
1
0
1
WST_PKT_DECODE_DISABLE
0
1
0x62
VDP_ADF_
CONFIG_1
Reserved
ADF_DID[4:0]
1
ADF_MODE[1:0]
ADF_ENABLE
0
0
0
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
0
1
0
0
1
0x63
VDP_ADF_
CONFIG_2
ADF_SDID[5:0]
Reserved
DUPLICATE_ADF
1
VDP_LINE_00E
VBI_DATA_P318[3:0]
Reserved
MAN_LINE_PGM
Notes
Masks DIAG_TRI1_L1
Unmasks DIAG_TRI1_L1
Masks DIAG_TRI2_L1
Unmasks DIAG_TRI2_L1
PAL: Teletext-ITU-BT.653-625/
50-A,
NTSC: reserved
PAL: Teletext-ITU-BT.653-625/
50-B (WST),
NTSC: Teletext-ITU-BT.653-525/
60-B
PAL: Teletext-ITU-BT.653-625/
50-C,
NTSC: Teletext-ITU-BT.653-525/
60-C, or
EIA516 (NABTS)
PAL: Teletext-ITU-BT.653-625/
50-D,
NTSC: Teletext-ITU-BT.653-525/
60-D
User programming of teletext
type disabled
User programming of teletext
type enabled
Enables hamming decoding of
WST packets
Disables hamming decoding of
WST packets
User-specified DID sent in the
ancillary data stream with VDP
decoded data
Nibble mode
Sets whether ancillary data
output mode in byte mode or
Byte mode, no code restrictions
nibble mode
Byte mode with 0x00 and 0xFF
prevented
Reserved
Disables insertion of VBI decoded
data into ancillary 656 stream
Enables insertion of VBI decoded
data into ancillary 656 stream
User-specified SDID sent in the
ancillary data stream with VDP
decoded data
x
0
1
0x64
Comments
UG-637
0
0
0
0
0
0
Ancillary data packet is spread
across the Y and C data streams
Ancillary data packet is
duplicated on the Y and C data
streams
Sets VBI standard to be decoded
from Line 318 (PAL), NTSC—not
applicable
0
0
Decode default VDP standards on
the expected lines.
Manually program the VBI
If set to 1, all
standard to be decoded on each VBI_DATA_Px_Ny bits can be
line.
set as desired
1
Rev. A | Page 95 of 104
UG-637
Interrupt/VDP Sub Map
Address Register
0x65
VDP_LINE_00F
0x66
VDP_LINE_010
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
Bit Description
VBI_DATA_P319_N286[3:0]
Bits (Shading Indicates Default)
7 6 5 4 3 2 1 0
0 0 0 0
VBI_DATA_P6_N23[3:0]
0
VDP_LINE_011
VDP_LINE_012
VDP_LINE_013
VDP_LINE_014
VDP_LINE_015
VDP_LINE_016
VDP_LINE_017
VDP_LINE_018
VDP_LINE_019
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VBI_DATA_P329_N277[3:0]
VBI_DATA_P16_N14[3:0]
0
0
VBI_DATA_P328_N276[3:0]
VBI_DATA_P15_N13[3:0]
0x6F
0
VBI_DATA_P327_N275[3:0]
VBI_DATA_P14_N12[3:0]
0x6E
0
VBI_DATA_P326_N274[3:0]
VBI_DATA_P13_N11[3:0]
0x6D
0
0
0
VBI_DATA_P325_N273[3:0]
VBI_DATA_P12_N10[3:0]
0x6C
0
VBI_DATA_P324_N272[3:0]
VBI_DATA_P11[3:0]
0x6B
0
VBI_DATA_P323[3:0]
VBI_DATA_P10[3:0]
0x6A
0
VBI_DATA_P322[3:0]
VBI_DATA_P9[3:0]
0x69
0
VBI_DATA_P321_N288[3:0]
VBI_DATA_P8_N25[3:0]
0x68
0
VBI_DATA_P320_N287[3:0]
VBI_DATA_P7_N24[3:0]
0x67
0
0
Rev. A | Page 96 of 104
Comments
Sets VBI standard to be decoded
from Line 319 (PAL), Line 286
(NTSC)
Sets VBI standard to be decoded
from Line 6 (PAL), Line 23 (NTSC)
Sets VBI standard to be decoded
from Line 320 (PAL), Line 287
(NTSC)
Sets VBI standard to be decoded
from Line 7 (PAL), Line 24 (NTSC)
Sets VBI standard to be decoded
from Line 321 (PAL), Line 288
(NTSC)
Sets VBI standard to be decoded
from Line 8 (PAL), Line 25 (NTSC)
Sets VBI standard to be decoded
from Line 322 (PAL), NTSC—not
applicable
Sets VBI standard to be decoded
from Line 9 (PAL), NTSC—not
applicable
Sets VBI standard to be decoded
from Line 323 (PAL), NTSC—not
applicable
Sets VBI standard to be decoded
from Line 10 (PAL), NTSC—not
applicable
Sets VBI standard to be decoded
from Line 324 (PAL), Line 272
(NTSC)
Sets VBI standard to be decoded
from Line 11 (PAL); NTSC—not
applicable
Sets VBI standard to be decoded
from Line 325 (PAL), Line 273
(NTSC)
Sets VBI standard to be decoded
from Line 12 (PAL), Line 10 (NTSC)
Sets VBI standard to be decoded
from Line 326 (PAL), Line 274
(NTSC)
Sets VBI standard to be decoded
from Line 13 (PAL), Line 11 (NTSC)
Sets VBI standard to be decoded
from Line 327 (PAL), Line 275
(NTSC)
Sets VBI standard to be decoded
from Line 14 (PAL), Line 12 (NTSC)
Sets VBI standard to be decoded
from Line 328 (PAL), Line 276
(NTSC)
Sets VBI standard to be decoded
from Line 15 (PAL), Line 13 (NTSC)
Sets VBI standard to be decoded
from Line 329 (PAL), Line 277
(NTSC)
Sets VBI standard to be decoded
from Line 16 (PAL), Line 14 (NTSC)
Notes
MAN_LINE_PGM must be set
to 1 for these bits to be
effective
MAN_LINE_PGM must be set
to 1 for these bits to be
effective
MAN_LINE_PGM must be set
to 1 for these bits to be
effective
MAN_LINE_PGM must be set
to 1 for these bits to be
effective
MAN_LINE_PGM must be set
to 1 for these bits to be
effective
MAN_LINE_PGM must be set
to 1 for these bits to be
effective
MAN_LINE_PGM must be set
to 1 for these bits to be
effective
MAN_LINE_PGM must be set
to 1 for these bits to be
effective
MAN_LINE_PGM must be set
to 1 for these bits to be
effective
MAN_LINE_PGM must be set
to 1 for these bits to be
effective
MAN_LINE_PGM must be set
to 1 for these bits to be
effective
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
Interrupt/VDP Sub Map
Address Register
0x70
VDP_LINE_01A
0x71
VDP_LINE_01B
Bit Description
VBI_DATA_P330_N278[3:0]
Bits (Shading Indicates Default)
7 6 5 4 3 2 1 0
0 0 0 0
VBI_DATA_P17_N15[3:0]
0
VDP_LINE_01C
VDP_LINE_01D
VDP_LINE_01E
VDP_LINE_01F
VDP_LINE_020
VDP_LINE_021
VDP_STATUS
(read only)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VBI_DATA_P337_N285[3:0]
VBI_DATA_P24_N22[3:0]
0x78
0
0
0
VBI_DATA_P336_N284[3:0]
VBI_DATA_P23_N21[3:0]
0x77
0
VBI_DATA_P335_N283[3:0]
VBI_DATA_P22_N20[3:0]
0x76
0
VBI_DATA_P334_N282[3:0]
VBI_DATA_P21_N19[3:0]
0x75
0
VBI_DATA_P333_N281[3:0]
VBI_DATA_P20_N18[3:0]
0x74
0
VBI_DATA_P332_N280[3:0]
VBI_DATA_P19_N17[3:0]
0x73
0
VBI_DATA_P331_N279[3:0]
VBI_DATA_P18_N16[3:0]
0x72
0
0
CC_AVL
0
1
CC_EVEN_FIELD
0
1
CGMS_WSS_AVL
Reserved
TTXT_AVL
VDP_STATUS_
CLEAR
(write only)
0
1
0
0
0
Closed captioning is detected
Closed captioning decoded from
odd field
Closed captioning decoded from
even field
CGMS/WSS is not detected
CGMS/WSS detected
Notes
MAN_LINE_PGM must be set
to 1 for these bits to be
effective
MAN_LINE_PGM must be set
to 1 for these bits to be
effective
MAN_LINE_PGM must be set
to 1 for these bits to be
effective
MAN_LINE_PGM must be set
to 1 for these bits to be
effective
MAN_LINE_PGM must be set
to 1 for these bits to be
effective
MAN_LINE_PGM must be set
to 1 for these bits to be
effective
MAN_LINE_PGM must be set
to 1 for these bits to be
effective
MAN_LINE_PGM must be set
to 1 for these bits to be
effective
CC_CLEAR resets the CC_AVL
bit
CGMS_WSS_CLEAR resets
the CGMS_WSS_AVL bit
0
0
1
CC_CLEAR
0
1
Reserved
CGMS_WSS_CLEAR
Teletext not detected
Teletext detected
Does not reinitialize the CCAP
readback registers
Reinitializes the CCAP readback
registers
This is a self-clearing bit
0
0
1
Reserved
Comments
Sets VBI standard to be decoded
from Line 330 (PAL), Line 278
(NTSC)
Sets VBI standard to be decoded
from Line 17 (PAL), Line 15 (NTSC)
Sets VBI standard to be decoded
from Line 331 (PAL), Line 279
(NTSC)
Sets VBI standard to be decoded
from Line 18 (PAL), Line 16 (NTSC)
Sets VBI standard to be decoded
from Line 332 (PAL), Line 280
(NTSC)
Sets VBI standard to be decoded
from Line 19 (PAL), Line 17 (NTSC)
Sets VBI standard to be decoded
from Line 333 (PAL), Line 281
(NTSC)
Sets VBI standard to be decoded
from Line 20 (PAL), Line 18 (NTSC)
Sets VBI standard to be decoded
from Line 334 (PAL), Line 282
(NTSC)
Sets VBI standard to be decoded
from Line 21 (PAL), Line 19 (NTSC)
Sets VBI standard to be decoded
from Line 335 (PAL), Line 283
(NTSC)
Sets VBI standard to be decoded
from Line 22 (PAL), Line 20 (NTSC)
Sets VBI standard to be decoded
from Line 336 (PAL), Line 284
(NTSC)
Sets VBI standard to be decoded
from Line 23 (PAL), Line 21 (NTSC)
Sets VBI standard to be decoded
from Line 337 (PAL), Line 285
(NTSC)
Sets VBI standard to be decoded
from Line 24 (PAL), Line 22 (NTSC)
Closed captioning not detected
UG-637
0
0
0
0
0
Rev. A | Page 97 of 104
Does not reinitialize the
CGMS/WSS readback registers
Reinitializes the CGMS/WSS
readback registers
This is a self-clearing bit
UG-637
Interrupt/VDP Sub Map
Address Register
VDP_CCAP_
0x79
DATA_0
(read only)
VDP_CCAP_
0x7A
DATA_1
(read only)
VDP_CGMS_
0x7D
WSS_DATA_0
(read only)
VDP_CGMS_
0x7E
WSS_DATA_1
(read only)
VDP_CGMS_
0x7F
WSS_DATA_2
(read only)
VDP_OUTPUT_
0x9C
SEL
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
Bit Description
CCAP_BYTE_1[7:0]
Bits (Shading Indicates Default)
7 6 5 4 3 2 1 0
x x x x x x x x
Comments
Decoded Byte 1 of CCAP
CCAP_BYTE_2[7:0]
x
x
x
x
CGMS_CRC[5:2]
Reserved
0
0
0
0
CGMS_WSS[13:8]
CGMS_CRC[1:0]
x
x
x
CGMS_WSS[7:0]
x
x
x
Reserved
WSS_CGMS_CB_CHANGE
x
x
x
x
Decoded Byte 2 of CCAP
x
x
x
x
Decoded CRC sequence for CGMS
x
x
x
x
x
Decoded CGMS/WSS data
Decoded CRC sequence for CGMS
x
x
x
x
x
Decoded CGMS/WSS data
0
0
0
0
0
1
Reserved
0
0
0
Rev. A | Page 98 of 104
Disable content-based updating
of CGMS and WSS data
Enable content-based updating
of CGMS and WSS data
Notes
The available bit shows the
availability of data only
when its content has
changed
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
UG-637
VPP MAP DESCRIPTION
To access the registers listed in Table 107, the user must set the VPP I2C device address by writing to VPP_SLAVE_ADDR[6:0].
VPP_SLAVE_ADDR[6:0] can be found in User Map Register 0xFD. Analog Devices recommended scripts set the VPP I2C device address to
0x84. The default bits are indicated by the gray shading.
Table 107. VPP Map Register Descriptions
VPP Map
Address Register
0x41
DEINT_RESET
Bit Description
DEINT_RESET
Reserved
0x55
0x5B
I2C_DEINT_ENABLE
ADV_TIMING_MODE_EN
Reserved
I2C_DEINT_ENABLE
Reserved
ADV_TIMING_MODE_EN
Bits (Shading Indicates Default)
6 5 4 3 2 1 0
0
1
0 0 0 0
0 0 0
7
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
Rev. A | Page 99 of 104
0
0
Comments
Notes
Reset the I2P core
Reserved
Reserved
Disable I2P converter
Enable I2P converter
Reserved
Enable advanced timing
mode
Disable advanced timing
mode
In order for the I2P converter to
operate correctly, the
ADV_TIMING_MODE_EN bit
must be set to 1. Also changes
to the output timing video are
needed. Refer to the Analog
Devices recommended scripts.
Advanced timing mode must
be enabled in order for the I2P
converter to work correctly
UG-637
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
CSI MAP DESCRIPTION
To access the registers listed in Table 108, the user must set the CSI I2C device address by writing to CSI_TX_SLAVE_ADDR[6:0].
CSI_TX_SLAVE_ADDR[6:0] can be found in User Map Register 0xFE. Analog Devices recommended scripts set the CSI I2C device address to
0x88. The gray shading is indicates the default.
Table 108. MIPI CSI Map Register Descriptions
MIPI CSI Map
Address
0x00
0x01
0x02
0x03
0x04
0x05
Register
CSITX_PWRDN
TLPX
THSPREP
THSZEROS
THSTRAIL
THSEXIT
Bit (Shading Indicates Default)
Bit Description
Reserved
CSITX_PWRDN
7
6
0
5
0
4
0
3
0
1
0
0
0
0
0
0
0
1
Reserved
TLPX[4:0]
0
0
0
1
1
Reserved
THSPREP[4:0]
0
0
0
1
1
Reserved
THSZEROS[4:0]
0
0
1
1
0
Reserved
THSTRAIL[4:0]
0
0
1
0
0
0
0
1
0
1
0
0
0
Reserved
THSEXIT[4:0]
2
0
0
0
0
0
0
0
0
0
0
Comments
Reserved
CSI Tx on
CSI Tx off
Reserved
These bits set the duration of the
TLPX period of the D0P/D0N MIPI
CSI-2 data lanes.
Reserved
These bits set the duration of the
THS-PREPARE period of the D0P/D0N
MIPI CSI-2 data lanes.
Reserved
These bits set the duration of the
HS-ZERO period of the D0P/D0N
MIPI CSI-2 data lanes.
Reserved
These bits set the duration of the
HS-TRAIL period of the D0P/D0N
MIPI CSI-2 data lanes.
Notes
For normal operation:
A 1 bit increase results in an increase
of 37.04 ns.
TLPX[4:0]must be greater than or
equal to 2.
In I2P mode:
A 1 bit increase results in an increase
of 18.52 ns.
TLPX[4:0] must be greater than or
equal to 3.
For normal operation:
A 1 bit increase results in an increase
of 37.04 ns.
THSPREP[4:0] must be greater than or
equal to 2.
In I2P mode:
A 1 bit increase results in an increase
of 18.52 ns.
THSPREP[4:0] must be greater than or
equal to 3.
For normal operation:
A 1 bit increase results in an increase
of 37.04 ns.
THSZEROS[4:0]must be greater than
or equal to 4.
In I2P mode:
A 1 bit increase results in an increase
of 18.52 ns.
THSZEROS[4:0] must be greater than
or equal to 7.
For normal operation:
A 1 bit increase results in an increase
of 37.04 ns.
THSTRAIL[4:0] must be greater than or
equal to 3.
In I2P mode:
A 1 bit increase results in an increase
of 18.52 ns.
THSTRAIL[4:0]must be greater than or
equal to 4.
Reserved
These bits set the duration of the
HS-EXIT period of the D0P/D0N
MIPI CSI-2 data lanes
Rev. A | Page 100 of 104
For normal operation:
A 1 bit increase results in an increase
of 37.04 ns.
THSEXIT[4:0]must be greater than or
equal to 3.
In I2P mode:
A 1 bit increase results in an increase
of 18.52 ns.
THSEXIT[4:0]must be greater than or
equal to 6.
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
MIPI CSI Map
Address
0x06
0x07
Register
TCLK_PREP
TCLK_ZEROS
Bit (Shading Indicates Default)
Bit Description
Reserved
7
6
5
TCLK_PREP[4:0]
0
1
0
TCLK_TRAIL
ANCILLARY_DI
VBIVIDEO_DI
LSPKT_DI
LEPKT_DI
1
0
1
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
0
0
0
0
1
0
0
0
0
0
1
1
0
Comments
Reserved
Notes
These bits set the duration of the
HS-PREPARE period of the
CLKP/CLKN MIPI CSI-2 clock lanes
For normal operation:
A 1 bit increase results in an increase
of 37.04 ns.
TCLK_PREP[4:0] must be greater than
or equal to 2.
In I2P mode:
A 1 bit increase results in an increase
of 18.52 ns.
TCLK_PREP[4:0] must be greater than
or equal to 4.
0
0
These bits set the duration of the For normal operation:
HS-ZERO period of the
A 1 bit increase results in an increase
CLKP/CLKN MIPI CSI-2 clock lanes. of 37.04 ns.
TCLK_ZEROS [4:0] must be greater
than or equal to 7.
In I2P mode:
A 1 bit increase results in an increase
of 18.52 ns.
TCLK_ZEROS [4:0] must be greater
than or equal to 14.
Reserved
0
These bits set the duration of the For normal operation:
HS-TRAIL period of the
A 1 bit increase results in an increase
CLKP/CLKN MIPI CSI-2 clock lanes. of 37.04 ns.
TCLK_TRAIL[3:0] must be greater than
or equal to 3.
In I2P mode:
A 1 bit increase results in an increase
of 18.52 ns.
TCLK_TRAIL[3:0] must be greater than
or equal to 4.
Reserved
0
Reserved
LEPKT_DI
1
0
1
Reserved
LSPKT_DI
0x0C
0
Reserved
VBIVIDEO_DI
0x0B
2
0
Reserved
ANCILLARY_DI
0x0A
3
0
0
Reserved
TCLK_TRAIL[3:0]
0x09
4
0
Reserved
TCLK_ZEROS[4:0]
0x08
UG-637
Data type for ancillary data
packets.
Sets the 6 data type bits used in the
data identifier byte. In this case the
data identifier byte is for ancillary data
packets.
Data type for VBI data packets.
Sets the 6 data type bits used in the
data identifier byte. In this case the
data identifier byte is for Vertical
Blanking Interval data packets.
0
0
Reserved
Data type for line start packets.
0
0
Sets the 6 data type bits used in the
data identifier byte. In this case the
data identifier byte is for line start
packets.
Reserved
Data type for line end packets.
Rev. A | Page 101 of 104
Sets the 6 data type bits used in the
data identifier byte. In this case the
data identifier byte is for line end
packets.
UG-637
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
MIPI CSI Map
Address
0x0D
0x0E
Register
VC_REF
CKSUM_EN
Bit (Shading Indicates Default)
Bit Description
Reserved
7
6
VC_REF
0
0
Reserved
CKSUM_EN
0x1F
CSI_FRAME_
NUM_CTL
CSI_
LINENUMBER_
INCR_
INTERLACED
0
3
0
0
2
0
0
1
0
0
0
0
0
ESC_MODE_CTL
Virtual channel identifier
Sets the virtual channel identifier bits
used in Data Identifier bytes. Data
identifier bytes are used in MIPI CSI-2
data packets.
Reserved
High speed long packet
checksum appended to MIPI CSI
stream
Reserved
0
0
0
0
0
0
0
The field number is set to 0 at the
start of the first field output.
1
The field number is set to 1 at the
start of the first field output.
0
Frame number is 1 for odd fields
and 2 for even fields.
1
Frame number is 2 for even fields
and 1 for odd fields.
Reserved
0
0
0
0
0
0
0
Sets frame number in frame start/end
packets
This I2C bit only applies for interlaced
video.
The line numbers in the line start (LS)
and line end (LE) packets for
interlaced video have to increment by
more than 1. This bit gives the option
of whether line numbers are
incremented in steps of 2 or 3.
This bit only applies for interlaced
video.
Increment line numbers by 3.
0
ESC_XSHUTDOWN_CLK
0
0
0
0
1
ESC_MODE_EN_CLK
0
1
ESC_XSHUTDOWN_D0
Sets frame number used in MIPI CSI-2
frame start/end packets of first frame.
Reserved
Increment line numbers by 2
(default).
0
Reserved
0
1
ESC_MODE_EN_D0
Notes
1
1
0x26
Comments
Reserved
High speed long packet
checksum replaced with 0xFFFF
FBIT_VAL_AT_
FIELD1START_
INTERLACED
LINENUMBER_INCR_
INTERLACED
0
4
0
0
Reserved
FRAMENUMBER_
INTERLACED
0x20
0
5
0
Reserved
These two bits are used to force
the MIPI Clock lanes (CLKP and
CLKN) to enter and exit the
Ultralow Power State
See MIPI CSI-2 Tx Output section for
more information.
These two bits are used to force
the MIPI Data lane (D0P and D0N)
to enter and exit the Ultralow
Power State
See MIPI CSI-2 Tx Output section for
more information.
0
1
0xDE
DPHY_PWDN_
CTL
DPHY_PWDN
0
1
DPHY_PWDN_
OVERRIDE
0
1
Reserved
0
0
0
0
0
0
MIPI D-PHY Block is not powered- In order to use this bit, the
DPHY_PWDN_OVERRIDE bit must be
down
set to 1.
MIPI D-PHY Block is powereddown
Disable manual control of MIPI DPHY powerdown.
Enable manual control of MIPI DPHY powerdown.
Reserved
Rev. A | Page 102 of 104
The MIPI D-PHY block can now be
powered down by using the
DPHY_PWDN bit.
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
UG-637
REFERENCES
CEA-861-D Standard, A DTV Profile for Uncompressed High Speed Digital Interfaces, Revision D, July 18, 2006.
ITU-R BT.656-4 Recommendation, Interface for Digital Component Video Signals in 525-Line and 625-Line Television Systems Operating at
the 4:2:2 Level of Recommendation
ITU-R BT.601, February 1998.
Rev. A | Page 103 of 104
UG-637
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
NOTES
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
HDMI, the HDMI Logo, and High-Definition Multimedia Interface are trademarks or registered trademarks of HDMI Licensing LLC in the United States and other
countries.
ESD Caution
ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection
circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality.
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UG11935-0-9/14(A)
Rev. A | Page 104 of 104