IDT IDT82V3285

WAN PLL
IDT82V3285
Version 1
December 9, 2008
6024 Silver Creek Valley Road, San Jose, CA 95138
Telephone: (800) 345-7015 • TWX: 910-338-2070 • FAX: (408) 284-2775
Printed in U.S.A.
© 2008 Integrated Device Technology, Inc.
DISCLAIMER
Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The Company makes no representations that circuitry
described herein is free from patent infringement or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent, patent rights or other
rights, of Integrated Device Technology, Inc.
LIFE SUPPORT POLICY
Integrated Device Technology's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the manufacturer and an officer of IDT.
1. Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform, when properly used in
accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any components of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its
safety or effectiveness.
Table of Contents
FEATURES .............................................................................................................................................................................. 9
HIGHLIGHTS.................................................................................................................................................................................................... 9
MAIN FEATURES ............................................................................................................................................................................................ 9
OTHER FEATURES ......................................................................................................................................................................................... 9
APPLICATIONS....................................................................................................................................................................... 9
DESCRIPTION....................................................................................................................................................................... 10
FUNCTIONAL BLOCK DIAGRAM ........................................................................................................................................ 11
1 PIN ASSIGNMENT ........................................................................................................................................................... 12
2 PIN DESCRIPTION .......................................................................................................................................................... 13
3 FUNCTIONAL DESCRIPTION ......................................................................................................................................... 18
3.1
3.2
3.3
RESET ........................................................................................................................................................................................................... 18
MASTER CLOCK .......................................................................................................................................................................................... 18
INPUT CLOCKS & FRAME SYNC SIGNAL ................................................................................................................................................. 19
3.3.1 Input Clocks .................................................................................................................................................................................... 19
3.3.2 Frame SYNC Input Signals ............................................................................................................................................................ 19
3.4 INPUT CLOCK PRE-DIVIDER ...................................................................................................................................................................... 20
3.5 INPUT CLOCK QUALITY MONITORING ..................................................................................................................................................... 21
3.5.1 Activity Monitoring ......................................................................................................................................................................... 21
3.5.2 Frequency Monitoring ................................................................................................................................................................... 22
3.6 T0 / T4 DPLL INPUT CLOCK SELECTION .................................................................................................................................................. 23
3.6.1 External Fast Selection (T0 only) .................................................................................................................................................. 23
3.6.2 Forced Selection ............................................................................................................................................................................ 24
3.6.3 Automatic Selection ....................................................................................................................................................................... 24
3.7 SELECTED INPUT CLOCK MONITORING .................................................................................................................................................. 25
3.7.1 T0 / T4 DPLL Locking Detection ................................................................................................................................................... 25
3.7.1.1 Fast Loss .......................................................................................................................................................................... 25
3.7.1.2 Coarse Phase Loss .......................................................................................................................................................... 25
3.7.1.3 Fine Phase Loss ............................................................................................................................................................... 25
3.7.1.4 Hard Limit Exceeding ....................................................................................................................................................... 25
3.7.2 Locking Status ............................................................................................................................................................................... 25
3.7.3 Phase Lock Alarm (T0 only) .......................................................................................................................................................... 26
3.8 SELECTED INPUT CLOCK SWITCH ........................................................................................................................................................... 27
3.8.1 Input Clock Validity ........................................................................................................................................................................ 27
3.8.2 Selected Input Clock Switch ......................................................................................................................................................... 27
3.8.2.1 Revertive Switch ............................................................................................................................................................... 27
3.8.2.2 Non-Revertive Switch (T0 only) ........................................................................................................................................ 28
3.8.3 Selected / Qualified Input Clocks Indication ................................................................................................................................ 28
3.9 SELECTED INPUT CLOCK STATUS VS. DPLL OPERATING MODE ....................................................................................................... 29
3.9.1 T0 Selected Input Clock vs. DPLL Operating Mode .................................................................................................................... 29
3.9.2 T4 Selected Input Clock vs. DPLL Operating Mode .................................................................................................................... 31
3.10 T0 / T4 DPLL OPERATING MODE ............................................................................................................................................................... 32
3.10.1 T0 DPLL Operating Mode .............................................................................................................................................................. 32
3.10.1.1 Free-Run Mode ................................................................................................................................................................ 32
3.10.1.2 Pre-Locked Mode ............................................................................................................................................................. 32
3.10.1.3 Locked Mode .................................................................................................................................................................... 32
3.10.1.3.1 Temp-Holdover Mode .................................................................................................................................... 32
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December 9, 2008
IDT82V3285
3.11
3.12
3.13
3.14
3.15
3.16
3.17
WAN PLL
3.10.1.4 Lost-Phase Mode ............................................................................................................................................................. 32
3.10.1.5 Holdover Mode ................................................................................................................................................................. 32
3.10.1.5.1 Automatic Instantaneous ............................................................................................................................... 33
3.10.1.5.2 Automatic Slow Averaged ............................................................................................................................. 33
3.10.1.5.3 Automatic Fast Averaged .............................................................................................................................. 33
3.10.1.5.4 Manual ........................................................................................................................................................... 33
3.10.1.5.5 Holdover Frequency Offset Read .................................................................................................................. 33
3.10.1.6 Pre-Locked2 Mode ........................................................................................................................................................... 33
3.10.2 T4 DPLL Operating Mode .............................................................................................................................................................. 33
3.10.2.1 Free-Run Mode ................................................................................................................................................................ 33
3.10.2.2 Locked Mode .................................................................................................................................................................... 33
3.10.2.3 Holdover Mode ................................................................................................................................................................. 33
T0 / T4 DPLL OUTPUT ................................................................................................................................................................................. 35
3.11.1 PFD Output Limit ............................................................................................................................................................................ 35
3.11.2 Frequency Offset Limit .................................................................................................................................................................. 35
3.11.3 PBO (T0 only) ................................................................................................................................................................................. 35
3.11.4 Phase Offset Selection (T0 only) .................................................................................................................................................. 35
3.11.5 Four Paths of T0 / T4 DPLL Outputs ............................................................................................................................................. 35
3.11.5.1 T0 Path ............................................................................................................................................................................. 35
3.11.5.2 T4 Path ............................................................................................................................................................................. 36
T0 / T4 APLL ................................................................................................................................................................................................. 37
OUTPUT CLOCKS & FRAME SYNC SIGNALS ........................................................................................................................................... 37
3.13.1 Output Clocks ................................................................................................................................................................................. 37
3.13.2 Frame SYNC Output Signals ......................................................................................................................................................... 39
MASTER / SLAVE CONFIGURATION ......................................................................................................................................................... 41
INTERRUPT SUMMARY ............................................................................................................................................................................... 42
T0 AND T4 SUMMARY ................................................................................................................................................................................. 42
POWER SUPPLY FILTERING TECHNIQUES ............................................................................................................................................. 43
4 TYPICAL APPLICATION ................................................................................................................................................. 44
4.1
MASTER / SLAVE APPLICATION ............................................................................................................................................................... 44
5.1
5.2
5.3
5.4
5.5
EPROM MODE .............................................................................................................................................................................................. 46
MULTIPLEXED MODE .................................................................................................................................................................................. 47
INTEL MODE ................................................................................................................................................................................................. 49
MOTOROLA MODE ...................................................................................................................................................................................... 51
SERIAL MODE .............................................................................................................................................................................................. 53
7.1
7.2
REGISTER MAP ............................................................................................................................................................................................ 56
REGISTER DESCRIPTION ........................................................................................................................................................................... 61
7.2.1 Global Control Registers ............................................................................................................................................................... 61
7.2.2 Interrupt Registers ......................................................................................................................................................................... 70
7.2.3 Input Clock Frequency & Priority Configuration Registers ....................................................................................................... 74
7.2.4 Input Clock Quality Monitoring Configuration & Status Registers ........................................................................................... 85
7.2.5 T0 / T4 DPLL Input Clock Selection Registers ............................................................................................................................. 96
7.2.6 T0 / T4 DPLL State Machine Control Registers ......................................................................................................................... 101
7.2.7 T0 / T4 DPLL & APLL Configuration Registers .......................................................................................................................... 103
7.2.8 Output Configuration Registers .................................................................................................................................................. 117
7.2.9 PBO & Phase Offset Control Registers ...................................................................................................................................... 124
7.2.10 Synchronization Configuration Registers ................................................................................................................................. 126
5 MICROPROCESSOR INTERFACE .................................................................................................................................. 45
6 JTAG ................................................................................................................................................................................ 55
7 PROGRAMMING INFORMATION .................................................................................................................................... 56
8 THERMAL MANAGEMENT ........................................................................................................................................... 127
8.1
8.2
JUNCTION TEMPERATURE ...................................................................................................................................................................... 127
EXAMPLE OF JUNCTION TEMPERATURE CALCULATION ................................................................................................................... 127
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IDT82V3285
WAN PLL
8.3
8.4
HEATSINK EVALUATION .......................................................................................................................................................................... 127
TQFP EPAD THERMAL RELEASE PATH ................................................................................................................................................. 128
9.1
9.2
9.3
ABSOLUTE MAXIMUM RATING ................................................................................................................................................................ 129
RECOMMENDED OPERATION CONDITIONS .......................................................................................................................................... 129
I/O SPECIFICATIONS ................................................................................................................................................................................. 130
9.3.1 CMOS Input / Output Port ............................................................................................................................................................ 130
9.3.2 PECL / LVDS Input / Output Port ................................................................................................................................................ 131
9.3.2.1 PECL Input / Output Port ................................................................................................................................................ 131
9.3.2.2 LVDS Input / Output Port ................................................................................................................................................ 133
JITTER & WANDER PERFORMANCE ....................................................................................................................................................... 134
OUTPUT WANDER GENERATION ............................................................................................................................................................ 137
INPUT / OUTPUT CLOCK TIMING ............................................................................................................................................................. 138
OUTPUT CLOCK TIMING ........................................................................................................................................................................... 139
9 ELECTRICAL SPECIFICATIONS .................................................................................................................................. 129
9.4
9.5
9.6
9.7
PACKAGE DIMENSIONS.................................................................................................................................................... 144
ORDERING INFORMATION................................................................................................................................................ 147
Table of Contents
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List of Tables
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Table 42:
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Table 46:
Table 47:
Table 48:
Pin Description ............................................................................................................................................................................................. 13
Related Bit / Register in Chapter 3.2 ........................................................................................................................................................... 18
Related Bit / Register in Chapter 3.3 ........................................................................................................................................................... 19
Related Bit / Register in Chapter 3.4 ........................................................................................................................................................... 20
Related Bit / Register in Chapter 3.5 ........................................................................................................................................................... 22
Input Clock Selection for T0 Path ................................................................................................................................................................ 23
Input Clock Selection for T4 Path ................................................................................................................................................................ 23
External Fast Selection ................................................................................................................................................................................ 23
Related Bit / Register in Chapter 3.6 ........................................................................................................................................................... 24
Coarse Phase Limit Programming (the selected input clock of 2 kHz, 4 kHz or 8 kHz) .............................................................................. 25
Coarse Phase Limit Programming (the selected input clock of other than 2 kHz, 4 kHz and 8 kHz) .......................................................... 25
Related Bit / Register in Chapter 3.7 ........................................................................................................................................................... 26
Conditions of Qualified Input Clocks Available for T0 & T4 Selection ......................................................................................................... 27
Related Bit / Register in Chapter 3.8 ........................................................................................................................................................... 28
T0 DPLL Operating Mode Control ............................................................................................................................................................... 29
T4 DPLL Operating Mode Control ............................................................................................................................................................... 31
Related Bit / Register in Chapter 3.9 ........................................................................................................................................................... 31
Frequency Offset Control in Temp-Holdover Mode ..................................................................................................................................... 32
Frequency Offset Control in Holdover Mode ............................................................................................................................................... 33
Holdover Frequency Offset Read ................................................................................................................................................................ 33
Related Bit / Register in Chapter 3.10 ......................................................................................................................................................... 34
Related Bit / Register in Chapter 3.11 ......................................................................................................................................................... 36
Related Bit / Register in Chapter 3.12 ......................................................................................................................................................... 37
Outputs on OUT1 ~ OUT5 if Derived from T0/T4 DPLL Outputs ................................................................................................................ 37
Outputs on OUT1 ~ OUT5 if Derived from T0/T4 APLL .............................................................................................................................. 38
Synchronization Control ............................................................................................................................................................................... 39
Related Bit / Register in Chapter 3.13 ......................................................................................................................................................... 40
Device Master / Slave Control ..................................................................................................................................................................... 41
Related Bit / Register in Chapter 3.15 ......................................................................................................................................................... 42
Microprocessor Interface ............................................................................................................................................................................. 45
Access Timing Characteristics in EPROM Mode ......................................................................................................................................... 46
Read Timing Characteristics in Multiplexed Mode ....................................................................................................................................... 47
Write Timing Characteristics in Multiplexed Mode ....................................................................................................................................... 48
Read Timing Characteristics in Intel Mode .................................................................................................................................................. 49
Write Timing Characteristics in Intel Mode .................................................................................................................................................. 50
Read Timing Characteristics in Motorola Mode ........................................................................................................................................... 51
Write Timing Characteristics in Motorola Mode ........................................................................................................................................... 52
Read Timing Characteristics in Serial Mode ................................................................................................................................................ 53
Write Timing Characteristics in Serial Mode ................................................................................................................................................ 54
JTAG Timing Characteristics ....................................................................................................................................................................... 55
Register List and Map .................................................................................................................................................................................. 56
Power Consumption and Maximum Junction Temperature ....................................................................................................................... 127
Thermal Data ............................................................................................................................................................................................. 127
Absolute Maximum Rating ......................................................................................................................................................................... 129
Recommended Operation Conditions ........................................................................................................................................................ 129
CMOS Input Port Electrical Characteristics ............................................................................................................................................... 130
CMOS Input Port with Internal Pull-Up Resistor Electrical Characteristics ................................................................................................ 130
CMOS Input Port with Internal Pull-Down Resistor Electrical Characteristics ........................................................................................... 130
List of Tables
6
December 9, 2008
IDT82V3285
Table 49:
Table 50:
Table 51:
Table 52:
Table 53:
Table 54:
Table 55:
Table 56:
Table 57:
Table 58:
Table 59:
Table 60:
Table 61:
WAN PLL
CMOS Output Port Electrical Characteristics ............................................................................................................................................
PECL Input / Output Port Electrical Characteristics ...................................................................................................................................
LVDS Input / Output Port Electrical Characteristics ...................................................................................................................................
Output Clock Jitter Generation ..................................................................................................................................................................
Output Clock Phase Noise .........................................................................................................................................................................
Input Jitter Tolerance (155.52 MHz) ..........................................................................................................................................................
Input Jitter Tolerance (1.544 MHz) ............................................................................................................................................................
Input Jitter Tolerance (2.048 MHz) ............................................................................................................................................................
Input Jitter Tolerance (8 kHz) ....................................................................................................................................................................
T0 DPLL Jitter Transfer & Damping Factor ...............................................................................................................................................
T4 DPLL Jitter Transfer & Damping Factor ...............................................................................................................................................
Input/Output Clock Timing 3 ......................................................................................................................................................................
Output Clock Timing ..................................................................................................................................................................................
List of Tables
7
130
132
133
134
135
135
135
135
135
136
136
138
139
December 9, 2008
List of Figures
Figure 1. Functional Block Diagram ............................................................................................................................................................................ 11
Figure 2. Pin Assignment (Top View) .......................................................................................................................................................................... 12
Figure 3. Pre-Divider for An Input Clock ..................................................................................................................................................................... 20
Figure 4. Input Clock Activity Monitoring ..................................................................................................................................................................... 21
Figure 5. External Fast Selection ................................................................................................................................................................................ 23
Figure 6. Qualified Input Clocks for Automatic Selection ............................................................................................................................................ 24
Figure 7. T0 Selected Input Clock vs. DPLL Automatic Operating Mode ................................................................................................................... 30
Figure 8. T4 Selected Input Clock vs. DPLL Automatic Operating Mode ................................................................................................................... 31
Figure 9. On Target Frame Sync Input Signal Timing ................................................................................................................................................. 39
Figure 10. 0.5 UI Early Frame Sync Input Signal Timing ............................................................................................................................................. 39
Figure 11. 0.5 UI Late Frame Sync Input Signal Timing .............................................................................................................................................. 40
Figure 12. 1 UI Late Frame Sync Input Signal Timing ................................................................................................................................................. 40
Figure 13. Physical Connection Between Two Devices .............................................................................................................................................. 41
Figure 14. IDT82V3285 Power Decoupling Scheme ................................................................................................................................................... 43
Figure 15. Typical Application ...................................................................................................................................................................................... 44
Figure 16. EPROM Access Timing Diagram ............................................................................................................................................................... 46
Figure 17. Multiplexed Read Timing Diagram ............................................................................................................................................................. 47
Figure 18. Multiplexed Write Timing Diagram .............................................................................................................................................................. 48
Figure 19. Intel Read Timing Diagram ......................................................................................................................................................................... 49
Figure 20. Intel Write Timing Diagram ......................................................................................................................................................................... 50
Figure 21. Motorola Read Timing Diagram .................................................................................................................................................................. 51
Figure 22. Motorola Write Timing Diagram .................................................................................................................................................................. 52
Figure 23. Serial Read Timing Diagram (CLKE Asserted Low) ................................................................................................................................... 53
Figure 24. Serial Read Timing Diagram (CLKE Asserted High) .................................................................................................................................. 53
Figure 25. Serial Write Timing Diagram ....................................................................................................................................................................... 54
Figure 26. JTAG Interface Timing Diagram ................................................................................................................................................................. 55
Figure 27. Assembly for Expose Pad thermal Release Path (Side View) ................................................................................................................. 128
Figure 28. Recommended PECL Input Port Line Termination .................................................................................................................................. 131
Figure 29. Recommended PECL Output Port Line Termination ................................................................................................................................ 131
Figure 30. Recommended LVDS Input Port Line Termination .................................................................................................................................. 133
Figure 31. Recommended LVDS Output Port Line Termination ................................................................................................................................ 133
Figure 32. Output Wander Generation ...................................................................................................................................................................... 137
Figure 33. Input / Output Clock Timing ...................................................................................................................................................................... 138
Figure 34. Output Clock Timing ................................................................................................................................................................................. 139
Figure 35. 100-Pin EQG Package Dimensions (a) (in Millimeters) ............................................................................................................................ 144
Figure 36. 100-Pin EQG Package Dimensions (b) (in Millimeters) ............................................................................................................................ 145
Figure 37. EQG100 Recommended Land Pattern with Exposed Pad (in Millimeters) .............................................................................................. 146
List of Figures
8
December 9, 2008
WAN PLL
FEATURES
•
HIGHLIGHTS
•
•
The first single PLL chip:
• Features 0.5 mHz to 560 Hz bandwidth
• Exceeds GR-253-CORE (OC-12) and ITU-T G.813 (STM-16/
Option I) jitter generation requirements
• Provides node clocks for Cellular and WLL base-station (GSM
and 3G networks)
• Provides clocks for DSL access concentrators (DSLAM), especially for Japan TCM-ISDN network timing based ADSL equipments
•
•
•
•
•
•
•
MAIN FEATURES
•
•
•
•
•
•
•
•
•
•
•
Provides an integrated single-chip solution for Synchronous Equipment Timing Source, including Stratum 2, 3E, 3, SMC, 4E and 4
clocks
Employs DPLL and APLL to feature excellent jitter performance
and minimize the number of the external components
Integrates T0 DPLL and T4 DPLL; T4 DPLL locks independently or
locks to T0 DPLL
Supports Forced or Automatic operating mode switch controlled by
an internal state machine; the primary operating modes are FreeRun, Locked and Holdover
Supports programmable DPLL bandwidth (0.5 mHz to 560 Hz in 19
steps) and damping factor (1.2 to 20 in 5 steps)
Supports 1.1X10-5 ppm absolute holdover accuracy and 4.4X10-8
ppm instantaneous holdover accuracy
Supports PBO to minimize phase transients on T0 DPLL output to
be no more than 0.61 ns
Supports phase absorption when phase-time changes on T0
selected input clock are greater than a programmable limit over an
interval of less than 0.1 seconds
Supports programmable input-to-output phase offset adjustment
Limits the phase and frequency offset of the outputs
Supports manual and automatic selected input clock switch
•
IDT82V3285
Supports automatic hitless selected input clock switch on clock failure
Supports three types of input clock sources: recovered clock from
STM-N or OC-n, PDH network synchronization timing and external
synchronization reference timing
Provides a 2 kHz, 4 kHz or 8 kHz frame sync input signal, and a 2
kHz and an 8 kHz frame sync output signals
Provides 5 input clocks whose frequency cover from 2 kHz to
622.08 MHz
Provides 5 output clocks whose frequency cover from 1 Hz to
622.08 MHz
Provides output clocks for BITS, GPS, 3G, GSM, etc.
Supports PECL/LVDS and CMOS input/output technologies
Supports master clock calibration
Supports Master/Slave application (two chips used together) to
enable system protection against single chip failure
Meets Telcordia GR-1244-CORE, GR-253-CORE, GR-1377CORE, ITU-T G.812, ITU-T G.813 and ITU-T G.783 criteria
OTHER FEATURES
•
•
•
•
Multiple microprocessor interface modes: EPROM, Multiplexed,
Intel, Motorola and Serial
IEEE 1149.1 JTAG Boundary Scan
Single 3.3 V operation with 5 V tolerant CMOS I/Os
100-pin TQFP package, Green package options available
APPLICATIONS
•
•
•
•
•
•
•
•
•
•
BITS / SSU
SMC / SEC (SONET / SDH)
DWDM cross-connect and transmission equipments
Central Office Timing Source and Distribution
Core and access IP switches / routers
Gigabit and Terabit IP switches / routers
IP and ATM core switches and access equipments
Cellular and WLL base-station node clocks
Broadband and multi-service access equipments
Any other telecom equipments that need synchronous equipment
system timing
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
9
 2008 Integrated Device Technology, Inc.
December 9, 2008
DSC-6988/1
IDT82V3285
WAN PLL
DESCRIPTION
quency data acquired in Locked mode. Whatever the operating mode is,
the DPLL gives a stable performance without being affected by operating conditions or silicon process variations.
The IDT82V3285 is an integrated, single-chip solution for the Synchronous Equipment Timing Source for Stratum 2, 3E, 3, SMC, 4E and 4
clocks in SONET / SDH equipments, DWDM and Wireless base station,
such as GSM, 3G, DSL concentrator, Router and Access Network applications.
If the DPLL outputs are processed by T0/T4 APLL, the outputs of the
device will be in a better jitter/wander performance.
The device provides programmable DPLL bandwidths: 0.5 mHz to
560 Hz in 19 steps and damping factors: 1.2 to 20 in 5 steps. Different
settings cover all SONET / SDH clock synchronization requirements.
The device supports three types of input clock sources: recovered
clock from STM-N or OC-n, PDH network synchronization timing and
external synchronization reference timing.
A high stable input is required for the master clock in different applications. The master clock is used as a reference clock for all the internal
circuits in the device. It can be calibrated within ±741 ppm.
Based on ITU-T G.783 and Telcordia GR-253-CORE, the device consists of T0 and T4 paths. The T0 path is a high quality and highly configurable path to provide system clock for node timing synchronization
within a SONET / SDH network. The T4 path is simpler and less configurable for equipment synchronization. The T4 path locks independently
from the T0 path or locks to the T0 path.
All the read/write registers are accessed through a microprocessor
interface. The device supports five microprocessor interface modes:
EPROM, Multiplexed, Intel, Motorola and Serial.
In general, the device can be used in Master/Slave application. In
this application, two devices should be used together to enable system
protection against single chip failure. See Chapter 4 Typical Application
for details.
An input clock is automatically or manually selected for T0 and T4
each for DPLL locking. Both the T0 and T4 paths support three primary
operating modes: Free-Run, Locked and Holdover. In Free-Run mode,
the DPLL refers to the master clock. In Locked mode, the DPLL locks to
the selected input clock. In Holdover mode, the DPLL resorts to the fre-
Description
10
December 9, 2008
Functional Block Diagram
Priority
Priority
Selection
EX_SYNC1
Priority
Input Pre-Divider
Input Pre-Divider
Priority
Input Pre-Divider
Input Pre-Divider
Priority
Input Pre-Divider
IN5
IN1
IN2
IN3
IN4
Input
T0 Input
Selector
Monitors
T4 Input
Selector
11
Divider
T0 PFD
& LPF
MUX
T4 DPLL
OSCI
APLL
PBO
Phase Offset
T0 8 kHz
Divider
T4 PFD
& LPF
Microprocessor Interface
T0 DPLL
12E1/24T1/E3/T3
16E1/16T1
GSM/OBSAI/16E1/16T1
77.76 MHz
8 k Divider
T0 77.76 MHz
12E1/24T1/E3/T3
16E1/16T1
GSM/GPS/16E1/16T1
77.76 MHz
JTAG
T0
APLL
MUX
T4
APLL
MUX
T0
APLL
T4
APLL
Output
10
10
10
10
10
OUT5
MUX
OUT4
MUX
OUT3
MUX
OUT2
MUX
OUT1
MUX
Auto
Divider
Auto
Divider
Divider
Divider
Divider
Divider
Divider
MFRSYNC_2K
FRSYNC_8K
OUT5
OUT4
OUT3
OUT2
OUT1
IDT82V3285
WAN PLL
FUNCTIONAL BLOCK DIAGRAM
Figure 1. Functional Block Diagram
December 9, 2008
IDT82V3285
AD0/SDO
AD1
AD2
AD3
AD4
AD5
AD6
AD7
83
82
80
78
77
76
79
VDDD6
DGND6
85
84
81
DGND7
VDDD7
86
87
90
NC
NC
AGND3
92
91
89
88
OUT3
OUT2
94
VDDA3
OUT1
IC5
NC
96
93
IC7
IC6
98
97
1
2
75
74
3
4
73
72
5
71
6
7
70
69
8
9
10
68
67
66
11
65
IDT82V3285
12
13
14
64
63
62
42
43
44
45
46
47
48
49
50
IN4_NEG
NC
EX_SYNC1
IN1
IN2
NC
DGND4
VDDD4
41
IN3_NEG
IN4_POS
40
39
VDD_DIFF2
IN3_POS
37
OUT5_NEG
GND_DIFF2
38
36
OUT5_POS
51
34
35
25
OUT4_POS
OUT4_NEG
24
54
53
52
33
22
23
32
55
GND_DIFF1
VDD_DIFF1
21
30
31
57
56
FRSYNC_8K
MFRSYNC_2K
19
20
28
29
60
59
58
NC
DGND8
16
17
18
27
61
26
15
VDDD8
NC
AGND
TRST
IC1
IC2
AGND1
VDDA1
TMS
INT_REQ
TCK
OSCI
DGND1
VDDD1
VDDD3
DGND3
DGND2
VDDD2
IC3
FF_SRCSW
VDDA2
AGND2
TDO
IC4
TDI
NC
NC
95
SONET/SDH
MS/SL
99
PIN ASSIGNMENT
100
1
WAN PLL
RDY
RST
ALE/SCLK
RD
WR
CS
A0/SDI
A1/CLKE
A2
A3
A4
A5
A6
DGND5
VDDD5
MPU_MODE0
MPU_MODE1
MPU_MODE2
NC
NC
NC
IN5
NC
NC
NC
Figure 2. Pin Assignment (Top View)
Pin Assignment
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December 9, 2008
IDT82V3285
2
WAN PLL
PIN DESCRIPTION
Table 1: Pin Description
Name
Pin No.
I/O
Description 1
Type
Global Control Signal
OSCI
10
I
CMOS
FF_SRCSW
18
I
pull-down
CMOS
MS/SL
99
I
pull-up
OSCI: Crystal Oscillator Master Clock
A nominal 12.8000 MHz clock provided by a crystal oscillator is input on this pin. It is the
master clock for the device.
FF_SRCSW: External Fast Selection Enable
During reset, this pin determines the default value of the EXT_SW bit (b4, 0BH) 2. The
EXT_SW bit determines whether the External Fast Selection is enabled.
High: The default value of the EXT_SW bit (b4, 0BH) is ‘1’ (External Fast selection is
enabled);
Low: The default value of the EXT_SW bit (b4, 0BH) is ‘0’ (External Fast selection is disabled).
After reset, this pin selects an input clock pair for the T0 DPLL if the External Fast selection is
enabled:
High: Pair IN1 / IN3 is selected.
Low: Pair IN2/ IN4 is selected.
After reset, the input on this pin takes no effect if the External Fast selection is disabled.
CMOS
MS/SL: Master / Slave Selection
This pin, together with the MS_SL_CTRL bit (b0, 13H), controls whether the device is configured as the Master or as the Slave. Refer to Chapter 3.14 Master / Slave Configuration for
details.
The signal level on this pin is reflected by the MASTER_SLAVE bit (b1, 09H).
SONET/SDH
100
I
pull-down
CMOS
SONET/SDH: SONET / SDH Frequency Selection
During reset, this pin determines the default value of the IN_SONET_SDH bit (b2, 09H):
High: The default value of the IN_SONET_SDH bit is ‘1’ (SONET);
Low: The default value of the IN_SONET_SDH bit is ‘0’ (SDH).
After reset, the value on this pin takes no effect.
RST
74
I
pull-up
CMOS
RST: Reset
A low pulse of at least 50 µs on this pin resets the device. After this pin is high, the device will
still be held in reset state for 500 ms (typical).
Frame Synchronization Input Signal
EX_SYNC1
45
I
pull-down
CMOS
EX_SYNC1: External Sync Input 1
A 2 kHz, 4 kHz or 8 kHz signal is input on this pin.
Input Clock
IN1
46
IN2
47
IN3_POS
40
IN3_NEG
41
IN4_POS
42
IN4_NEG
43
Pin Description
IN1: Input Clock 1
I
CMOS
A 2 kHz, 4 kHz, N x 8 kHz 3, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.48 MHz, 19.44 MHz,
pull-down
25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz or 155.52 MHz clock is input on this pin.
IN2: Input Clock 2
I
CMOS
A 2 kHz, 4 kHz, N x 8 kHz 3, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.48 MHz, 19.44 MHz,
pull-down
25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz or 155.52 MHz clock is input on this pin.
IN3_POS / IN3_NEG: Positive / Negative Input Clock 3
A 2 kHz, 4 kHz, N x 8 kHz 3, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.48 MHz, 19.44 MHz,
I
PECL/LVDS 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz, 155.52 MHz, 311.04 MHz or 622.08 MHz
clock is differentially input on this pair of pins. Whether the clock signal is PECL or LVDS is
automatically detected.
IN4_POS / IN4_NEG: Positive / Negative Input Clock 4
A 2 kHz, 4 kHz, N x 8 kHz 3, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.48 MHz, 19.44 MHz,
I
PECL/LVDS 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz, 155.52 MHz, 311.04 MHz or 622.08 MHz
clock is differentially input on this pair of pins. Whether the clock signal is PECL or LVDS is
automatically detected.
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IDT82V3285
WAN PLL
Table 1: Pin Description (Continued)
Name
IN5
Pin No.
54
I/O
I
pull-down
Type
Description 1
CMOS
IN5: Input Clock 5
A 2 kHz, 4 kHz, N x 8 kHz 3, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.48 MHz, 19.44 MHz,
25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz or 155.52 MHz clock is input on this pin.
In Slave operation, the frequency of the T0 selected input clock IN5 is recommended to be
6.48 MHz.
Output Frame Synchronization Signal
FRSYNC_8K
30
O
CMOS
MFRSYNC_2K
31
O
CMOS
FRSYNC_8K: 8 kHz Frame Sync Output
An 8 kHz signal is output on this pin.
MFRSYNC_2K: 2 kHz Multiframe Sync Output
A 2 kHz signal is output on this pin.
Output Clock
OUT1
90
O
OUT2
93
O
OUT3
94
O
OUT4_POS
34
OUT4_NEG
35
OUT5_POS
36
OUT5_NEG
37
O
O
OUT1: Output Clock 1
A 1 Hz, 400 Hz, 2 kHz, 8 kHz, 64 kHz, N x E1 4, N x T1 5, N x 13.0 MHz 6, N x 3.84 MHz 7,
CMOS
5 MHz, 10 MHz, 20 MHz, E3, T3, 6.48 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz,
77.76 MHz or 155.52 MHz clock is output on this pin.
OUT2: Output Clock 2
A 1 Hz, 400 Hz, 2 kHz, 8 kHz, 64 kHz, N x E1 4, N x T1 5, N x 13.0 MHz 6, N x 3.84 MHz 7,
CMOS
5 MHz, 10 MHz, 20 MHz, E3, T3, 6.48 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz,
77.76 MHz or 155.52 MHz clock is output on this pin.
OUT3: Output Clock 3
A 1 Hz, 400 Hz, 2 kHz, 8 kHz, 64 kHz, N x E1 4, N x T1 5, N x 13.0 MHz 6, N x 3.84 MHz 7,
CMOS
5 MHz, 10 MHz, 20 MHz, E3, T3, 6.48 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz,
77.76 MHz or 155.52 MHz clock is output on this pin.
OUT4_POS / OUT4_NEG: Positive / Negative Output Clock 4
A 1 Hz, 400 Hz, 2 kHz, 8 kHz, 64 kHz, N x E1 4, N x T1 5, N x 13.0 MHz 6, N x 3.84 MHz 7,
PECL/LVDS 5 MHz, 10 MHz, 20 MHz, E3, T3, 6.48 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz,
77.76 MHz, 155.52 MHz, 311.04 MHz or 622.08 MHz clock is differentially output on this pair
of pins.
OUT5_POS / OUT5_NEG: Positive / Negative Output Clock 5
A 1 Hz, 400 Hz, 2 kHz, 8 kHz, 64 kHz, N x E1 4, N x T1 5, N x 13.0 MHz 6, N x 3.84 MHz 7,
PECL/LVDS 5 MHz, 10 MHz, 20 MHz, E3, T3, 6.48 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz,
77.76 MHz, 155.52 MHz, 311.04 MHz or 622.08 MHz clock is differentially output on this pair
of pins.
Microprocessor Interface
CS
70
I
pull-up
CMOS
INT_REQ
8
O
CMOS
Pin Description
CS: Chip Selection
A transition from high to low must occur on this pin for each read or write operation and this
pin should remain low until the operation is over.
INT_REQ: Interrupt Request
This pin is used as an interrupt request. The output characteristics are determined by the
HZ_EN bit (b1, 0CH) and the INT_POL bit (b0, 0CH).
14
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IDT82V3285
WAN PLL
Table 1: Pin Description (Continued)
Name
Pin No.
MPU_MODE0
60
MPU_MODE1
59
MPU_MODE2
58
A0 / SDI
69
A1 / CLKE
68
A2
67
A3
66
A4
65
A5
64
A6
63
AD0 / SDO
83
AD1
82
AD2
81
AD3
80
AD4
79
AD5
78
AD6
77
AD7
76
I/O
I
pull-down
I
pull-down
CMOS
MPU_MODE[2:0]: Microprocessor Interface Mode Selection
The device supports five microprocessor interface modes: EPROM, Multiplexed, Intel, Motorola and Serial.
During reset, these pins determine the default value of the MPU_SEL_CNFG[2:0] bits (b2~0,
7FH) as follows:
001 (EPROM mode);
010 (Multiplexed mode);
011 (Intel mode);
100 (Motorola mode);
101 (Serial mode);
110 - 111 (Reserved).
After reset, these pins are general purpose inputs. The microprocessor interface mode is
selected by the MPU_SEL_CNFG[2:0] bits (b2~0, 7FH).
The value of these pins is always reflected by the MPU_PIN_STS[2:0] bits (b2~0, 02H).
A[6:0]: Address Bus
In ERPOM, Intel and Motorola modes, these pins are the address bus of the microprocessor
interface.
SDI: Serial Data Input
In Serial mode, this pin is used as the serial data input. Address and data on this pin are serially clocked into the device on the rising edge of SCLK.
CMOS
CLKE: SCLK Active Edge Selection
In Serial mode, this pin selects the active edge of SCLK to update the SDO:
High - The falling edge;
Low - The rising edge.
In Multiplexed mode, A0/SDI, A1/CLKE and A[6:2] pins should be connected to ground.
In Serial mode, A[6:2] pins should be connected to ground.
AD[7:0]: Address / Data Bus
In EPROM, Intel and Motorola modes, these pins are the bi-directional data bus of the microprocessor interface.
In Multiplexed mode, these pins are the bi-directional address/data bus of the microprocessor interface.
I/O
pull-down
CMOS
SDO: Serial Data Output
In Serial mode, this pin is used as the serial data output. Data on this pin is serially clocked
out of the device on the active edge of SCLK.
In Serial mode, AD[7:1] pins should be connected to ground.
WR
71
I
pull-up
RD
72
I
pull-up
Pin Description
Description 1
Type
CMOS
WR: Write Operation
In Multiplexed and Intel modes, this pin is asserted low to initiate a write operation.
In Motorola mode, this pin is asserted low to initiate a write operation or s asserted high to initiate a read operation.
In EPROM and Serial modes, this pin should be connected to ground.
CMOS
RD: Read Operation
In Multiplexed and Intel modes, this pin is asserted low to initiate a read operation.
In EPROM, Motorola and Serial modes, this pin should be connected to ground.
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IDT82V3285
WAN PLL
Table 1: Pin Description (Continued)
Name
Pin No.
I/O
Description 1
Type
ALE: Address Latch Enable
In Multiplexed mode, the address on AD[7:0] pins is sampled into the device on the falling
edge of ALE.
ALE / SCLK
RDY
73
75
I
pull-down
O
CMOS
CMOS
SCLK: Shift Clock
In Serial mode, a shift clock is input on this pin.
Data on SDI is sampled by the device on the rising edge of SCLK. Data on SDO is updated
on the active edge of SCLK. The active edge is determined by the CLKE.
In EPROM, Intel and Motorola modes, this pin should be connected to ground.
RDY: Ready/Data Acknowledge
In Multiplexed and Intel modes, a high level on this pin indicates that a read/write cycle is
completed. A low level on this pin indicates that wait state must be inserted.
In Motorola mode, a low level on this pin indicates that valid information on the data bus is
ready for a read operation or acknowledges the acceptance of the written data during a write
operation.
In EPROM and Serial modes, this pin should be connected to ground.
JTAG (per IEEE 1149.1)
TRST
2
I
pull-down
CMOS
TMS
7
I
pull-up
CMOS
TCK
9
I
pull-down
CMOS
TDI
23
I
pull-up
CMOS
TDO
21
O
CMOS
TRST: JTAG Test Reset (Active Low)
A low signal on this pin resets the JTAG test port.
This pin should be connected to ground when JTAG is not used.
TMS: JTAG Test Mode Select
The signal on this pin controls the JTAG test performance and is sampled on the rising edge
of TCK.
TCK: JTAG Test Clock
The clock for the JTAG test is input on this pin. TDI and TMS are sampled on the rising edge
of TCK and TDO is updated on the falling edge of TCK.
If TCK is idle at a low level, all stored-state devices contained in the test logic will indefinitely
retain their state.
TDI: JTAG Test Data Input
The test data is input on this pin. It is clocked into the device on the rising edge of TCK.
TDO: JTAG Test Data Output
The test data is output on this pin. It is clocked out of the device on the falling edge of TCK.
TDO pin outputs a high impedance signal except during the process of data scanning.
This pin can indicate the interrupt of T0 selected input clock fail, as determined by the
LOS_FLAG_ON_TDO bit (b6, 0BH). Refer to Chapter 3.8.1 Input Clock Validity for details.
Power & Ground
VDDD1
12
VDDD2
16
VDDD3
13
VDDD4
50
VDDD5
61
VDDD6
85
VDDD7
86
Pin Description
VDDDn: 3.3 V Digital Power Supply
VDDDn connections should be connected using the recommended decoupling scheme
shown in Figure 14.
Power
-
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IDT82V3285
WAN PLL
Table 1: Pin Description (Continued)
Type
Description 1
Power
-
VDDAn: 3.3 V Analog Power Supply
VDDAn connections should be connected using the recommended decoupling scheme
shown in Figure 14.
Power
Power
Power
-
Ground
-
Name
Pin No.
I/O
VDDA1
6
VDDA2
19
VDDA3
VDDD8
VDD_DIFF1
VDD_DIFF2
DGND1
91
26
33
39
11
DGND2
15
DGND3
14
DGND4
49
DGND5
62
DGND6
84
DGND7
AGND1
87
5
AGND2
20
Ground
-
AGND3
GND_DIFF1
GND_DIFF2
DGND8
AGND
92
32
38
29
1
Ground
Ground
Ground
Ground
-
VDDD8: 3.3 V Digital Power Supply
VDD_DIFF1: 3.3 V Power Supply for OUT4
VDD_DIFF2: 3.3 V Power Supply for OUT5
DGNDn: Digital Ground
AGNDn: Analog Ground
GND_DIFF: Ground for OUT4
GND_DIFF: Ground for OUT5
DGND8: Digital Ground
AGND: Analog Ground
Others
IC1
3
IC2
4
IC3
17
IC4
22
IC5
96
IC6
97
IC7
98
24, 25, 27, 28, 44, 48,
51, 52, 53, 55, 56, 57,
88, 89, 95
NC
IC: Internally Connected
Internal Use. These pins should be left open for normal operation.
-
-
-
-
NC: Not Connected
Note:
1. All the unused input pins should be connected to ground; the output of all the unused output pins are don’t-care.
2. The contents in the brackets indicate the position of the register bit/bits.
3. N x 8 kHz: 1 < N < 19440.
4. N x E1: N = 1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64.
5. N x T1: N = 1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96.
6. N x 13.0 MHz: N = 1, 2, 4.
7. N x 3.84 MHz: N = 1, 2, 4, 8, 16, 10, 20, 40.
Pin Description
17
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IDT82V3285
WAN PLL
3
FUNCTIONAL DESCRIPTION
3.2
3.1
RESET
A nominal 12.8000 MHz clock, provided by a crystal oscillator, is
input on the OSCI pin. This clock is provided for the device as a master
clock. The master clock is used as a reference clock for all the internal
circuits. A better active edge of the master clock is selected by the
OSC_EDGE bit to improve jitter and wander performance.
The reset operation resets all registers and state machines to their
default value or status.
After power on, the device must be reset for normal operation.
MASTER CLOCK
In fact, an offset from the nominal frequency may input on the OSCI
pin. This offset can be compensated by setting the
NOMINAL_FREQ_VALUE[23:0] bits. The calibration range is within
±741 ppm.
For a complete reset, the RST pin must be asserted low for at least
50 µs. After the RST pin is pulled high, the device will still be in reset
state for 500 ms (typical). If the RST pin is held low continuously, the
device remains in reset state.
The performance of the master clock should meet GR-1244-CORE,
GR-253-CORE, ITU-T G.812 and G.813 criteria.
Table 2: Related Bit / Register in Chapter 3.2
Bit
Register
Address (Hex)
NOMINAL_FREQ_VALUE[23:0]
OSC_EDGE
NOMINAL_FREQ[23:16]_CNFG, NOMINAL_FREQ[15:8]_CNFG, NOMINAL_FREQ[7:0]_CNFG
DIFFERENTIAL_IN_OUT_OSCI_CNFG
06, 05, 04
0A
Functional Description
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IDT82V3285
3.3
WAN PLL
INPUT CLOCKS & FRAME SYNC SIGNAL
For SDH and SONET networks, the default frequency is different.
SONET / SDH frequency selection is controlled by the IN_SONET_SDH
bit. During reset, the default value of the IN_SONET_SDH bit is determined by the SONET/SDH pin: high for SONET and low for SDH. After
reset, the input signal on the SONET/SDH pin takes no effect.
Altogether 5 clocks and 1 frame sync signal are input to the device.
3.3.1
INPUT CLOCKS
The device provides 5 input clock ports.
3.3.2
According to the input port technology, the input ports support the following technologies:
• PECL/LVDS
• CMOS
A 2 kHz, 4 kHz or 8 kHz frame sync signal is input on the EX_SYNC1
pin. It is a CMOS input. The input frequency should match the setting in
the SYNC_FREQ[1:0] bits.
The frame sync input signal is used for frame sync output signal synchronization. Refer to Chapter 3.13.2 Frame SYNC Output Signals for
details.
According to the input clock source, the following clock sources are
supported:
• T1: Recovered clock from STM-N or OC-n
• T2: PDH network synchronization timing
• T3: External synchronization reference timing
Table 3: Related Bit / Register in Chapter 3.3
IN1, IN2 and IN5 support CMOS input signal only and the clock
sources can be from T1, T2 or T3.
IN3 and IN4 support PECL/LVDS input signal only and automatically
detect whether the signal is PECL or LVDS. The clock sources can be
from T1, T2 or T3.
Functional Description
FRAME SYNC INPUT SIGNALS
19
Bit
Register
Address (Hex)
IN_SONET_SDH
SYNC_FREQ[1:0]
INPUT_MODE_CNFG
09
December 9, 2008
IDT82V3285
3.4
WAN PLL
INPUT CLOCK PRE-DIVIDER
Once the division factor is set for the input clock selected by the
PRE_DIV_CH_VALUE[3:0] bits, it is valid until a different division factor
is set for the same input clock. The division factor is calculated as follows:
Each input clock is assigned an internal Pre-Divider. The Pre-Divider
is used to divide the clock frequency down to the DPLL required frequency, which is no more than 38.88 MHz.
Division Factor = (the frequency of the clock input to the DivN
Divider ÷ the frequency of the DPLL required clock set by the
IN_FREQ[3:0] bits) - 1
For IN1 ~ IN5, the DPLL required frequency is set by the corresponding IN_FREQ[3:0] bits.
If the input clock is of 2 kHz, 4 kHz or 8 kHz, the Pre-Divider is
bypassed automatically and the corresponding IN_FREQ[3:0] bits
should be set to match the input frequency; the input clock can be
inverted, as determined by the IN_2K_4K_8K_INV bit.
The DivN Divider can only divide the input clock whose frequency is
lower than (<) 155.52 MHz.
Each Pre-Divider consists of a HF (High Frequency) Divider (only
available for IN3 and IN4), a DivN Divider and a Lock 8k Divider, as
shown in Figure 3.
The Pre-Divider configuration and the division factor setting depend
on the input clock on one of the IN1 ~ IN5 pins and the DPLL required
clock. Here is an example:
The HF Divider, which is only available for IN3 and IN4, should be
used when the input clock is higher than (>) 155.52 MHz. The input
clock can be divided by 4, 5 or can bypass the HF Divider, as determined by the IN3_DIV[1:0]/IN4_DIV[1:0] bits correspondingly.
The input clock on the IN4 pin is 622.08 MHz; the DPLL required
clock is 6.48 MHz by programming the IN_FREQ[3:0] bits of register IN4
to ‘0010’. Do the following step by step to divide the input clock:
1. Use the HF Divider to divide the clock down to 155.52 MHz:
622.08 ÷ 155.52 = 4, so set the IN4_DIV[1:0] bits to ‘01’;
2. Use the DivN Divider to divide the clock down to 6.48 MHz:
Set the PRE_DIV_CH_VALUE[3:0] bits to ‘0110’;
Set the DIRECT_DIV bit in Register IN4_CNFG to ‘1’ and the
LOCK_8K bit in Register IN4_CNFG to ‘0’;
155.52 ÷ 6.48 = 24; 24 - 1 = 23, so set the
PRE_DIVN_VALUE[14:0] bits to ‘10111’.
When the Lock 8k Divider is used, the input clock is divided down to
8 kHz automatically.
Either the DivN Divider or the Lock 8k Divider can be used or both
can be bypassed, as determined by the DIRECT_DIV bit and the
LOCK_8K bit.
When the DivN Divider is used for INn (1 ≤ n ≤ 5), the division factor
setting should observe the following order:
1. Select an input clock by the PRE_DIV_CH_VALUE[3:0] bits;
2. Write the lower eight bits of the division factor to the
PRE_DIVN_VALUE[7:0] bits;
3. Write the higher eight bits of the division factor to the
PRE_DIVN_VALUE[14:8] bits.
Pre-Divider
IN3_DIV[1:0] bits / IN4_DIV[1:0] bits
Input Clock INn
(1 ≤ n ≤ 5)
HF Divider
(for IN3 & IN4 only)
DIRECT_DIV bit
DivN Divider
LOCK_8K bit
Lock 8k Divider
DPLL required clock
Figure 3. Pre-Divider for An Input Clock
Table 4: Related Bit / Register in Chapter 3.4
Bit
IN3_DIV[1:0]
IN4_DIV[1:0]
IN_FREQ[3:0]
IN_2K_4K_8K_INV
DIRECT_DIV
LOCK_8K
PRE_DIV_CH_VALUE[3:0]
PRE_DIVN_VALUE[14:0]
Functional Description
Register
Address (Hex)
IN3_IN4_HF_DIV_CNFG
18
IN1_CNFG ~ IN5_CNFG
FR_MFR_SYNC_CNFG
16 ~ 17, 19 ~ 1A, 1F
74
IN1_CNFG ~ IN5_CNFG
16 ~ 17, 19 ~ 1A, 1F
PRE_DIV_CH_CNFG
PRE_DIVN[14:8]_CNFG, PRE_DIVN[7:0]_CNFG
23
25, 24
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December 9, 2008
IDT82V3285
3.5
WAN PLL
INPUT CLOCK QUALITY MONITORING
There are four configurations (0 - 3) for a leaky bucket accumulator.
The leaky bucket configuration for an input clock is selected by the corresponding BUCKET_SEL[1:0] bits. Each leaky bucket configuration
consists of four elements: upper threshold, lower threshold, bucket size
and decay rate.
The qualities of all the input clocks are always monitored in the following aspects:
• Activity
• Frequency
The bucket size is the capability of the accumulator. If the number of
the accumulated events reaches the bucket size, the accumulator will
stop increasing even if further events are detected. The upper threshold
is a point above which a no-activity alarm is raised. The lower threshold
is a point below which the no-activity alarm is cleared. The decay rate is
a certain period during which the accumulator decreases by 1 if no event
is detected.
Activity and frequency monitoring are conducted on all the input
clocks.
The qualified clocks are available for T0/T4 DPLL selection. The T0
and T4 selected input clocks have to be monitored further. Refer to
Chapter 3.7 Selected Input Clock Monitoring for details.
3.5.1
ACTIVITY MONITORING
The leaky bucket configuration is programmed by one of four groups
of register bits: the BUCKET_SIZE_n_DATA[7:0] bits, the UPPER_
THRESHOLD_n_DATA[7:0] bits, the LOWER_THRESHOLD_n_
DATA[7:0] bits and the DECAY_RATE_n_DATA[1:0] bits respectively; ‘n’
is 3.
Activity is monitored by using an internal leaky bucket accumulator,
as shown in Figure 4.
Each input clock is assigned an internal leaky bucket accumulator.
The input clock is monitored for each period of 128 ms and the internal
leaky bucket accumulator increases by 1 when an event is detected; it
decreases by 1 if no event is detected within the period set by the decay
rate. The event is that an input clock drifts outside (>) ±500 ppm with
respect to the master clock within a 128 ms period.
The no-activity alarm status of the input clock is indicated by the
INn_NO_ACTIVITY_ALARM bit (1 ≤ n ≤ 5).
The input clock with a no-activity alarm is disqualified for clock selection for T0/T4 DPLL.
clock signal with events
clock signal with no event
Input Clock
Decay
Rate
Bucket Size
Upper Threshold
Leaky Bucket Accumulator
Lower Threshold
0
No-activity Alarm Indication
Figure 4. Input Clock Activity Monitoring
Functional Description
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IDT82V3285
3.5.2
WAN PLL
The input clock with a frequency hard alarm is disqualified for clock
selection for T0/T4 DPLL.
FREQUENCY MONITORING
Frequency is monitored by comparing the input clock with a reference clock. The reference clock can be derived from the master clock or
the output of T0 DPLL, as determined by the FREQ_MON_CLK bit.
In addition, if the input clock is 2 kHz, 4 kHz or 8 kHz, its clock edges
with respect to the reference clock are monitored. If any edge drifts outside ±5%, the input clock is disqualified for clock selection for T0/T4
DPLL. The input clock is qualified if any edge drifts inside ±5%. This
function is supported only when the IN_NOISE_WINDOW bit is ‘1’.
A frequency hard alarm threshold is set for frequency monitoring. If
the FREQ_MON_HARD_EN bit is ‘1’, a frequency hard alarm is raised
when the frequency of the input clock with respect to the reference clock
is above the threshold; the alarm is cleared when the frequency is below
the threshold.
The frequency of each input clock with respect to the reference clock
can be read by doing the following step by step:
1. Select an input clock by setting the IN_FREQ_READ_CH[3:0]
bits;
2. Read the value in the IN_FREQ_VALUE[7:0] bits and calculate
as follows:
The frequency hard alarm threshold can be calculated as follows:
Frequency Hard Alarm Threshold (ppm) = (ALL_FREQ_HARD_
THRESHOLD[3:0] + 1) X FREQ_MON_FACTOR[3:0]
If the FREQ_MON_HARD_EN bit is ‘1’, the frequency hard alarm
status of the input clock is indicated by the INn_FREQ_HARD_ALARM
bit (1 ≤ n ≤ 5). When the FREQ_MON_HARD_EN bit is ‘0’, no frequency
hard alarm is raised even if the input clock is above the frequency hard
alarm threshold.
Input Clock Frequency (ppm) = IN_FREQ_VALUE[7:0] X
FREQ_MON_FACTOR[3:0]
Note that the value set by the FREQ_MON_FACTOR[3:0] bits
depends on the application.
Table 5: Related Bit / Register in Chapter 3.5
Bit
Register
Address (Hex)
BUCKET_SIZE_n_DATA[7:0] (n = 3)
UPPER_THRESHOLD_n_DATA[7:0] (n = 3)
LOWER_THRESHOLD_n_DATA[7:0] (n = 3)
DECAY_RATE_n_DATA[1:0] (n = 3)
BUCKET_SEL[1:0]
BUCKET_SIZE_3_CNFG
UPPER_THRESHOLD_3_CNFG
LOWER_THRESHOLD_3_CNFG
DECAY_RATE_3_CNFG
IN1_CNFG ~ IN5_CNFG
3F
3D
3E
40
16 ~ 17, 19 ~ 1A, 1F
IN1_IN2_STS, IN3_IN4_STS, IN5_STS
44~ 45, 48
MON_SW_PBO_CNFG
0B
ALL_FREQ_MON_THRESHOLD_CNFG
FREQ_MON_FACTOR_CNFG
PHASE_MON_PBO_CNFG
IN_FREQ_READ_CH_CNFG
IN_FREQ_READ_STS
2F
2E
78
41
42
INn_NO_ACTIVITY_ALARM ( 1 ≤ n ≤ 5)
INn_FREQ_HARD_ALARM (1 ≤ n ≤ 5)
FREQ_MON_CLK
FREQ_MON_HARD_EN
ALL_FREQ_HARD_THRESHOLD[3:0]
FREQ_MON_FACTOR[3:0]
IN_NOISE_WINDOW
IN_FREQ_READ_CH[3:0]
IN_FREQ_VALUE[7:0]
Functional Description
22
December 9, 2008
IDT82V3285
3.6
WAN PLL
T0 / T4 DPLL INPUT CLOCK SELECTION
Automatic selection is done based on the results of input clocks quality monitoring and the related registers configuration.
An input clock is selected for T0 DPLL and for T4 DPLL respectively.
The selected input clock is attempted to be locked in T0/T4 DPLL.
For T0 path, the EXT_SW bit and the T0_INPUT_SEL[3:0] bits determine the input clock selection, as shown in Table 6:
3.6.1
The External Fast selection is supported by T0 path only. In External
Fast selection, only IN1/IN3 and IN2/IN4 pairs are available for selection. Refer to Figure 5. The results of input clocks quality monitoring
(refer to Chapter 3.5 Input Clock Quality Monitoring) do not affect input
clock selection.
Table 6: Input Clock Selection for T0 Path
Control Bits
EXT_SW
T0_INPUT_SEL[3:0]
1
don’t-care
other than 0000
0000
0
EXTERNAL FAST SELECTION (T0 ONLY)
Input Clock Selection
External Fast selection
Forced selection
Automatic selection
The T0 input clock selection is determined by the FF_SRCSW pin
after reset (this pin determines the default value of the EXT_SW bit during reset, refer to Chapter 2 Pin Description), the
IN1_SEL_PRIORITY[3:0] bits and the IN2_SEL_PRIORITY[3:0] bits, as
shown in Figure 5 and Table 8:
For T4 path, the T4 DPLL may lock to a T0 DPLL output or lock independently from T0 path, as determined by the T4_LOCK_T0 bit. When
the T4 DPLL locks to the T0 DPLL output, the T4 selected input clock is
a 77.76 MHz or 8 kHz signal from the T0 DPLL 77.76 MHz path (refer to
Chapter 3.11.5.1 T0 Path), as determined by the T0_FOR_T4 bit. When
the T4 path locks independently from the T0 path, the T4 DPLL input
clock selection is determined by the T4_INPUT_SEL[3:0] bits. Refer to
Table 7:
IN1_SEL_PRIORITY[3:0] bits
FF_SRCSW pin
IN1
IN3
attempted to be
locked in T0 DPLL
Table 7: Input Clock Selection for T4 Path
Control Bits - T4_INPUT_SEL[3:0]
Input Clock Selection
IN2
other than 0000
0000
Forced selection
Automatic selection
IN4
External Fast selection is done between IN1/IN3 and IN2/IN4 pairs.
IN2_SEL_PRIORITY[3:0] bits
Forced selection is done by setting the related registers.
Figure 5. External Fast Selection
Table 8: External Fast Selection
Control Pin & Bits
FF_SRCSW (after reset)
IN1_SEL_PRIORITY[3:0]
IN2_SEL_PRIORITY[3:0]
high
0000
other than 0000
don’t-care
low
don’t-care
0000
other than 0000
Functional Description
23
Selected Input Clock
IN3
IN1
IN4
IN2
December 9, 2008
IDT82V3285
3.6.2
WAN PLL
depends on the results of input clock quality monitoring (refer to
Chapter 3.5 Input Clock Quality Monitoring). Locking allowance is configured by the corresponding INn_VALID bit(1 ≤ n ≤ 5). Refer to
Figure 6. In all the qualified input clocks, the one with the highest priority
is selected. The priority is set by the corresponding
INn_SEL_PRIORITY[3:0] bits (1 ≤ n ≤ 5). If more than one qualified
input clock INn is available and has the same priority, the input clock
with the smallest ‘n’ is selected.
FORCED SELECTION
In Forced selection, the selected input clock is set by the
T0_INPUT_SEL[3:0] / T4_INPUT_SEL[3:0] bits. The results of input
clocks quality monitoring (refer to Chapter 3.5 Input Clock Quality Monitoring) do not affect the input clock selection.
3.6.3
AUTOMATIC SELECTION
In Automatic selection, the input clock selection is determined by its
validity, priority and locking allowance configuration. The validity
Validity
Priority
No
Locking Allowance
No
No
INn_SEL_PRIORITY[3:0]
'0000', ((1 ≤ n ≤ 5))
Input Clock Quality Monitoring
(Activity, Frequency)
INn = '1', (1 ≤ n ≤ 5)
INn_VALID = '0',
((1 ≤ n ≤ 5))
Yes
Yes
Yes
All qualified input clocks are available for Automatic selection
Figure 6. Qualified Input Clocks for Automatic Selection
Table 9: Related Bit / Register in Chapter 3.6
Bit
Register
Address (Hex)
EXT_SW
T0_INPUT_SEL[3:0]
T4_LOCK_T0
T0_FOR_T4
T4_INPUT_SEL[3:0]
MON_SW_PBO_CNFG
T0_INPUT_SEL_CNFG
0B
50
T4_INPUT_SEL_CNFG
51
IN1_IN2_SEL_PRIORITY_CNFG
IN3_IN4_SEL_PRIORITY_CNFG
IN5_SEL_PRIORITY_CNFG
REMOTE_INPUT_VALID1_CNFG,
REMOTE_INPUT_VALID2_CNFG
INPUT_VALID1_STS, INPUT_VALID2_STS
T4_T0_REG_SEL_CNFG
INn_SEL_PRIORITY[3:0] (1 ≤ n ≤ 5)
INn_VALID (1 ≤ n ≤ 5)
INn (1 ≤ n ≤ 5)
T4_T0_SEL
27 ~ 28, 2B
4C, 4D
4A, 4B
07
Note: * The setting in the 26 ~ 2C registers is either for T0 path or for T4 path, as determined by the T4_T0_SEL bit.
Functional Description
24
December 9, 2008
IDT82V3285
3.7
WAN PLL
SELECTED INPUT CLOCK MONITORING
3.7.1.3
The T0/T4 DPLL compares the selected input clock with the feedback signal. If the phase-compared result exceeds the fine phase limit
programmed by the PH_LOS_FINE_LIMT[2:0] bits, a fine phase loss is
triggered. It is cleared once the phase-compared result is within the fine
phase limit.
The quality of the selected input clock is always monitored (refer to
Chapter 3.5 Input Clock Quality Monitoring) and the DPLL locking status
is always monitored.
3.7.1
T0 / T4 DPLL LOCKING DETECTION
The following events are always monitored:
• Fast Loss;
• Coarse Phase Loss;
• Fine Phase Loss;
• Hard Limit Exceeding.
3.7.1.1
The occurrence of the fine phase loss will result in T0/T4 DPLL being
unlocked if the FINE_PH_LOS_LIMT_EN bit is ‘1’.
3.7.1.4
A fast loss is triggered when the selected input clock misses 2 consecutive clock cycles. It is cleared once an active clock edge is detected.
For T0 path, the occurrence of the fast loss will result in T0 DPLL
being unlocked if the FAST_LOS_SW bit is ‘1’. For T4 path, the occurrence of the fast loss will result in T4 DPLL being unlocked regardless of
the FAST_LOS_SW bit.
Coarse Phase Loss
The DPLL soft limit is set by the DPLL_FREQ_SOFT_LIMT[6:0] bits
and can be calculated as follows:
The T0/T4 DPLL compares the selected input clock with the feedback signal. If the phase-compared result exceeds the coarse phase
limit, a coarse phase loss is triggered. It is cleared once the phase-compared result is within the coarse phase limit.
DPLL Soft Limit (ppm) = DPLL_FREQ_SOFT_LIMT[6:0] X 0.724
The DPLL hard limit is set by the DPLL_FREQ_HARD_LIMT[15:0]
bits and can be calculated as follows:
When the selected input clock is of 2 kHz, 4 kHz or 8 kHz, the coarse
phase limit depends on the MULTI_PH_8K_4K_2K_EN bit, the
WIDE_EN bit and the PH_LOS_COARSE_LIMT[3:0] bits. Refer to
Table 10. When the selected input clock is of other frequencies than 2
kHz, 4 kHz and 8 kHz, the coarse phase limit depends on the WIDE_EN
bit and the PH_LOS_COARSE_LIMT[3:0] bits. Refer to Table 11.
DPLL Hard Limit (ppm) = DPLL_FREQ_HARD_LIMT[15:0] X 0.0014
3.7.2
0
Coarse Phase Limit
don’t-care
±1 UI
0
±1 UI
1
set by the PH_LOS_COARSE_LIMT[3:0] bits
1
If the FAST_LOS_SW bit, the COARSE_PH_LOS_LIMT_EN bit, the
FINE_PH_LOS_LIMT_EN bit or the FREQ_LIMT_PH_LOS bit is ‘0’, the
DPLL locking status will not be affected even if the corresponding event
is triggered. If all these bits are ‘0’, the DPLL will be in locked state in 2
seconds.
Table 11: Coarse Phase Limit Programming (the selected input
clock of other than 2 kHz, 4 kHz and 8 kHz)
WIDE_EN
Coarse Phase Limit
0
1
±1 UI
set by the PH_LOS_COARSE_LIMT[3:0] bits
The DPLL locking status is indicated by the T0_DPLL_LOCK /
T4_DPLL_LOCK bit.
The T4_STS 1 bit will be set when the locking status of the T4 DPLL
changes (from ‘locked’ to ‘unlocked’ or from ‘unlocked’ to ‘locked’). If the
T4_STS 2 bit is ‘1’, an interrupt will be generated.
The occurrence of the coarse phase loss will result in T0/T4 DPLL
being unlocked if the COARSE_PH_LOS_LIMT_EN bit is ‘1’.
Functional Description
LOCKING STATUS
The DPLL locking status depends on the locking monitoring results.
The DPLL is in locked state if none of the following events is triggered
during 2 seconds; otherwise, the DPLL is unlocked.
• Fast Loss (the FAST_LOS_SW bit is ‘1’);
• Coarse Phase Loss (the COARSE_PH_LOS_LIMT_EN bit is
‘1’);
• Fine Phase Loss (the FINE_PH_LOS_LIMT_EN bit is ‘1’);
• DPLL Hard Alarm (the FREQ_LIMT_PH_LOS bit is ‘1’).
Table 10: Coarse Phase Limit Programming (the selected input
clock of 2 kHz, 4 kHz or 8 kHz)
MULTI_PH_8K_4K
WIDE_EN
_2K_EN
Hard Limit Exceeding
Two limits are available for this monitoring. They are DPLL soft limit
and DPLL hard limit. When the frequency of the DPLL output with
respect to the master clock exceeds the DPLL soft / hard limit, a DPLL
soft / hard alarm will be raised; the alarm is cleared once the frequency
is within the corresponding limit. The occurrence of the DPLL soft alarm
does not affect the T0/T4 DPLL locking status. The DPLL soft alarm is
indicated by the corresponding T0_DPLL_SOFT_FREQ_ALARM /
T4_DPLL_SOFT_FREQ_ALARM bit. The occurrence of the DPLL hard
alarm will result in T0/T4 DPLL being unlocked if the
FREQ_LIMT_PH_LOS bit is ‘1’.
Fast Loss
3.7.1.2
Fine Phase Loss
25
December 9, 2008
IDT82V3285
3.7.3
WAN PLL
• Be cleared when a ‘1’ is written to the corresponding
INn_PH_LOCK_ALARM bit;
• Be cleared after the period (= TIME_OUT_VALUE[5:0] X
MULTI_FACTOR[1:0] in seconds) which starts from when the
alarm is raised.
PHASE LOCK ALARM (T0 ONLY)
A phase lock alarm will be raised when the selected input clock can
not be locked in T0 DPLL within a certain period. This period can be calculated as follows:
Period (sec.) = TIME_OUT_VALUE[5:0] X MULTI_FACTOR[1:0]
The selected input clock with a phase lock alarm is disqualified for T0
DPLL locking.
The phase lock alarm is indicated by the corresponding
INn_PH_LOCK_ALARM bit (1 ≤ n ≤ 5).
Note that no phase lock alarm is raised if the T4 selected input clock
can not be locked.
The phase lock alarm can be cleared by the following two ways, as
selected by the PH_ALARM_TIMEOUT bit:
Table 12: Related Bit / Register in Chapter 3.7
Bit
Register
Address (Hex)
PHASE_LOSS_FINE_LIMIT_CNFG
5B *
PHASE_LOSS_COARSE_LIMIT_CNFG
5A *
OPERATING_STS
52
DPLL_FREQ_SOFT_LIMIT_CNFG
65
DPLL_FREQ_HARD_LIMT[15:0]
DPLL_FREQ_HARD_LIMIT[15:8]_CNFG,
DPLL_FREQ_HARD_LIMIT[7:0]_CNFG
67, 66
T4_STS 1
INTERRUPTS3_STS
0F
INTERRUPTS3_ENABLE_CNFG
12
PHASE_ALARM_TIME_OUT_CNFG
08
IN1_IN2_STS, IN3_IN4_STS, IN5_STS
INPUT_MODE_CNFG
T4_T0_REG_SEL_CNFG
44 ~ 45, 48
09
07
FAST_LOS_SW
PH_LOS_FINE_LIMT[2:0]
FINE_PH_LOS_LIMT_EN
MULTI_PH_8K_4K_2K_EN
WIDE_EN
PH_LOS_COARSE_LIMT[3:0]
COARSE_PH_LOS_LIMT_EN
T0_DPLL_SOFT_FREQ_ALARM
T4_DPLL_SOFT_FREQ_ALARM
T0_DPLL_LOCK
T4_DPLL_LOCK
DPLL_FREQ_SOFT_LIMT[6:0]
FREQ_LIMT_PH_LOS
2
T4_STS
TIME_OUT_VALUE[5:0]
MULTI_FACTOR[1:0]
INn_PH_LOCK_ALARM (1 ≤ n ≤ 5)
PH_ALARM_TIMEOUT
T4_T0_SEL
Note: * The setting in the 5A and 5B registers is either for T0 path or for T4 path, as determined by the T4_T0_SEL bit.
Functional Description
26
December 9, 2008
IDT82V3285
3.8
WAN PLL
SELECTED INPUT CLOCK SWITCH
For T0 path, Revertive and Non-Revertive switches are supported,
as selected by the REVERTIVE_MODE bit.
If the input clock is selected by External Fast selection or by Forced
selection, it can be switched by setting the related registers (refer to
Chapter 3.6.1 External Fast Selection (T0 only) & Chapter 3.6.2 Forced
Selection) any time. In this case, whether the input clock is qualified for
DPLL locking does not affect the clock switch. If the T4 selected input
clock is a T0 DPLL output, it can only be switched by setting the
T0_FOR_T4 bit.
For T4 path, only Revertive switch is supported.
The difference between Revertive and Non-Revertive switches is
that whether the selected input clock is switched when another qualified
input clock with a higher priority than the current selected input clock is
available for selection. In Non-Revertive switch, input clock switch is
minimized.
When the input clock is selected by Automatic selection, the input
clock switch depends on its validity, priority and locking allowance configuration. If the current selected input clock is disqualified, a new qualified input clock may be switched to.
3.8.1
Conditions of the qualified input clocks available for T0 selection are
different from that for T4 selection, as shown in Table 13:
Table 13: Conditions of Qualified Input Clocks Available for T0 & T4
Selection
INPUT CLOCK VALIDITY
Conditions of Qualified Input Clocks Available for T0 & T4 Selection
For all the input clocks, the validity depends on the results of input
clock quality monitoring (refer to Chapter 3.5 Input Clock Quality Monitoring). When all of the following conditions are satisfied, the input clock
is valid; otherwise, it is invalid.
• No no-activity alarm (the INn_NO_ACTIVITY_ALARM bit is ‘0’);
• No frequency hard alarm (the INn_FREQ_HARD_ALARM bit is
‘0’);
• If the IN_NOISE_WINDOW bit is ‘1’, all the edges of the input
clock of 2 kHz, 4 kHz or 8 kHz drift inside ±5%; if the
IN_NOISE_WINDOW bit is ‘0’, this condition is ignored.
• Valid, i.e., the INn 1 bit is ‘1’;
• Priority enabled, i.e., the corresponding INn_SEL_PRIORITY[3:0] bits
T0 are not ‘0000’;
• Locking to the input clock is allowed, i.e., the corresponding INn_VALID
bit is ‘0’.
• Valid (all the validity conditions listed in Chapter 3.8.1 Input Clock Validity are satisfied);
• Priority enabled, i.e., the corresponding INn_SEL_PRIORITY[3:0] bits
T4
are not ‘0000’;
• Locking to the input clock is allowed, i.e., the corresponding INn_VALID
bit is ‘0’.
The validity qualification of the T0 selected input clock is different
from that of the T4 selected input clock. The validity qualification of the
T4 selected input clock is the same as the above. The T0 selected input
clock is valid when all of the above and the following conditions are satisfied; otherwise, it is invalid.
• No phase lock alarm, i.e., the INn_PH_LOCK_ALARM bit is ‘0’;
• If the ULTR_FAST_SW bit is ‘1’, the T0 selected input clock
misses less than (<) 2 consecutive clock cycles; if the
ULTR_FAST_SW bit is ‘0’, this condition is ignored.
The input clock is disqualified if any of the above conditions is not
satisfied.
In summary, the selected input clock can be switched by:
• External Fast selection (supported by T0 path only);
• Forced selection;
• Revertive switch;
• Non-Revertive switch (supported by T0 path only);
• T4 DPLL locked to T0 DPLL output (supported by T4 path only).
The validities of all the input clocks are indicated by the INn 1 bit (1 ≤
n ≤ 5). When the input clock validity changes (from ‘valid’ to ‘invalid’ or
from ‘invalid’ to ‘valid’), the INn 2 bit will be set. If the INn 3 bit is ‘1’, an
interrupt will be generated.
3.8.2.1
In Revertive switch, the selected input clock is switched when
another qualified input clock with a higher priority than the current
selected input clock is available.
When the T0 selected input clock has failed, i.e., the validity of the T0
selected input clock changes from ‘valid’ to ‘invalid’, the
T0_MAIN_REF_FAILED 1 bit will be set. If the T0_MAIN_REF_FAILED 2
bit is ‘1’, an interrupt will be generated. This interrupt can also be indicated by hardware - the TDO pin, as determined by the
LOS_FLAG_TO_TDO bit. When the TDO pin is used to indicate this
interrupt, it will be set high when this interrupt is generated and will
remain high until this interrupt is cleared.
3.8.2
Revertive Switch
The selected input clock is switched if any of the following is satisfied:
• the selected input clock is disqualified;
• another qualified input clock with a higher priority than the
selected input clock is available.
A qualified input clock with the highest priority is selected by revertive
switch. If more than one qualified input clock INn is available and has the
same priority, the input clock with the smallest ‘n’ is selected.
SELECTED INPUT CLOCK SWITCH
When the device is configured as Automatic input clock selection, T0
input clock switch is different from T4 input clock switch.
Functional Description
27
December 9, 2008
IDT82V3285
3.8.2.2
WAN PLL
The qualified input clocks with the three highest priorities are indicated by HIGHEST_PRIORITY_VALIDATED[3:0] bits, the SECOND_
PRIORITY_VALIDATED[3:0] bits and the THIRD_PRIORITY
_VALIDATED[3:0] bits respectively. If more than one input clock INn has
the same priority, the input clock with the smallest ‘n’ is indicated by the
HIGHEST_PRIORITY_VALIDATED[3:0] bits.
Non-Revertive Switch (T0 only)
In Non-Revertive switch, the T0 selected input clock is not switched
when another qualified input clock with a higher priority than the current
selected input clock is available. In this case, the selected input clock is
switched and a qualified input clock with the highest priority is selected
only when the T0 selected input clock is disqualified. If more than one
qualified input clock is available and has the same priority, the input
clock with the smallest ‘n’ is selected.
3.8.3
When the device is configured in Automatic selection and Revertive
switch is enabled, the input clock indicated by the
CURRENTLY_SELECTED_INPUT[3:0] bits is the same as the one indicated by the HIGHEST_PRIORITY_VALIDATED[3:0] bits; otherwise,
they are not the same.
SELECTED / QUALIFIED INPUT CLOCKS INDICATION
The
selected
input
clock
is
indicated
by
the
CURRENTLY_SELECTED_INPUT[3:0] bits. Note if the T4 selected
input clock is a T0 DPLL output, it can not be indicated by these bits.
When all the input clocks for T4 path become unqualified, the
INPUT_TO_T4 1 bit will be set. If the INPUT_TO_T4 2 bit is ‘1’, an interrupt will be generated.
Table 14: Related Bit / Register in Chapter 3.8
Bit
Register
T0_FOR_T4
Address (Hex)
T4_INPUT_SEL_CNFG
51
≤ n ≤ 5)
INPUT_VALID1_STS, INPUT_VALID2_STS
4A, 4B
INn 2 (1 ≤ n ≤ 5)
INTERRUPTS1_STS, INTERRUPTS2_STS
0D, 0E
≤ n ≤ 5)
INn_NO_ACTIVITY_ALARM (1 ≤ n ≤ 5)
INn_FREQ_HARD_ALARM (1 ≤ n ≤ 5)
INn_PH_LOCK_ALARM (1 ≤ n ≤ 5)
INTERRUPTS1_ENABLE_CNFG, INTERRUPTS2_ENABLE_CNFG
10, 11
IN1_IN2_STS, IN3_IN4_STS, IN5_STS
44 ~ 45, 48
IN_NOISE_WINDOW
ULTR_FAST_SW
LOS_FLAG_TO_TDO
PHASE_MON_PBO_CNFG
78
MON_SW_PBO_CNFG
0B
T0_MAIN_REF_FAILED 1
INTERRUPTS2_STS
0E
T0_MAIN_REF_FAILED 2
INTERRUPTS2_ENABLE_CNFG
11
INTERRUPTS3_STS
0F
INn 1 (1
INn
3 (1
INPUT_TO_T4
1
INPUT_TO_T4 2
INTERRUPTS3_ENABLE_CNFG
12
REVERTIVE_MODE
INPUT_MODE_CNFG
IN1_IN2_SEL_PRIORITY_CNFG, IN3_IN4_SEL_PRIORITY_CNFG,
IN5_SEL_PRIORITY_CNFG
09
INn_SEL_PRIORITY[3:0] (1 ≤ n ≤ 5)
INn_VALID (1 ≤ n ≤ 5)
CURRENTLY_SELECTED_INPUT[3:0]
HIGHEST_PRIORITY_VALIDATED[3:0]
SECOND_PRIORITY_VALIDATED[3:0]
THIRD_PRIORITY_VALIDATED[3:0]
T4_T0_SEL
27 ~ 28, 2B
REMOTE_INPUT_VALID1_CNFG, REMOTE_INPUT_VALID2_CNFG
4C, 4D
PRIORITY_TABLE1_STS
4E *
PRIORITY_TABLE2_STS
4F *
T4_T0_REG_SEL_CNFG
07
Note: * The setting in the 26 ~ 2C, 4E and 4F registers is either for T0 path or for T4 path, as determined by the T4_T0_SEL bit.
Functional Description
28
December 9, 2008
IDT82V3285
3.9
WAN PLL
SELECTED INPUT CLOCK STATUS VS. DPLL
OPERATING MODE
3.9.1
The T0 DPLL operating mode is controlled
T0_OPERATING_MODE[2:0] bits, as shown in Table 15:
The operating modes supported by T0 DPLL are more complex than
the ones supported by T4 DPLL for T0 path is the main one. T0 DPLL
supports three primary operating modes: Free-Run, Locked and Holdover, and three secondary, temporary operating modes: Pre-Locked,
Pre-Locked2 and Lost-Phase. T4 DPLL supports three operating
modes: Free-Run, Locked and Holdover. The operating modes of T0
DPLL and T4 DPLL can be switched automatically or by force, as controlled by the T0_OPERATING_MODE[2:0] / T4_OPERATING_
MODE[2:0] bits respectively.
by
the
Table 15: T0 DPLL Operating Mode Control
When the operating mode is switched by force, the operating mode
switch is under external control and the status of the selected input clock
takes no effect to the operating mode selection. The forced operating
mode switch is applicable for special cases, such as testing.
T0_OPERATING_MODE[2:0]
T0 DPLL Operating Mode
000
001
010
100
101
110
111
Automatic
Forced - Free-Run
Forced - Holdover
Forced - Locked
Forced - Pre-Locked2
Forced - Pre-Locked
Forced - Lost-Phase
When the operating mode is switched automatically, the operation of
the internal state machine is shown in Figure 7.
When the operating mode is switched automatically, the internal
state machines for T0 and for T4 automatically determine the operating
mode respectively.
Functional Description
T0 SELECTED INPUT CLOCK VS. DPLL OPERATING
MODE
Whether the operating mode is under external control or is switched
automatically, the current operating mode is always indicated by the
T0_DPLL_OPERATING_MODE[2:0] bits. When the operating mode
switches, the T0_OPERATING_MODE 1 bit will be set. If the
T0_OPERATING_MODE 2 bit is ‘1’, an interrupt will be generated.
29
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IDT82V3285
WAN PLL
1
Free-Run mode
3
2
Pre-Locked
mode
4
5
Locked
mode
10
9
15
Pre-Locked2
mode
8
6
Holdover
mode
7
11
12
Lost-Phase
mode
13
14
Figure 7. T0 Selected Input Clock vs. DPLL Automatic Operating Mode
Notes to Figure 7:
1. Reset.
2. An input clock is selected.
3. The T0 selected input clock is disqualified AND No qualified input clock is available.
4. The T0 selected input clock is switched to another one.
5. The T0 selected input clock is locked (the T0_DPLL_LOCK bit is ‘1’).
6. The T0 selected input clock is disqualified AND No qualified input clock is available.
7. The T0 selected input clock is unlocked (the T0_DPLL_LOCK bit is ‘0’).
8. The T0 selected input clock is locked again (the T0_DPLL_LOCK bit is ‘1’).
9. The T0 selected input clock is switched to another one.
10. The T0 selected input clock is locked (the T0_DPLL_LOCK bit is ‘1’).
11. The T0 selected input clock is disqualified AND No qualified input clock is available.
12. The T0 selected input clock is switched to another one.
13. The T0 selected input clock is disqualified AND No qualified input clock is available.
14. An input clock is selected.
15. The T0 selected input clock is switched to another one.
Functional Description
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IDT82V3285
WAN PLL
Notes to Figure 8:
1. Reset.
2. An input clock is selected.
3. (The T4 selected input clock is disqualified) OR (A qualified input
clock with a higher priority is switched to) OR (The T4 selected
input clock is switched to another one by Forced selection) OR
(When T4 DPLL locks to the T0 DPLL output, the T4 selected
input clock is switched by setting the T0_FOR_T4 bit).
4. An input clock is selected.
5. No input clock is selected.
The causes of Item 4, 9, 12, 15 - ‘the T0 selected input clock is
switched to another one’ - are: (The T0 selected input clock is disqualified AND Another input clock is switched to) OR (In Revertive switch, a
qualified input clock with a higher priority is switched to) OR (The T0
selected input clock is switched to another one by External Fast selection or Forced selection).
Refer to Table 13 for details about the input clock qualification for T0
path.
3.9.2
T4 SELECTED INPUT CLOCK VS. DPLL OPERATING
MODE
The T4 DPLL operating mode is controlled
T4_OPERATING_MODE[2:0] bits, as shown in Table 16:
by
Refer to Table 13 for details about the input clock qualification for T4
path.
the
Table 17: Related Bit / Register in Chapter 3.9
Table 16: T4 DPLL Operating Mode Control
T4_OPERATING_MODE[2:0]
T4 DPLL Operating Mode
000
001
010
100
Automatic
Forced - Free-Run
Forced - Holdover
Forced - Locked
Bit
Address
(Hex)
Register
T0_OPERATING_MODE[2:0] T0_OPERATING_MODE_CNFG
T4_OPERATING_MODE[2:0] T4_OPERATING_MODE_CNFG
T0_DPLL_OPERATING_MOD
E[2:0]
OPERATING_STS
T0_DPLL_LOCK
When the operating mode is switched automatically, the operation of
the internal state machine is shown in Figure 8:
T0_OPERATING_MODE 1
T0_OPERATING_MODE
T0_FOR_T4
1
2
53
54
52
INTERRUPTS2_STS
0E
INTERRUPTS2_ENABLE_CNFG
11
T4_INPUT_SEL_CNFG
51
Free-Run mode
2
Locked mode
3
4
Holdover
mode
5
Figure 8. T4 Selected Input Clock vs. DPLL Automatic
Operating Mode
Functional Description
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December 9, 2008
IDT82V3285
3.10
WAN PLL
T0 / T4 DPLL OPERATING MODE
3.10.1.1
In Free-Run mode, the T0 DPLL output refers to the master clock
and is not affected by any input clock. The accuracy of the T0 DPLL output is equal to that of the master clock.
The T0/T4 DPLL gives a stable performance in different applications
without being affected by operating conditions or silicon process variations. It integrates a PFD (Phase & Frequency Detector), a LPF (Low
Pass Filter) and a DCO (Digital Controlled Oscillator), which form a
closed loop. If no input clock is selected, the loop is not closed, and the
PFD and LPF do not function.
3.10.1.2
Pre-Locked Mode
In Pre-Locked mode, the T0 DPLL output attempts to track the
selected input clock.
The PFD detects the phase error, including the fast loss, coarse
phase loss and fine phase loss (refer to Chapter 3.7.1.1 Fast Loss to
Chapter 3.7.1.3 Fine Phase Loss). The averaged phase error of the T0/
T4 DPLL feedback with respect to the selected input clock is indicated
by the CURRENT_PH_DATA[15:0] bits. It can be calculated as follows:
The Pre-Locked mode is a secondary, temporary mode.
3.10.1.3
Locked Mode
In Locked mode, the T0 selected input clock is locked. The phase
and frequency offset of the T0 DPLL output track those of the T0
selected input clock.
Averaged Phase Error (ns) = CURRENT_PH_DATA[15:0] X 0.61
The LPF filters jitters. Its 3 dB bandwidth and damping factor are programmable. A range of bandwidths and damping factors can be set to
meet different application requirements. Generally, the lower the damping factor is, the longer the locking time is and the more the gain is.
In this mode, if the T0 selected input clock is in fast loss status and
the FAST_LOS_SW bit is ‘1’, the T0 DPLL is unlocked (refer to
Chapter 3.7.1.1 Fast Loss) and will enter Lost-Phase mode when the
operating mode is switched automatically; if the T0 selected input clock
is in fast loss status and the FAST_LOS_SW bit is ‘0’, the T0 DPLL locking status is not affected and the T0 DPLL will enter Temp-Holdover
mode automatically.
The DCO controls the DPLL output. The frequency of the DPLL output is always multiplied on the basis of the master clock. The phase and
frequency offset of the DPLL output may be locked to those of the
selected input clock. The current frequency offset with respect to the
master clock is indicated by the CURRENT_DPLL_FREQ[23:0] bits, and
can be calculated as follows:
3.10.1.3.1 Temp-Holdover Mode
The T0 DPLL will automatically enter Temp-Holdover mode with a
selected input clock switch or no qualified input clock available when the
operating mode switch is under external control.
Current Frequency Offset (ppm) = CURRENT_DPLL_FREQ[23:0] X
0.000011
3.10.1
Free-Run Mode
In Temp-Holdover mode, the T0 DPLL has temporarily lost the
selected input clock. The T0 DPLL operation in Temp-Holdover mode
and that in Holdover mode are alike (refer to Chapter 3.10.1.5 Holdover
Mode) except the frequency offset acquiring methods. See
Chapter 3.10.1.5 Holdover Mode for details about the methods. The
method is selected by the TEMP_HOLDOVER_MODE[1:0] bits, as
shown in Table 18:
T0 DPLL OPERATING MODE
The T0 DPLL loop is closed except in Free-Run mode and Holdover
mode.
For a closed loop, different bandwidths and damping factors can be
used depending on DPLL locking stages: starting, acquisition and
locked.
In the first two seconds when the T0 DPLL attempts to lock to the
selected input clock, the starting bandwidth and damping factor are
used. They are set by the T0_DPLL_START_BW[4:0] bits and the
T0_DPLL_START_DAMPING[2:0] bits respectively.
Table 18: Frequency Offset Control in Temp-Holdover Mode
TEMP_HOLDOVER_MODE[1:0]
Frequency Offset Acquiring Method
00
01
10
11
the same as that used in Holdover mode
Automatic Instantaneous
Automatic Fast Averaged
Automatic Slow Averaged
During the acquisition, the acquisition bandwidth and damping factor
are used. They are set by the T0_DPLL_ACQ_BW[4:0] bits and the
T0_DPLL_ACQ_DAMPING[2:0] bits respectively.
When the T0 selected input clock is locked, the locked bandwidth
and damping factor are used. They are set by the
T0_DPLL_LOCKED_BW[4:0]
bits
and
the
T0_DPLL_LOCKED_DAMPING[2:0] bits respectively.
The device automatically controls the T0 DPLL to exit from TempHoldover mode.
3.10.1.4
Lost-Phase Mode
The corresponding bandwidth and damping factor are used when the
T0 DPLL operates in different DPLL locking stages: starting, acquisition
and locked, as controlled by the device automatically.
In Lost-Phase mode, the T0 DPLL output attempts to track the
selected input clock.
Only the locked bandwidth and damping factor can be used regardless of the T0 DPLL locking stage, as controlled by the AUTO_BW_SEL
bit.
3.10.1.5
Functional Description
The Lost-Phase mode is a secondary, temporary mode.
Holdover Mode
In Holdover mode, the T0 DPLL resorts to the stored frequency data
acquired in Locked mode to control its output. The T0 DPLL output is not
32
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IDT82V3285
WAN PLL
phase locked to any input clock. The frequency offset acquiring method
is selected by the MAN_HOLDOVER bit, the AUTO_AVG bit and the
FAST_AVG bit, as shown in Table 19:
Table 19: Frequency Offset Control in Holdover Mode
MAN_HOLDOVER
AUTO_AVG
FAST_AVG
Frequency Offset Acquiring Method
0
don’t-care
0
1
Automatic Instantaneous
Automatic Slow Averaged
Automatic Fast Averaged
Manual
0
1
1
don’t-care
3.10.1.5.1 Automatic Instantaneous
Table 20: Holdover Frequency Offset Read
By this method, the T0 DPLL freezes at the operating frequency
when it enters Holdover mode. The accuracy is 4.4X10-8 ppm.
READ_AVG FAST_AVG
3.10.1.5.2 Automatic Slow Averaged
0
By this method, an internal IIR (Infinite Impulse Response) filter is
employed to get the frequency offset. The IIR filter gives a 3 dB attenuation point corresponding to a period of 110 minutes. The accuracy is
1.1X10-5 ppm.
1
3.10.1.5.3 Automatic Fast Averaged
don’t-care The value is equal to the one written to.
The value is acquired by Automatic Slow Averaged
0
method, not equal to the one written to.
The value is acquired by Automatic Fast Averaged
1
method, not equal to the one written to.
The frequency offset in ppm is calculated as follows:
Holdover Frequency Offset (ppm) = T0_HOLDOVER_FREQ[23:0] X
0.000011
By this method, an internal IIR (Infinite Impulse Response) filter is
employed to get the frequency offset. The IIR filter gives a 3 dB attenuation point corresponding to a period of 8 minutes. The accuracy is
1.1X10-5 ppm.
3.10.1.6
Pre-Locked2 Mode
In Pre-Locked2 mode, the T0 DPLL output attempts to track the
selected input clock.
3.10.1.5.4 Manual
By this method, the frequency offset is set by
T0_HOLDOVER_FREQ[23:0] bits. The accuracy is 1.1X10-5 ppm.
Offset Value Read from
T0_HOLDOVER_FREQ[23:0]
The Pre-Locked2 mode is a secondary, temporary mode.
the
3.10.2
The frequency offset of the T0 DPLL output is indicated by the
CURRENT_DPLL_FREQ[23:0] bits.
T4 DPLL OPERATING MODE
The T4 path is simpler compared with the T0 path.
3.10.2.1
The device provides a reference for the value to be written to the
T0_HOLDOVER_FREQ[23:0] bits. The value to be written can refer to
the value read from the CURRENT_DPLL_FREQ[23:0] bits or the
T0_HOLDOVER_FREQ[23:0] bits (refer to Chapter 3.10.1.5.5 Holdover
Frequency Offset Read); or then be processed by external software filtering.
Free-Run Mode
In Free-Run mode, the T4 DPLL output refers to the master clock
and is affected by any input clock. The accuracy of the T4 DPLL output
is equal to that of the master clock.
3.10.2.2
Locked Mode
3.10.1.5.5 Holdover Frequency Offset Read
In Locked mode, the T4 selected input clock may be locked in the T4
DPLL.
The offset value, which is acquired by Automatic Slow Averaged,
Automatic Fast Averaged and is set by related register bits, can be read
from the T0_HOLDOVER_FREQ[23:0] bits by setting the READ_AVG
bit and the FAST_AVG bit, as shown in Table 20.
When the T4 selected input clock is locked, the phase and frequency
offset of the T4 DPLL output track those of the T4 selected input clock;
when unlocked, the phase and frequency offset of the T4 DPLL output
attempt to track those of the selected input clock.
The T4 DPLL loop is closed in Locked mode. Its bandwidth and
damping factor are set by the T4_DPLL_LOCKED_BW[1:0] bits and the
T4_DPLL_LOCKED_DAMPING[2:0] bits respectively.
3.10.2.3
Holdover Mode
In Holdover mode, the T4 DPLL resorts to the stored frequency data
acquired in Locked mode to control its output. The T4 DPLL output is not
Functional Description
33
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IDT82V3285
WAN PLL
phase locked to any input clock. The T4 DPLL freezes at the operating
frequency when it enters Holdover mode. The accuracy is 4.4X10-8
ppm.
Table 21: Related Bit / Register in Chapter 3.10
Bit
Register
Address (Hex)
CURRENT_PH_DATA[15:0]
CURRENT_DPLL_PHASE[15:8]_STS, CURRENT_DPLL_PHASE[7:0]_STS
CURRENT_DPLL_FREQ[23:16]_STS, CURRENT_DPLL_FREQ[15:8]_STS,
CURRENT_DPLL_FREQ[7:0]_STS
69 *, 68 *
CURRENT_DPLL_FREQ[23:0]
T0_DPLL_START_BW[4:0]
T0_DPLL_START_DAMPING[2:0]
T0_DPLL_ACQ_BW[4:0]
T0_DPLL_ACQ_DAMPING[2:0]
T0_DPLL_LOCKED_BW[4:0]
T0_DPLL_LOCKED_DAMPING[2:0]
AUTO_BW_SEL
FAST_LOS_SW
TEMP_HOLDOVER_MODE[1:0]
MAN_HOLDOVER
AUTO_AVG
FAST_AVG
READ_AVG
T0_HOLDOVER_FREQ[23:0]
T4_DPLL_LOCKED_BW[1:0]
T4_DPLL_LOCKED_DAMPING[2:0]
T4_T0_SEL
64 *, 63 *, 62 *
T0_DPLL_START_BW_DAMPING_CNFG
56
T0_DPLL_ACQ_BW_DAMPING_CNFG
57
T0_DPLL_LOCKED_BW_DAMPING_CNFG
58
T0_BW_OVERSHOOT_CNFG
PHASE_LOSS_FINE_LIMIT_CNFG
59
5B *
T0_HOLDOVER_MODE_CNFG
5C
T0_HOLDOVER_FREQ[23:16]_CNFG, T0_HOLDOVER_FREQ[15:8]_CNFG,
T0_HOLDOVER_FREQ[7:0]_CNFG
5F, 5E, 5D
T4_DPLL_LOCKED_BW_DAMPING_CNFG
61
T4_T0_REG_SEL_CNFG
07
Note: * The setting in the 5B, 62 ~ 64, 68 and 69 registers is either for T0 path or for T4 path, as determined by the T4_T0_SEL bit.
Functional Description
34
December 9, 2008
IDT82V3285
3.11
WAN PLL
T0 / T4 DPLL OUTPUT
1.0 µs but less than 3.5 µs that occur over an interval of less than 0.1
seconds may or may not be built-out.
The DPLL output is locked to the selected input clock. According to
the phase-compared result of the feedback and the selected input clock,
and the DPLL output frequency offset, the PFD output is limited and the
DPLL output is frequency offset limited.
3.11.1
An integrated Phase Transient Monitor can be enabled by the
PH_MON_EN bit to monitor the phase-time changes on the T0 selected
input clock. When the phase-time changes are greater than a limit over
an interval of less than 0.1 seconds, a PBO event is triggered and the
phase transients on the DPLL output are absorbed. The limit is programmed by the PH_TR_MON_LIMT[3:0] bits, and can be calculated as
follows:
PFD OUTPUT LIMIT
The PFD output is limited to be within ±1 UI or within the coarse
phase limit (refer to Chapter 3.7.1.2 Coarse Phase Loss), as determined
by the MULTI_PH_APP bit.
3.11.2
Limit (ns) = (PH_TR_MON_LIMT[3:0] + 7) X 156
The phase offset induced by PBO will never result in a coarse or fine
phase loss.
FREQUENCY OFFSET LIMIT
The DPLL output is limited to be within the DPLL hard limit (refer to
Chapter 3.7.1.4 Hard Limit Exceeding).
3.11.4
The phase offset of the T0 selected input clock with respect to the T0
DPLL output can be adjusted. If the device is configured as the Master,
the PH_OFFSET_EN bit determines whether the input-to-output phase
offset is enabled; if the device is configured as the Slave, the input-tooutput phase offset is always enabled. If enabled, the input-to-output
phase offset can be adjusted by setting the PH_OFFSET[9:0] bits.
For T0 DPLL, the integral path value can be frozen when the DPLL
hard limit is reached. This function, enabled by the T0_LIMT bit, will minimize the subsequent overshoot when T0 DPLL is pulling in.
3.11.3
PBO (T0 ONLY)
The PBO function is only supported by the T0 path.
When a PBO event is triggered, the phase offset of the selected input
clock with respect to the T0 DPLL output is measured. The device then
automatically accounts for the measured phase offset and compensates
an appropriate phase offset into the DPLL output so that the phase transients on the T0 DPLL output are minimized.
The input-to-output phase offset can be calculated as follows:
Phase Offset (ns) = PH_OFFSET[9:0] X 0.61
3.11.5
FOUR PATHS OF T0 / T4 DPLL OUTPUTS
The T0 DPLL output and the T4 DPLL output are phase aligned with
the T0 selected input clock and the T4 selected input clock respectively
every 125 µs period. Each DPLL has four output paths.
A PBO event is triggered if any one of the following conditions
occurs:
• T0 selected input clock switches (the PBO_EN bit is ‘1’);
• T0 DPLL exits from Holdover mode or Free-Run mode (the
PBO_EN bit is ‘1’);
• Phase-time changes on the T0 selected input clock are greater
than a programmable limit over an interval of less than 0.1 seconds (the PH_MON_PBO_EN bit is ‘1’).
3.11.5.1
T0 Path
The four paths for T0 DPLL output are as follows:
• 77.76 MHz path - outputs a 77.76 MHz clock;
• 16E1/16T1 path - outputs a 16E1 or 16T1 clock, as selected by
the IN_SONET_SDH bit;
• GSM/OBSAI/16E1/16T1 path - outputs a GSM, OBSAI, 16E1 or
16T1 clock, as selected by the T0_GSM_OBSAI_16E1_16T1_
SEL[1:0] bits;
• 12E1/24T1/E3/T3 path - outputs a 12E1, 24T1, E3 or T3 clock,
as selected by the T0_12E1_24T1_E3_T3_SEL[1:0] bits.
For the first two conditions, the phase transients on the T0 DPLL output are minimized to be no more than 0.61 ns with PBO. The PBO can
also be frozen at the current phase offset by setting the PBO_FREZ bit.
When the PBO is frozen, the device will ignore any further PBO events
triggered by the above two conditions, and maintain the current phase
offset. When the PBO is disabled, there may be a phase shift on the T0
DPLL output and the T0 DPLL output tracks back to 0 degree phase offset with respect to the T0 selected input clock.
T0 selected input clock is compared with a T0 DPLL output for DPLL
locking. The output can only be derived from the 77.76 MHz path or the
16E1/16T1 path. The output path is automatically selected and the output is automatically divided to get the same frequency as the T0
selected input clock.
The last condition is specially for stratum 2 and 3E clocks. The PBO
requirement specified in the Telcordia GR-1244-CORE is: ‘Input phasetime changes of 3.5 µs or greater over an interval of less than 0.1 seconds or less shall be built-out by stratum 2 and 3E clocks to reduce the
resulting clock phase-time change to less than 50 ns. Phase-time
changes of 1.0 µs or less over an interval of 0.1 seconds shall not be
built-out.’ Based on this requirement, phase-time changes of more than
Functional Description
PHASE OFFSET SELECTION (T0 ONLY)
The T0 DPLL 77.76 MHz output or an 8 kHz signal derived from it
can be provided for the T4 DPLL input clock selection (refer to
Chapter 3.6 T0 / T4 DPLL Input Clock Selection).
T0 DPLL outputs are provided for T0/T4 APLL or device output process.
35
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IDT82V3285
3.11.5.2
WAN PLL
16E1/16T1 path. In this case, the output path is automatically selected
and the output is automatically divided to get the same frequency as the
T4 selected input clock.
T4 Path
The four paths for T4 DPLL output are as follows:
• 77.76 MHz path - outputs a 77.76 MHz clock;
• 16E1/16T1 path - outputs a 16E1 or 16T1 clock, as selected by
the IN_SONET_SDH bit;
• GSM/GPS/16E1/16T1 path - outputs a GSM, GPS, 16E1 or
16T1 clock, as selected by the T4_GSM_GPS_16E1_16T1_
SEL[1:0] bits;
• 12E1/24T1/E3/T3 path - outputs a 12E1, 24T1, E3 or T3 clock,
as selected by the T4_12E1_24T1_E3_T3_SEL[1:0] bits.
In addition, T4 selected input clock is compared with the T0 selected
input clock to get the phase difference between T0 and T4 selected input
clocks, as determined by the T4_TEST_T0_PH bit.
T4 DPLL outputs are provided for T0/T4 APLL or device output process.
T4 selected input clock is compared with a T4 DPLL output for DPLL
locking. The output can be derived from the 77.76 MHz path or the
Table 22: Related Bit / Register in Chapter 3.11
Bit
Register
Address (Hex)
MULTI_PH_APP
T0_LIMT
PBO_EN
PBO_FREZ
PH_MON_PBO_EN
PH_MON_EN
PH_TR_MON_LIMT[3:0]
PH_OFFSET_EN
PH_OFFSET[9:0]
IN_SONET_SDH
T0_GSM_OBSAI_16E1_16T1_SEL[1:0]
T0_12E1_24T1_E3_T3_SEL[1:0]
T4_GSM_GPS_16E1_16T1_SEL[1:0]
T4_12E1_24T1_E3_T3_SEL[1:0]
T4_TEST_T0_PH
T4_T0_SEL
PHASE_LOSS_COARSE_LIMIT_CNFG
T0_BW_OVERSHOOT_CNFG
5A *
59
MON_SW_PBO_CNFG
0B
PHASE_MON_PBO_CNFG
78
PHASE_OFFSET[9:8]_CNFG
PHASE_OFFSET[9:8]_CNFG, PHASE_OFFSET[7:0]_CNFG
INPUT_MODE_CNFG
7B
7B, 7A
09
T0_DPLL_APLL_PATH_CNFG
55
T4_DPLL_APLL_PATH_CNFG
60
T4_INPUT_SEL_CNFG
T4_T0_REG_SEL_CNFG
51
07
Note: * The setting in the 5A register is either for T0 path or for T4 path, as determined by the T4_T0_SEL bit.
Functional Description
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December 9, 2008
IDT82V3285
3.12
WAN PLL
T0 / T4 APLL
3.13.1
The device provides 5 output clocks.
A T0 APLL and a T4 APLL are provided for a better jitter and wander
performance of the device output clocks.
According to the output port technology, the output ports support the
following technologies:
• PECL/LVDS;
• CMOS.
The bandwidths of the T0/T4 APLL are set by the T0_APLL_BW[1:0]
/ T4_APLL_BW[1:0] bits respectively. The lower the bandwidth is, the
better the jitter and wander performance of the T0/T4 APLL output are.
OUT1 ~ OUT3 output CMOS signals.
The input of the T0/T4 APLL can be derived from one of the T0 and
T4 DPLL outputs, as selected by the T0_APLL_PATH[3:0] /
T4_APLL_PATH[3:0] bits respectively.
OUT4 and OUT5 output PECL or LVDS signals, as selected by the
OUT4_PECL_LVDS bit and the OUT5_PECL_LVDS bit respectively.
Both the APLL and DPLL outputs are provided for selection for the
device output.
The outputs on OUT1 ~ OUT5 are variable, depending on the signals
derived from the T0/T4 DPLL and T0/T4 APLL outputs, and the corresponding OUTn_PATH_SEL[3:0] bits (1 ≤ n ≤ 5). The derived signal can
be from the T0/T4 DPLL and T0/T4 APLL outputs, as selected by the
corresponding OUTn_PATH_SEL[3:0] bits (1 ≤ n ≤ 5). If the signal is
derived from one of the T0/T4 DPLL outputs, please refer to Table 24 for
the output frequency. If the signal is derived from the T0/T4 APLL output,
please refer to Table 25 for the output frequency.
Table 23: Related Bit / Register in Chapter 3.12
Bit
T0_APLL_BW[1:0]
T4_APLL_BW[1:0]
T0_APLL_PATH[3:0]
T4_APLL_PATH[3:0]
3.13
Register
Address (Hex)
T0_T4_APLL_BW_CNFG
6A
T0_DPLL_APLL_PATH_CNFG
T4_DPLL_APLL_PATH_CNFG
55
60
OUTPUT CLOCKS
The outputs on OUT1 to OUT5 can be inverted, as determined by the
corresponding OUTn_INV bit (1 ≤ n ≤ 5).
OUTPUT CLOCKS & FRAME SYNC SIGNALS
All the output clocks derived from T0/T4 selected input clock are
aligned with the T0/T4 selected input clock respectively every 125 µs
period.
The device supports 5 output clocks and 2 frame sync output signals
altogether.
Table 24: Outputs on OUT1 ~ OUT5 if Derived from T0/T4 DPLL Outputs
OUTn_DIVIDER[3:0]
(Output Divider) 1
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
outputs on OUT1 ~ OUT5 if derived from T0/T4 DPLL outputs 2
77.76 MHz
12E1
16E1
24T1
16T1
E3
T3
GSM
(26 MHz)
OBSAI
(30.72 MHz)
GPS
(40 MHz)
13 MHz
15.36 MHz
20
10
Output is disabled (output low).
12E1
6E1
3E1
2E1
16E1
8E1
4E1
2E1
E1
24T1
12T1
6T1
4T1
3T1
2T1
16T1
8T1
4T1
E3
2T1
E1
T3
5
T1
T1
64 kHz
8 kHz
2 kHz
400 Hz
1Hz
Output is disabled (output high).
Note:
1. 1 ≤ n ≤ 5. Each output is assigned a frequency divider.
2. E1 = 2.048 MHz, T1 = 1.544 MHz, E3 = 34.368 MHz, T3 = 44.736 MHz. The blank cell means the configuration is reserved.
Functional Description
37
December 9, 2008
IDT82V3285
WAN PLL
Table 25: Outputs on OUT1 ~ OUT5 if Derived from T0/T4 APLL
OUTn_DIVIDER[3:0]
(Output Divider) 1 77.76 MHz X 4 12E1 X 4
outputs on OUT1 ~ OUT5 if derived from T0/T4 APLL output 2
16E1 X 4
24T1 X 4
0000
T3
GSM
OBSAI
(26 MHz X 2) (30.72 MHz X 10)
GPS
(40 MHz)
Output is disabled (output low).
622.08 MHz
0010
311.04 MHz 3
155.52 MHz
77.76 MHz
51.84 MHz
38.88 MHz
25.92 MHz
19.44 MHz
1001
48E1
64E1
96T1
64T1
24E1
12E1
8E1
6E1
4E1
3E1
32E1
16E1
48T1
24T1
16T1
12T1
8T1
6T1
32T1
16T1
8E1
4E1
2E1
1010
1011
E3
3
0001
0011
0100
0101
0110
0111
1000
16T1 X 4
1100
1101
1110
1111
T3
8T1
E1
3T1
26 MHz
13 MHz
153.6 MHz
76.8 MHz
20 MHz
10 MHz
38.4 MHz
5 MHz
61.44 MHz 4
2T1
30.72 MHz 4
15.36 MHz 4
2T1
E1
52 MHz
4T1
4T1
2E1
6.48 MHz
E3
T1
7.68 MHz 4
3.84 MHz 4
T1
Output is disabled (output high).
Note:
1. 1 ≤ n ≤ 5. Each output is assigned a frequency divider.
2. In the APLL, the selected T0/T4 DPLL output may be multiplied. E1 = 2.048 MHz, T1 = 1.544 MHz, E3 = 34.368 MHz, T3 = 44.736 MHz. The blank cell means the configuration is
reserved.
3. The 622.08 MHz and 311.04 MHz differential signals are only output on OUT4 and OUT5.
4. The 61.44 MHz, 30.72 MHz, 15.36 MHz, 7.68 MHz and 3.84 MHz outputs are only derived from T0 APLL.
Functional Description
38
December 9, 2008
IDT82V3285
3.13.2
WAN PLL
selected input clock. Nominally, the falling edge of EX_SYNC1 is aligned
with the rising edge of the T0 selected input clock. EX_SYNC1 may be
0.5 UI early/late or 1 UI late due to the circuit and board wiring delays.
Setting the sampling of EX_SYNC1 by the SYNC_PH1[1:0] bits will
compensate this early/late. Refer to Figure 9 to Figure 12.
FRAME SYNC OUTPUT SIGNALS
An 8 kHz and a 2 kHz frame sync signals are output on the
FRSYNC_8K and MFRSYNC_2K pins if enabled by the 8K_EN and
2K_EN bits respectively. They are CMOS outputs.
The two frame sync signals are derived from the T0 APLL output and
are aligned with the output clock. They can be synchronized to the frame
sync input signal.
The EX_SYNC_ALARM_MON bit indicates whether EX_SYNC1 is in
external sync alarm status. The external sync alarm is indicated by the
EX_SYNC_ALARM 1 bit. If the EX_SYNC_ALARM 2 bit is ‘1’, the occurrence of the external sync alarm will trigger an interrupt.
If the frame sync input signal with respect to the T0 selected input
clock is above a limit set by the SYNC_MON_LIMT[2:0] bits, an external
sync alarm will be raised and EX_SYNC1 is disabled to synchronize the
frame sync output signals. The external sync alarm is cleared once
EX_SYNC1 with respect to the T0 selected input clock is within the limit.
If it is within the limit, whether EX_SYNC1 is enabled to synchronize the
frame sync output signal is determined by the AUTO_EXT_SYNC_EN
bit and the EXT_SYNC_EN bit. Refer to Table 26 for details.
The 8 kHz and the 2 kHz frame sync output signals can be inverted
by setting the 8K_INV and 2K_INV bits respectively. The frame sync outputs can be 50:50 duty cycle or pulsed, as determined by the 8K_PUL
and 2K_PUL bits respectively. When they are pulsed, the pulse width is
defined by the period of OUT1; and they are pulsed on the position of
the falling or rising edge of the standard 50:50 duty cycle, as selected by
the 2K_8K_PUL_POSITION bit.
When the frame sync input signal is enabled to synchronize the
frame sync output signal, it should be adjusted to align itself with the T0
Table 26: Synchronization Control
AUTO_EXT_SYNC_EN EXT_SYNC_EN
don’t-care
0
1
0
1
1
Synchronization
Disabled
Enabled
Enabled if the T0 selected input clock is IN5; otherwise, disabled.
T0 selected
input clock
T0 selected
input clock
EX_SYNC1
EX_SYNC1
Frame sync
output signals
Frame sync
output signals
Output clocks
Output clocks
Figure 10. 0.5 UI Early Frame Sync Input Signal Timing
Figure 9. On Target Frame Sync Input Signal Timing
Functional Description
39
December 9, 2008
IDT82V3285
WAN PLL
T0 selected
input clock
T0 selected
input clock
EX_SYNC1
EX_SYNC1
Frame sync
output signals
Frame sync
output signals
Output clocks
Output clocks
Figure 12. 1 UI Late Frame Sync Input Signal Timing
Figure 11. 0.5 UI Late Frame Sync Input Signal Timing
Table 27: Related Bit / Register in Chapter 3.13
Bit
Register
Address (Hex)
DIFFERENTIAL_IN_OUT_OSCI_CNFG
0A
OUT1_FREQ_CNFG ~ OUT5_FREQ_CNFG
6D ~ 71
INPUT_MODE_CNFG
09
FR_MFR_SYNC_CNFG
74
EX_SYNC_ALARM_MON
SYNC_MONITOR_CNFG
SYNC_PHASE_CNFG
OPERATING_STS
7C
7D
52
EX_SYNC_ALARM 1
INTERRUPTS3_STS
0F
EX_SYNC_ALARM 2
INTERRUPTS3_ENABLE_CNFG
12
OUT4_PECL_LVDS
OUT5_PECL_LVDS
OUTn_PATH_SEL[3:0] (1 ≤ n ≤ 5)
OUTn_DIVIDER[3:0] (1 ≤ n ≤ 5)
IN_SONET_SDH
AUTO_EXT_SYNC_EN
EXT_SYNC_EN
8K_EN
2K_EN
8K_INV
2K_INV
8K_PUL
2K_PUL
2K_8K_PUL_POSITION
SYNC_MON_LIMT[2:0]
SYNC_PH1[1:0]
Functional Description
40
December 9, 2008
IDT82V3285
3.14
WAN PLL
MASTER / SLAVE CONFIGURATION
In this application, all the output clocks derived from the T0 selected
input clock and the frame sync output signals from the two devices are
at the same frequency offset and phase. Refer to Chapter 3.13.2 Frame
SYNC Output Signals for details.
Master / Slave configuration is only supported by the T0 path of the
device.
Two devices should be used together in order to:
• Enable system protection against single chip failure;
• Guarantee no service interrupt during system maintenance, such
as software or hardware upgrade.
The difference between the Master and the Slave is: in the Master,
the IN5 should not be selected by the T0 DPLL; in the Slave, the following functions are automatically forced:
• The T0 selected input clock is IN5;
• T0 PBO is disabled;
• T0 DPLL operates at the acquisition bandwidth and damping factor;
• EX_SYNC1 is used for synchronization;
• T0 DPLL operates in Locked mode.
Of the two devices, one is configured as the Master and the other is
configured as the Slave. The configuration is made by the MS/SL pin
and the MS_SL_CTRL bit (b0, 13H), as shown in Table 28:
Table 28: Device Master / Slave Control
Master / Slave Control
MS/SL pin
MS_SL_CTRL Bit
0
1
0
1
High
Low
In the Slave, the corresponding registers of the above forced functions can still be configured, but their configuration does not take any
effect. The frequency of the T0 selected input clock IN5 is recommended
to be 6.48 MHz.
Result
Master
Slave
Slave
Master
Backplane connections
Hardware
control
EX_SYNC1
MS/SL
IN1
IN2
IN3
IN4
OUT1
.
.
.
Chip A
one output
clock
OUT5
one output
FRSYNC_8K/ frame sync
MFRSYNC_2K signal
IN5
EX_SYNC1
MS/SL
IN1
IN2
IN3
IN4
IN5
OUT1 one output
.
clock
.
Chip B
.
OUT5
one output
FRSYNC_8K/ frame sync
MFRSYNC_2K signal
Backplane
Backplane
Figure 13. Physical Connection Between Two Devices
Functional Description
41
December 9, 2008
IDT82V3285
3.15
WAN PLL
INTERRUPT SUMMARY
3.16
The interrupt sources of the device are as follows:
• T4 DPLL locking status change
• Input clocks for T0 path validity change
• T0 selected input clock fail
• No qualified input clock for T4 path is available
• T0 DPLL operating mode switch
• External sync alarm
The main features supported by the T0 path are as follows:
• Phase lock alarm;
• Forced or Automatic input clock selection/switch;
• 3 primary and 3 secondary, temporary DPLL operating modes,
switched automatically or under external control;
• Automatic switch between starting, acquisition and locked bandwidths/damping factors;
• Programmable DPLL bandwidths from 0.5 mHz to 560 Hz in 19
steps;
• Programmable damping factors: 1.2, 2.5, 5, 10 and 20;
• Fast loss, coarse phase loss, fine phase loss and hard limit
exceeding monitoring;
• Output phase and frequency offset limited;
• Automatic Instantaneous, Automatic Slow Averaged, Automatic
Fast Averaged or Manual holdover frequency offset acquiring;
• PBO to minimize output phase transients;
• Programmable output phase offset;
• Low jitter multiple clock outputs with programmable polarity;
• Low jitter 2 kHz and 8 kHz frame sync signal outputs with programmable pulse width and polarity;
• Master / Slave application to enable system protection against
single device failure.
All of the above interrupt events are indicated by the corresponding
interrupt status bit. If the corresponding interrupt enable bit is set, any of
the interrupts can be reported by the INT_REQ pin. The output characteristics on the INT_REQ pin are determined by the HZ_EN bit and the
INT_POL bit.
Interrupt events are cleared by writing a ‘1’ to the corresponding
interrupt status bit. The INT_REQ pin will be inactive only when all the
pending enabled interrupts are cleared.
In addition, the interrupt of T0 selected input clock fail can be
reported by the TDO pin, as determined by the LOS_FLAG_TO_TDO
bit.
Table 29: Related Bit / Register in Chapter 3.15
Bit
HZ_EN
INT_POL
LOS_FLAG_TO_TDO
Functional Description
Register
Address (Hex)
INTERRUPT_CNFG
0C
MON_SW_PBO_CNFG
0B
T0 AND T4 SUMMARY
The main features supported by the T4 path are as follows:
• Forced or Automatic input clock selection/switch;
• Locking to T0 DPLL output;
• 3 DPLL operating modes, switched automatically or under external control;
• Programmable DPLL bandwidth: 18 Hz, 35 Hz, 70 Hz and 560
Hz;
• Programmable damping factor: 1.2, 2.5, 5, 10 and 20;
• Fast loss, coarse phase loss, fine phase loss and hard limit
exceeding monitoring;
• Output phase and frequency offset limited;
• Automatic Instantaneous holdover frequency offset;
• Low jitter multiple clock outputs with programmable polarity.
42
December 9, 2008
IDT82V3285
3.17
WAN PLL
POWER SUPPLY FILTERING TECHNIQUES
3.3V
IDT82V3285
SLF7028T-100M1R1
VDDA
0.1 µF
10 µF
0.1 µF
0.1 µF
0.1 µF
6, 19, 91
0.1 µF
1, 5, 20, 92
11, 14, 15, 29, 62, 84, 87
33, 39
32, 38
VDD_DIFF
AGND
DGND
GND_DIFF
3.3V
SLF7028T-100M1R1
10 µF
VDDD
0.1 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
12, 13, 16, 26, 50, 61, 85, 86
0.1 µF
Figure 14. IDT82V3285 Power Decoupling Scheme
The analog power supply VDDA and VDD_DIFF should have low
impedance. This can be achieved by using one 10 uF (1210 case size,
ceramic) and at least four 0.1 uF (0402 case size, ceramic) capacitors in
parallel. The 0.1 uF (0402 case size, ceramic) capacitors must be
placed right next to the VDDA and VDD_DIFF pins as close as possible.
Note that the 10 uF capacitor must be of 1210 case size, and it must be
ceramic for lowest ESR (Effective Series Resistance) possible. The 0.1
uF should be of case size 0402, this offers the lowest ESL (Effective
Series Inductance) to achieve low impedance towards the high speed
range.
To achieve optimum jitter performance, power supply filtering is
required to minimize supply noise modulation of the output clocks. The
common sources of power supply noise are switch power supplies and
the high switching noise from the outputs to the internal PLL. The
IDT82V3285 provides separate VDDA power pins for the internal analog
PLL, VDD_DIFF for the differential output driver circuit and VDDD pins
for the core logic as well as I/O driver circuits.
To minimize switching power supply noise generated by the switching regulator, the power supply output should be filtering with sufficient
bulk capacity to minimize ripple and 0.1 uF (0402 case size, ceramic)
caps to filter out the switching transients.
For VDDD, at least ten 0.1 uF (0402 case size, ceramic) and one 10
uF (1210 case size, ceramic) capacitors are recommended. The 0.1 uF
capacitors should be placed as close to the VDDD pins as possible.
For the IDT82V3285, the decoupling for VDDA, VDD_DIFF and
VDDD are handled individually. VDDD, VDD_DIFF and VDDA should be
individually connected to the power supply plane through vias, and
bypass capacitors should be used for each pin. Figure 14 illustrated how
bypass capacitor and ferrite bead should be connected to power pins.
Functional Description
Please refer to evaluation board schematic for details.
43
December 9, 2008
IDT82V3285
4
WAN PLL
TYPICAL APPLICATION
The device supports Master / Slave application, as shown in
Figure 15:
PRS
(Primary Reference Source)
BITS/SSU
Timing Module
Stratum 2/3E
IDT82V3288
BITS/SSU
Timing Module
Stratum 2/3E
IDT82V3288
Typical 8 kHz/1.544 MHz/2.048 MHz
Line Timing
Typical 19.44
MHz and other
OC-N clock
Stratum
2/3E/3/SMC/SEC
Module
IDT82V3285
Master/Slave
Stratum
2/3E/3/SMC/SEC
Module
IDT82V3285
Central Clock
Modules
Line Timing
Typical 19.44
MHz and other
OC-N clock
Typical 19.44 MHz
and other OC-N clock
Typical 19.44 MHz
and other OC-N clock
SDH/SONET
or other Equipment
Timing System
155.52 Mbit/s
Line Card
IDT82V3255
...
622.08 Mbit/s
Line Card
IDT82V3255
2.5 Gbit/s
Line Card
IDT82V3255
...
10 Gbit/s
Line Card
IDT82V3255
Figure 15. Typical Application
4.1
MASTER / SLAVE APPLICATION
In Master / Slave application, two devices should be used together.
Of the two devices, one is configured as the Master and the other is configured as the Slave. Refer to Chapter 3.14 Master / Slave Configuration
for details.
Master / Slave application is only supported by the T0 path of the
device.
Typical Application
44
December 9, 2008
IDT82V3285
5
WAN PLL
MICROPROCESSOR INTERFACE
The microprocessor interface provides access to read and write the
registers in the device. The microprocessor interface supports the following five modes:
• EPROM mode;
• Multiplexed mode;
• Intel mode;
• Motorola mode;
• Serial mode.
The microprocessor interface mode is selected by the
MPU_SEL_CNFG[2:0] bits (b2~0, 7FH). The interface pins in different
interface modes are listed in Table 30:
Table 30: Microprocessor Interface
MPU_SEL_CNFG[2:0] bits
Microprocessor Interface Mode
Interface Pins
001
ERPOM
CS, A[6:0], AD[7:0]
010
Multiplexed
CS, ALE, WR, RD, AD[7:0], RDY
011
Intel
CS, WR, RD, A[6:0], AD[7:0], RDY
100
Motorola
CS, WR, A[6:0], AD[7:0], RDY
101
Serial
CS, SCLK, SDI, SDO, CLKE
Microprocessor Interface
45
December 9, 2008
IDT82V3285
5.1
WAN PLL
EPROM MODE
In this mode, the device is used with an EPROM. The configuration
data will be automatically read from the EPROM after the device is powered on.
CS
A[6:0]
address
tacc
AD[7:0]
data
High-Z
High-Z
Figure 16. EPROM Access Timing Diagram
Table 31: Access Timing Characteristics in EPROM Mode
Symbol
Parameter
tacc
CS to valid data delay time
Microprocessor Interface
Min
46
Typ
Max
Unit
920
ns
December 9, 2008
IDT82V3285
5.2
WAN PLL
MULTIPLEXED MODE
tT
tpw3
ALE
tsu1
th1
CS
tsu2
WR
tpw1
th2
RD
td1
AD[7:0]
RDY
td4
data
address
High-Z
td2
tpw2
th3
td5
High-Z
td6
Figure 17. Multiplexed Read Timing Diagram
Table 32: Read Timing Characteristics in Multiplexed Mode
Symbol
Parameter
Min
Typ
Max
Unit
T
One cycle time of the master clock
12.86
ns
tin
Delay of input pad
5
ns
tout
Delay of output pad
5
ns
tsu1
Valid address to ALE falling edge setup time
2
tsu2
ns
Valid CS to Valid RD setup time
0
td1
Valid RD to valid data delay time
td2
Valid CS to valid RDY delay time
13
ns
td4
RD rising edge to AD[7:0] high impedance delay time
10
ns
td5
RD rising edge to RDY low delay time
13
ns
td6
CS rising edge to RDY release delay time
13
ns
tpw1
Valid RD pulse width low
4.5T + 10 *
ns
tpw2
Valid RDY pulse width low
4.5T + 10
ns
tpw3
Valid ALE pulse width high
2
ns
th1
Valid address after ALE falling edge hold time
3
ns
th2
Valid CS after RD rising edge hold time
0
ns
th3
ns
3.5T + 10
ns
Valid RD after RDY rising edge hold time
0
ns
tT
Time between ALE falling edge and RD falling edge
0
ns
tTI
Time between consecutive Read-Read or Read-Write accesses
(RD rising edge to ALE rising edge)
>T
ns
Note:
* Timing with RDY. If RDY is not used, tpw1 is 3.5T + 10.
Microprocessor Interface
47
December 9, 2008
IDT82V3285
WAN PLL
tpw3
tT
ALE
th1
tsu1
CS
RD
th2
tpw1
tsu2
WR
th4
tsu3
AD[7:0]
data
address
td2
RDY
tpw2
th3
td5
High-Z
High-Z
td6
Figure 18. Multiplexed Write Timing Diagram
Table 33: Write Timing Characteristics in Multiplexed Mode
Symbol
Parameter
Min
Typ
Max
Unit
T
One cycle time of the master clock
12.86
ns
tin
Delay of input pad
5
ns
tout
Delay of output pad
5
ns
tsu1
Valid address to ALE falling edge setup time
2
ns
tsu2
Valid CS to valid WR setup time
0
ns
tsu3
Valid data to WR rising edge setup time
3
td2
Valid CS to valid RDY delay time
13
ns
td5
WR rising edge to RDY low delay time
13
ns
td6
CS rising edge to RDY release delay time
13
ns
tpw1
Valid WR pulse width low
1.5T + 10
ns
tpw2
Valid RDY pulse width low
1.5T + 10
ns
tpw3
Valid ALE pulse width high
2
ns
th1
Valid address after ALE falling edge hold time
3
ns
th2
Valid CS after WR rising edge hold time
0
ns
th3
Valid WR after RDY rising edge hold time
0
ns
th4
ns
Valid data after WR rising edge hold time
9
ns
tT
Time between ALE falling edge and WR falling edge
0
ns
tTI
Time between consecutive Write-Read or Write-Write accesses
(WR rising edge to ALE rising edge)
>7T
ns
Microprocessor Interface
48
December 9, 2008
IDT82V3285
5.3
WAN PLL
INTEL MODE
CS
WR
tpw1
tsu2
th2
RD
th1
tsu1
A[6:0]
address
td4
td1
High-Z
td2
RDY
High-Z
data
AD[7:0]
tpw2
th3
td5
High-Z
High-Z
td6
Figure 19. Intel Read Timing Diagram
Table 34: Read Timing Characteristics in Intel Mode
Symbol
Parameter
Min
Typ
Max
Unit
T
One cycle time of the master clock
12.86
ns
tin
Delay of input pad
5
ns
tout
Delay of output pad
5
ns
tsu1
Valid address to valid CS setup time
0
ns
tsu2
Valid CS to valid RD setup time
0
ns
td1
Valid RD to valid data delay time
3.5T + 10
ns
td2
Valid CS to valid RDY delay time
13
ns
td4
RD rising edge to AD[7:0] high impedance delay time
10
ns
td5
RD rising edge to RDY low delay time
13
ns
td6
CS rising edge to RDY release delay time
13
ns
tpw1
Valid RD pulse width low
4.5T + 10 *
ns
tpw2
Valid RDY pulse width low
4.5T + 10
ns
th1
Valid address after RD rising edge hold time
0
ns
th2
Valid CS after RD rising edge hold time
0
ns
th3
Valid RD after RDY rising edge hold time
0
ns
tTI
Time between consecutive Read-Read or Read-Write accesses
(RD rising edge to RD falling edge, or RD rising edge to WR falling edge)
>T
ns
Note:
* Timing with RDY. If RDY is not used, tpw1 is 3.5T + 10.
Microprocessor Interface
49
December 9, 2008
IDT82V3285
WAN PLL
CS
tsu2
tpw1
th2
WR
RD
tsu1
th1
A[6:0]
address
tsu3
AD[7:0]
data
td2
RDY
th4
tpw2
th3
td5
High-Z
High-Z
td6
Figure 20. Intel Write Timing Diagram
Table 35: Write Timing Characteristics in Intel Mode
Symbol
Parameter
Min
Typ
Max
Unit
T
One cycle time of the master clock
12.86
ns
tin
Delay of input pad
5
ns
tout
Delay of output pad
5
ns
tsu1
Valid address to valid CS setup time
0
ns
tsu2
Valid CS to valid WR setup time
0
ns
tsu3
Valid data before WR rising edge setup time
3
ns
td2
Valid CS to valid RDY delay time
13
ns
td5
WR rising edge to RDY low delay time
13
ns
td6
CS rising edge to RDY release delay time
13
ns
tpw1
Valid WR pulse width low
1.5T + 10
ns
tpw2
Valid RDY pulse width low
1.5T + 10
ns
th1
Valid address after WR rising edge hold time
0
ns
th2
Valid CS after WR rising edge hold time
0
ns
th3
Valid WR after RDY rising edge hold time
0
ns
th4
Valid data after WR rising edge hold time
9
ns
tTI
Time between consecutive Write-Read or Write-Write accesses
(WR rising edge to WR falling edge, or WR rising edge to RD falling edge)
>7T
ns
Microprocessor Interface
50
December 9, 2008
IDT82V3285
5.4
WAN PLL
MOTOROLA MODE
tpw1
CS
th2
tsu2
WR
th1
tsu1
address
A[6:0]
td3
td1
AD[7:0]
High-Z
data
td2
RDY
tpw2
th3
High-Z
tr1
td4
High-Z
High-Z
Figure 21. Motorola Read Timing Diagram
Table 36: Read Timing Characteristics in Motorola Mode
Symbol
Parameter
Min
Typ
T
One cycle time of the master clock
12.86
tin
Delay of input pad
5
Max
Unit
ns
tout
Delay of output pad
tsu1
Valid address to valid CS setup time
0
ns
tsu2
Valid WR to valid CS setup time
0
ns
td1
Valid CS to valid data delay time
td2
Valid CS to valid RDY delay time
13
ns
td3
CS rising edge to AD[7:0] high impedance delay time
10
ns
td4
CS rising edge to RDY release delay time
13
ns
tpw1
Valid CS pulse width low
4.5T + 10 *
ns
tpw2
Valid RDY pulse width high
4.5T + 10
ns
th1
Valid address after CS rising edge hold time
0
ns
th2
Valid WR after CS rising edge hold time
0
ns
th3
Valid CS after RDY falling edge hold time
0
tr1
RDY release time
tTI
Time between consecutive Read-Read or Read-Write accesses
(CS rising edge to CS falling edge)
5
ns
3.5T + 10
ns
3
>T
ns
ns
ns
Note:
* Timing with RDY. If RDY is not used, tpw1 is 3.5T +10.
Microprocessor Interface
51
December 9, 2008
IDT82V3285
WAN PLL
tpw1
CS
th2
tsu2
WR
tsu1
th1
A[6:0]
address
th4
tsu3
AD[7:0]
data
td2
RDY
th3
tpw2
tr1
td4
High-Z
High-Z
Figure 22. Motorola Write Timing Diagram
Table 37: Write Timing Characteristics in Motorola Mode
Symbol
Parameter
T
One cycle time of the master clock
Min
Typ
12.86
Max
Unit
ns
tin
Delay of input pad
5
ns
tout
Delay of output pad
5
ns
tsu1
Valid address to valid CS setup time
0
ns
tsu2
Valid WR to valid CS setup time
0
ns
tsu3
Valid data before CS rising edge setup time
3
ns
td2
Valid CS to valid RDY delay time
13
ns
td4
CS rising edge to RDY release delay time
13
ns
tpw1
Valid CS pulse width low
1.5T + 10
ns
tpw2
Valid RDY pulse width high
1.5T + 10
ns
th1
Valid address after valid CS rising edge hold time
0
ns
th2
Valid WR after valid CS rising edge hold time
0
ns
th3
Valid CS after RDY falling edge hold time
0
ns
th4
Valid data after valid CS rising edge hold time
9
tr1
RDY release time
tTI
Time between consecutive Write-Write or Write-Read accesses
(CS rising edge to CS falling edge)
Microprocessor Interface
ns
3
52
> 7T
ns
ns
December 9, 2008
IDT82V3285
5.5
WAN PLL
SERIAL MODE
ing edge of SCLK. When CLKE is asserted high, data on SDO will be
clocked out on the falling edge of SCLK.
In a read operation, the active edge of SCLK is selected by CLKE.
When CLKE is asserted low, data on SDO will be clocked out on the ris-
In a write operation, data on SDI will be clocked in on the rising edge
of SCLK.
CS
SCLK
tsu1
th1
tpw1
R/W
SDI
th2
tpw2
tsu2
A0
A1
A2
A3
A4
A5
A6
td1
High-Z
SDO
td2
D0
D1
D2
D3
D4
D5
D6
D7
Figure 23. Serial Read Timing Diagram (CLKE Asserted Low)
CS
th2
SCLK
SDI
R/W
A0
A1
A2
A3
A4
A5
A6
td1
High-Z
td2
D0
SDO
D1
D2
D3
D4
D5
D6
D7
Figure 24. Serial Read Timing Diagram (CLKE Asserted High)
Table 38: Read Timing Characteristics in Serial Mode
Symbol
Parameter
Min
Typ
Max
Unit
T
One cycle time of the master clock
12.86
ns
tin
Delay of input pad
5
ns
tout
Delay of output pad
5
ns
tsu1
Valid SDI to valid SCLK setup time
4
tsu2
Valid CS to valid SCLK setup time
14
td1
Valid SCLK to valid data delay time
10
ns
td2
CS rising edge to SDO high impedance delay time
10
ns
tpw1
SCLK pulse width low
3.5T + 5
ns
tpw2
SCLK pulse width high
3.5T + 5
ns
th1
Valid SDI after valid SCLK hold time
6
ns
th2
Valid CS after valid SCLK hold time (CLKE = 0/1)
5
ns
tTI
Time between consecutive Read-Read or Read-Write accesses
(CS rising edge to CS falling edge)
10
ns
Microprocessor Interface
53
ns
ns
December 9, 2008
IDT82V3285
WAN PLL
CS
tsu2
SCLK
th1
tpw1
tsu1
SDI
th2
tpw2
R/W
A0
A1
A2
A3
A4
A5
A6
D0
D1
D2
D3
D4
D5
D6
D7
High-Z
SDO
Figure 25. Serial Write Timing Diagram
Table 39: Write Timing Characteristics in Serial Mode
Symbol
Parameter
Min
Typ
Max
Unit
T
One cycle time of the master clock
12.86
ns
tin
Delay of input pad
5
ns
tout
Delay of output pad
5
ns
tsu1
Valid SDI to valid SCLK setup time
4
ns
tsu2
Valid CS to valid SCLK setup time
14
ns
tpw1
SCLK pulse width low
3.5T
ns
tpw2
SCLK pulse width high
3.5T
ns
th1
Valid SDI after valid SCLK hold time
6
ns
th2
Valid CS after valid SCLK hold time
5
ns
tTI
Time between consecutive Write-Write or Write-Read accesses
(CS rising edge to CS falling edge)
10
ns
Microprocessor Interface
54
December 9, 2008
IDT82V3285
6
WAN PLL
JTAG
This device is compliant with the IEEE 1149.1 Boundary Scan standard except the following:
• The output boundary scan cells do not capture data from the
core and the device does not support EXTEST instruction;
• The TRST pin is set low by default and JTAG is disabled in order
to be consistent with other manufacturers.
The JTAG interface timing diagram is shown in Figure 26.
tTCK
TCK
tS
tH
TMS
TDI
tD
TDO
Figure 26. JTAG Interface Timing Diagram
Table 40: JTAG Timing Characteristics
Symbol
JTAG
Parameter
Min
tTCK
Typ
Max
TCK period
100
ns
tS
TMS / TDI to TCK setup time
25
ns
tH
TCK to TMS / TDI Hold Time
25
ns
tD
TCK to TDO delay time
50
55
Unit
ns
December 9, 2008
IDT82V3285
7
WAN PLL
PROGRAMMING INFORMATION
The access of the Multi-word Registers is different from that of the
Single-word Registers. Take the registers (04H, 05H and 06H) for an
example, the write operation for the Multi-word Registers follows a fixed
sequence. The register (04H) is configured first and the register (06H) is
configured last. The three registers are configured continuously and
should not be interrupted by any operation. The crystal calibration configuration will take effect after all the three registers are configured. During read operation, the register (04H) is read first and the register (06H)
is read last. The crystal calibration reading should be continuous and not
be interrupted by any operation.
After reset, all the registers are set to their default values. The registers are read or written via the microprocessor interface.
Before any write operation, the value in register
PROTECTION_CNFG is recommended to be confirmed to make sure
whether the write operation is enabled. The device provides 3 register
protection modes:
• Protected mode: no other registers can be written except register
PROTECTION_CNFG itself;
• Fully Unprotected mode: all the writable registers can be written;
• Single Unprotected mode: one more register can be written
besides register PROTECTION_CNFG. After write operation
(not including writing a ‘1’ to clear a bit to ‘0’), the device automatically switches to Protected mode.
Certain bit locations within the device register map are designated as
Reserved. To ensure proper and predictable operation, bits designated
as Reserved should not be written by the users. In addition, their value
should be masked out from any testing or error detection methods that
are implemented.
Writing ‘0’ to the registers will take no effect if the registers are
cleared by writing ‘1’.
7.1
T0 and T4 paths share some registers, whose addresses are 27H,
28H, 2BH, 4EH, 4FH, 5AH, 5BH, 62H ~ 64H, 68H and 69H. The names
of shared registers are marked with a *. Before register read/write operation, register T4_T0_REG_SEL_CNFG is recommended to be confirmed to make sure whether the register operation is available for T0 or
T4 path.
REGISTER MAP
Table 41 is the map of all the registers, sorted in an ascending order
of their addresses.
Table 41: Register List and Map
Address
(Hex)
Register Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reference
Page
Global Control Registers
00
01
02
04
05
06
07
08
09
0A
ID[7:0] - Device ID 1
ID[15:8] - Device ID 2
MPU_PIN_STS - MPU_MODE[2:0]
Pins Status
NOMINAL_FREQ[7:0]_CNFG - Crystal Oscillator Frequency Offset Calibration Configuration 1
NOMINAL_FREQ[15:8]_CNFG - Crystal Oscillator Frequency Offset Calibration Configuration 2
NOMINAL_FREQ[23:16]_CNFG
Crystal Oscillator Frequency Offset
Calibration Configuration 3
T4_T0_REG_SEL_CNFG - T0 / T4
Registers Selection Configuration
PHASE_ALARM_TIME_OUT_CNFG Phase Lock Alarm Time-Out Configuration
ID[7:0]
ID[15:8]
-
-
-
-
-
-
-
MPU_PIN_STS[2:0]
P 62
NOMINAL_FREQ_VALUE[7:0]
P 62
NOMINAL_FREQ_VALUE[15:8]
P 62
NOMINAL_FREQ_VALUE[23:16]
P 63
-
T4_T0_SE
L
MULTI_FACTOR[1:0]
-
-
-
-
TIME_OUT_VALUE[5:0]
AUTO_EX
PH_ALAR
INPUT_MODE_CNFG - Input Mode
EXT_SYN
T_SYNC_
M_TIMEO
Configuration
C_EN
EN
UT
DIFFERENTIAL_IN_OUT_OSCI_CNF
G - Differential Input / Output Port &
Master Clock Configuration
Programming Information
P 61
P 62
56
SYNC_FREQ[1:0]
-
-
P 63
P 64
IN_SONET MASTER_ REVERTIV
_SDH
SLAVE
E_MODE
P 65
OSC_EDG OUT5_PE OUT4_PE
E
CL_LVDS CL_LVDS
P 66
December 9, 2008
IDT82V3285
WAN PLL
Table 41: Register List and Map (Continued)
Address
(Hex)
0B
13
7E
7F
0C
0D
0E
0F
10
11
12
16
17
18
19
1A
1F
23
24
25
27
Register Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MON_SW_PBO_CNFG - Frequency
LOS_FLA
FREQ_MO
FREQ_MO
ULTR_FAS
PBO_FRE
Monitor, Input Clock Selection & PBO
G_TO_TD
EXT_SW
PBO_EN
N_HARD_
N_CLK
T_SW
Z
Control
O
EN
MS_SL_CTRL_CNFG - Master Slave
MS_SL_C
Control
TRL
PROTECTION_CNFG - Register ProPROTECTION_DATA[7:0]
tection Mode Configuration
MPU_SEL_CNFG - Microprocessor
MPU_SEL_CNFG[2:0]
Interface Mode Configuration
Interrupt Registers
INTERRUPT_CNFG - Interrupt ConfigHZ_EN
INT_POL
uration
INTERRUPTS1_STS - Interrupt Status
IN[4:1]
1
T0_OPER T0_MAIN_
INTERRUPTS2_STS - Interrupt Status
IN5
ATING_MO REF_FAIL
2
DE
ED
INTERRUPTS3_STS - Interrupt Status EX_SYNC
INPUT_TO
T4_STS
3
_ALARM
_T4
INTERRUPTS1_ENABLE_CNFG
IN[4:1]
Interrupt Control 1
T0_OPER T0_MAIN_
INTERRUPTS2_ENABLE_CNFG
ATING_MO REF_FAIL
IN5
Interrupt Control 2
DE
ED
INTERRUPTS3_ENABLE_CNFG
- EX_SYNC
INPUT_TO
T4_STS
Interrupt Control 3
_ALARM
_T4
Input Clock Frequency & Priority Configuration Registers
IN1_CNFG - Input Clock 1 Configura- DIRECT_D
LOCK_8K
BUCKET_SEL[1:0]
IN_FREQ[3:0]
tion
IV
IN2_CNFG - Input Clock 2 Configura- DIRECT_D
LOCK_8K
BUCKET_SEL[1:0]
IN_FREQ[3:0]
tion
IV
IN3_IN4_HF_DIV_CNFG - Input Clock
3 & 4 High Frequency Divider ConfiguIN4_DIV[1:0]
IN3_DIV[1:0]
ration
IN3_CNFG - Input Clock 3 Configura- DIRECT_D
LOCK_8K
BUCKET_SEL[1:0]
IN_FREQ[3:0]
tion
IV
IN4_CNFG - Input Clock 4 Configura- DIRECT_D
LOCK_8K
BUCKET_SEL[1:0]
IN_FREQ[3:0]
tion
IV
IN5_CNFG - Input Clock 5 Configura- DIRECT_D
LOCK_8K
BUCKET_SEL[1:0]
IN_FREQ[3:0]
tion
IV
PRE_DIV_CH_CNFG - DivN Divider
PRE_DIV_CH_VALUE[3:0]
Channel Selection
PRE_DIVN[7:0]_CNFG - DivN Divider
PRE_DIVN_VALUE[7:0]
Division Factor Configuration 1
PRE_DIVN[14:8]_CNFG
DivN
PRE_DIVN_VALUE[14:8]
Divider Division Factor Configuration 2
IN1_IN2_SEL_PRIORITY_CNFG
Input Clock 1 & 2 Priority Configuration
IN2_SEL_PRIORITY[3:0]
IN1_SEL_PRIORITY[3:0]
*
Programming Information
57
Reference
Page
P 67
P 68
P 68
P 69
P 70
P 70
P 71
P 72
P 72
P 73
P 73
P 74
P 75
P 76
P 77
P 78
P 79
P 80
P 80
P 81
P 82
December 9, 2008
IDT82V3285
WAN PLL
Table 41: Register List and Map (Continued)
Address
(Hex)
28
2B
2E
2F
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
40
Register Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
IN3_IN4_SEL_PRIORITY_CNFG
Input Clock 3 & 4 Priority Configuration
IN4_SEL_PRIORITY[3:0]
IN3_SEL_PRIORITY[3:0]
*
IN5_SEL_PRIORITY_CNFG - Input
IN5_SEL_PRIORITY[3:0]
Clock 5 Priority Configuration *
Input Clock Quality Monitoring Configuration & Status Registers
FREQ_MON_FACTOR_CNFG - FacFREQ_MON_FACTOR[3:0]
tor of Frequency Monitor Configuration
ALL_FREQ_MON_THRESHOLD_CN
FG - Frequency Monitor Threshold for
ALL_FREQ_HARD_THRESHOLD[3:0]
All Input Clocks Configuration
UPPER_THRESHOLD_0_CNFG
Upper Threshold for Leaky Bucket
UPPER_THRESHOLD_0_DATA[7:0]
Configuration 0
LOWER_THRESHOLD_0_CNFG
Lower Threshold for Leaky Bucket
LOWER_THRESHOLD_0_DATA[7:0]
Configuration 0
BUCKET_SIZE_0_CNFG - Bucket
BUCKET_SIZE_0_DATA[7:0]
Size for Leaky Bucket Configuration 0
DECAY_RATE_0_CNFG - Decay Rate
DECAY_RATE_0_DATA
for Leaky Bucket Configuration 0
[1:0]
UPPER_THRESHOLD_1_CNFG
Upper Threshold for Leaky Bucket
UPPER_THRESHOLD_1_DATA[7:0]
Configuration 1
LOWER_THRESHOLD_1_CNFG
Lower Threshold for Leaky Bucket
LOWER_THRESHOLD_1_DATA[7:0]
Configuration 1
BUCKET_SIZE_1_CNFG - Bucket
BUCKET_SIZE_1_DATA[7:0]
Size for Leaky Bucket Configuration 1
DECAY_RATE_1_CNFG - Decay Rate
DECAY_RATE_1_DATA
for Leaky Bucket Configuration 1
[1:0]
UPPER_THRESHOLD_2_CNFG
Upper Threshold for Leaky Bucket
UPPER_THRESHOLD_2_DATA[7:0]
Configuration 2
LOWER_THRESHOLD_2_CNFG
Lower Threshold for Leaky Bucket
LOWER_THRESHOLD_2_DATA[7:0]
Configuration 2
BUCKET_SIZE_2_CNFG - Bucket
BUCKET_SIZE_2_DATA[7:0]
Size for Leaky Bucket Configuration 2
DECAY_RATE_2_CNFG - Decay Rate
DECAY_RATE_2_DATA
for Leaky Bucket Configuration 2
[1:0]
UPPER_THRESHOLD_3_CNFG
Upper Threshold for Leaky Bucket
UPPER_THRESHOLD_3_DATA[7:0]
Configuration 3
LOWER_THRESHOLD_3_CNFG
Lower Threshold for Leaky Bucket
LOWER_THRESHOLD_3_DATA[7:0]
Configuration 3
BUCKET_SIZE_3_CNFG - Bucket
BUCKET_SIZE_3_DATA[7:0]
Size for Leaky Bucket Configuration 3
DECAY_RATE_3_CNFG - Decay Rate
DECAY_RATE_3_DATA
for Leaky Bucket Configuration 3
[1:0]
Programming Information
58
Reference
Page
P 83
P 84
P 85
P 85
P 86
P 86
P 86
P 87
P 87
P 87
P 88
P 88
P 88
P 89
P 89
P 89
P 90
P 90
P 90
P 91
December 9, 2008
IDT82V3285
WAN PLL
Table 41: Register List and Map (Continued)
Address
(Hex)
41
42
Register Name
IN_FREQ_READ_CH_CNFG - Input
Clock Frequency Read Channel
Selection
IN_FREQ_READ_STS - Input Clock
Frequency Read Value
Bit 7
Bit 6
Bit 5
Bit 4
-
-
-
-
IN1_IN2_STS - Input Clock 1 & 2 Status
-
45
IN3_IN4_STS - Input Clock 3 & 4 Status
-
48
IN5_STS - Input Clock 5 Status
-
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
Bit 2
Bit 1
Bit 0
IN_FREQ_READ_CH[3:0]
IN2_FREQ
_HARD_A
LARM
IN4_FREQ
_HARD_A
LARM
IN2_NO_A
CTIVITY_A
LARM
IN4_NO_A
CTIVITY_A
LARM
IN2_PH_L
OCK_ALA
RM
IN4_PH_L
OCK_ALA
RM
-
-
-
-
-
-
P 92
IN1_FREQ
_HARD_A
LARM
IN3_FREQ
_HARD_A
LARM
IN5_FREQ
_HARD_A
LARM
IN1_NO_A
CTIVITY_A
LARM
IN3_NO_A
CTIVITY_A
LARM
IN5_NO_A
CTIVITY_A
LARM
IN1_PH_L
OCK_ALA
RM
IN3_PH_L
OCK_ALA
RM
IN5_PH_L
OCK_ALA
RM
T0 / T4 DPLL Input Clock Selection Registers
INPUT_VALID1_STS - Input Clocks
IN[4:1]
Validity 1
INPUT_VALID2_STS - Input Clocks
IN5
Validity 2
REMOTE_INPUT_VALID1_CNFG -D
IN4_VALID IN3_VALID IN2_VALID IN1_VALID
Input Clocks Validity Configuration 1
REMOTE_INPUT_VALID2_CNFG IN5_VALID
Input Clocks Validity Configuration 2
PRIORITY_TABLE1_STS - Priority
HIGHEST_PRIORITY_VALIDATED[3:0]
CURRENTLY_SELECTED_INPUT[3:0]
Status 1 *
PRIORITY_TABLE2_STS - Priority
SECOND_HIGHEST_PRIORITY_VALIDATED[3:0
THIRD_HIGHEST_PRIORITY_VALIDATED[3:0]
Status 2 *
]
T0_INPUT_SEL_CNFG - T0 Selected
T0_INPUT_SEL[3:0]
Input Clock Configuration
T4_LOCK_ T0_FOR_T T4_TEST_
T4_INPUT_SEL_CNFG - T4 Selected
T4_INPUT_SEL[3:0]
T0
4
T0_PH
Input Clock Configuration
T0 / T4 DPLL State Machine Control Registers
EX_SYNC
T0_DPLL_ T4_DPLL_
OPERATING_STS - DPLL Operating
T4_DPLL_
T0_DPLL_
_ALARM_
SOFT_FRE SOFT_FRE
T0_DPLL_OPERATING_MODE[2:0]
Status
LOCK
LOCK
MON
Q_ALARM Q_ALRAM
T0_OPERATING_MODE_CNFG - T0
T0_OPERATING_MODE[2:0]
DPLL Operating Mode Configuration
T4_OPERATING_MODE_CNFG - T4
T4_OPERATING_MODE[2:0]
DPLL Operating Mode Configuration
T0 / T4 DPLL & APLL Configuration Registers
T0_DPLL_APLL_PATH_CNFG - T0
T0_GSM_OBSAI_16E1 T0_12E1_24T1_E3_T3
T0_APLL_PATH[3:0]
DPLL & APLL Path Configuration
_16T1_SEL[1:0]
_SEL[1:0]
T0_DPLL_START_BW_DAMPING_C
NFG - T0 DPLL Start Bandwidth & T0_DPLL_START_DAMPING[2:0]
T0_DPLL_START_BW[4:0]
Damping Factor Configuration
T0_DPLL_ACQ_BW_DAMPING_CNF
G - T0 DPLL Acquisition Bandwidth & T0_DPLL_ACQ_DAMPING[2:0]
T0_DPLL_ACQ_BW[4:0]
Damping Factor Configuration
Programming Information
59
Reference
Page
P 91
IN_FREQ_VALUE[7:0]
44
4A
Bit 3
P 93
P 94
P 95
P 96
P 96
P 96
P 97
P 97
P 98
P 99
P 100
P 101
P 102
P 102
P 103
P 104
P 105
December 9, 2008
IDT82V3285
WAN PLL
Table 41: Register List and Map (Continued)
Address
(Hex)
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
Register Name
T0_DPLL_LOCKED_BW_DAMPING_
CNFG - T0 DPLL Locked Bandwidth &
Damping Factor Configuration
T0_BW_OVERSHOOT_CNFG - T0
DPLL Bandwidth Overshoot Configuration
PHASE_LOSS_COARSE_LIMIT_CNF
G - Phase Loss Coarse Detector Limit
Configuration *
PHASE_LOSS_FINE_LIMIT_CNFG Phase Loss Fine Detector Limit Configuration *
T0_HOLDOVER_MODE_CNFG - T0
DPLL Holdover Mode Configuration
T0_HOLDOVER_FREQ[7:0]_CNFG T0 DPLL Holdover Frequency Configuration 1
T0_HOLDOVER_FREQ[15:8]_CNFG
- T0 DPLL Holdover Frequency Configuration 2
T0_HOLDOVER_FREQ[23:16]_CNFG
- T0 DPLL Holdover Frequency Configuration 3
T4_DPLL_APLL_PATH_CNFG - T4
DPLL & APLL Path Configuration
T4_DPLL_LOCKED_BW_DAMPING_
CNFG - T4 DPLL Locked Bandwidth &
Damping Factor Configuration
CURRENT_DPLL_FREQ[7:0]_STS DPLL Current Frequency Status 1 *
CURRENT_DPLL_FREQ[15:8]_STS DPLL Current Frequency Status 2 *
CURRENT_DPLL_FREQ[23:16]_STS
- DPLL Current Frequency Status 3 *
DPLL_FREQ_SOFT_LIMIT_CNFG DPLL Soft Limit Configuration
DPLL_FREQ_HARD_LIMIT[7:0]_CNF
G - DPLL Hard Limit Configuration 1
DPLL_FREQ_HARD_LIMIT[15:8]_CN
FG - DPLL Hard Limit Configuration 2
CURRENT_DPLL_PHASE[7:0]_STS DPLL Current Phase Status 1 *
CURRENT_DPLL_PHASE[15:8]_STS
- DPLL Current Phase Status 2 *
T0_T4_APLL_BW_CNFG - T0 / T4
APLL Bandwidth Configuration
Bit 7
Bit 6
Bit 5
Bit 4
T0_DPLL_LOCKED_DAMPING[2:0]
AUTO_BW
_SEL
-
-
Bit 3
Bit 2
Bit 1
Bit 0
T0_DPLL_LOCKED_BW[4:0]
-
T0_LIMT
-
-
P 106
-
COARSE_
MULTI_PH
MULTI_PH
PH_LOS_L WIDE_EN
_8K_4K_2
PH_LOS_COARSE_LIMT[3:0]
_APP
IMT_EN
K_EN
FINE_PH_
FAST_LOS
LOS_LIMT
PH_LOS_FINE_LIMT[2:0]
_SW
_EN
MAN_HOL AUTO_AV
READ_AV TEMP_HOLDOVER_M
FAST_AVG
DOVER
G
G
ODE[1:0]
P 108
P 109
P 110
P 110
T0_HOLDOVER_FREQ[15:8]
P 111
T0_HOLDOVER_FREQ[23:16]
P 111
T4_DPLL_LOCKED_DAMPING[2:0]
-
T4_GSM_GPS_16E1_1 T4_12E1_24T1_E3_T3
6T1_SEL[1:0]
_SEL[1:0]
P 112
T4_DPLL_LOCKED_B
W[1:0]
P 113
-
-
CURRENT_DPLL_FREQ[7:0]
P 113
CURRENT_DPLL_FREQ[15:8]
P 113
CURRENT_DPLL_FREQ[23:16]
P 114
FREQ_LIM
T_PH_LOS
DPLL_FREQ_SOFT_LIMT[6:0]
-
P 107
T0_HOLDOVER_FREQ[7:0]
T4_APLL_PATH[3:0]
-
Reference
Page
P 114
DPLL_FREQ_HARD_LIMT[7:0]
P 114
DPLL_FREQ_HARD_LIMT[15:8]
P 115
CURRENT_PH_DATA[7:0]
P 115
CURRENT_PH_DATA[15:8]
P 115
T0_APLL_BW[1:0]
-
-
T4_APLL_BW[1:0]
P 116
Output Configuration Registers
6D
OUT1_FREQ_CNFG - Output Clock 1
Frequency Configuration
Programming Information
OUT1_PATH_SEL[3:0]
60
OUT1_DIVIDER[3:0]
P 117
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IDT82V3285
WAN PLL
Table 41: Register List and Map (Continued)
Address
(Hex)
Register Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Reference
Page
Bit 0
OUT2_FREQ_CNFG - Output Clock 2
OUT2_PATH_SEL[3:0]
OUT2_DIVIDER[3:0]
Frequency Configuration
OUT3_FREQ_CNFG - Output Clock 3
OUT3_PATH_SEL[3:0]
OUT3_DIVIDER[3:0]
Frequency Configuration
OUT4_FREQ_CNFG - Output Clock 4
OUT4_PATH_SEL[3:0]
OUT4_DIVIDER[3:0]
Frequency Configuration
OUT5_FREQ_CNFG - Output Clock 5
OUT5_PATH_SEL[3:0]
OUT5_DIVIDER[3:0]
Frequency Configuration
OUTPUT_INV2 - Output Clock 4 & 5
OUT5_INV OUT4_INV
Invert Configuration
OUTPUT_INV1 - Output Clock 1 ~ 3
OUT3_INV OUT2_INV OUT1_INV
Invert Configuration
FR_MFR_SYNC_CNFG - Frame Sync
2K_8K_PU
IN_2K_4K_
& Multiframe Sync Output Configura8K_EN
2K_EN
L_POSITI 8K_INV
8K_PUL
2K_INV
2K_PUL
8K_INV
tion
ON
PBO & Phase Offset Control Registers
PHASE_MON_PBO_CNFG - Phase
IN_NOISE
PH_MON_ PH_MON_
Transient Monitor & PBO ConfiguraPH_TR_MON_LIMT[3:0]
_WINDOW
EN
PBO_EN
tion
PHASE_OFFSET[7:0]_CNFG - Phase
PH_OFFSET[7:0]
Offset Configuration 1
PHASE_OFFSET[9:8]_CNFG - Phase PH_OFFS
PH_OFFSET[9:8]
Offset Configuration 2
ET_EN
Synchronization Configuration Registers
SYNC_MONITOR_CNFG - Sync MonSYNC_MON_LIMT[2:0]
itor Configuration
SYNC_PHASE_CNFG - Sync Phase
SYNC_PH1[1:0]
Configuration
6E
6F
70
71
72
73
74
78
7A
7B
7C
7D
7.2
REGISTER DESCRIPTION
7.2.1
GLOBAL CONTROL REGISTERS
P 118
P 119
P 120
P 121
P 121
P 122
P 123
P 124
P 124
P 125
P 126
P 126
ID[7:0] - Device ID 1
Address: 00H
Type: Read
Default Value: 10001000
7
6
5
4
3
2
1
0
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
Bit
Name
7-0
ID[7:0]
Programming Information
Description
Refer to the description of the ID[15:8] bits (b7~0, 01H).
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ID[15:8] - Device ID 2
Address: 01H
Type: Read
Default Value: 00010001
7
6
5
4
3
2
1
0
ID15
ID14
ID13
ID12
ID11
ID10
ID9
ID8
Bit
Name
Description
7-0
ID[15:8]
The value in the ID[15:0] bits are pre-set, representing the identification number for the IDT82V3285.
MPU_PIN_STS - MPU_MODE[2:0] Pins Status
Address: 02H
Type: Read
Default Value: XXXXXXXX
7
6
5
4
3
2
1
0
-
-
-
-
-
MPU_PIN_STS2
MPU_PIN_STS1
MPU_PIN_STS0
Bit
Name
7-3
-
Description
Reserved.
These bits indicate the value of the MPU_MODE[2:0] pins.
MPU_PIN_STS[2:0]
The default value of these bits is determined by the MPU_MODE[2:0] pins during reset.
2-0
NOMINAL_FREQ[7:0]_CNFG - Crystal Oscillator Frequency Offset Calibration Configuration 1
Address: 04H
Type: Read / Write
Default Value: 00000000
7
6
5
4
3
2
1
0
NOMINAL_FRE
Q_VALUE7
NOMINAL_FRE
Q_VALUE6
NOMINAL_FRE
Q_VALUE5
NOMINAL_FRE
Q_VALUE4
NOMINAL_FRE
Q_VALUE3
NOMINAL_FRE
Q_VALUE2
NOMINAL_FRE
Q_VALUE1
NOMINAL_FRE
Q_VALUE0
Bit
7-0
Name
Description
NOMINAL_FREQ_VALUE[7:0] Refer to the description of the NOMINAL_FREQ_VALUE[23:16] bits (b7~0, 06H).
NOMINAL_FREQ[15:8]_CNFG - Crystal Oscillator Frequency Offset Calibration Configuration 2
Address: 05H
Type: Read / Write
Default Value: 00000000
7
6
5
4
3
2
1
0
NOMINAL_FRE
Q_VALUE15
NOMINAL_FRE
Q_VALUE14
NOMINAL_FRE
Q_VALUE13
NOMINAL_FRE
Q_VALUE12
NOMINAL_FRE
Q_VALUE11
NOMINAL_FRE
Q_VALUE10
NOMINAL_FRE
Q_VALUE9
NOMINAL_FRE
Q_VALUE8
Bit
7-0
Name
Description
NOMINAL_FREQ_VALUE[15:8] Refer to the description of the NOMINAL_FREQ_VALUE[23:16] bits (b7~0, 06H).
Programming Information
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NOMINAL_FREQ[23:16]_CNFG - Crystal Oscillator Frequency Offset Calibration Configuration 3
Address: 06H
Type: Read / Write
Default Value: 00000000
7
6
5
4
3
2
1
0
NOMINAL_FRE
Q_VALUE23
NOMINAL_FRE
Q_VALUE22
NOMINAL_FRE
Q_VALUE21
NOMINAL_FRE
Q_VALUE20
NOMINAL_FRE
Q_VALUE19
NOMINAL_FRE
Q_VALUE18
NOMINAL_FRE
Q_VALUE17
NOMINAL_FRE
Q_VALUE16
Bit
7-0
Name
Description
The NOMINAL_FREQ_VALUE[23:0] bits represent a 2’s complement signed integer. If the value is multiplied by
0.0000884, the calibration value for the master clock in ppm will be gotten.
For example, the frequency offset on OSCI is +3 ppm. Though -3 ppm should be compensated, the calibration value is
NOMINAL_FREQ_VALUE[23:16] calculated as +3 ppm:
3 ÷ 0.0000884 = 33937 (Dec.) = 8490 (Hex);
So ‘008490’ should be written into these bits.
The calibration range is within ±741 ppm.
T4_T0_REG_SEL_CNFG - T0 / T4 Registers Selection Configuration
Address: 07H
Type: Read / Write
Default Value: XXX0XXXX
7
6
5
4
3
2
1
0
-
-
-
T4_T0_SEL
-
-
-
-
Bit
Name
Description
7-5
-
4
T4_T0_SEL
3-0
-
Reserved.
A part of the registers are shared by T0 and T4 paths. These registers are addressed 27H, 28H, 2BH, 4EH, 4FH, 5AH, 5BH, 62H
~ 64H, 68H and 69H. This bit determines whether the register configuration is available for T0 or T4 path.
0: T0 path (default).
1: T4 path.
Reserved.
Programming Information
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PHASE_ALARM_TIME_OUT_CNFG - Phase Lock Alarm Time-Out Configuration
Address: 08H
Type: Read / Write
Default Value: 00110010
7
6
5
4
3
2
1
0
MULTI_FACTO
R1
MULTI_FACTO
R0
TIME_OUT_VA
LUE5
TIME_OUT_VA
LUE4
TIME_OUT_VA
LUE3
TIME_OUT_VA
LUE2
TIME_OUT_VA
LUE1
TIME_OUT_VAL
UE0
Bit
7-6
5-0
Name
Description
These bits determine a factor which has a relationship with a period in seconds. A phase lock alarm will be raised if the T0
selected input clock is not locked in T0 DPLL within this period. If the PH_ALARM_TIMEOUT bit (b5, 09H) is ‘1’, the
phase lock alarm will be cleared after this period (starting from when the alarm is raised). Refer to the description of the
TIME_OUT_VALUE[5:0] bits (b5~0, 08H).
MULTI_FACTOR[1:0]
00: 2 (default)
01: 4
10: 8
11: 16
These bits represent an unsigned integer. If the value in these bits is multiplied by the value in the MULTI_FACTOR[1:0]
bits (b7~6, 08H), a period in seconds will be gotten.
TIME_OUT_VALUE[5:0] A phase lock alarm will be raised if the T0 selected input clock is not locked in T0 DPLL within this period. If the
PH_ALARM_TIMEOUT bit (b5, 09H) is ‘1’, the phase lock alarm will be cleared after this period (starting from when the
alarm is raised).
Programming Information
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INPUT_MODE_CNFG - Input Mode Configuration
Address: 09H
Type: Read / Write
Default Value: 10100XX0
7
6
5
4
3
2
1
0
AUTO_EXT_SY
NC_EN
EXT_SYNC_EN
PH_ALARM_TI
MEOUT
SYNC_FREQ1
SYNC_FREQ0
IN_SONET_SD
H
MASTER_SLAV
E
REVERTIVE_M
ODE
Bit
7
6
5
4-3
2
1
0
Name
Description
AUTO_EXT_SYNC_EN Refer to the description of the EXT_SYNC_EN bit (b6, 09H).
This bit, together with the AUTO_EXT_SYNC_EN bit (b7, 09H), determines whether EX_SYNC1 is enabled to synchronize
the frame sync output signals.
EXT_SYNC_EN
AUTO_EXT_SYNC_EN
EXT_SYNC_EN
Synchronization
don’t-care
0
1
0
1
1
Disabled (default)
Enabled
Enabled if the T0 selected input clock is IN5; otherwise, disabled.
This bit determines how to clear the phase lock alarm.
0: The phase lock alarm will be cleared when a ‘1’ is written to the corresponding INn_PH_LOCK_ALARM bit (b4/0, 44H &
PH_ALARM_TIMEOUT 45H & 48H).
1: The phase lock alarm will be cleared after a period (= TIME_OUT_VALUE[5:0] (b5~0, 08H) X MULTI_FACTOR[1:0]
(b7~6, 08H) in seconds) which starts from when the alarm is raised. (default)
These bits set the frequency of the frame sync signal input on the EX_SYNC1 pin.
00: 8 kHz (default)
SYNC_FREQ[1:0] 01: 8 kHz.
10: 4 kHz.
11: 2 kHz.
This bit selects the SDH or SONET network type.
0: SDH. The DPLL required clock is 2.048 MHz when the IN_FREQ[3:0] bits (b3~0, 16H & 17H & 19H) are ‘0001’; the T0/T4
DPLL output from the 16E1/16T1 path is 16E1.
IN_SONET_SDH
1: SONET. The DPLL required clock is 1.544 MHz when the IN_FREQ[3:0] bits (b3~0, 16H & 17H & 19H) are ‘0001’; the T0/
T4 DPLL output from the 16E1/16T1 path is 16T1.
The default value of this bit is determined by the SONET/SDH pin during reset.
This bit is read only. It indicates the value of the MS/SL pin.
MASTER_SLAVE
Its default value is determined by the MS/SL pin during reset.
This bit selects Revertive or Non-Revertive switch for T0 path.
REVERTIVE_MODE 0: Non-Revertive switch. (default)
1: Revertive switch.
Programming Information
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IDT82V3285
WAN PLL
DIFFERENTIAL_IN_OUT_OSCI_CNFG - Differential Input / Output Port & Master Clock Configuration
Address: 0AH
Type: Read / Write
Default Value: XXXXX001
7
6
5
4
3
2
1
0
-
-
-
-
-
OSC_EDGE
OUT5_PECL_LVDS
OUT4_PECL_LVDS
Bit
Name
7-3
-
2
1
0
Description
Reserved.
This bit selects a better active edge of the master clock.
OSC_EDGE
0: The rising edge. (default)
1: The falling edge.
This bit selects a port technology for OUT5.
OUT5_PECL_LVDS 0: LVDS. (default)
1: PECL.
This bit selects a port technology for OUT4.
OUT4_PECL_LVDS 0: LVDS.
1: PECL. (default)
Programming Information
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IDT82V3285
WAN PLL
MON_SW_PBO_CNFG - Frequency Monitor, Input Clock Selection & PBO Control
Address: 0BH
Type: Read / Write
Default Value: 100X01X1
7
6
5
4
3
2
1
0
FREQ_MON_C
LK
LOS_FLAG_TO
_TDO
ULTR_FAST_SW
EXT_SW
PBO_FREZ
PBO_EN
-
FREQ_MON_H
ARD_EN
Bit
7
6
5
4
3
2
1
0
Name
Description
The bit selects a reference clock for input clock frequency monitoring.
0: The output of T0 DPLL.
1: The master clock. (default)
The bit determines whether the interrupt of T0 selected input clock fail - is reported by the TDO pin.
0: Not reported. TDO pin is used as JTAG test data output which complies with IEEE 1149.1. (default)
LOS_FLAG_TO_TDO
1: Reported. TDO pin mimics the state of the T0_MAIN_REF_FAILED bit (b6, 0EH) and does not strictly comply with IEEE
1149.1.
This bit determines whether the T0 selected input clock is valid when missing 2 consecutive clock cycles or more.
ULTR_FAST_SW
0: Valid. (default)
1: Invalid.
This bit determines the T0 input clock selection.
0: Forced selection or Automatic selection, as controlled by the T0_INPUT_SEL[3:0] bits (b3~0, 50H).
EXT_SW
1: External Fast selection.
The default value of this bit is determined by the FF_SRCSW pin during reset.
This bit is valid only when the PBO is enabled by the PBO_EN bit (b2, 0BH). It determines whether PBO is frozen at the current phase offset when a PBO event is triggered.
PBO_FREZ
0: Not frozen. (default)
1: Frozen. Further PBO events are ignored and the current phase offset is maintained.
This bit determines whether PBO is enabled when the T0 selected input clock switch or the T0 DPLL exiting from Holdover
mode or Free-Run mode occurs.
PBO_EN
0: Disabled.
1: Enabled. (default)
Reserved.
This bit determines whether the frequency hard alarm is enabled when the frequency of the input clock with respect to the
reference clock is above the frequency hard alarm threshold. The reference clock can be the output of T0 DPLL or the masFREQ_MON_HARD_EN ter clock, as determined by the FREQ_MON_CLK bit (b7, 0BH).
0: Disabled.
1: Enabled. (default)
FREQ_MON_CLK
Programming Information
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WAN PLL
MS_SL_CTRL_CNFG - Master Slave Control
Address: 13H
Type: Read / Write
Default Value: XXXXXXX0
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
MS_SL_CTRL
Bit
Name
7-1
-
Description
Reserved.
This bit, together with the MS/SL pin, controls whether the device is configured as the Master or as the Slave.
Master/Slave Control
MS/SL pin
0
MS_SL_CTRL
Result
MS_SL_CTRL Bit
0
1
0
1
High
Low
Master
Slave
Slave
Master
The default value of this bit is ‘0’.
PROTECTION_CNFG - Register Protection Mode Configuration
Address: 7EH
Type: Read / Write
Default Value: 10000101
7
6
5
4
3
2
1
0
PROTECTION_
DATA7
PROTECTION_
DATA6
PROTECTION_
DATA5
PROTECTION_
DATA4
PROTECTION_
DATA3
PROTECTION_
DATA2
PROTECTION_
DATA1
PROTECTION_
DATA0
Bit
7-0
Name
Description
These bits select a register write protection mode.
00000000 - 10000100, 10000111 - 11111111: Protected mode. No other registers can be written except this register.
PROTECTION_DATA[7:0] 10000101: Fully Unprotected mode. All the writable registers can be written. (default)
10000110: Single Unprotected mode. One more register can be written besides this register. After write operation (not
including writing a ‘1’ to clear the bit to ‘0’), the device automatically switches to Protected mode.
Programming Information
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MPU_SEL_CNFG - Microprocessor Interface Mode Configuration
Address: 7FH
Type: Read / Write
Default Value: XXXXXXXX
7
6
5
4
3
2
1
0
-
-
-
-
-
MPU_SEL_CNFG2
MPU_SEL_CNFG1
MPU_SEL_CNFG0
Bit
Name
7-3
-
2-0
Description
Reserved.
These bits select a microprocessor interface mode:
000: Reserved.
001: ERPOM mode.
010: Multiplexed mode.
MPU_SEL_CNFG[2:0] 011: Intel mode.
100: Motorola mode.
101: Serial mode.
110, 111: Reserved.
The default value of these bits are determined by the MPU_MODE[2:0] pins during reset.
Programming Information
69
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IDT82V3285
7.2.2
WAN PLL
INTERRUPT REGISTERS
INTERRUPT_CNFG - Interrupt Configuration
Address: 0CH
Type: Read / Write
Default Value: XXXXXX10
7
6
5
4
3
2
1
0
-
-
-
-
-
-
HZ_EN
INT_POL
Bit
Name
Description
7-2
-
1
HZ_EN
0
INT_POL
Reserved.
This bit determines the output characteristics of the INT_REQ pin.
0: The output on the INT_REQ pin is high/low when the interrupt is active; the output is the opposite when the interrupt is inactive.
1: The output on the INT_REQ pin is high/low when the interrupt is active; the output is in high impedance state when the interrupt
is inactive. (default)
This bit determines the active level on the INT_REQ pin for an active interrupt indication.
0: Active low. (default)
1: Active high.
INTERRUPTS1_STS - Interrupt Status 1
Address: 0DH
Type: Read / Write
Default Value: 11111111
7
6
5
4
3
2
1
0
-
-
IN4
IN3
IN2
IN1
-
-
Bit
Name
Description
7-6
-
5-2
INn
1-0
-
Reserved.
This bit indicates the validity changes (from ‘valid’ to ‘invalid’ or from ‘invalid’ to ‘valid’) for the corresponding INn; i.e., whether
there is a transition (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on the corresponding INn bit (b5~2, 4AH). Here n is any one of 4 to 1.
0: Has not changed.
1: Has changed. (default)
This bit is cleared by writing a ‘1’.
Reserved.
Programming Information
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WAN PLL
INTERRUPTS2_STS - Interrupt Status 2
Address: 0EH
Type: Read / Write
Default Value: 00111111
7
6
5
4
3
2
1
0
T0_OPERATING
_MODE
T0_MAIN_REF_F
AILED
-
-
-
IN5
-
-
Bit
7
6
5-3
2
1-0
Name
Description
This bit indicates the operating mode switch for T0 DPLL; i.e., whether the value in the
T0_DPLL_OPERATING_MODE[2:0] bits (b2~0, 52H) changes.
T0_OPERATING_MODE 0: Has not switched. (default)
1: Has switched.
This bit is cleared by writing a ‘1’.
This bit indicates whether the T0 selected input clock has failed. The T0 selected input clock fails when its validity
changes from ‘valid’ to ‘invalid’; i.e., when there is a transition from ‘1’ to ‘0’ on the corresponding INn bit (4AH, 4BH).
T0_MAIN_REF_FAILED 0: Has not failed. (default)
1: Has failed.
This bit is cleared by writing a ‘1’.
Reserved.
This bit indicates the validity changes (from ‘valid’ to ‘invalid’ or from ‘invalid’ to ‘valid’) for IN5 for T0 path, i.e., whether
there is a transition (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on IN5 bit (b2, 4BH).
IN5
0: Has not changed.
1: Has changed. (default)
This bit is cleared by writing a ‘1’.
Reserved.
Programming Information
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IDT82V3285
WAN PLL
INTERRUPTS3_STS - Interrupt Status 3
Address: 0FH
Type: Read / Write
Default Value: 11X10000
7
6
5
4
3
2
1
0
EX_SYNC_ALARM
T4_STS
-
INPUT_TO_T4
-
-
-
-
Bit
Name
Description
This bit indicates whether an external sync alarm is raised; i.e., whether there is a transition from ‘0’ to ‘1’ on the
EX_SYNC_ALARM_MON bit (b7, 52H).
EX_SYNC_ALARM 0: Not raised.
1: Raised. (default)
This bit is cleared by writing a ‘1’.
This bit indicates the T4 DPLL locking status changes (from ‘locked’ to ‘unlocked’ or from ‘unlocked’ to ‘locked’); i.e., whether
there is a transition (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on the T4_DPLL_LOCK bit (b6, 52H).
T4_STS
0: Has not changed.
1: Has changed. (default)
This bit is cleared by writing a ‘1’.
Reserved.
This bit indicates whether all the input clocks for T4 path change to be unqualified; i.e., whether the
HIGHEST_PRIORITY_VALIDATED[3:0] bits (b7~4, 4EH) are set to ‘0000’ when these bits are available for T4 path.
INPUT_TO_T4 0: Has not changed.
1: Has changed. (default)
This bit is cleared by writing a ‘1’.
Reserved.
7
6
5
4
3-0
INTERRUPTS1_ENABLE_CNFG - Interrupt Control 1
Address: 10H
Type: Read / Write
Default Value: 00000000
7
6
5
4
3
2
1
0
-
-
IN4
IN3
IN2
IN1
-
-
Bit
Name
Description
7-6
-
5-2
INn
0 -1
-
Reserved.
This bit controls whether the interrupt is enabled to be reported on the INT_REQ pin when the input clock validity changes (from
‘valid’ to ‘invalid’ or from ‘invalid’ to ‘valid’), i.e., when the corresponding INn bit (b5~2, 0DH) is ‘1’. Here n is any one of 4 to 1.
0: Disabled. (default)
1: Enabled.
Reserved
Programming Information
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WAN PLL
INTERRUPTS2_ENABLE_CNFG - Interrupt Control 2
Address: 11H
Type: Read / Write
Default Value: 00000000
7
6
5
4
3
2
1
0
T0_OPERATING
_MODE
T0_MAIN_REF_F
AILED
-
-
-
IN5
-
-
Bit
Name
Description
This bit controls whether the interrupt is enabled to be reported on the INT_REQ pin when the T0 DPLL operating mode
switches, i.e., when the T0_OPERATING_MODE bit (b7, 0EH) is ‘1’.
T0_OPERATING_MODE
0: Disabled. (default)
1: Enabled.
This bit controls whether the interrupt is enabled to be reported on the INT_REQ pin when the T0 selected input clock
has failed; i.e., when the T0_MAIN_REF_FAILED bit (b6, 0EH) is ‘1’.
T0_MAIN_REF_FAILED
0: Disabled. (default)
1: Enabled.
Reserved.
This bit controls whether the interrupt is enabled to be reported on the INT_REQ pin when the input clock validity
changes (from ‘valid’ to ‘invalid’ or from ‘invalid’ to ‘valid’), i.e., when IN5 bit (b2, 0EH) is ‘1’.
IN5
0: Disabled. (default)
1: Enabled.
Reserved.
7
6
5-3
2
1-0
INTERRUPTS3_ENABLE_CNFG - Interrupt Control 3
Address: 12H
Type: Read / Write
Default Value: 00X00000
7
6
5
4
3
2
1
0
EX_SYNC_ALARM
T4_STS
-
INPUT_TO_T4
-
-
-
-
Bit
7
6
5
4
3-0
Name
Description
This bit controls whether the interrupt is enabled to be reported on the INT_REQ pin when an external sync alarm has
occurred, i.e., when the EX_SYNC_ALARM bit (b7, 0FH) is ‘1’.
EX_SYNC_ALARM
0: Disabled. (default)
1: Enabled.
This bit controls whether the interrupt is enabled to be reported on the INT_REQ pin when the T4 DPLL locking status
changes (from ‘locked’ to ‘unlocked’ or from ‘unlocked’ to ‘locked’), i.e., when the T4_STS bit (b6, 0FH) is ‘1’.
T4_STS
0: Disabled. (default)
1: Enabled.
Reserved.
This bit controls whether the interrupt is enabled to be reported on the INT_REQ pin when all the input clocks for T4 path
become unqualified, i.e., when the INPUT_TO_T4 bit (b4, 0FH) is ‘1’.
INPUT_TO_T4
0: Disabled. (default)
1: Enabled.
Reserved.
Programming Information
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December 9, 2008
IDT82V3285
7.2.3
WAN PLL
INPUT CLOCK FREQUENCY & PRIORITY CONFIGURATION REGISTERS
IN1_CNFG - Input Clock 1 Configuration
Address: 16H
Type: Read / Write
Default Value: 00000000
7
6
5
4
3
2
1
0
DIRECT_DIV
LOCK_8K
BUCKET_SEL1
BUCKET_SEL0
IN_FREQ3
IN_FREQ2
IN_FREQ1
IN_FREQ0
Bit
Name
Description
7
DIRECT_DIV
Refer to the description of the LOCK_8K bit (b6, 16H).
This bit, together with the DIRECT_DIV bit (b7, 16H), determines whether the DivN Divider or the Lock 8k Divider is used for
IN1:
6
5-4
3-0
LOCK_8K
DIRECT_DIV bit
LOCK_8K bit
Used Divider
0
0
1
1
0
1
0
1
Both bypassed (default)
Lock 8k Divider
DivN Divider
Reserved
These bits select one of the four groups of leaky bucket configuration registers for IN1:
00: Group 0; the addresses of the configuration registers are 31H ~ 34H. (default)
BUCKET_SEL[1:0] 01: Group 1; the addresses of the configuration registers are 35H ~ 38H.
10: Group 2; the addresses of the configuration registers are 39H ~ 3CH.
11: Group 3; the addresses of the configuration registers are 3DH ~ 40H.
These bits set the DPLL required frequency for IN1:
0000: 8 kHz. (default)
0001: 1.544 MHz (when the IN_SONET_SDH bit (b2, 09H) is ‘1’) / 2.048 MHz (when the IN_SONET_SDH bit (b2, 09H) is ‘0’).
0010: 6.48 MHz.
0011: 19.44 MHz.
0100: 25.92 MHz.
IN_FREQ[3:0]
0101: 38.88 MHz.
0110 ~ 1000: Reserved.
1001: 2 kHz.
1010: 4 kHz.
1011 ~ 1111: Reserved.
For IN1, the required frequency should not be set higher than that of the input clock.
Programming Information
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December 9, 2008
IDT82V3285
WAN PLL
IN2_CNFG - Input Clock 2 Configuration
Address: 17H
Type: Read / Write
Default Value: 00000000
7
6
5
4
3
2
1
0
DIRECT_DIV
LOCK_8K
BUCKET_SEL1
BUCKET_SEL0
IN_FREQ3
IN_FREQ2
IN_FREQ1
IN_FREQ0
Bit
Name
Description
7
DIRECT_DIV
Refer to the description of the LOCK_8K bit (b6, 17H).
This bit, together with the DIRECT_DIV bit (b7, 17H), determines whether the DivN Divider or the Lock 8k Divider is used for
IN2:
6
5-4
3-0
LOCK_8K
DIRECT_DIV bit
LOCK_8K bit
Used Divider
0
0
1
1
0
1
0
1
Both bypassed (default)
Lock 8k Divider
DivN Divider
Reserved
These bits select one of the four groups of leaky bucket configuration registers for IN2:
00: Group 0; the addresses of the configuration registers are 31H ~ 34H. (default)
BUCKET_SEL[1:0] 01: Group 1; the addresses of the configuration registers are 35H ~ 38H.
10: Group 2; the addresses of the configuration registers are 39H ~ 3CH.
11: Group 3; the addresses of the configuration registers are 3DH ~ 40H.
These bits set the DPLL required frequency for IN2
0000: 8 kHz. (default)
0001: 1.544 MHz (when the IN_SONET_SDH bit (b2, 09H) is ‘1’) / 2.048 MHz (when the IN_SONET_SDH bit (b2, 09H) is ‘0’).
0010: 6.48 MHz.
0011: 19.44 MHz.
0100: 25.92 MHz.
IN_FREQ[3:0]
0101: 38.88 MHz.
0110 ~ 1000: Reserved.
1001: 2 kHz.
1010: 4 kHz.
1011 ~ 1111: Reserved.
For the IN2, the required frequency should not be set higher than that of the input clock.
Programming Information
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December 9, 2008
IDT82V3285
WAN PLL
IN3_IN4_HF_DIV_CNFG - Input Clock 3 & 4 High Frequency Divider Configuration
Address: 18H
Type: Read / Write
Default Value: 00XXXX00
7
6
5
4
3
2
1
0
IN4_DIV1
IN4_DIV0
-
-
-
-
IN3_DIV1
IN3_DIV0
Bit
Name
7-6
IN4_DIV[1:0]
5-2
-
1-0
IN3_DIV[1:0]
Programming Information
Description
These bits determine whether the HF Divider is used and what the division factor is for IN4 frequency division:
00: Bypassed. (default)
01: Divided by 4.
10: Divided by 5.
11: Reserved.
Reserved.
These bits determine whether the HF Divider is used and what the division factor is for IN3 frequency division:
00: Bypassed. (default)
01: Divided by 4.
10: Divided by 5.
11: Reserved.
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IDT82V3285
WAN PLL
IN3_CNFG - Input Clock 3 Configuration
Address: 19H
Type: Read / Write
Default Value: 00000011
7
6
5
4
3
2
1
0
DIRECT_DIV
LOCK_8K
BUCKET_SEL1
BUCKET_SEL0
IN_FREQ3
IN_FREQ2
IN_FREQ1
IN_FREQ0
Bit
Name
Description
7
DIRECT_DIV
Refer to the description of the LOCK_8K bit (b6, 19H).
This bit, together with the DIRECT_DIV bit (b7, 19H), determines whether the DivN Divider or the Lock 8k Divider is used for
IN3:
6
5-4
3-0
LOCK_8K
DIRECT_DIV bit
LOCK_8K bit
Used Divider
0
0
1
1
0
1
0
1
Both bypassed (default)
Lock 8k Divider
DivN Divider
Reserved
These bits select one of the four groups of leaky bucket configuration registers for IN3:
00: Group 0; the addresses of the configuration registers are 31H ~ 34H. (default)
BUCKET_SEL[1:0] 01: Group 1; the addresses of the configuration registers are 35H ~ 38H.
10: Group 2; the addresses of the configuration registers are 39H ~ 3CH.
11: Group 3; the addresses of the configuration registers are 3DH ~ 40H.
These bits set the DPLL required frequency for IN3:
0000: 8 kHz.
0001: 1.544 MHz (when the IN_SONET_SDH bit (b2, 09H) is ‘1’) / 2.048 MHz (when the IN_SONET_SDH bit (b2, 09H) is ‘0’).
0010: 6.48 MHz.
0011: 19.44 MHz. (default)
0100: 25.92 MHz.
IN_FREQ[3:0]
0101: 38.88 MHz.
0110 ~ 1000: Reserved.
1001: 2 kHz.
1010: 4 kHz.
1011 ~ 1111: Reserved.
The required frequency should not be set higher than that of the input clock.
Programming Information
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December 9, 2008
IDT82V3285
WAN PLL
IN4_CNFG - Input Clock 4 Configuration
Address: 1AH
Type: Read / Write
Default Value: 00000011
7
6
5
4
3
2
1
0
DIRECT_DIV
LOCK_8K
BUCKET_SEL1
BUCKET_SEL0
IN_FREQ3
IN_FREQ2
IN_FREQ1
IN_FREQ0
Bit
Name
Description
7
DIRECT_DIV
Refer to the description of the LOCK_8K bit (b6, 1AH).
This bit, together with the DIRECT_DIV bit (b7, 1AH), determines whether the DivN Divider or the Lock 8k Divider is used for
IN4:
6
5-4
3-0
LOCK_8K
DIRECT_DIV bit
LOCK_8K bit
Used Divider
0
0
1
1
0
1
0
1
Both bypassed (default)
Lock 8k Divider
DivN Divider
Reserved
These bits select one of the four groups of leaky bucket configuration registers for IN4
00: Group 0; the addresses of the configuration registers are 31H ~ 34H. (default)
BUCKET_SEL[1:0] 01: Group 1; the addresses of the configuration registers are 35H ~ 38H.
10: Group 2; the addresses of the configuration registers are 39H ~ 3CH.
11: Group 3; the addresses of the configuration registers are 3DH ~ 40H.
These bits set the DPLL required frequency for IN4:
0000: 8 kHz.
0001: 1.544 MHz (when the IN_SONET_SDH bit (b2, 09H) is ‘1’) / 2.048 MHz (when the IN_SONET_SDH bit (b2, 09H) is ‘0’).
0010: 6.48 MHz.
0011: 19.44 MHz. (default)
0100: 25.92 MHz.
IN_FREQ[3:0]
0101: 38.88 MHz.
0110 ~ 1000: Reserved.
1001: 2 kHz.
1010: 4 kHz.
1011 ~ 1111: Reserved.
For IN4, the required frequency should not be set higher than that of the input clock.
Programming Information
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December 9, 2008
IDT82V3285
WAN PLL
IN5_CNFG - Input Clock 5 Configuration
Address: 1FH
Type: Read / Write
Default Value: 0000XXXX
7
6
5
4
3
2
1
0
DIRECT_DIV
LOCK_8K
BUCKET_SEL1
BUCKET_SEL0
IN_FREQ3
IN_FREQ2
IN_FREQ1
IN_FREQ0
Bit
Name
Description
7
DIRECT_DIV
Refer to the description of the LOCK_8K bit (b6, 1FH).
This bit, together with the DIRECT_DIV bit (b7, 1FH), determines whether the DivN Divider or the Lock 8k Divider is used for
IN5:
6
5-4
3-0
LOCK_8K
DIRECT_DIV bit
LOCK_8K bit
Used Divider
0
0
1
1
0
1
0
1
Both bypassed (default)
Lock 8k Divider
DivN Divider
Reserved
These bits select one of the four groups of leaky bucket configuration registers for IN5:
00: Group 0; the addresses of the configuration registers are 31H ~ 34H. (default)
BUCKET_SEL[1:0] 01: Group 1; the addresses of the configuration registers are 35H ~ 38H.
10: Group 2; the addresses of the configuration registers are 39H ~ 3CH.
11: Group 3; the addresses of the configuration registers are 3DH ~ 40H.
These bits set the DPLL required frequency for IN5:
0000: 8 kHz.
0001: 1.544 MHz (when the IN_SONET_SDH bit (b2, 09H) is ‘1’) / 2.048 MHz (when the IN_SONET_SDH bit (b2, 09H) is ‘0’).
0010: 6.48 MHz.
0011: 19.44 MHz.
0100: 25.92 MHz.
0101: 38.88 MHz.
IN_FREQ[3:0] 0110 ~ 1000: Reserved.
1001: 2 kHz.
1010: 4 kHz.
1011 ~ 1111: Reserved.
For IN5, the required frequency should not be set higher than that of the input clock.
The default value of these bits depends on the device application as follows:
In Master / Slave application, when the device is configured as the Master, the default value is ‘0001’; when the device is configured as the Slave, the default value is ‘0010’.
Programming Information
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IDT82V3285
WAN PLL
PRE_DIV_CH_CNFG - DivN Divider Channel Selection
Address: 23H
Type: Read / Write
Default Value: XXXX0000
7
6
5
4
3
2
1
0
-
-
-
-
PRE_DIV_CH_VALUE3
PRE_DIV_CH_VALUE2
PRE_DIV_CH_VALUE1
PRE_DIV_CH_VALUE0
Bit
Name
7-4
-
Description
Reserved.
This register is an indirect address register for Register 24H and 25H.
These bits select an input clock. The value set in the PRE_DIVN_VALUE[14:0] bits (25H, 24H) is available for the
selected input clock.
0000: Reserved. (default)
0001, 0010: Reserved.
0011: IN1.
PRE_DIV_CH_VALUE[3:0]
0100: IN2.
0101: IN3
0110: IN4
0111, 1000, 1001, 1010: Reserved
1011: IN5
1100, 1101, 1110, 1111: Reserved.
3-0
PRE_DIVN[7:0]_CNFG - DivN Divider Division Factor Configuration 1
Address: 24H
Type: Read / Write
Default Value: 00000000
7
6
5
4
3
2
1
0
PRE_DIVN_VA
LUE7
PRE_DIVN_VA
LUE6
PRE_DIVN_VA
LUE5
PRE_DIVN_VA
LUE4
PRE_DIVN_VA
LUE3
PRE_DIVN_VA
LUE2
PRE_DIVN_VA
LUE1
PRE_DIVN_VA
LUE0
Bit
7-0
Name
Description
PRE_DIVN_VALUE[7:0] Refer to the description of the PRE_DIVN_VALUE[14:8] bits (b6~0, 25H).
Programming Information
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December 9, 2008
IDT82V3285
WAN PLL
PRE_DIVN[14:8]_CNFG - DivN Divider Division Factor Configuration 2
Address: 25H
Type: Read / Write
Default Value: X0000000
7
6
5
4
3
2
1
0
-
PRE_DIVN_VAL
UE14
PRE_DIVN_VAL
UE13
PRE_DIVN_VAL
UE12
PRE_DIVN_VAL
UE11
PRE_DIVN_VAL
UE10
PRE_DIVN_VAL
UE9
PRE_DIVN_VAL
UE8
Bit
Name
Description
7
-
6-0
PRE_DIVN_VALUE[14:8]
Reserved.
The division factor for an input clock is the value in the PRE_DIVN_VALUE[14:0] bits plus 1. The input clock is selected
by the PRE_DIV_CH_VALUE[3:0] bits (b3~0, 23H).
A value from ‘0’ to ‘4BEF’ (Hex) can be written into, corresponding to a division factor from 1 to 19440. The others are
reserved. So the DivN Divider only supports an input clock whose frequency is lower than (<) 155.52 MHz.
The division factor setting should observe the following order:
1. Write the lower eight bits of the division factor to the PRE_DIVN_VALUE[7:0] bits;
2. Write the higher eight bits of the division factor to the PRE_DIVN_VALUE[14:8] bits.
Programming Information
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December 9, 2008
IDT82V3285
WAN PLL
IN1_IN2_SEL_PRIORITY_CNFG - Input Clock 1 & 2 Priority Configuration *
Address: 27H
Type: Read / Write
Default Value: T0 - 01010100 / T4 - 00000000
7
6
5
4
3
2
1
0
IN2_SEL_PRIO
RITY3
IN2_SEL_PRIO
RITY2
IN2_SEL_PRIO
RITY1
IN2_SEL_PRIO
RITY0
IN1_SEL_PRIO
RITY3
IN1_SEL_PRIO
RITY2
IN1_SEL_PRIO
RITY1
IN1_SEL_PRIO
RITY0
Bit
Name
7-4
INn_SEL_PRIORITY[3:0]
3-0
INn_SEL_PRIORITY[3:0]
Programming Information
Description
These bits set the priority of the corresponding INn. Here n is 2.
0000: Disable INn for automatic selection. (T4 default)
0001: Priority 1.
0010: Priority 2.
0011: Priority 3.
0100: Priority 4.
0101: Priority 5. (T0 default)
0110: Priority 6.
0111: Priority 7.
1000: Priority 8.
1001: Priority 9.
1010: Priority 10.
1011: Priority 11.
1100: Priority 12.
1101: Priority 13.
1110: Priority 14.
1111: Priority 15.
These bits set the priority of the corresponding INn. Here n is 1.
0000: Disable INn for automatic selection. (T4 default)
0001: Priority 1.
0010: Priority 2.
0011: Priority 3.
0100: Priority 4. (T0 default)
0101: Priority 5.
0110: Priority 6.
0111: Priority 7.
1000: Priority 8.
1001: Priority 9.
1010: Priority 10.
1011: Priority 11.
1100: Priority 12.
1101: Priority 13.
1110: Priority 14.
1111: Priority 15.
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December 9, 2008
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WAN PLL
IN3_IN4_SEL_PRIORITY_CNFG - Input Clock 3 & 4 Priority Configuration *
Address: 28H
Type: Read / Write
Default Value: T0/T4 - 01110110
7
6
5
4
3
2
1
0
IN4_SEL_PRIO
RITY3
IN4_SEL_PRIO
RITY2
IN4_SEL_PRIO
RITY1
IN4_SEL_PRIO
RITY0
IN3_SEL_PRIO
RITY3
IN3_SEL_PRIO
RITY2
IN3_SEL_PRIO
RITY1
IN3_SEL_PRIO
RITY0
Bit
Name
7-4
INn_SEL_PRIORITY[3:0]
3-0
INn_SEL_PRIORITY[3:0]
Programming Information
Description
These bits set the priority of the corresponding INn. Here n is 4.
0000: Disable INn for automatic selection.
0001: Priority 1.
0010: Priority 2.
0011: Priority 3.
0100: Priority 4.
0101: Priority 5.
0110: Priority 6.
0111: Priority 7. (default)
1000: Priority 8.
1001: Priority 9.
1010: Priority 10.
1011: Priority 11.
1100: Priority 12.
1101: Priority 13.
1110: Priority 14.
1111: Priority 15.
These bits set the priority of the corresponding INn. Here n is 3.
0000: Disable INn for automatic selection.
0001: Priority 1.
0010: Priority 2.
0011: Priority 3.
0100: Priority 4.
0101: Priority 5.
0110: Priority 6. (default)
0111: Priority 7.
1000: Priority 8.
1001: Priority 9.
1010: Priority 10.
1011: Priority 11.
1100: Priority 12.
1101: Priority 13.
1110: Priority 14.
1111: Priority 15.
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December 9, 2008
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WAN PLL
IN5_SEL_PRIORITY_CNFG - Input Clock 5 Priority Configuration *
Address: 2BH
Type: Read / Write
Default Value: 11011100 (T0 Master)/11010001 (T0 Slave) 00000000 (T4)
7
6
5
4
3
2
1
0
-
-
-
-
IN5_SEL_PRIO
RITY3
IN5_SEL_PRIO
RITY2
IN5_SEL_PRIO
RITY1
IN5_SEL_PRIO
RITY0
Bit
Name
7-4
-
3-0
Description
Reserved
These bits set the priority of the corresponding INn. Here n is 5:
0000: Disable INn for automatic selection. (T4 default)
0001: Priority 1. (T0 Slave default)
0010: Priority 2.
0011: Priority 3.
0100: Priority 4.
0101: Priority 5.
0110: Priority 6.
INn_SEL_PRIORITY[3:0] 0111: Priority 7.
1000: Priority 8.
1001: Priority 9.
1010: Priority 10.
1011: Priority 11.
1100: Priority 12. (T0 Master default)
1101: Priority 13.
1110: Priority 14.
1111: Priority 15.
Programming Information
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December 9, 2008
IDT82V3285
7.2.4
WAN PLL
INPUT CLOCK QUALITY MONITORING CONFIGURATION & STATUS REGISTERS
FREQ_MON_FACTOR_CNFG - Factor of Frequency Monitor Configuration
Address: 2EH
Type: Read / Write
Default Value: XXXX1011
7
6
5
4
3
2
1
0
-
-
-
-
FREQ_MON_F
ACTOR3
FREQ_MON_F
ACTOR2
FREQ_MON_F
ACTOR1
FREQ_MON_F
ACTOR0
Bit
Name
7-4
-
3-0
Description
Reserved.
These bits determine a factor. The factor has a relationship with the frequency hard alarm threshold in ppm (refer to
the description of the ALL_FREQ_HARD_THRESHOLD[3:0] bits (b3~0, 2FH)) and with the frequency of the input
clock with respect to the master clock in ppm (refer to the description of the IN_FREQ_VALUE[7:0] bits (b7~0, 42H)).
The factor represents the accuracy of the frequency monitor and should be set according to the requirements of different applications.
0000: 0.0032.
0001: 0.0064.
0010: 0.0127.
0011: 0.0257.
FREQ_MON_FACTOR[3:0]
0100: 0.0514.
0101: 0.103.
0110: 0.206.
0111: 0.412.
1000: 0.823.
1001: 1.646.
1010: 3.292.
1011: 3.81. (default)
1100 - 1111: 4.6.
ALL_FREQ_MON_THRESHOLD_CNFG - Frequency Monitor Threshold for All Input Clocks Configuration
Address: 2FH
Type: Read / Write
Default Value: XXXX0011
7
6
5
4
3
2
1
0
-
-
-
-
ALL_FREQ_HARD_
THRESHOLD3
ALL_FREQ_HARD_
THRESHOLD2
ALL_FREQ_HARD_
THRESHOLD1
ALL_FREQ_HARD_
THRESHOLD0
Bit
Name
7-4
-
3-0
Description
Reserved.
These bits represent an unsigned integer. The frequency hard alarm threshold in ppm can be calculated as
follows:
ALL_FREQ_HARD_THRESHOLD[3:0] Frequency Hard Alarm Threshold (ppm) = (ALL_FREQ_HARD_THRESHOLD[3:0] + 1) X
FREQ_MON_FACTOR[3:0] (b3~0, 2EH)
This threshold is symmetrical about zero.
Programming Information
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December 9, 2008
IDT82V3285
WAN PLL
UPPER_THRESHOLD_0_CNFG - Upper Threshold for Leaky Bucket Configuration 0
Address: 31H
Type: Read / Write
Default Value: 00000110
7
6
5
4
3
2
1
0
UPPER_THRE
SHOLD_0_DAT
A7
UPPER_THRE
SHOLD_0_DAT
A6
UPPER_THRE
SHOLD_0_DAT
A5
UPPER_THRE
SHOLD_0_DAT
A4
UPPER_THRE
SHOLD_0_DAT
A3
UPPER_THRE
SHOLD_0_DAT
A2
UPPER_THRE
SHOLD_0_DAT
A1
UPPER_THRE
SHOLD_0_DAT
A0
Bit
Name
Description
7-0
UPPER_THRESHOLD_0_DATA[7:0]
These bits set an upper threshold for the internal leaky bucket accumulator. When the number of the accumulated events is above this threshold, a no-activity alarm is raised.
LOWER_THRESHOLD_0_CNFG - Lower Threshold for Leaky Bucket Configuration 0
Address: 32H
Type: Read / Write
Default Value: 00000100
7
6
5
4
3
2
1
0
LOWER_THRE
SHOLD_0_DAT
A7
LOWER_THRE
SHOLD_0_DAT
A6
LOWER_THRE
SHOLD_0_DAT
A5
LOWER_THRE
SHOLD_0_DAT
A4
LOWER_THRE
SHOLD_0_DAT
A3
LOWER_THRE
SHOLD_0_DAT
A2
LOWER_THRE
SHOLD_0_DAT
A1
LOWER_THRE
SHOLD_0_DAT
A0
Bit
Name
Description
7-0
LOWER_THRESHOLD_0_DATA[7:0]
These bits set a lower threshold for the internal leaky bucket accumulator. When the number of the accumulated
events is below this threshold, the no-activity alarm is cleared.
BUCKET_SIZE_0_CNFG - Bucket Size for Leaky Bucket Configuration 0
Address: 33H
Type: Read / Write
Default Value: 00001000
7
6
5
4
3
2
1
0
BUCKET_SIZE
_0_DATA7
BUCKET_SIZE
_0_DATA6
BUCKET_SIZE
_0_DATA5
BUCKET_SIZE
_0_DATA4
BUCKET_SIZE
_0_DATA3
BUCKET_SIZE
_0_DATA2
BUCKET_SIZE
_0_DATA1
BUCKET_SIZE
_0_DATA0
Bit
Name
Description
7-0
BUCKET_SIZE_0_DATA[7:0]
These bits set a bucket size for the internal leaky bucket accumulator. If the number of the accumulated events reach
the bucket size, the accumulator will stop increasing even if further events are detected.
Programming Information
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December 9, 2008
IDT82V3285
WAN PLL
DECAY_RATE_0_CNFG - Decay Rate for Leaky Bucket Configuration 0
Address: 34H
Type: Read / Write
Default Value: XXXXXX01
7
6
5
4
3
2
1
0
-
-
-
-
-
-
DECAY_RATE_
0_DATA1
DECAY_RATE_
0_DATA0
Bit
Name
7-2
-
Description
Reserved.
These bits set a decay rate for the internal leaky bucket accumulator:
00: The accumulator decreases by 1 in every 128 ms with no event detected.
DECAY_RATE_0_DATA[1:0] 01: The accumulator decreases by 1 in every 256 ms with no event detected. (default)
10: The accumulator decreases by 1 in every 512 ms with no event detected.
11: The accumulator decreases by 1 in every 1024 ms with no event detected.
1-0
UPPER_THRESHOLD_1_CNFG - Upper Threshold for Leaky Bucket Configuration 1
Address: 35H
Type: Read / Write
Default Value: 00000110
7
6
5
4
3
2
1
0
UPPER_THRE
SHOLD_1_DAT
A7
UPPER_THRE
SHOLD_1_DAT
A6
UPPER_THRE
SHOLD_1_DAT
A5
UPPER_THRE
SHOLD_1_DAT
A4
UPPER_THRE
SHOLD_1_DAT
A3
UPPER_THRE
SHOLD_1_DAT
A2
UPPER_THRE
SHOLD_1_DAT
A1
UPPER_THRE
SHOLD_1_DAT
A0
Bit
Name
Description
7-0
UPPER_THRESHOLD_1_DATA[7:0]
These bits set an upper threshold for the internal leaky bucket accumulator. When the number of the accumulated events is above this threshold, a no-activity alarm is raised.
LOWER_THRESHOLD_1_CNFG - Lower Threshold for Leaky Bucket Configuration 1
Address: 36H
Type: Read / Write
Default Value: 00000100
7
6
5
4
3
2
1
0
LOWER_THRE
SHOLD_1_DAT
A7
LOWER_THRE
SHOLD_1_DAT
A6
LOWER_THRE
SHOLD_1_DAT
A5
LOWER_THRE
SHOLD_1_DAT
A4
LOWER_THRE
SHOLD_1_DAT
A3
LOWER_THRE
SHOLD_1_DAT
A2
LOWER_THRE
SHOLD_1_DAT
A1
LOWER_THRE
SHOLD_1_DAT
A0
Bit
7-0
Name
Description
These bits set a lower threshold for the internal leaky bucket accumulator. When the number of the accumulated
LOWER_THRESHOLD_1_DATA[7:0]
events is below this threshold, the no-activity alarm is cleared.
Programming Information
87
December 9, 2008
IDT82V3285
WAN PLL
BUCKET_SIZE_1_CNFG - Bucket Size for Leaky Bucket Configuration 1
Address: 37H
Type: Read / Write
Default Value: 00001000
7
6
5
4
3
2
1
0
BUCKET_SIZE
_1_DATA7
BUCKET_SIZE
_1_DATA6
BUCKET_SIZE
_1_DATA5
BUCKET_SIZE
_1_DATA4
BUCKET_SIZE
_1_DATA3
BUCKET_SIZE
_1_DATA2
BUCKET_SIZE
_1_DATA1
BUCKET_SIZE
_1_DATA0
Bit
Name
Description
These bits set a bucket size for the internal leaky bucket accumulator. If the number of the accumulated events reach
BUCKET_SIZE_1_DATA[7:0]
the bucket size, the accumulator will stop increasing even if further events are detected.
7-0
DECAY_RATE_1_CNFG - Decay Rate for Leaky Bucket Configuration 1
Address: 38H
Type: Read / Write
Default Value: XXXXXX01
7
6
5
4
3
2
1
0
-
-
-
-
-
-
DECAY_RATE_
1_DATA1
DECAY_RATE_
1_DATA0
Bit
Name
7-2
-
Description
Reserved.
These bits set a decay rate for the internal leaky bucket accumulator:
00: The accumulator decreases by 1 in every 128 ms with no event detected.
DECAY_RATE_1_DATA[1:0] 01: The accumulator decreases by 1 in every 256 ms with no event detected. (default)
10: The accumulator decreases by 1 in every 512 ms with no event detected.
11: The accumulator decreases by 1 in every 1024 ms with no event detected.
1-0
UPPER_THRESHOLD_2_CNFG - Upper Threshold for Leaky Bucket Configuration 2
Address: 39H
Type: Read / Write
Default Value: 00000110
7
6
5
4
3
2
1
0
UPPER_THRE
SHOLD_2_DAT
A7
UPPER_THRE
SHOLD_2_DAT
A6
UPPER_THRE
SHOLD_2_DAT
A5
UPPER_THRE
SHOLD_2_DAT
A4
UPPER_THRE
SHOLD_2_DAT
A3
UPPER_THRE
SHOLD_2_DAT
A2
UPPER_THRE
SHOLD_2_DAT
A1
UPPER_THRE
SHOLD_2_DAT
A0
Bit
7-0
Name
Description
These bits set an upper threshold for the internal leaky bucket accumulator. When the number of the accumuUPPER_THRESHOLD_2_DATA[7:0]
lated events is above this threshold, a no-activity alarm is raised.
Programming Information
88
December 9, 2008
IDT82V3285
WAN PLL
LOWER_THRESHOLD_2_CNFG - Lower Threshold for Leaky Bucket Configuration 2
Address: 3AH
Type: Read / Write
Default Value: 00000100
7
6
5
4
3
2
1
0
LOWER_THRE
SHOLD_2_DAT
A7
LOWER_THRE
SHOLD_2_DAT
A6
LOWER_THRE
SHOLD_2_DAT
A5
LOWER_THRE
SHOLD_2_DAT
A4
LOWER_THRE
SHOLD_2_DAT
A3
LOWER_THRE
SHOLD_2_DAT
A2
LOWER_THRE
SHOLD_2_DAT
A1
LOWER_THRE
SHOLD_2_DAT
A0
Bit
Name
Description
7-0
LOWER_THRESHOLD_2_DATA[7:0]
These bits set a lower threshold for the internal leaky bucket accumulator. When the number of the accumulated events is below this threshold, the no-activity alarm is cleared.
BUCKET_SIZE_2_CNFG - Bucket Size for Leaky Bucket Configuration 2
Address: 3BH
Type: Read / Write
Default Value: 00001000
7
6
5
4
3
2
1
0
BUCKET_SIZE
_2_DATA7
BUCKET_SIZE
_2_DATA6
BUCKET_SIZE
_2_DATA5
BUCKET_SIZE
_2_DATA4
BUCKET_SIZE
_2_DATA3
BUCKET_SIZE
_2_DATA2
BUCKET_SIZE
_2_DATA1
BUCKET_SIZE
_2_DATA0
Bit
Name
Description
7-0
BUCKET_SIZE_2_DATA[7:0]
These bits set a bucket size for the internal leaky bucket accumulator. If the number of the accumulated events reaches
the bucket size, the accumulator will stop increasing even if further events are detected.
DECAY_RATE_2_CNFG - Decay Rate for Leaky Bucket Configuration 2
Address: 3CH
Type: Read / Write
Default Value: XXXXXX01
7
6
5
4
3
2
1
0
-
-
-
-
-
-
DECAY_RATE_
2_DATA1
DECAY_RATE_
2_DATA0
Bit
Name
7-2
-
1-0
Description
Reserved.
These bits set a decay rate for the internal leaky bucket accumulator:
00: The accumulator decreases by 1 in every 128 ms with no event detected.
DECAY_RATE_2_DATA[1:0] 01: The accumulator decreases by 1 in every 256 ms with no event detected. (default)
10: The accumulator decreases by 1 in every 512 ms with no event detected.
11: The accumulator decreases by 1 in every 1024 ms with no event detected.
Programming Information
89
December 9, 2008
IDT82V3285
WAN PLL
UPPER_THRESHOLD_3_CNFG - Upper Threshold for Leaky Bucket Configuration 3
Address: 3DH
Type: Read / Write
Default Value: 00000110
7
6
5
4
3
2
1
0
UPPER_THRE
SHOLD_3_DAT
A7
UPPER_THRE
SHOLD_3_DAT
A6
UPPER_THRE
SHOLD_3_DAT
A5
UPPER_THRE
SHOLD_3_DAT
A4
UPPER_THRE
SHOLD_3_DAT
A3
UPPER_THRE
SHOLD_3_DAT
A2
UPPER_THRE
SHOLD_3_DAT
A1
UPPER_THRE
SHOLD_3_DAT
A0
Bit
Name
Description
7-0
UPPER_THRESHOLD_3_DATA[7:0]
These bits set an upper threshold for the internal leaky bucket accumulator. When the number of the accumulated events is above this threshold, a no-activity alarm is raised.
LOWER_THRESHOLD_3_CNFG - Lower Threshold for Leaky Bucket Configuration 3
Address: 3EH
Type: Read / Write
Default Value: 00000100
7
6
5
4
3
2
1
0
LOWER_THRE
SHOLD_3_DAT
A7
LOWER_THRE
SHOLD_3_DAT
A6
LOWER_THRE
SHOLD_3_DAT
A5
LOWER_THRE
SHOLD_3_DAT
A4
LOWER_THRE
SHOLD_3_DAT
A3
LOWER_THRE
SHOLD_3_DAT
A2
LOWER_THRE
SHOLD_3_DAT
A1
LOWER_THRE
SHOLD_3_DAT
A0
Bit
Name
Description
7-0
LOWER_THRESHOLD_3_DATA[7:0]
These bits set a lower threshold for the internal leaky bucket accumulator. When the number of the accumulated events is below this threshold, the no-activity alarm is cleared.
BUCKET_SIZE_3_CNFG - Bucket Size for Leaky Bucket Configuration 3
Address: 3FH
Type: Read / Write
Default Value: 00001000
7
6
5
4
3
2
1
0
BUCKET_SIZE
_3_DATA7
BUCKET_SIZE
_3_DATA6
BUCKET_SIZE
_3_DATA5
BUCKET_SIZE
_3_DATA4
BUCKET_SIZE
_3_DATA3
BUCKET_SIZE
_3_DATA2
BUCKET_SIZE
_3_DATA1
BUCKET_SIZE
_3_DATA0
Bit
Name
Description
7-0
BUCKET_SIZE_3_DATA[7:0]
These bits set a bucket size for the internal leaky bucket accumulator. If the number of the accumulated events
reaches the bucket size, the accumulator will stop increasing even if further events are detected.
Programming Information
90
December 9, 2008
IDT82V3285
WAN PLL
DECAY_RATE_3_CNFG - Decay Rate for Leaky Bucket Configuration 3
Address: 40H
Type: Read / Write
Default Value: XXXXXX01
7
6
5
4
3
2
1
0
-
-
-
-
-
-
DECAY_RATE_
3_DATA1
DECAY_RATE_
3_DATA0
Bit
Name
7-2
-
Description
Reserved.
These bits set a decay rate for the internal leaky bucket accumulator:
00: The accumulator decreases by 1 in every 128 ms with no event detected.
DECAY_RATE_3_DATA[1:0] 01: The accumulator decreases by 1 in every 256 ms with no event detected. (default)
10: The accumulator decreases by 1 in every 512 ms with no event detected.
11: The accumulator decreases by 1 in every 1024 ms with no event detected.
1-0
IN_FREQ_READ_CH_CNFG - Input Clock Frequency Read Channel Selection
Address: 41H
Type: Read / Write
Default Value: XXXX0000
7
6
5
4
3
2
1
0
-
-
-
-
IN_FREQ_READ
_CH3
IN_FREQ_READ
_CH2
IN_FREQ_READ
_CH1
IN_FREQ_READ
_CH0
Bit
Name
7-4
-
3-0
Description
Reserved.
These bits select an input clock, the frequency of which with respect to the reference clock can be read.
0000: Reserved. (default)
0001, 0010: Reserved.
0011: IN1.
0100: IN2.
IN_FREQ_READ_CH[3:0]
0101: IN3.
0110: IN4.
0111, 1000, 1001, 1010: Reserved.
1011: IN5.
1100, 1101, 1110, 1111: Reserved.
Programming Information
91
December 9, 2008
IDT82V3285
WAN PLL
IN_FREQ_READ_STS - Input Clock Frequency Read Value
Address: 42H
Type: Read
Default Value: 00000000
7
6
5
4
3
2
1
0
IN_FREQ_VAL
UE7
IN_FREQ_VAL
UE6
IN_FREQ_VAL
UE5
IN_FREQ_VAL
UE4
IN_FREQ_VAL
UE3
IN_FREQ_VAL
UE2
IN_FREQ_VAL
UE1
IN_FREQ_VAL
UE0
Bit
7-0
Name
Description
These bits represent a 2’s complement signed integer. If the value is multiplied by the value in the
FREQ_MON_FACTOR[3:0] bits (b3~0, 2EH), the frequency of an input clock with respect to the reference clock in ppm will
IN_FREQ_VALUE[7:0]
be gotten. The input clock is selected by the IN_FREQ_READ_CH[3:0] bits (b3~0, 41H).
The value in these bits is updated every 16 seconds, starting when an input clock is selected.
Programming Information
92
December 9, 2008
IDT82V3285
WAN PLL
IN1_IN2_STS - Input Clock 1 & 2 Status
Address: 44H
Type: Read
Default Value: X110X110
7
6
5
4
3
2
1
0
-
IN2_FREQ_HAR
D_ALARM
IN2_NO_ACTIVI
TY_ALARM
IN2_PH_LOCK_
ALARM
-
IN1_FREQ_HAR
D_ALARM
IN1_NO_ACTIVI
TY_ALARM
IN1_PH_LOCK_
ALARM
Bit
Name
Description
7
-
6
IN2_FREQ_HARD_ALARM
5
IN2_NO_ACTIVITY_ALARM
4
IN2_PH_LOCK_ALARM
3
-
2
IN1_FREQ_HARD_ALARM
1
IN1_NO_ACTIVITY_ALARM
0
IN1_PH_LOCK_ALARM
Reserved.
This bit indicates whether IN2 is in frequency hard alarm status.
0: No frequency hard alarm.
1: In frequency hard alarm status. (default)
This bit indicates whether IN2 is in no-activity alarm status.
0: No no-activity alarm.
1: In no-activity alarm status. (default)
This bit indicates whether IN2 is in phase lock alarm status.
0: No phase lock alarm. (default)
1: In phase lock alarm status.
If the PH_ALARM_TIMEOUT bit (b5, 09H) is ‘0’, this bit is cleared by writing ‘1’ to this bit; if the
PH_ALARM_TIMEOUT bit (b5, 09H) is ‘1’, this bit is cleared after a period (= TIME_OUT_VALUE[5:0] (b5~0,
08H) X MULTI_FACTOR[1:0] (b7~6, 08H) in seconds) which starts from when the alarm is raised.
Reserved.
This bit indicates whether IN1 is in frequency hard alarm status.
0: No frequency hard alarm.
1: In frequency hard alarm status. (default)
This bit indicates whether IN1 is in no-activity alarm status.
0: No no-activity alarm.
1: In no-activity alarm status. (default)
This bit indicates whether IN1 is in phase lock alarm status.
0: No phase lock alarm. (default)
1: In phase lock alarm status.
If the PH_ALARM_TIMEOUT bit (b5, 09H) is ‘0’, this bit is cleared by writing ‘1’ to this bit; if the
PH_ALARM_TIMEOUT bit (b5, 09H) is ‘1’, this bit is cleared after a period (= TIME_OUT_VALUE[5:0] (b5~0,
08H) X MULTI_FACTOR[1:0] (b7~6, 08H) in seconds) which starts from when the alarm is raised.
Programming Information
93
December 9, 2008
IDT82V3285
WAN PLL
IN3_IN4_STS - Input Clock 3 & 4 Status
Address: 45H
Type: Read
Default Value: X110X110
7
6
5
4
3
2
1
0
-
IN4_FREQ_HAR
D_ALARM
IN4_NO_ACTIVI
TY_ALARM
IN4_PH_LOCK_
ALARM
-
IN3_FREQ_HAR
D_ALARM
IN3_NO_ACTIVI
TY_ALARM
IN3_PH_LOCK_
ALARM
Bit
Name
Description
7
-
6
IN4_FREQ_HARD_ALARM
5
IN4_NO_ACTIVITY_ALARM
4
IN4_PH_LOCK_ALARM
3
-
2
IN3_FREQ_HARD_ALARM
1
IN3_NO_ACTIVITY_ALARM
0
IN3_PH_LOCK_ALARM
Reserved.
This bit indicates whether IN4 is in frequency hard alarm status.
0: No frequency hard alarm.
1: In frequency hard alarm status. (default)
This bit indicates whether IN4 is in no-activity alarm status.
0: No no-activity alarm.
1: In no-activity alarm status. (default)
This bit indicates whether IN4 is in phase lock alarm status.
0: No phase lock alarm. (default)
1: In phase lock alarm status.
If the PH_ALARM_TIMEOUT bit (b5, 09H) is ‘0’, this bit is cleared by writing ‘1’ to this bit; if the
PH_ALARM_TIMEOUT bit (b5, 09H) is ‘1’, this bit is cleared after a period (= TIME_OUT_VALUE[5:0] (b5~0,
08H) X MULTI_FACTOR[1:0] (b7~6, 08H) in seconds) which starts from when the alarm is raised.
Reserved.
This bit indicates whether IN3 is in frequency hard alarm status.
0: No frequency hard alarm.
1: In frequency hard alarm status. (default)
This bit indicates whether IN3 is in no-activity alarm status.
0: No no-activity alarm.
1: In no-activity alarm status. (default)
This bit indicates whether IN3 is in phase lock alarm status.
0: No phase lock alarm. (default)
1: In phase lock alarm status.
If the PH_ALARM_TIMEOUT bit (b5, 09H) is ‘0’, this bit is cleared by writing ‘1’ to this bit; if the
PH_ALARM_TIMEOUT bit (b5, 09H) is ‘1’, this bit is cleared after a period (= TIME_OUT_VALUE[5:0] (b5~0,
08H) X MULTI_FACTOR[1:0] (b7~6, 08H) in seconds) which starts from when the alarm is raised.
Programming Information
94
December 9, 2008
IDT82V3285
WAN PLL
IN5_STS - Input Clock 5 Status
Address: 48H
Type: Read
Default Value: X110X110
7
6
5
4
3
2
1
0
-
-
-
-
-
IN5_FREQ_HA
RD_ALARM
IN5_NO_ACTIV
ITY_ALARM
IN5_PH_LOCK
_ALARM
Bit
Name
7-3
-
2
1
0
Description
Reserved.
This bit indicates whether IN5 is in frequency hard alarm status.
IN5_FREQ_HARD_ALARM 0: No frequency hard alarm.
1: In frequency hard alarm status. (default)
This bit indicates whether IN5 is in no-activity alarm status.
IN5_NO_ACTIVITY_ALARM 0: No no-activity alarm.
1: In no-activity alarm status. (default)
This bit indicates whether IN5 is in phase lock alarm status.
0: No phase lock alarm. (default)
1: In phase lock alarm status.
IN5_PH_LOCK_ALARM
If the PH_ALARM_TIMEOUT bit (b5, 09H) is ‘0’, this bit is cleared by writing ‘1’ to this bit; if the
PH_ALARM_TIMEOUT bit (b5, 09H) is ‘1’, this bit is cleared after a period (= TIME_OUT_VALUE[5:0] (b5~0, 08H)
X MULTI_FACTOR[1:0] (b7~6, 08H) in seconds) which starts from when the alarm is raised.
Programming Information
95
December 9, 2008
IDT82V3285
7.2.5
WAN PLL
T0 / T4 DPLL INPUT CLOCK SELECTION REGISTERS
INPUT_VALID1_STS - Input Clocks Validity 1
Address: 4AH
Type: Read
Default Value: 00000000
7
6
5
4
3
2
1
0
-
-
IN4
IN3
IN2
IN1
-
-
Bit
Name
7-6
-
5-2
INn
1-0
-
Description
Reserved.
This bit indicates the validity of the corresponding INn. Here n is any of 4 to 1.
0: Invalid. (default)
1: Valid.
Reserved.
INPUT_VALID2_STS - Input Clocks Validity 2
Address: 4BH
Type: Read
Default Value: XX000000
7
6
5
4
3
2
1
0
-
-
-
-
-
IN5
-
-
Bit
Name
7-3
-
2
IN5
1-0
-
Description
Reserved.
This bit indicates the validity of IN5.
0: Invalid. (default)
1: Valid.
Reserved.
REMOTE_INPUT_VALID1_CNFG - Input Clocks Validity Configuration 1
Address: 4CH
Type: Read / Write
Default Value: 11111111
7
6
5
4
3
2
1
0
-
-
IN4_VALID
IN3_VALID
IN2_VALID
IN1_VALID
-
-
Bit
Name
7-6
-
5-2
INn_VALID
1-0
-
Programming Information
Description
Reserved.
This bit controls whether the corresponding INn is allowed to be locked for automatic selection. Here n is any one of 4 to 1.
0: Enabled.
1: Disabled. (default)
Reserved.
96
December 9, 2008
IDT82V3285
WAN PLL
REMOTE_INPUT_VALID2_CNFG - Input Clocks Validity Configuration 2
Address: 4DH
Type: Read / Write
Default Value: XX111111
7
6
5
4
3
2
1
0
-
-
-
-
-
IN5_VALID
-
-
Bit
Name
7-3
-
Description
2
IN5_VALID
1-0
-
Reserved.
This bit controls whether IN5 is allowed to be locked for automatic selection.
0: Enabled.
1: Disabled. (default)
Reserved.
PRIORITY_TABLE1_STS - Priority Status 1 *
Address: 4EH
Type: Read
Default Value: 00000000
7
6
5
4
3
2
1
0
HIGHEST_PRI
ORITY_VALIDA
TED3
HIGHEST_PRI
ORITY_VALIDA
TED2
HIGHEST_PRI
ORITY_VALIDA
TED1
HIGHEST_PRI
ORITY_VALIDA
TED0
CURRENTLY_S
ELECTED_INP
UT3
CURRENTLY_S
ELECTED_INP
UT2
CURRENTLY_S
ELECTED_INP
UT1
CURRENTLY_S
ELECTED_INP
UT0
Bit
7-4
3-0
Name
Description
These bits indicate a qualified input clock with the highest priority.
0000: No input clock is qualified. (default)
0001, 0010: Reserved.
0011: IN1.
0100: IN2.
0101: IN3.
HIGHEST_PRIORITY_VALIDATED[3:0]
0110: IN4.
0111, 1000, 1001, 1010: Reserved.
1011: IN5.
1100, 1101, 1110, 1111: Reserved.
Note that the input clock is indicated by these bits only when the corresponding INn (b5-2, 4CH) or INn
(b2, 4DH) bit is ‘0’.
These bits indicate the T0/T4 selected input clock.
0000: No input clock is selected; or the T4 selected input clock is the T0 DPLL output. (default)
0001, 0010: Reserved.
0011: IN1 is selected.
0100: IN2 is selected.
0101: IN3 is selected.
CURRENTLY_SELECTED_INPUT[3:0]
0110: IN4 is selected.
0111, 1000, 1001, 1010: Reserved.
1011: IN5 is selected.
1100, 1101, 1110, 1111: Reserved.
Note that the input clock is indicated by these bits only when the corresponding INn (b5-2, 4CH) or INn
(b2, 4DH) bit is ‘0’.
Programming Information
97
December 9, 2008
IDT82V3285
WAN PLL
PRIORITY_TABLE2_STS - Priority Status 2 *
Address: 4FH
Type: Read
Default Value: 00000000
7
6
5
4
3
2
1
0
THIRD_HIGHE
ST_PRIORITY_
VALIDATED3
THIRD_HIGHE
ST_PRIORITY_
VALIDATED2
THIRD_HIGHE
ST_PRIORITY_
VALIDATED1
THIRD_HIGHE
ST_PRIORITY_
VALIDATED0
SECOND_HIGH
EST_PRIORITY
_VALIDATED3
SECOND_HIGH
EST_PRIORITY
_VALIDATED2
SECOND_HIGH
EST_PRIORITY
_VALIDATED1
SECOND_HIGH
EST_PRIORITY
_VALIDATED0
Bit
7-4
3-0
Name
Description
These bits indicate a qualified input clock with the third highest priority.
0000: No input clock is qualified. (default)
0001, 0010: Reserved.
0011: IN1.
0100: IN2.
0101: IN3.
THIRD_HIGHEST_PRIORITY_VALIDATED[3:0]
0110: IN4.
0111, 1000, 1001, 1010: Reserved.
1011: IN5.
1100, 1101, 1110, 1111: Reserved.
Note that the input clock is indicated by these bits only when the corresponding INn (b5-2,
4CH) or INn (b2, 4DH) bit is ‘0’.
These bits indicate a qualified input clock with the second highest priority.
0000: No input clock is qualified. (default)
0001, 0010: Reserved.
0011: IN1.
0100: IN2.
0101: IN3.
SECOND_HIGHEST_PRIORITY_VALIDATED[3:0]
0110: IN4.
0111, 1000, 1001, 1010: Reserved.
1011: IN5.
1100, 1101, 1110, 1111: Reserved.
Note that the input clock is indicated by these bits only when the corresponding INn (b5-2,
4CH) or INn (b2, 4DH) bit is ‘0’.
Programming Information
98
December 9, 2008
IDT82V3285
WAN PLL
T0_INPUT_SEL_CNFG - T0 Selected Input Clock Configuration
Address: 50H
Type: Read / Write
Default Value: XXXX0000
7
6
5
4
3
2
1
0
-
-
-
-
T0_INPUT_SEL3
T0_INPUT_SEL2
T0_INPUT_SEL1
T0_INPUT_SEL0
Bit
Name
7-4
-
3-0
Description
Reserved.
This bit determines T0 input clock selection. It is valid only when the EXT_SW bit (b4, 0BH) is ‘0’.
0000: Automatic selection. (default)
0001, 0010: Reserved.
0011: Forced selection - IN1 is selected.
0100: Forced selection - IN2 is selected.
T0_INPUT_SEL[3:0]
0101: Forced selection - IN3 is selected.
0110: Forced selection - IN4 is selected.
0111, 1000, 1001, 1010: Reserved.
1011: Forced selection - IN5 is selected.
1100, 1101, 1110, 1111: Reserved.
Programming Information
99
December 9, 2008
IDT82V3285
WAN PLL
T4_INPUT_SEL_CNFG - T4 Selected Input Clock Configuration
Address: 51H
Type: Read / Write
Default Value: X0000000
7
6
5
4
3
2
1
0
-
T4_LOCK_T0
T0_FOR_T4
T4_TEST_T0_PH
T4_INPUT_SEL3
T4_INPUT_SEL2
T4_INPUT_SEL1
T4_INPUT_SEL0
Bit
Name
7
-
6
5
4
3-0
Description
Reserved.
This bit determines whether the T4 DPLL locks to a T0 DPLL output or locks independently from the T0 DPLL.
T4_LOCK_T0
0: Independently from the T0 path. (default)
1: Locks to a 77.76 MHz or 8 kHz signal from the T0 DPLL 77.76 MHz path.
This bit is valid only when the T4_LOCK_T0 bit (b6, 51H) is ‘1’. It determines whether a 77.76 MHz or 8 kHz signal from the
T0 DPLL 77.76 MHz path is selected by the T4 DPLL.
T0_FOR_T4
0: 77.76 MHz. (default)
1: 8 kHz.
This bit determines whether T4 selected input clock is compared with the feedback signal of the T4 DPLL for T4 DPLL locking
or is compared with the T0 selected input clock to get the phase difference between T0 and T4 selected input clocks.
T4_TEST_T0_PH
0: The T4 DPLL output. (default)
1: The T0 selected input clock.
These bits are valid only when the T4_LOCK_T0 bit (b6, 51H) is ‘0’. They determines the T4 DPLL input clock selection.
0000: Automatic selection. (default)
0001, 0010: Reserved.
0011: Forced selection - IN1 is selected.
0100: Forced selection - IN2 is selected.
T4_INPUT_SEL[3:0]
0101: Forced selection - IN3 is selected.
0110: Forced selection - IN4 is selected.
0111, 1000, 1001, 1010: Reserved.
1011: Forced selection - IN5 is selected.
1100, 1101, 1110, 1111: Reserved.
Programming Information
100
December 9, 2008
IDT82V3285
7.2.6
WAN PLL
T0 / T4 DPLL STATE MACHINE CONTROL REGISTERS
OPERATING_STS - DPLL Operating Status
Address: 52H
Type: Read
Default Value: 10000001
7
6
5
4
3
2
1
0
EX_SYNC_ALA
RM_MON
T4_DPLL_LO
CK
T0_DPLL_SOFT
_FREQ_ALARM
T4_DPLL_SOFT
_FREQ_ALARM
T0_DPLL_LO
CK
T0_DPLL_OPER
ATING_MODE2
T0_DPLL_OPER
ATING_MODE1
T0_DPLL_OPER
ATING_MODE0
Bit
7
6
5
4
3
2-0
Name
Description
This bit indicates whether the frame sync input signal is in external sync alarm status.
0: No external sync alarm.
1: In external sync alarm status. (default)
This bit indicates the T4 DPLL locking status.
T4_DPLL_LOCK
0: Unlocked. (default)
1: Locked.
This bit indicates whether the T0 DPLL is in soft alarm status.
T0_DPLL_SOFT_FREQ_ALARM 0: No T0 DPLL soft alarm. (default)
1: In T0 DPLL soft alarm status.
This bit indicates whether the T4 DPLL is in soft alarm status.
T4_DPLL_SOFT_FREQ_ALARM 0: No T4 DPLL soft alarm. (default)
1: In T4 DPLL soft alarm status.
This bit indicates the T0 DPLL locking status.
T0_DPLL_LOCK
0: Unlocked. (default)
1: Locked.
These bits indicate the current operating mode of T0 DPLL.
000: Reserved.
001: Free-Run. (default)
010: Holdover.
T0_DPLL_OPERATING_MODE[2:0] 011: Reserved.
100: Locked.
101: Pre-Locked2.
110: Pre-Locked.
111: Lost-Phase.
EX_SYNC_ALARM_MON
Programming Information
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IDT82V3285
WAN PLL
T0_OPERATING_MODE_CNFG - T0 DPLL Operating Mode Configuration
Address: 53H
Type: Read / Write
Default Value: XXXXX000
7
6
5
4
3
2
1
0
-
-
-
-
-
T0_OPERATING_MODE2
T0_OPERATING_MODE1
T0_OPERATING_MODE0
Bit
Name
7-3
-
2-0
Description
Reserved.
These bits control the T0 DPLL operating mode.
000: Automatic. (default)
001: Forced - Free-Run.
010: Forced - Holdover.
T0_OPERATING_MODE[2:0] 011: Reserved.
100: Forced - Locked.
101: Forced - Pre-Locked2.
110: Forced - Pre-Locked.
111: Forced - Lost-Phase.
T4_OPERATING_MODE_CNFG - T4 DPLL Operating Mode Configuration
Address: 54H
Type: Read / Write
Default Value: XXXXX000
7
6
5
4
3
2
1
0
-
-
-
-
-
T4_OPERATING_MODE2
T4_OPERATING_MODE1
T4_OPERATING_MODE0
Bit
Name
7-3
-
2-0
Description
Reserved.
These bits control the T4 DPLL operating mode.
000: Automatic. (default)
001: Forced - Free-Run.
T4_OPERATING_MODE[2:0] 010: Forced - Holdover.
011: Reserved.
100: Forced - Locked.
101, 110, 111: Reserved.
Programming Information
102
December 9, 2008
IDT82V3285
7.2.7
WAN PLL
T0 / T4 DPLL & APLL CONFIGURATION REGISTERS
T0_DPLL_APLL_PATH_CNFG - T0 DPLL & APLL Path Configuration
Address: 55H
Type: Read / Write
Default Value: 00000X0X
7
6
5
4
3
2
1
0
T0_APLL_PATH
3
T0_APLL_PA
TH2
T0_APLL_PA
TH1
T0_APLL_PA
TH0
T0_GSM_OBSAI_
16E1_16T1_SEL1
T0_GSM_OBSAI_
16E1_16T1_SEL0
T0_12E1_24T1_
E3_T3_SEL1
T0_12E1_24T1_
E3_T3_SEL0
Bit
7-4
3-2
1-0
Name
Description
These bits select an input to the T0 APLL.
0000: The output of T0 DPLL 77.76 MHz path. (default)
0001: The output of T0 DPLL 12E1/24T1/E3/T3 path.
0010: The output of T0 DPLL 16E1/16T1 path.
0011: The output of T0 DPLL GSM/OBSAI/16E1/16T1 path.
T0_APLL_PATH[3:0]
0100: The output of T4 DPLL 77.76 MHz path.
0101: The output of T4 DPLL 12E1/24T1/E3/T3 path.
0110: The output of T4 DPLL 16E1/16T1 path.
0111: The output of T4 DPLL GSM/GPS/16E1/16T1 path.
1XXX: Reserved.
These bits select an output clock from the T0 DPLL GSM/OBSAI/16E1/16T1 path.
00: 16E1.
01: 16T1.
T0_GSM_OBSAI_16E1_16T1_SEL[1:0] 10: GSM.
11: OBSAI.
The default value of the T0_GSM_OBSAI_16E1_16T1_SEL0 bit is determined by the SONET/SDH pin during reset.
These bits select an output clock from the T0 DPLL 12E1/24T1/E3/T3 path.
00: 12E1.
01: 24T1.
T0_12E1_24T1_E3_T3_SEL[1:0]
10: E3.
11: T3.
The default value of the T0_12E1_24T1_E3_T3_SEL0 bit is determined by the SONET/SDH pin during
reset.
Programming Information
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IDT82V3285
WAN PLL
T0_DPLL_START_BW_DAMPING_CNFG - T0 DPLL Start Bandwidth & Damping Factor Configuration
Address: 56H
Type: Read / Write
Default Value: 01101111
7
6
5
4
3
2
1
0
T0_DPLL_STA
RT_DAMPING2
T0_DPLL_STA
RT_DAMPING1
T0_DPLL_STA
RT_DAMPING0
T0_DPLL_STA
RT_BW4
T0_DPLL_STA
RT_BW3
T0_DPLL_STA
RT_BW2
T0_DPLL_STA
RT_BW1
T0_DPLL_STA
RT_BW0
Bit
7-5
4-0
Name
Description
These bits set the starting damping factor for T0 DPLL.
000: Reserved.
001: 1.2.
010: 2.5.
T0_DPLL_START_DAMPING[2:0]
011: 5. (default)
100: 10.
101: 20.
110, 111: Reserved.
These bits set the starting bandwidth for T0 DPLL.
00000: 0.5 mHz.
00001: 1 mHz.
00010: 2 mHz.
00011: 4 mHz.
00100: 8 mHz.
00101: 15 mHz.
00110: 30 mHz.
00111: 60 mHz.
01000: 0.1 Hz.
T0_DPLL_START_BW[4:0]
01001: 0.3 Hz.
01010: 0.6 Hz.
01011: 1.2 Hz.
01100: 2.5 Hz.
01101: 4 Hz.
01110: 8 Hz.
01111: 18 Hz. (default)
10000: 35 Hz.
10001: 70 Hz.
10010: 560 Hz.
10011 ~ 11111: Reserved.
Programming Information
104
December 9, 2008
IDT82V3285
WAN PLL
T0_DPLL_ACQ_BW_DAMPING_CNFG - T0 DPLL Acquisition Bandwidth & Damping Factor Configuration
Address: 57H
Type: Read / Write
Default Value: 01101111
7
6
5
4
3
2
1
0
T0_DPLL_ACQ
_DAMPING2
T0_DPLL_ACQ
_DAMPING1
T0_DPLL_ACQ
_DAMPING0
T0_DPLL_ACQ
_BW4
T0_DPLL_ACQ
_BW3
T0_DPLL_ACQ
_BW2
T0_DPLL_ACQ
_BW1
T0_DPLL_ACQ
_BW0
Bit
7-5
4-0
Name
Description
These bits set the acquisition damping factor for T0 DPLL.
000: Reserved.
001: 1.2.
010: 2.5.
T0_DPLL_ACQ_DAMPING[2:0]
011: 5. (default)
100: 10.
101: 20.
110, 111: Reserved.
These bits set the acquisition bandwidth for T0 DPLL.
00000: 0.5 mHz.
00001: 1 mHz.
00010: 2 mHz.
00011: 4 mHz.
00100: 8 mHz.
00101: 15 mHz.
00110: 30 mHz.
00111: 60 mHz.
01000: 0.1 Hz.
T0_DPLL_ACQ_BW[4:0]
01001: 0.3 Hz.
01010: 0.6 Hz.
01011: 1.2 Hz.
01100: 2.5 Hz.
01101: 4 Hz.
01110: 8 Hz.
01111: 18 Hz. (default)
10000: 35 Hz.
10001: 70 Hz.
10010: 560 Hz.
10011 ~ 11111: Reserved.
Programming Information
105
December 9, 2008
IDT82V3285
WAN PLL
T0_DPLL_LOCKED_BW_DAMPING_CNFG - T0 DPLL Locked Bandwidth & Damping Factor Configuration
Address: 58H
Type: Read / Write
Default Value: 01101011
7
6
5
4
3
2
1
0
T0_DPLL_LOCK
ED_DAMPING2
T0_DPLL_LOCK
ED_DAMPING1
T0_DPLL_LOCK
ED_DAMPING0
T0_DPLL_LOC
KED_BW4
T0_DPLL_LOC
KED_BW3
T0_DPLL_LOC
KED_BW2
T0_DPLL_LOC
KED_BW1
T0_DPLL_LOC
KED_BW0
Bit
7-5
4-0
Name
Description
These bits set the locked damping factor for T0 DPLL.
000: Reserved.
001: 1.2.
010: 2.5.
T0_DPLL_LOCKED_DAMPING[2:0]
011: 5. (default)
100: 10.
101: 20.
110, 111: Reserved.
These bits set the locked bandwidth for T0 DPLL.
00000: 0.5 mHz.
00001: 1 mHz.
00010: 2 mHz.
00011: 4 mHz.
00100: 8 mHz.
00101: 15 mHz.
00110: 30 mHz.
00111: 60 mHz.
01000: 0.1 Hz.
T0_DPLL_LOCKED_BW[4:0]
01001: 0.3 Hz.
01010: 0.6 Hz.
01011: 1.2 Hz. (default)
01100: 2.5 Hz.
01101: 4 Hz.
01110: 8 Hz.
01111: 18 Hz.
10000: 35 Hz.
10001: 70 Hz.
10010: 560 Hz.
10011 ~ 11111: Reserved.
Programming Information
106
December 9, 2008
IDT82V3285
WAN PLL
T0_BW_OVERSHOOT_CNFG - T0 DPLL Bandwidth Overshoot Configuration
Address: 59H
Type: Read / Write
Default Value: 1XXX1XXX
7
6
5
4
3
2
1
0
AUTO_BW_SEL
-
-
-
T0_LIMT
-
-
-
Bit
7
6-4
3
2-0
Name
Description
This bit determines whether starting or acquisition bandwidth / damping factor is used for T0 DPLL.
0: The starting and acquisition bandwidths / damping factors are not used. Only the locked bandwidth / damping factor is used
AUTO_BW_SEL regardless of the T0 DPLL locking stage.
1: The starting, acquisition or locked bandwidth / damping factor is used automatically depending on different T0 DPLL locking
stages. (default)
Reserved.
This bit determines whether the integral path value is frozen when the T0 DPLL hard limit is reached.
T0_LIMT
0: Not frozen.
1: Frozen. It will minimize the subsequent overshoot when T0 DPLL is pulling in. (default)
Reserved.
Programming Information
107
December 9, 2008
IDT82V3285
WAN PLL
PHASE_LOSS_COARSE_LIMIT_CNFG - Phase Loss Coarse Detector Limit Configuration *
Address: 5AH
Type: Read / Write
Default Value: 10000101
7
6
5
4
3
2
1
0
COARSE_PH_L
OS_LIMT_EN
WIDE_EN
MULTI_PH_APP
MULTI_PH_8K_
4K_2K_EN
PH_LOS_COA
RSE_LIMT3
PH_LOS_COA
RSE_LIMT2
PH_LOS_COA
RSE_LIMT1
PH_LOS_COA
RSE_LIMT0
Bit
7
6
5
Name
Description
This bit controls whether the occurrence of the coarse phase loss will result in the T0/T4 DPLL being unlocked.
COARSE_PH_LOS_LIMT_EN 0: Disabled.
1: Enabled. (default)
WIDE_EN
Refer to the description of the MULTI_PH_8K_4K_2K_EN bit (b4, 5AH).
This bit determines whether the PFD output of T0/T4 DPLL is limited to ±1 UI or is limited to the coarse phase limit.
0: Limited to ±1 UI. (default)
1: Limited to the coarse phase limit. When the selected input clock is of 2 kHz, 4 kHz or 8 kHz, the coarse phase limit depends
MULTI_PH_APP
on the MULTI_PH_8K_4K_2K_EN bit, the WIDE_EN bit and the PH_LOS_COARSE_LIMT[3:0] bits; when the selected input
clock is of other frequencies than 2 kHz, 4 kHz and 8 kHz, the coarse phase limit depends on the WIDE_EN bit and the
PH_LOS_COARSE_LIMT[3:0] bits. Refer to the description of the MULTI_PH_8K_4K_2K_EN bit (b4, 5AH) for details.
This bit, together with the WIDE_EN bit (b6, 5AH) and the PH_LOS_COARSE_LIMT[3:0] bits (b3~0, 5AH), determines the
coarse phase limit when the selected input clock is of 2 kHz, 4 kHz or 8 kHz. When the selected input clock is of other frequencies than 2 kHz, 4 kHz and 8 kHz, the coarse phase limit depends on the WIDE_EN bit and the PH_LOS_COARSE_LIMT[3:0]
bits.
Selected Input Clock MULTI_PH_8K_4K_2K_EN WIDE_EN
4
0
MULTI_PH_8K_4K_2K_EN
2 kHz, 4 kHz or 8 kHz
other than 2 kHz, 4
kHz and 8 kHz
1
don’t-care
0
1
0
don’t-care
1
Coarse Phase Limit
±1 UI
±1 UI
set by the PH_LOS_COARSE_LIMT[3:0] bits
(b3~0, 5AH).
±1 UI
set by the PH_LOS_COARSE_LIMT[3:0] bits
(b3~0, 5AH).
These bit set the coarse phase limit. The limit is used only in some cases. Refer to the description of the
MULTI_PH_8K_4K_2K_EN bit (b4, 5AH).
0000: ±1 UI.
0001: ±3 UI.
0010: ±7 UI.
0011: ±15 UI.
3 - 0 PH_LOS_COARSE_LIMT[3:0] 0100: ±31 UI.
0101: ±63 UI. (default)
0110: ±127 UI.
0111: ±255 UI.
1000: ±511 UI.
1001: ±1023 UI (T0); Reserved (T4).
1010-1111: Reserved.
Programming Information
108
December 9, 2008
IDT82V3285
WAN PLL
PHASE_LOSS_FINE_LIMIT_CNFG - Phase Loss Fine Detector Limit Configuration *
Address: 5BH
Type: Read / Write
Default Value: 10XXX010
7
6
5
4
3
2
1
0
FINE_PH_LOS_
LIMT_EN
FAST_LOS_SW
-
-
-
PH_LOS_FINE
_LIMT2
PH_LOS_FINE
_LIMT1
PH_LOS_FINE
_LIMT0
Bit
7
6
5-3
2-0
Name
Description
This bit controls whether the occurrence of the fine phase loss will result in the T0/T4 DPLL being unlocked.
FINE_PH_LOS_LIMT_EN 0: Disabled.
1: Enabled. (default)
The value in this bit can be switched only when it is available for T0 path; this bit is always ‘1’ when it is available for T4
path.
This bit controls whether the occurrence of the fast loss will result in the T0/T4 DPLL being unlocked.
FAST_LOS_SW
0: Does not result in the T0 DPLL being unlocked. T0 DPLL will enter Temp-Holdover mode automatically. (default)
1: Results in the T0/T4 DPLL being unlocked. For T0 path, T0 DPLL will enter Lost-Phase mode if the T0 DPLL operating mode is switched automatically.
Reserved.
These bits set a fine phase limit.
000: 0.
001: ± (45 ° ~ 90 °).
010: ± (90 ° ~ 180 °). (default)
PH_LOS_FINE_LIMT[2:0] 011: ± (180 ° ~ 360 °).
100: ± (20 ns ~ 25 ns).
101: ± (60 ns ~ 65 ns).
110: ± (120 ns ~ 125 ns).
111: ± (950 ns ~ 955 ns).
Programming Information
109
December 9, 2008
IDT82V3285
WAN PLL
T0_HOLDOVER_MODE_CNFG - T0 DPLL Holdover Mode Configuration
Address: 5CH
Type: Read / Write
Default Value: 010001XX
7
6
5
4
3
2
1
0
MAN_HOLDOV
ER
AUTO_AVG
FAST_AVG
READ_AVG
TEMP_HOLDO
VER_MODE1
TEMP_HOLDO
VER_MODE0
-
-
Bit
Name
Description
7
6
MAN_HOLDOVER
AUTO_AVG
Refer to the description of the FAST_AVG bit (b5, 5CH).
Refer to the description of the FAST_AVG bit (b5, 5CH).
This bit, together with the AUTO_AVG bit (b6, 5CH) and the MAN_HOLDOVER bit (b7, 5CH), determines a frequency offset acquiring method in T0 DPLL Holdover Mode.
MAN_HOLDOVER
5
AUTO_AVG
FAST_AVG
Frequency Offset Acquiring Method
0
don’t-care
0
1
Automatic Instantaneous
Automatic Slow Averaged (default)
Automatic Fast Averaged
Manual
FAST_AVG
0
1
1
don’t-care
This bit controls the holdover frequency offset reading, which is read from the T0_HOLDOVER_FREQ[23:0] bits
(5FH ~ 5DH).
0: The value read from the T0_HOLDOVER_FREQ[23:0] bits (5FH ~ 5DH) is equal to the one written to them.
READ_AVG
(default)
1: The value read from the T0_HOLDOVER_FREQ[23:0] bits (5FH ~ 5DH) is not equal to the one written to them.
The value is acquired by Automatic Slow Averaged method if the FAST_AVG bit (b5, 5CH) is ‘0’; or is acquired by
Automatic Fast Averaged method if the FAST_AVG bit (b5, 5CH) is ‘1’.
These bits determine the frequency offset acquiring method in T0 DPLL Temp-Holdover Mode.
00: The method is the same as that used in T0 DPLL Holdover mode.
TEMP_HOLDOVER_MODE[1:0] 01: Automatic Instantaneous. (default)
10: Automatic Fast Averaged.
11: Automatic Slow Averaged.
Reserved.
4
3-2
1-0
T0_HOLDOVER_FREQ[7:0]_CNFG - T0 DPLL Holdover Frequency Configuration 1
Address: 5DH
Type: Read / Write
Default Value: 00000000
7
6
5
4
3
2
1
0
T0_HOLDOVER
_FREQ7
T0_HOLDOVER
_FREQ6
T0_HOLDOVER
_FREQ5
T0_HOLDOVE
R_FREQ4
T0_HOLDOVE
R_FREQ3
T0_HOLDOVE
R_FREQ2
T0_HOLDOVE
R_FREQ1
T0_HOLDOVE
R_FREQ0
Bit
7-0
Name
Description
T0_HOLDOVER_FREQ[7:0] Refer to the description of the T0_HOLDOVER_FREQ[23:16] bits (b7~0, 5FH).
Programming Information
110
December 9, 2008
IDT82V3285
WAN PLL
T0_HOLDOVER_FREQ[15:8]_CNFG - T0 DPLL Holdover Frequency Configuration 2
Address: 5EH
Type: Read / Write
Default Value: 00000000
7
6
5
4
3
2
1
0
T0_HOLDOVER
_FREQ15
T0_HOLDOVER
_FREQ14
T0_HOLDOVER
_FREQ13
T0_HOLDOVE
R_FREQ12
T0_HOLDOVE
R_FREQ11
T0_HOLDOVE
R_FREQ10
T0_HOLDOVE
R_FREQ9
T0_HOLDOVE
R_FREQ8
Bit
Name
7-0
Description
T0_HOLDOVER_FREQ[15:8] Refer to the description of the T0_HOLDOVER_FREQ[23:16] bits (b7~0, 5FH).
T0_HOLDOVER_FREQ[23:16]_CNFG - T0 DPLL Holdover Frequency Configuration 3
Address: 5FH
Type: Read / Write
Default Value: 00000000
7
6
5
4
3
2
1
0
T0_HOLDOVER
_FREQ23
T0_HOLDOVER
_FREQ22
T0_HOLDOVER
_FREQ21
T0_HOLDOVE
R_FREQ20
T0_HOLDOVE
R_FREQ19
T0_HOLDOVE
R_FREQ18
T0_HOLDOVE
R_FREQ17
T0_HOLDOVE
R_FREQ16
Bit
7-0
Name
Description
The T0_HOLDOVER_FREQ[23:0] bits represent a 2’s complement signed integer.
In T0 DPLL Holdover mode, the value written to these bits multiplied by 0.000011 is the frequency offset set manuT0_HOLDOVER_FREQ[23:16]
ally; the value read from these bits multiplied by 0.000011 is the frequency offset automatically slow or fast averaged or manually set, as determined by the READ_AVG bit (b4, 5CH) and the FAST_AVG bit (b5, 5CH).
Programming Information
111
December 9, 2008
IDT82V3285
WAN PLL
T4_DPLL_APLL_PATH_CNFG - T4 DPLL & APLL Path Configuration
Address: 60H
Type: Read / Write
Default Value: 01000X0X
7
6
5
4
3
2
1
0
T4_APLL_PATH
3
T4_APLL_PA
TH2
T4_APLL_PA
TH1
T4_APLL_PA
TH0
T4_GSM_GPS_16
E1_16T1_SEL1
T4_GSM_GPS_16
E1_16T1_SEL0
T4_12E1_24T1_
E3_T3_SEL1
T4_12E1_24T1_
E3_T3_SEL0
Bit
7-4
3-2
1-0
Name
Description
These bits select an input to the T4 APLL.
0000: The output of T0 DPLL 77.76 MHz path.
0001: The output of T0 DPLL 12E1/24T1/E3/T3 path.
0010: The output of T0 DPLL 16E1/16T1 path.
0011: The output of T0 DPLL GSM/OBSAI/16E1/16T1 path.
T4_APLL_PATH[3:0]
0100: The output of T4 DPLL 77.76 MHz path. (default)
0101: The output of T4 DPLL 12E1/24T1/E3/T3 path.
0110: The output of T4 DPLL 16E1/16T1 path.
0111: The output of T4 DPLL GSM/GPS/16E1/16T1 path.
1XXX: Reserved.
These bits select an output clock from the T4 DPLL GSM/GPS/16E1/16T1 path.
00: 16E1.
01: 16T1.
T4_GSM_GPS_16E1_16T1_SEL[1:0] 10: GSM.
11: GPS.
The default value of the T0_GSM_GPS_16E1_16T1_SEL0 bit is determined by the SONET/SDH pin during
reset.
These bits select an output clock from the T4 DPLL 12E1/24T1/E3/T3 path.
00: 12E1.
01: 24T1.
T4_12E1_24T1_E3_T3_SEL[1:0]
10: E3.
11: T3.
The default value of the T4_12E1_24T1_E3_T3_SEL0 bit is determined by the SONET/SDH pin during reset.
Programming Information
112
December 9, 2008
IDT82V3285
WAN PLL
T4_DPLL_LOCKED_BW_DAMPING_CNFG - T4 DPLL Locked Bandwidth & Damping Factor Configuration
Address: 61H
Type: Read / Write
Default Value: 011XXX00
7
6
5
4
3
2
1
0
T4_DPLL_LOCK
ED_DAMPING2
T4_DPLL_LOCK
ED_DAMPING1
T4_DPLL_LOCK
ED_DAMPING0
-
-
-
T4_DPLL_LOC
KED_BW1
T4_DPLL_LOC
KED_BW0
Bit
Name
7-5
4-2
1-0
Description
These bits set the locked damping factor for T4 DPLL.
000: Reserved.
001: 1.2.
010: 2.5.
T4_DPLL_LOCKED_DAMPING[2:0]
011: 5. (default)
100: 10.
101: 20.
110, 111: Reserved.
Reserved.
These bits set the locked bandwidth for T4 DPLL.
00: 18 Hz. (default)
T4_DPLL_LOCKED_BW[1:0]
01: 35 Hz.
10: 70 Hz.
11: 560 Hz.
CURRENT_DPLL_FREQ[7:0]_STS - DPLL Current Frequency Status 1 *
Address: 62H
Type: Read
Default Value: 00000000
7
6
5
4
3
2
1
0
CURRENT_DP
LL_FREQ7
CURRENT_DP
LL_FREQ6
CURRENT_DP
LL_FREQ5
CURRENT_DP
LL_FREQ4
CURRENT_DP
LL_FREQ3
CURRENT_DP
LL_FREQ2
CURRENT_DP
LL_FREQ1
CURRENT_DP
LL_FREQ0
Bit
Name
7-0
Description
CURRENT_DPLL_FREQ[7:0] Refer to the description of the CURRENT_DPLL_FREQ[23:16] bits (b7~0, 64H).
CURRENT_DPLL_FREQ[15:8]_STS - DPLL Current Frequency Status 2 *
Address: 63H
Type: Read
Default Value: 00000000
7
6
5
4
3
2
1
0
CURRENT_DP
LL_FREQ15
CURRENT_DP
LL_FREQ14
CURRENT_DP
LL_FREQ13
CURRENT_DP
LL_FREQ12
CURRENT_DP
LL_FREQ11
CURRENT_DP
LL_FREQ10
CURRENT_DP
LL_FREQ9
CURRENT_DP
LL_FREQ8
Bit
7-0
Name
Description
CURRENT_DPLL_FREQ[15:8] Refer to the description of the CURRENT_DPLL_FREQ[23:16] bits (b7~0, 64H).
Programming Information
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WAN PLL
CURRENT_DPLL_FREQ[23:16]_STS - DPLL Current Frequency Status 3 *
Address: 64H
Type: Read
Default Value: 00000000
7
6
5
4
3
2
1
0
CURRENT_DP
LL_FREQ23
CURRENT_DP
LL_FREQ22
CURRENT_DP
LL_FREQ21
CURRENT_DP
LL_FREQ20
CURRENT_DP
LL_FREQ19
CURRENT_DP
LL_FREQ18
CURRENT_DP
LL_FREQ17
CURRENT_DP
LL_FREQ16
Bit
Name
Description
The CURRENT_DPLL_FREQ[23:0] bits represent a 2’s complement signed integer. If the value in these bits is mulCURRENT_DPLL_FREQ[23:16] tiplied by 0.000011, the current frequency offset of the T0/T4 DPLL output in ppm with respect to the master clock
will be gotten.
7-0
DPLL_FREQ_SOFT_LIMIT_CNFG - DPLL Soft Limit Configuration
Address: 65H
Type: Read / Write
Default Value: 10001100
7
6
5
4
3
2
1
0
FREQ_LIMT_P
H_LOS
DPLL_FREQ_S
OFT_LIMT6
DPLL_FREQ_S
OFT_LIMT5
DPLL_FREQ_S
OFT_LIMT4
DPLL_FREQ_S
OFT_LIMT3
DPLL_FREQ_S
OFT_LIMT2
DPLL_FREQ_S
OFT_LIMT1
DPLL_FREQ_S
OFT_LIMT0
Bit
Name
Description
This bit determines whether the T0/T4 DPLL in hard alarm status will result in its being unlocked.
0: Disabled.
1: Enabled. (default)
These bits represent an unsigned integer. If the value is multiplied by 0.724, the DPLL soft limit for T0 and T4 paths in
DPLL_FREQ_SOFT_LIMT[6:0] ppm will be gotten.
The DPLL soft limit is symmetrical about zero.
7
FREQ_LIMT_PH_LOS
6-0
DPLL_FREQ_HARD_LIMIT[7:0]_CNFG - DPLL Hard Limit Configuration 1
Address: 66H
Type: Read / Write
Default Value: 10101011
7
6
5
4
3
2
1
0
DPLL_FREQ_H
ARD_LIMT7
DPLL_FREQ_H
ARD_LIMT6
DPLL_FREQ_H
ARD_LIMT5
DPLL_FREQ_H
ARD_LIMT4
DPLL_FREQ_H
ARD_LIMT3
DPLL_FREQ_H
ARD_LIMT2
DPLL_FREQ_H
ARD_LIMT1
DPLL_FREQ_H
ARD_LIMT0
Bit
7-0
Name
Description
DPLL_FREQ_HARD_LIMT[7:0] Refer to the description of the DPLL_FREQ_HARD_LIMT[15:8] bits (b7~0, 67H).
Programming Information
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DPLL_FREQ_HARD_LIMIT[15:8]_CNFG - DPLL Hard Limit Configuration 2
Address: 67H
Type: Read / Write
Default Value: 00011001
7
6
5
4
3
2
1
0
DPLL_FREQ_H
ARD_LIMT15
DPLL_FREQ_H
ARD_LIMT14
DPLL_FREQ_H
ARD_LIMT13
DPLL_FREQ_H
ARD_LIMT12
DPLL_FREQ_H
ARD_LIMT11
DPLL_FREQ_H
ARD_LIMT10
DPLL_FREQ_H
ARD_LIMT9
DPLL_FREQ_H
ARD_LIMT8
Bit
Name
7-0
Description
The DPLL_FREQ_HARD_LIMT[15:0] bits represent an unsigned integer. If the value is multiplied by 0.0014, the
DPLL_FREQ_HARD_LIMT[15:8] DPLL hard limit for T0 and T4 paths in ppm will be gotten.
The DPLL hard limit is symmetrical about zero.
CURRENT_DPLL_PHASE[7:0]_STS - DPLL Current Phase Status 1 *
Address: 68H
Type: Read
Default Value: 00000000
7
6
5
4
3
2
1
0
CURRENT_PH
_DATA7
CURRENT_PH
_DATA6
CURRENT_PH
_DATA5
CURRENT_PH
_DATA4
CURRENT_PH
_DATA3
CURRENT_PH
_DATA2
CURRENT_PH
_DATA1
CURRENT_PH
_DATA0
Bit
Name
7-0
Description
CURRENT_PH_DATA[7:0] Refer to the description of the CURRENT_PH_DATA[15:8] bits (b7~0, 69H).
CURRENT_DPLL_PHASE[15:8]_STS - DPLL Current Phase Status 2 *
Address: 69H
Type: Read
Default Value: 00000000
7
6
5
4
3
2
1
0
CURRENT_PH
_DATA15
CURRENT_PH
_DATA14
CURRENT_PH
_DATA13
CURRENT_PH
_DATA12
CURRENT_PH
_DATA11
CURRENT_PH
_DATA10
CURRENT_PH
_DATA9
CURRENT_PH
_DATA8
Bit
7-0
Name
Description
The CURRENT_PH_DATA[15:0] bits represent a 2’s complement signed integer. If the value is multiplied by 0.61, the
CURRENT_PH_DATA[15:8]
averaged phase error of the T0/T4 DPLL feedback with respect to the selected input clock in ns will be gotten.
Programming Information
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WAN PLL
T0_T4_APLL_BW_CNFG - T0 / T4 APLL Bandwidth Configuration
Address: 6AH
Type: Read / Write
Default Value: XX01XX01
7
6
5
4
3
2
1
0
-
-
T0_APLL_BW1
T0_APLL_BW0
-
-
T4_APLL_BW1
T4_APLL_BW0
Bit
Name
7-6
-
5-4
3-2
1-0
Description
Reserved.
These bits set the bandwidth for T0 APLL.
00: 100 kHz.
T0_APLL_BW[1:0] 01: 500 kHz. (default)
10: 1 MHz.
11: 2 MHz.
Reserved.
These bits set the bandwidth for T4 APLL.
00: 100 kHz.
T4_APLL_BW[1:0] 01: 500 kHz. (default)
10: 1 MHz.
11: 2 MHz.
Programming Information
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IDT82V3285
7.2.8
WAN PLL
OUTPUT CONFIGURATION REGISTERS
OUT1_FREQ_CNFG - Output Clock 1 Frequency Configuration
Address: 6DH
Type: Read / Write
Default Value: 00001000
7
6
5
4
3
2
1
0
OUT1_PATH_S
EL3
OUT1_PATH_S
EL2
OUT1_PATH_S
EL1
OUT1_PATH_S
EL0
OUT1_DIVIDER
3
OUT1_DIVIDER
2
OUT1_DIVIDER
1
OUT1_DIVIDER
0
Bit
7-4
3-0
Name
Description
These bits select an input to OUT1.
0000 ~ 0011: The output of T0 APLL. (default: 0000)
0100: The output of T0 DPLL 77.76 MHz path.
0101: The output of T0 DPLL 12E1/24T1/E3/T3 path.
0110: The output of T0 DPLL 16E1/16T1 path.
OUT1_PATH_SEL[3:0] 0111: The output of T0 DPLL GSM/OBSAI/16E1/16T1 path.
1000 ~ 1011: The output of T4 APLL.
1100: The output of T4 DPLL 77.76 MHz path.
1101: The output of T4 DPLL 12E1/24T1/E3/T3 path.
1110: The output of T4 DPLL 16E1/16T1 path.
1111: The output of T4 DPLL GSM/GPS/16E1/16T1 path.
These bits select a division factor of the divider for OUT1.
The output frequency is determined by the division factor and the signal derived from T0/T4 DPLL or T0/T4 APLL output
OUT1_DIVIDER[3:0] (selected by the OUT1_PATH_SEL[3:0] bits (b7~4, 6DH)). If the signal is derived from one of the T0/T4 DPLL outputs,
please refer to Table 24 for the division factor selection. If the signal is derived from the T0/T4 APLL output, please refer to
Table 25 for the division factor selection.
Programming Information
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OUT2_FREQ_CNFG - Output Clock 2 Frequency Configuration
Address: 6EH
Type: Read / Write
Default Value: 00000110
7
6
5
4
3
2
1
0
OUT2_PATH_S
EL3
OUT2_PATH_S
EL2
OUT2_PATH_S
EL1
OUT2_PATH_S
EL0
OUT2_DIVIDER
3
OUT2_DIVIDER
2
OUT2_DIVIDER
1
OUT2_DIVIDER
0
Bit
7-4
3-0
Name
Description
These bits select an input to OUT2.
0000 ~ 0011: The output of T0 APLL. (default: 0000)
0100: The output of T0 DPLL 77.76 MHz path.
0101: The output of T0 DPLL 12E1/24T1/E3/T3 path.
0110: The output of T0 DPLL 16E1/16T1 path.
OUT2_PATH_SEL[3:0] 0111: The output of T0 DPLL GSM/OBSAI/16E1/16T1 path.
1000 ~ 1011: The output of T4 APLL.
1100: The output of T4 DPLL 77.76 MHz path.
1101: The output of T4 DPLL 12E1/24T1/E3/T3 path.
1110: The output of T4 DPLL 16E1/16T1 path.
1111: The output of T4 DPLL GSM/GPS/16E1/16T1 path.
These bits select a division factor of the divider for OUT2.
The output frequency is determined by the division factor and the signal derived from T0/T4 DPLL or T0/T4 APLL output
OUT2_DIVIDER[3:0] (selected by the OUT2_PATH_SEL[3:0] bits (b7~4, 6EH)). If the signal is derived from one of the T0/T4 DPLL outputs,
please refer to Table 24 for the division factor selection. If the signal is derived from the T0/T4 APLL output, please refer to
Table 25 for the division factor selection.
Programming Information
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WAN PLL
OUT3_FREQ_CNFG - Output Clock 3 Frequency Configuration
Address: 6FH
Type: Read / Write
Default Value: 00000100
7
6
5
4
3
2
1
0
OUT3_PATH_S
EL3
OUT3_PATH_S
EL2
OUT3_PATH_S
EL1
OUT3_PATH_S
EL0
OUT3_DIVIDER
3
OUT3_DIVIDER
2
OUT3_DIVIDER
1
OUT3_DIVIDER
0
Bit
7-4
3-0
Name
Description
These bits select an input to OUT3.
0000 ~ 0011: The output of T0 APLL. (default: 0000)
0100: The output of T0 DPLL 77.76 MHz path.
0101: The output of T0 DPLL 12E1/24T1/E3/T3 path.
0110: The output of T0 DPLL 16E1/16T1 path.
OUT3_PATH_SEL[3:0] 0111: The output of T0 DPLL GSM/OBSAI/16E1/16T1 path.
1000 ~ 1011: The output of T4 APLL.
1100: The output of T4 DPLL 77.76 MHz path.
1101: The output of T4 DPLL 12E1/24T1/E3/T3 path.
1110: The output of T4 DPLL 16E1/16T1 path.
1111: The output of T4 DPLL GSM/GPS/16E1/16T1 path.
These bits select a division factor of the divider for OUT3.
The output frequency is determined by the division factor and the signal derived from T0/T4 DPLL or T0/T4 APLL output
OUT3_DIVIDER[3:0] (selected by the OUT3_PATH_SEL[3:0] bits (b7~4, 6FH)). If the signal is derived from one of the T0/T4 DPLL outputs,
please refer to Table 24 for the division factor selection. If the signal is derived from the T0/T4 APLL output, please refer to
Table 25 for the division factor selection.
Programming Information
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WAN PLL
OUT4_FREQ_CNFG - Output Clock 4 Frequency Configuration
Address:70H
Type: Read / Write
Default Value: 00000110
7
6
5
4
3
2
1
0
OUT4_PATH_S
EL3
OUT4_PATH_S
EL2
OUT4_PATH_S
EL1
OUT4_PATH_S
EL0
OUT4_DIVIDER
3
OUT4_DIVIDER
2
OUT4_DIVIDER
1
OUT4_DIVIDER
0
Bit
7-4
3-0
Name
Description
These bits select an input to OUT4.
0000 ~ 0011: The output of T0 APLL. (default: 0000)
0100: The output of T0 DPLL 77.76 MHz path.
0101: The output of T0 DPLL 12E1/24T1/E3/T3 path.
0110: The output of T0 DPLL 16E1/16T1 path.
OUT4_PATH_SEL[3:0] 0111: The output of T0 DPLL GSM/OBSAI/16E1/16T1 path.
1000 ~ 1011: The output of T4 APLL.
1100: The output of T4 DPLL 77.76 MHz path.
1101: The output of T4 DPLL 12E1/24T1/E3/T3 path.
1110: The output of T4 DPLL 16E1/16T1 path.
1111: The output of T4 DPLL GSM/GPS/16E1/16T1 path.
These bits select a division factor of the divider for OUT4.
The output frequency is determined by the division factor and the signal derived from T0/T4 DPLL or T0/T4 APLL output
OUT4_DIVIDER[3:0] (selected by the OUT4_PATH_SEL[3:0] bits (b7~4, 70H)). If the signal is derived from one of the T0/T4 DPLL outputs,
please refer to Table 24 for the division factor selection. If the signal is derived from the T0/T4 APLL output, please refer to
Table 25 for the division factor selection.
Programming Information
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OUT5_FREQ_CNFG - Output Clock 5 Frequency Configuration
Address:71H
Type: Read / Write
Default Value: 00001000
7
6
5
4
3
2
1
0
OUT5_PATH_S
EL3
OUT5_PATH_S
EL2
OUT5_PATH_S
EL1
OUT5_PATH_S
EL0
OUT5_DIVIDER
3
OUT5_DIVIDER
2
OUT5_DIVIDER
1
OUT5_DIVIDER
0
Bit
Name
Description
These bits select an input to OUT5.
0000 ~ 0011: The output of T0 APLL. (default: 0000)
0100: The output of T0 DPLL 77.76 MHz path.
0101: The output of T0 DPLL 12E1/24T1/E3/T3 path.
0110: The output of T0 DPLL 16E1/16T1 path.
OUT5_PATH_SEL[3:0] 0111: The output of T0 DPLL GSM/OBSAI/16E1/16T1 path.
1000 ~ 1011: The output of T4 APLL.
1100: The output of T4 DPLL 77.76 MHz path.
1101: The output of T4 DPLL 12E1/24T1/E3/T3 path.
1110: The output of T4 DPLL 16E1/16T1 path.
1111: The output of T4 DPLL GSM/GPS/16E1/16T1 path.
These bits select a division factor of the divider for OUT5.
The output frequency is determined by the division factor and the signal derived from T0/T4 DPLL or T0/T4 APLL output
OUT5_DIVIDER[3:0] (selected by the OUT5_PATH_SEL[3:0] bits (b7~4, 71H)). If the signal is derived from one of the T0/T4 DPLL outputs,
please refer to Table 24 for the division factor selection. If the signal is derived from the T0/T4 APLL output, please refer to
Table 25 for the division factor selection.
7-4
3-0
OUTPUT_INV2 - Output Clock 4 & 5 Invert Configuration
Address:72H
Type: Read / Write
Default Value: 01000000
7
6
5
4
3
2
1
0
-
-
-
-
-
-
OUT5_INV
OUT4_INV
Bit
Name
7-2
-
1
OUT5_INV
0
OUT4_INV
Programming Information
Description
Reserved.
This bit determines whether the output on OUT5 is inverted.
0: Not inverted. (default)
1: Inverted.
This bit determines whether the output on OUT4 is inverted.
0: Not inverted. (default)
1: Inverted.
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OUTPUT_INV1 - Output Clock 1 ~ 3 Invert Configuration
Address:73H
Type: Read / Write
Default Value: 01000000
7
6
5
4
3
2
1
0
-
-
-
OUT3_INV
OUT2_INV
OUT1_INV
-
-
Bit
Name
7-5
-
4
OUT3_INV
3
OUT2_INV
2
OUT1_INV
1-0
-
Programming Information
Description
Reserved.
This bit determines whether the output on OUT3 is inverted.
0: Not inverted. (default)
1: Inverted.
This bit determines whether the output on OUT2 is inverted.
0: Not inverted. (default)
1: Inverted.
This bit determines whether the output on OUT1 is inverted.
0: Not inverted. (default)
1: Inverted.
Reserved.
122
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FR_MFR_SYNC_CNFG - Frame Sync & Multiframe Sync Output Configuration
Address:74H
Type: Read / Write
Default Value: 01100000
7
6
5
4
3
2
1
0
IN_2K_4K_8K_I
NV
8K_EN
2K_EN
2K_8K_PUL_P
OSITION
8K_INV
8K_PUL
2K_INV
2K_PUL
Bit
7
6
5
4
3
2
1
0
Name
Description
This bit determines whether the input clock is inverted before locked by the T0/T4 DPLL when the input clock is 2 kHz, 4
kHz or 8 kHz.
IN_2K_4K_8K_INV
0: Not inverted. (default)
1: Inverted.
This bit determines whether an 8 kHz signal is enabled to be output on FRSYNC_8K.
8K_EN
0: Disabled. FRSYNC_8K outputs low.
1: Enabled. (default)
This bit determines whether a 2 kHz signal is enabled to be output on MFRSYNC_2K.
2K_EN
0: Disabled. MFRSYNC_2K outputs low.
1: Enabled. (default)
This bit is valid only when FRSYNC_8K and/or MFRSYNC_2K output pulse; i.e., when one of the 8K_PUL bit (b2, 74H)
and the 2K_PUL bit (b0, 74H) is ‘1’ or when the 8K_PUL bit (b2, 74H) and the 2K_PUL bit (b0, 74H) are both ‘1’. It deter2K_8K_PUL_POSITION mines the pulse position referring to the standard 50:50 duty cycle.
0: Pulsed on the falling edge of the standard 50:50 duty cycle position. (default)
1: Pulsed on the rising edge of the standard 50:50 duty cycle position.
This bit determines whether the output on FRSYNC_8K is inverted.
8K_INV
0: Not inverted. (default)
1: Inverted.
This bit determines whether the output on FRSYNC_8K is 50:50 duty cycle or pulsed.
8K_PUL
0: 50:50 duty cycle. (default)
1: Pulsed. The pulse width is defined by the period of the output on OUT1.
This bit determines whether the output on MFRSYNC_2K is inverted.
2K_INV
0: Not inverted. (default)
1: Inverted.
This bit determines whether the output on MFRSYNC_2K is 50:50 duty cycle or pulsed.
2K_PUL
0: 50:50 duty cycle. (default)
1: Pulsed. The pulse width is defined by the period of the output on OUT1.
Programming Information
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IDT82V3285
7.2.9
WAN PLL
PBO & PHASE OFFSET CONTROL REGISTERS
PHASE_MON_PBO_CNFG - Phase Transient Monitor & PBO Configuration
Address:78H
Type: Read / Write
Default Value: 0X000110
7
6
5
4
3
2
1
0
IN_NOISE_WIN
DOW
-
PH_MON_EN
PH_MON_PBO
_EN
PH_TR_MON_L
IMT3
PH_TR_MON_L
IMT2
PH_TR_MON_L
IMT1
PH_TR_MON_L
IMT0
Bit
Name
Description
This bit determines whether the input clock whose edge respect to the reference clock is outside ±5% is enabled to be
selected for T0/T4 DPLL.
IN_NOISE_WINDOW
0: Disabled. (default)
1: Enabled.
Reserved.
This bit is valid only when the PH_MON_PBO_EN bit (b4, 78H) is ‘1’. It determines whether the Phase Transient Monitor
is enabled to monitor the phase-time changes on the T0 selected input clock.
PH_MON_EN
0: Disabled. (default)
1: Enabled.
This bit determines whether a PBO event is triggered when the phase-time changes on the T0 selected input clock are
greater than a programmable limit over an interval of less than 0.1 seconds with the PH_MON_EN bit being ‘1’. The limit
PH_MON_PBO_EN is programmed by the PH_TR_MON_LIMT[3:0] bits (b3~0, 78H).
0: Disabled. (default)
1: Enabled.
These bits represent an unsigned integer. The Phase Transient Monitor limit in ns can be calculated as follows:
PH_TR_MON_LIMT[3:0]
Limit (ns) = (PH_TR_MON_LIMT[3:0] + 7) X 156.
7
6
5
4
3-0
PHASE_OFFSET[7:0]_CNFG - Phase Offset Configuration 1
Address:7AH
Type: Read / Write
Default Value: 00000000
7
6
5
4
3
2
1
0
PH_OFFSET7
PH_OFFSET6
PH_OFFSET5
PH_OFFSET4
PH_OFFSET3
PH_OFFSET2
PH_OFFSET1
PH_OFFSET0
Bit
7-0
Name
Description
PH_OFFSET[7:0] Refer to the description of the PH_OFFSET[9:8] bits (b1~0, 7BH).
Programming Information
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WAN PLL
PHASE_OFFSET[9:8]_CNFG - Phase Offset Configuration 2
Address:7BH
Type: Read / Write
Default Value: 0XXXXX00
7
6
5
4
3
2
1
0
PH_OFFSET_E
N
-
-
-
-
-
PH_OFFSET9
PH_OFFSET8
Bit
7
6-2
1-0
Name
Description
This bit determines whether the input-to-output phase offset is enabled.
If the device is configured as the Master, the input-to-output phase offset:
PH_OFFSET_EN 0: Disabled. (default)
1: Enabled.
If the device is configured as the Slave, the input-to-output phase offset is always enabled.
Reserved.
These bits represent a 2’s complement signed integer. If the value is multiplied by 0.61, the input-to-output phase offset in ns
PH_OFFSET[9:8]
to adjust will be gotten.
Programming Information
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IDT82V3285
7.2.10
WAN PLL
SYNCHRONIZATION CONFIGURATION REGISTERS
SYNC_MONITOR_CNFG - Sync Monitor Configuration
Address:7CH
Type: Read / Write
Default Value: X0101011
7
6
5
4
3
2
1
0
-
SYNC_MON_LIMT2
SYNC_MON_LIMT1
SYNC_MON_LIMT0
-
-
-
-
Bit
Name
7
-
Description
Reserved.
These bits set the limit for the external sync alarm.
000: ±1 UI.
001: ±2 UI.
010: ±3 UI. (default)
SYNC_MON_LIMT[2:0] 011: ±4 UI.
100: ±5 UI.
101: ±6 UI.
110: ±7 UI.
111: ±8 UI.
These bits must be set to ‘1011’.
6-4
3-0
SYNC_PHASE_CNFG - Sync Phase Configuration
Address:7DH
Type: Read / Write
Default Value: XXXXXX00
7
6
5
4
3
2
1
0
-
-
-
-
-
-
SYNC_PH11
SYNC_PH10
Bit
Name
Description
7-2
-
1-0
SYNC_PH1[1:0]
Reserved.
These bits set the sampling of EX_SYNC1 when EX_SYNC1 is enabled to synchronize the frame sync output signal. Nominally, the falling edge of EX_SYNC1 is aligned with the rising edge of the T0 selected input clock.
00: On target. (default)
01: 0.5 UI early.
10: 1 UI late.
11: 0.5 UI late.
Programming Information
126
December 9, 2008
IDT82V3285
8
WAN PLL
THERMAL MANAGEMENT
The junction temperature Tj can be calculated as follows:
Tj = TA + P X θJA = 85°C + 1.9W X 18.9°C/W = 120.9°C
The device operates over the industry temperature range -40°C ~
+85°C. To ensure the functionality and reliability of the device, the maximum junction temperature Tjmax should not exceed 125°C. In some
applications, the device will consume more power and a thermal solution
should be provided to ensure the junction temperature Tj does not
exceed the Tjmax.
8.1
The junction temperature of 120.9°C is below the maximum junction
temperature of 125°C so no extra heat enhancement is required.
In some operation environments, the calculated junction temperature
might exceed the maximum junction temperature of 125°C and an external thermal solution such as a heatsink is required.
8.3
JUNCTION TEMPERATURE
A heatsink is expanding the surface area of the device to which it is
attached. θJA is now a combination of device case and heat-sink thermal
resistance, as the heat flowing from the die junction to ambient goes
through the package and the heatsink. θJA can be calculated as follows:
Junction temperature Tj is the temperature of package typically at the
geographical center of the chip where the device's electrical circuits are.
It can be calculated as follows:
Equation 1: Tj = TA + P X θJA
Equation 2: θJA = θJC + θCH+ θHA
Where:
θJA = Junction-to-Ambient Thermal Resistance of the Package
Where:
θJC = Junction-to-Case Thermal Resistance
θCH = Case-to-Heatsink Thermal Resistance
θHA = Heatsink-to-Ambient Thermal Resistance
Tj = Junction Temperature
TA = Ambient Temperature
P = Device Power Consumption
θCH+ θHA determines which heatsink and heatsink attachment can
In order to calculate junction temperature, an appropriate θJA must
be used. The θJA is shown in Table 43.
be selected to ensure the junction temperature does not exceed the
maximum junction temperature. According to Equation 1 and 2,
Power consumption is the core power excluding the power dissipated
in the loads. Table 42 provides power consumption in special environments.
θCH+ θHA can be calculated as follows:
Equation 3: θCH+ θHA = (Tj - TA) / P - θJC
Assume:
Table 42: Power Consumption and Maximum Junction Temperature
Package
Power
Consumption (W)
Operating
Voltage
(V)
1.9
1.9
3.6
3.6
TQFP/PN100
TQFP/EQG100
8.2
HEATSINK EVALUATION
Tj = 125°C (Tjmax)
Maximum
TA (°C)
Junction
Temperature (°C)
85
85
TA = 85°C
P = 1.9 W
θJC = 16.1°C/W (TQFP/EQG100)
125
125
θCH+ θHA can be calculated as follows:
θCH+ θHA = (125°C - 85°C ) / 1.9W - 16.1°C/W = 5.0°C/W
EXAMPLE OF JUNCTION TEMPERATURE
CALCULATION
That is, if a heatsink and heatsink attachment whose θCH+ θHA is
below or equal to 5.0°C/W is used in such operation environment, the
junction temperature will not exceed the maximum junction temperature.
Assume:
TA = 85°C
θJA = 18.9°C/W (TQFP/EQG100 Soldered & when airflow rate is 0
m/s)
P = 1.9W
Table 43: Thermal Data
Package
Pin Count
Thermal Pad
TQFP/PN100
100
No
TQFP/EQG100
100
Yes/Exposed
TQFP/EQG100
100
Yes/Soldered*
*note: Simulated with 3 x 3 array of thermal vias.
Thermal Management
θJC (°C/W)
θJB (°C/W)
11.0
16.1
16.1
34.2
34.2
1.3
127
θJA (°C/W) vs Air Flow in m/s
0
1
2
3
4
5
39.3
35.8
18.9
36.2
31.1
14.6
34.3
29.5
13.5
33.5
28.6
12.9
32.9
27.9
12.6
32.6
27.4
12.4
December 9, 2008
IDT82V3285
8.4
WAN PLL
TQFP EPAD THERMAL RELEASE PATH
by the solder mask, should be at least the same size/shape as the
exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed on the PCB
between the outer edges of the land pattern and the inner edges of pad
pattern for the leads to avoid any shorts.
In order to maximize both the removal of heat from the package and
the electrical performance, a land pattern must be incorporated on the
Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in Figure 27. The solderable area on the PCB, as defined
SOLDER
PIN
PIN
PAD
EXPOSED HEAT SLUG
GROUND
PLANE
THERMAL
VIA
SOLDER
LAND
PATTERN
SOLDER
PIN
PIN
PAD
(GROUND PAD)
Figure 27. Assembly for Expose Pad thermal Release Path (Side View)
nected to ground as possible. It is also recommended that the via
diameter should be 12 to 13mils (0.30 to 0.33mm) with 1 oz copper via
barrel plating. This is desirable to avoid any solder wicking inside the via
during the soldering process which may result in voids in solder between
the exposed pad/slug and the thermal land. Precautions should be taken
to eliminate any solder voids between the exposed heat slug and the
land pattern. Note: These recommendations are to be used as a guideline only. For further information, please refer to the Application Note on
the Surface Mount Assembly of Amkor’s Thermally/Electrically Enhance
Leadfame Base Package, Amkor Technology.
While the land pattern on the PCB provides a means of heat transfer
and electrical grounding from the package to the board through a solder
joint, thermal vias are necessary to effectively conduct from the surface
of the PCB to the ground plane(s). The land pattern must be connected
to ground through these vias. The vias act as ‘heat pipes’. The number
of vias (i.e. ‘heat pipes’) are application specific and dependent upon the
package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. Maximum thermal
and electrical performance is achieved when an array of vias is incorporated in the land pattern. It is recommended to use as many vias con-
Thermal Management
128
December 9, 2008
IDT82V3285
WAN PLL
9
ELECTRICAL SPECIFICATIONS
9.1
ABSOLUTE MAXIMUM RATING
Table 44: Absolute Maximum Rating
Symbol
Parameter
Min
Max
Unit
VDD
Supply Voltage VDD
-0.5
3.6
V
VIN
Input Voltage (non-supply pins)
5.5
V
VOUT
Output Voltage (non-supply pins)
5.5
V
TA
Ambient Operating Temperature Range
-40
+85
°C
TSTOR
Storage Temperature
-50
+150
°C
9.2
RECOMMENDED OPERATION CONDITIONS
Table 45: Recommended Operation Conditions
Symbol
Parameter
Min
Typ
Max
Unit
VDD
Power Supply (DC voltage) VDD
3.0
3.3
3.6
V
TA
Ambient Temperature Range
-40
+85
°C
IDD
Supply Current
455
528
mA
PTOT
Total Power Dissipation
1.5
1.9
W
Electrical Specifications
129
Test Condition
Exclude the loading
current and power
December 9, 2008
IDT82V3285
WAN PLL
9.3
I/O SPECIFICATIONS
9.3.1
CMOS INPUT / OUTPUT PORT
From Table 46 to Table 49, VDD is 3.3 V.
Table 46: CMOS Input Port Electrical Characteristics
Parameter
Description
Min
VIH
Input Voltage High
0.7VDD
VIL
Input Voltage Low
IIN
Input Current
VIN
Input Voltage
Typ
Max
Unit
Test Condition
V
-0.5
0.2VDD
V
10
µA
5.5
V
Max
Unit
Table 47: CMOS Input Port with Internal Pull-Up Resistor Electrical Characteristics
Parameter
Description
Min
VIH
Input Voltage High
0.7VDD
VIL
Input Voltage Low
PU
Pull-Up Resistor
IIN
Input Current
VIN
Input Voltage
Typ
Test Condition
V
10
-0.5
0.2VDD
V
80
KΩ
250
µA
5.5
V
Table 48: CMOS Input Port with Internal Pull-Down Resistor Electrical Characteristics
Parameter
Description
Min
VIH
Input Voltage High
0.7VDD
VIL
Input Voltage Low
PD
Pull-Down Resistor
IIN
Input Current
VIN
Input Voltage
Typ
Max
-0.5
Test Condition
V
0.2VDD
10
5
100
Unit
80
40
300
350
700
40
5.5
V
other CMOS input port with internal pull-down resistor
TRST and TCK pin
A[6:0], AD[7:0] pins
other CMOS input port with internal pull-down resistor
TRST and TCK pin
A[6:0], AD[7:0] pins
KΩ
µA
V
Table 49: CMOS Output Port Electrical Characteristics
Application Pin
Parameter
Description
Min
VOH
Output Voltage High
VOL
Output Voltage Low
tR
Rise time
3
tF
Fall time
3
Output Clock
Typ
Max
Unit
Test Condition
2.4
VDD
V
IOH = 8 mA
0
0.4
V
IOL = 8 mA
4
ns
15 pF
4
ns
15 pF
2.5
VDD
V
IOH = 4 mA
0
0.4
V
IOL= 4 mA
VOH
Output Voltage High
VOL
Output Voltage Low
tR
Rise Time
10
ns
50 pF
tF
Fall Time
10
ns
50 pF
Other Output
Electrical Specifications
130
December 9, 2008
IDT82V3285
WAN PLL
9.3.2
PECL / LVDS INPUT / OUTPUT PORT
9.3.2.1
PECL Input / Output Port
130 Ω 82 Ω
VDD (+ 3.3 V)
GND
50 Ω (transmission line)
2 kHz
OUT4_POS
to
667 MHz
OUT4_NEG
50 Ω (transmission line)
VDD (+ 3.3 V)
GND
130 Ω 82 Ω
VDD (+ 3.3 V)
50 Ω (transmission line)
130 Ω
IN3_POS
82 Ω
2 kHz
to
667 MHz
GND
130 Ω 82 Ω
VDD (+ 3.3 V)
GND
50 Ω (transmission line)
2
kHz
OUT5_POS
to
667 MHz
OUT5_NEG
50 Ω (transmission line)
VDD (+ 3.3 V)
GND
130 Ω 82 Ω
VDD (+ 3.3 V)
50 Ω (transmission line)
130 Ω
IN3_NEG
82 Ω
GND
VDD (+ 3.3 V)
50 Ω (transmission line)
Figure 29. Recommended PECL Output Port Line Termination
130 Ω
IN4_POS
82 Ω
2 kHz
to
667 MHz
GND
VDD (+ 3.3 V)
50 Ω (transmission line)
130 Ω
IN4_NEG
82 Ω
GND
Figure 28. Recommended PECL Input Port Line Termination
Electrical Specifications
131
December 9, 2008
IDT82V3285
WAN PLL
Table 50: PECL Input / Output Port Electrical Characteristics
Parameter
Description
Min
Max
Unit
VDD - 2.5
VDD - 0.5
V
VDD - 2.4
VDD - 0.4
V
Input Differential Voltage
0.1
1.4
V
VIL_S
Input Low Voltage, Single-ended Input 2
VDD - 2.4
VDD - 1.5
V
VIH_S
VDD - 1.3
VDD - 0.5
V
IIH
Input High Voltage, Single-ended Input 2
Input High Current, Input Differential Voltage VID = 1.4 V
-10
10
µA
IIL
Input Low Current, Input Differential Voltage VID = 1.4 V
-10
10
µA
VOL
Output Voltage Low 3
VDD - 2.1
VDD - 1.62
V
VOH
Output Voltage High 3
VDD - 1.25
VDD - 0.88
V
VOD
Output Differential Voltage3
580
900
mV
tRISE
Output Rise time (20% to 80%)
200
300
pS
tFALL
Output Fall time (20% to 80%)
200
300
pS
tSKEW
Output Differential Skew
50
pS
VIL
Input Low Voltage, Differential Inputs
1
VIH
Input High Voltage, Differential Inputs 1
VID
Typ
Test Condition
Note:
1. Assuming a differential input voltage of at least 100 mV.
2. Unused differential input terminated to VDD-1.4 V.
3. With 50 Ω load on each pin to VDD-2 V, i.e. 82 Ω to GND and 130 Ω to VDD.
Electrical Specifications
132
December 9, 2008
IDT82V3285
9.3.2.2
WAN PLL
LVDS Input / Output Port
50 Ω (transmission line)
2 kHz
to
667 MHz
OUT4_POS
100 Ω
IN3_POS
100 Ω
50 Ω (transmission line)
50 Ω (transmission line)
OUT4_NEG
IN3_NEG
OUT5_POS
50 Ω (transmission line)
IN4_POS
2 kHz
to
100 Ω
667 MHz
IN4_NEG
50 Ω (transmission line)
50 Ω (transmission line)
50 Ω (transmission line)
100 Ω
OUT5_NEG
50 Ω (transmission line)
2 kHz
to
667 MHz
2 kHz
to
667 MHz
Figure 31. Recommended LVDS Output Port Line Termination
Figure 30. Recommended LVDS Input Port Line Termination
Table 51: LVDS Input / Output Port Electrical Characteristics
Parameter
Description
VCM
Min
Typ
Max
Unit
VDIFF
Input Common-mode Voltage Range
0
1200
2400
mV
Input Peak Differential Voltage
100
900
mV
-100
100
mV
Test Condition
VIDTH
Input Differential Threshold
RTERM
External Differential Termination Impedance
95
105
Ω
VOH
Output Voltage High
1350
1475
mV
VOL
Output Voltage Low
925
1100
mV
RLOAD = 100 Ω ± 1%
100
RLOAD = 100 Ω ± 1%
VOD
Differential Output Voltage
250
400
mV
RLOAD = 100 Ω ± 1%
VOS
Output Offset Voltage
1125
1275
mV
RLOAD = 100 Ω ± 1%
80
120
Ω
VCM = 1.0 V or 1.4 V
RO
Differential Output Impedance
∆RO
RO Mismatch between A and B
20
%
VCM = 1.0 V or 1.4 V
∆VOD
Change in VOD between Logic 0 and Logic 1
25
mV
RLOAD = 100 Ω ± 1%
25
mV
RLOAD = 100 Ω ± 1%
100
∆VOS
Change in VOS between Logic 0 and Logic 1
ISA, ISB
Output Current
24
mA
Driver shorted to GND
ISAB
Output Current
12
mA
Driver shorted together
tRISE
Output Rise time (20% to 80%)
200
300
pS
RLOAD = 100 Ω ± 1%
tFALL
Output Fall time (20% to 80%)
200
300
pS
RLOAD = 100 Ω ± 1%
tSKEW
Output Differential Skew
50
pS
RLOAD = 100 Ω ± 1%
Electrical Specifications
133
December 9, 2008
IDT82V3285
9.4
WAN PLL
JITTER & WANDER PERFORMANCE
Table 52: Output Clock Jitter Generation
Test Definition 1
Peak to Peak
Typ
RMS
Typ
N x 2.048MHz without APLL
N x 2.048MHz with T0/T4 APLL
N x 1.544 MHz without APLL
N x 1.544 MHz with T0/T4 APLL
44.736 MHz without APLL
44.736 MHz with T0/T4 APLL
34.368 MHz without APLL
34.368 MHz with T0/T4 APLL
<2 ns
<1 ns
<2 ns
<1 ns
<2 ns
<1 ns
<2 ns
<1 ns
<200 ps
<100 ps
<200 ps
<100 ps
<200 ps
<100 ps
<200 ps
<100 ps
0.004 UI p-p 0.001 UI RMS
OC-3
(Chip T0 DPLL + T0/T4 APLL) 6.48 MHz, 19.44 MHz, 25.92
0.004 UI p-p 0.001 UI RMS
MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz, 155.52 MHz,
311.04 MHz, 622.08 MHz output
0.001 UI p-p 0.001 UI RMS
0.018 UI p-p 0.007 UI RMS
OC-12
(Chip T0 DPLL + T0/T4 APLL) 6.48 MHz, 19.44 MHz, 25.92
MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz, 155.52 MHz,
0.028 UI p-p 0.009 UI RMS
311.04 MHz, 622.08 MHz output + Intel GD16523 + Optical
transceiver)
0.002 UI p-p 0.001 UI RMS
STM-16
0.162 UI p-p 0.03 UI RMS
(Chip T0 DPLL + T0/T4 APLL) 6.48 MHz, 19.44 MHz, 25.92
MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz, 155.52 MHz,
311.04 MHz, 622.08 MHz output + Intel GD16523 + Optical
0.01 UI p-p 0.009 UI RMS
transceiver)
Note
Test Filter
See Table 53: Output Clock Phase Noise for details
See Table 53: Output Clock Phase Noise for details
See Table 53: Output Clock Phase Noise for details
See Table 53: Output Clock Phase Noise for details
GR-253, G.813 Option 2
limit 0.1 UI p-p
(1 UI-6430 ps)
G.813 Option 1, G.812
limit 0.5 UI p-p
(1 UI-6430 ps)
G.813 Option 1
limit 0.1 UI p-p
(1 UI-6430 ps)
GR-253, G.813 Option 2
limit 0.1 UI p-p
(1 UI-1608 ps)
G.813 Option 1, G.812
limit 0.5 UI p-p
(1 UI-1608 ps)
G.813 Option 1, G.812
limit 0.1 UI p-p
(1 UI-160 8ps)
G.813 Option 1, G.812
limit 0.5 UI p-p
(1 UI-402 ps)
G.813 Option 1, G.812
limit 0.1 UI p-p
(1 UI-402 ps)
20 Hz - 100 kHz
20 Hz - 100 kHz
10 Hz - 40 kHz
10 Hz - 40 kHz
100 Hz - 800 kHz
100 Hz - 800 kHz
10 Hz - 400 kHz
10 Hz - 400 kHz
12 kHz - 1.3 MHz
500 Hz - 1.3 MHz
65 kHz - 1.3 MHz
12 kHz - 5 MHz
1 kHz - 5 MHz
250 kHz - 5 MHz
5 kHz - 20 MHz
1 MHz - 20 MHz
Note:
1. CMAC E2747 TCXO is used.
Electrical Specifications
134
December 9, 2008
IDT82V3285
WAN PLL
Table 53: Output Clock Phase Noise
Output Clock 1
@100Hz Offset
Typ
@1kHz Offset
Typ
622.08 MHz (T0 DPLL + T0/T4 APLL)
155.52 MHz (T0 DPLL + T0/T4 APLL)
38.88 MHz (T0 DPLL + T0/T4 APLL)
16E1 (T0/T4 APLL)
16T1 (T0/T4 APLL)
E3 (T0/T4 APLL)
T3 (T0/T4 APLL)
-70
-82
-94
-94
-95
-93
-92
-86
-98
-110
-110
-112
-109
-108
@10kHz Offset @100kHz Offset
Typ
Typ
-95
-107
-118
-118
-120
-116
-116
-100
-112
-124
-125
-127
-124
-122
@1MHz Offset @5MHz Offset
Typ
Typ
-107
-119
-131
-131
-132
-131
-126
-128
-140
-143
-142
-143
-138
-141
Unit
dBC/Hz
dBC/Hz
dBC/Hz
dBC/Hz
dBC/Hz
dBC/Hz
dBC/Hz
Note:
1. CMAC E2747 TCXO is used.
Table 54: Input Jitter Tolerance (155.52 MHz)
Table 56: Input Jitter Tolerance (2.048 MHz)
Jitter Frequency
Jitter Tolerance Amplitude (UI p-p)
Jitter Frequency
Jitter Tolerance Amplitude (UI p-p)
12 µHz
178 µHz
1.6 mHz
15.6 mHz
0.125 Hz
19.3 Hz
500 Hz
6.5 kHz
65 kHz
1.3 MHz
> 2800
> 2800
> 311
> 311
> 39
> 39
> 1.5
> 1.5
> 0.15
> 0.15
1 Hz
5 Hz
20 Hz
300 Hz
400 Hz
700 Hz
2400 Hz
10 kHz
50 kHz
100 kHz
150
140
130
40
33
18
5.5
1.3
0.4
0.4
Table 55: Input Jitter Tolerance (1.544 MHz)
Table 57: Input Jitter Tolerance (8 kHz)
Jitter Frequency
Jitter Tolerance Amplitude (UI p-p)
Jitter Frequency
Jitter Tolerance Amplitude (UI p-p)
1 Hz
5 Hz
20 Hz
300 Hz
400 Hz
700 Hz
2400 Hz
10 kHz
40 kHz
150
140
130
38
25
15
5
1.2
0.5
1 Hz
5 Hz
20 Hz
300 Hz
400 Hz
700 Hz
2400 Hz
3600 Hz
0.8
0.7
0.6
0.16
0.14
0.07
0.02
0.01
Electrical Specifications
135
December 9, 2008
IDT82V3285
WAN PLL
Table 58: T0 DPLL Jitter Transfer & Damping Factor
Table 59: T4 DPLL Jitter Transfer & Damping Factor
3 dB Bandwidth
Programmable Damping Factor
3 dB Bandwidth
Programmable Damping Factor
0.5 mHz
1 mHz
2 mHz
4 mHz
8 mHz
15 mHz
30 mHz
60 mHz
0.1 Hz
0.3 Hz
0.6 Hz
1.2 Hz
2.5 Hz
4 Hz
8 Hz
18 Hz
35 Hz
70 Hz
560 Hz
1.2, 2.5, 5, 10, 20
1.2, 2.5, 5, 10, 20
1.2, 2.5, 5, 10, 20
1.2, 2.5, 5, 10, 20
1.2, 2.5, 5, 10, 20
1.2, 2.5, 5, 10, 20
1.2, 2.5, 5, 10, 20
1.2, 2.5, 5, 10, 20
1.2, 2.5, 5, 10, 20
1.2, 2.5, 5, 10, 20
1.2, 2.5, 5, 10, 20
1.2, 2.5, 5, 10, 20
1.2, 2.5, 5, 10, 20
1.2, 2.5, 5, 10, 20
1.2, 2.5, 5, 10, 20
1.2, 2.5, 5, 10, 20
1.2, 2.5, 5, 10, 20
1.2, 2.5, 5, 10, 20
1.2, 2.5, 5, 10, 20
18 Hz
35 Hz
70 Hz
560 Hz
1.2, 2.5, 5, 10, 20
1.2, 2.5, 5, 10, 20
1.2, 2.5, 5, 10, 20
1.2, 2.5, 5, 10, 20
Electrical Specifications
136
December 9, 2008
IDT82V3285
9.5
WAN PLL
OUTPUT WANDER GENERATION
template
template
tested result
tested result
Figure 32. Output Wander Generation
Electrical Specifications
137
December 9, 2008
IDT82V3285
9.6
WAN PLL
INPUT / OUTPUT CLOCK TIMING
The inputs and outputs are aligned ideally. But due to the circuit delays, there is delay between the inputs and outputs.
8 kHz Input Clock
t1
8 kHz Output Clock
6.48 MHz Input Clock
t2
6.48 MHz Output Clock
19.44 MHz Input Clock
t3
19.44 MHz Output Clock
25.92 MHz Input Clock
t4
25.92 MHz Output Clock
38.88 MHz Input Clock
t5
38.88 MHz Output Clock
51.84 MHz Input Clock
t6
51.84 MHz Output Clock
Figure 33. Input / Output Clock Timing
Table 60: Input/Output Clock Timing 3
Symbol
Typical Delay 1 (ns)
Peak to Peak Delay Variation 2 (ns)
t1
4
1.6
t2
1
1.6
t3
1
1.6
t4
2
1.6
t5
1.4
1.6
t6
3
1.6
Note:
1. Typical delay provided as reference only.
2. ‘Peak to Peak Delay Variation’ is the delay variation that is guaranteed not to be exceeded for IN5 in Master/Slave operation.
3. Tested when IN5 is selected.
Electrical Specifications
138
December 9, 2008
IDT82V3285
9.7
WAN PLL
OUTPUT CLOCK TIMING
MFRSYNC_2K/
FRSYNC_8K
N X T1 (1.544 MHz)
t1
N X E1 (2.048 MHz)
t2
E3 (34.368 MHz)
t3
t4
T3 (44.736 MHz)
t5
6.48 MHz
t6
19.44 MHz
t7
25.92 MHz
t8
38.88 MHz
t9
51.84 MHz
t10
77.76 MHz
t11
155.52 MHz
t12
311.04 MHz
t13
622.08 MHz
Figure 34. Output Clock Timing
Table 61: Output Clock Timing
Symbol
Typical Delay (ns)
Peak to Peak Delay Variation (ns)
t1
0
2
t2
0
2
t3
0
2
t4
0
2
t5
0
2
t6
0
2
t7
0
2
t8
0
2
2
t9
0
t10
0
2
t11
0
1.5
t12
0
1.5 (not recommended to use)
t13
0
1.5 (not recommended to use)
Electrical Specifications
139
December 9, 2008
Glossary
3G
---
Third Generation
ADSL
---
Asymmetric Digital Subscriber Line
APLL
---
Analog Phase Locked Loop
ATM
---
Asynchronous Transfer Mode
BITS
---
Building Integrated Timing Supply
CMOS
---
Complementary Metal-Oxide Semiconductor
DCO
---
Digital Controlled Oscillator
DPLL
---
Digital Phase Locked Loop
DSL
---
Digital Subscriber Line
DSLAM
---
Digital Subscriber Line Access MUX
DWDM
---
Dense Wavelength Division Multiplexing
EPROM
---
Erasable Programmable Read Only Memory
GPS
---
Global Positioning System
GSM
---
Global System for Mobile Communications
IIR
---
Infinite Impulse Response
IP
---
Internet Protocol
ISDN
---
Integrated Services Digital Network
JTAG
---
Joint Test Action Group
LPF
---
Low Pass Filter
LVDS
---
Low Voltage Differential Signal
MTIE
---
Maximum Time Interval Error
MUX
---
Multiplexer
OBSAI
---
Open Base Station Architecture Initiative
OC-n
---
Optical Carried rate, n = 1, 3, 12, 48, 192, 768; 51 Mbit/s, 155 Mbit/s, 622 Mbit/s, 2.5 Gbit/s, 10 Gbit/s, 40 Gbit/s.
PBO
---
Phase Build-Out
PDH
---
Plesiochronous Digital Hierarchy
Glossary
140
December 9, 2008
IDT82V3285
WAN PLL
PECL
---
Positive Emitter Coupled Logic
PFD
---
Phase & Frequency Detector
PLL
---
Phase Locked Loop
RMS
---
Root Mean Square
PRS
---
Primary Reference Source
SDH
---
Synchronous Digital Hierarchy
SEC
---
SDH / SONET Equipment Clock
SMC
---
SONET Minimum Clock
SONET
---
Synchronous Optical Network
SSU
---
Synchronization Supply Unit
STM
---
Synchronous Transfer Mode
TCM-ISDN
---
Time Compression Multiplexing Integrated Services Digital Network
TDEV
---
Time Deviation
UI
---
Unit Interval
WLL
---
Wireless Local Loop
Glossary
141
December 9, 2008
Index
A
Frequency Hard Alarm .................................................................22, 27
Averaged Phase Error ........................................................................ 32
Frequency Hard Alarm Threshold ...................................................... 22
B
H
Bandwidths and Damping Factors ..................................................... 32
Acquisition Bandwidth and Damping Factor ............................... 32
Locked Bandwidth and Damping Factor ..................................... 32
Starting Bandwidth and Damping Factor .................................... 32
Hard Limit ........................................................................................... 25
Holdover Frequency Offset ................................................................ 33
C
IIR ...................................................................................................... 33
Calibration .......................................................................................... 18
Input Clock Frequency ....................................................................... 22
Coarse Phase Loss ............................................................................ 25
Input Clock Selection ......................................................................... 23
Automatic selection ..............................................................24, 27
External Fast selection .........................................................23, 27
Forced selection ...................................................................24, 27
I
Crystal Oscillator ................................................................................ 18
Current Frequency Offset ................................................................... 32
Internal Leaky Bucket Accumulator ................................................... 21
Bucket Size ................................................................................ 21
Decay Rate ................................................................................ 21
Lower Threshold ........................................................................ 21
Upper Threshold ........................................................................ 21
D
DCO ................................................................................................... 32
Division Factor .................................................................................... 20
DPLL Hard Alarm ............................................................................... 25
L
DPLL Hard Limit ................................................................................. 25
Limit ................................................................................................... 35
DPLL Operating Mode ................................................................. 32, 33
Free-Run mode ................................................................... 32, 33
Holdover mode .................................................................... 32, 33
Automatic Fast Averaged ................................................... 33
Automatic Instantaneous .................................................... 33
Automatic Slow Averaged .................................................. 33
Manual ................................................................................ 33
Locked mode ....................................................................... 32, 33
Temp-Holdover mode ......................................................... 32
Lost-Phase mode ....................................................................... 32
Pre-Locked mode ....................................................................... 32
Pre-Locked2 mode ..................................................................... 33
LPF .................................................................................................... 32
M
Master / Slave Application ................................................................. 44
Master / Slave Configuration .............................................................. 41
Master Clock ...................................................................................... 18
Microprocessor Interface ................................................................... 45
microprocessor interface
EPROM ...................................................................................... 46
Intel ............................................................................................ 49
Motorola ..................................................................................... 51
Multiplexed ................................................................................. 47
Serial .......................................................................................... 53
DPLL Soft Alarm ................................................................................. 25
DPLL Soft Limit .................................................................................. 25
E
N
External Sync Alarm ........................................................................... 39
No-activity Alarm ..........................................................................21, 27
F
Fast Loss ............................................................................................ 25
P
Fine Phase Loss ................................................................................. 25
PBO ................................................................................................... 35
Index
142
December 9, 2008
IDT82V3285
WAN PLL
PFD .................................................................................................... 32
R
Phase Lock Alarm ....................................................................... 26, 27
Reference Clock ................................................................................ 22
Phase Offset ....................................................................................... 35
S
Phase-compared ......................................................................... 25, 35
Selected Input Clock Switch .............................................................. 27
Non-Revertive switch ................................................................. 28
Revertive switch ......................................................................... 27
Phase-time ......................................................................................... 35
Pre-Divider ......................................................................................... 20
DivN Divider ................................................................................ 20
HF Divider ................................................................................... 20
Lock 8k Divider ........................................................................... 20
State Machine ..............................................................................29, 31
V
Validity ............................................................................................... 27
Index
143
December 9, 2008
IDT82V3285
WAN PLL
PACKAGE DIMENSIONS
Figure 35. 100-Pin EQG Package Dimensions (a) (in Millimeters)
144
December 9, 2008
IDT82V3285
WAN PLL
Figure 36. 100-Pin EQG Package Dimensions (b) (in Millimeters)
145
December 9, 2008
IDT82V3285
WAN PLL
Figure 37. EQG100 Recommended Land Pattern with Exposed Pad (in Millimeters)
146
December 9, 2008
IDT82V3285
WAN PLL
ORDERING INFORMATION
XXXXXXX
Device Type
XX
X
Process/
Temperature
Range
Blank
Industrial (-40 °C to +85 °C)
PF
PFG
EQG
Thin Quad Flatpack (TQFP, PN100)
82V3285
WAN PLL
Green Thin Quad Flatpack (TQFP, PNG100)
Green Thin Quad Flatpack (TQFP, EQG100)
DATASHEET DOCUMENT HISTORY
12/09/2008 pgs. 127, 128, 129, 134, 144, 145, 146, 147
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147
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