DATASHEET IDT5V50017 LOW EMI CLOCK GENERATOR Description Features The IDT5V50017 generates a low EMI output clock from a clock input. The part is designed to dither the LCD interface clock for PDAs, printers, DTVs, scanners, modems, copiers, and others. Using IDT’s proprietary mix of analog and digital Phase-Locked Loop (PLL) technology, the device spreads the frequency spectrum of the output, reducing the frequency amplitude peaks by several dB. • • • • Packaged in 8-pin SOIC Provides a spread spectrum output clock 15 - 60 MHz operation Accepts a clock input (provides same frequency dithered output) • Down spread modulation • Peak reduction by 8 dB to 16 dB typical on 3rd through IDT offers many other clocks for computers and computer peripherals. Consult IDT when you need to remove crystals and oscillators from your board. 19th odd harmonics • Low EMI feature can be disabled • Operating voltage of 3.3 V • Advanced, low-power CMOS process Block Diagram VDD S1:0 2 PLL Clock Synthesis and Spread Spectrum Circuitry SSCLK ICLK GND IDT™ LOW EMI CLOCK GENERATOR 1 IDT5V50017 REV D 040709 IDT5V50017 LOW EMI CLOCK GENERATOR SSCG Pin Assignment Spread Direction and Percentage Select Table ICLK 1 8 VDD VDD 2 7 S0 GND 3 6 S1 SSCLK 4 5 GND S1 Pin 6 S0 Pin 7 Spread Direction Spread Percentage 0 0 1 1 0 1 0 1 OFF Down Down Down -1.0% -2.0% -3.0% 0 = connect to GND 1 = connect directly to VDD 8 pin (150 mil) SOIC Pin Descriptions Pin Number Pin Name Pin Type 1 ICLK Input 15-60 MHz clock input. 2 VDD Power Connect to +3.3 V. 3 GND Power Connect to ground. 4 SSCLK Output Clock output with spread spectrum. 5 GND Power Connect to ground. 6 S1 Input Function select 1 input. Selects spread amount and direction per table above. Internal pull-down. 7 S0 Input Function select 0 input. Selects spread amount and direction per table above. Internal pull-down. 8 VDD Power Connect to +3.3 V. IDT™ LOW EMI CLOCK GENERATOR Pin Description 2 IDT5V50017 REV D 040709 IDT5V50017 LOW EMI CLOCK GENERATOR SSCG External Components Spread Spectrum Profile The IDT5V50017 low EMI clock generator uses an optimized frequency slew rate algorithm to facilitate down stream tracking of zero delay buffers and other PLL devices. The frequency modulation amplitude is constant with variations of the input frequency. The IDT5V50017 requires a minimum number of external components for proper operation. Decoupling Capacitor A decoupling capacitor of 0.01µF must be connected between VDD and GND on pins 2 and 3, as close to these pins as possible. For optimum device performance, the decoupling capacitor should be mounted on the component side of the PCB. Avoid the use of vias in the decoupling circuit. Frequency Modulation Rate Series Termination Resistor When the PCB trace between the clock output and the load is over 1 inch, series termination should be used. To series terminate a 50Ω trace (a commonly used trace impedance) place a 33Ω resistor in series with the clock line, as close to the clock output pin as possible. The nominal impedance of the clock output is 20Ω. Time PCB Layout Recommendations For optimum device performance and lowest output phase noise, the following guidelines should be observed. 1) The 0.01µF decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as possible. No vias should be used between the decoupling capacitor and VDD pin. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. 2) To minimize EMI, the 33Ω series termination resistor (if needed) should be placed close to the clock output. 3) An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers. Other signal traces should be routed away from the IDT5V50017. This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. IDT™ LOW EMI CLOCK GENERATOR 3 IDT5V50017 REV D 040709 IDT5V50017 LOW EMI CLOCK GENERATOR SSCG Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the IDT5V50017. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Item Rating Supply Voltage, VDD 7V All Inputs and Outputs -0.5 V to VDD+0.5 V Ambient Operating Temperature 0 to +70° C Storage Temperature -65 to +150° C Junction Temperature 125° C Soldering Temperature 260° C Recommended Operation Conditions Parameter Min. Ambient Operating Temperature 0 Power Supply Voltage (measured in respect to GND) IDT™ LOW EMI CLOCK GENERATOR Typ. 4 +2.97 3.3 Max. Units +70 °C 3.63 V IDT5V50017 REV D 040709 IDT5V50017 LOW EMI CLOCK GENERATOR SSCG DC Electrical Characteristics Unless stated otherwise, VDD = 3.3 V, Ambient Temperature 0 to +70° C Parameter Symbol Conditions Min. Typ. Max. Units 2.97 3.3 3.63 V 17 20 mA Operating Voltage VDD Supply Current IDD ICLK=50 MHz, Note 1 Input High Voltage VIH S1: S0 Input Low Voltage VIL S1: S0 Output High Voltage VOH IOH = -6 mA 2.4 V IOH =- 20 mA 2.0 V Output Low Voltage VOL 2.0 V 0.8 V IOL = 6 mA 0.4 V IOL = 20 mA 1.2 V 5 pF Input Capacitance CIN1 All inputs Pull-down Resistance RPD S1, S0 3 4 240 kΩ Note 1: CL = 15 pF. AC Electrical Characteristics Unless stated otherwise, VDD = 3.3 V, Ambient Temperature 0 to +70° C Parameter Symbol Conditions Input Clock Frequency Min. Typ. Max. Units 15 45 60 MHz 50 55 % Output Clock Duty Cycle All outputs Short term Cycle to cycle Jitter ICLK=50 MHz, SS OFF 50 100 ps ICLK=50 MHz, SS ON 80 100 ps Short term Period Jitter SS OFF 50 100 ps One-sigma jitter SS OFF 15 ps Output Rise Time tR 20% to 80%, CL=15 pF, 50 MHz 0.9 ns Output Fall Time tF 80% to 20%, CL=15 pF, 50 MHz 0.9 ns ICLK=20 MHz 32 kHz Modulation Frequency Note1: Cycle-to-cycle jitter is the maximum observed variation between two adjacent cycle’s periods over a defined number of observed cycles. The JEDEC specification for the number of cycles observed is 1000 cycles. IDT™ LOW EMI CLOCK GENERATOR 5 IDT5V50017 REV D 040709 IDT5V50017 LOW EMI CLOCK GENERATOR SSCG Thermal Characteristics Parameter Thermal Resistance Junction to Ambient Symbol Conditions Min. Typ. Max. Units θJA Still air 150 ° C/W θJA 1 m/s air flow 140 ° C/W θJA 3 m/s air flow 120 ° C/W 40 ° C/W 20 ° C/W Thermal Resistance Junction to Case θJC Thermal Resistance Junction to Top of Case ΨJT Still air Marking Diagram 8 5 IDT5V50 017DCG #YYWW$ 1 4 Notes: 1. YYWW is the digits of the year and week that the part was assembled. 2. “$” is the assembly mark code. 3. “G” designates RoHS compliant package. 4. “#” is the lot code. 5. Bottom marking: country of origin if not USA. IDT™ LOW EMI CLOCK GENERATOR 6 IDT5V50017 REV D 040709 IDT5V50017 LOW EMI CLOCK GENERATOR SSCG Package Outline and Package Dimensions (8-pin SOIC, 150 Mil. Body) Package dimensions are kept current with JEDEC Publication No. 95 Millimeters 8 Symbol E Min A A1 B C D E e H h L α H INDEX AREA 1 2 D A Inches Max Min 1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 4.80 5.00 3.80 4.00 1.27 BASIC 5.80 6.20 0.25 0.50 0.40 1.27 0° 8° Max .0532 .0688 .0040 .0098 .013 .020 .0075 .0098 .1890 .1968 .1497 .1574 0.050 BASIC .2284 .2440 .010 .020 .016 .050 0° 8° h x 45 A1 C -Ce B SEATING PLANE L .10 (.004) C Ordering Information Part / Order Number Marking Shipping Packaging Package Temperature 5V50017DCG 5V50017DCG8 see page 6 Tubes Tape and Reel 8-pin SOIC 8-pin SOIC 0 to +70° C 0 to +70° C Parts that are ordered with a "G" after the two-letter package code are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT™ LOW EMI CLOCK GENERATOR 7 IDT5V50017 REV D 040709 IDT5V50017 LOW EMI CLOCK GENERATOR SSCG Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 www.idt.com/go/clockhelp Corporate Headquarters Integrated Device Technology, Inc. www.idt.com © 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA