RENESAS HD66789

Preliminary
HD66789
528-channel, One-chip Driver for Amorphous TFT Panels
with 262,144-color display RAM, Power Supply Circuit, and
Gate Circuit
REJxxxxxxx-xxxx
Rev.0.12
10 June, 2003
Description ......................................................................................................... 5
Features
......................................................................................................... 6
Block Diagram .................................................................................................... 7
Pin Functions ...................................................................................................... 8
PAD arrangement................................................................................................ 14
PAD Coordinate.................................................................................................. 15
BUMP Arrangements.......................................................................................... 17
Block Function.................................................................................................... 18
1. System Interface ............................................................................................................... 18
2. External Display Interface ................................................................................................ 19
3. Bit Operations ................................................................................................................... 19
4. Address Counter (AC) ...................................................................................................... 19
5. Graphics RAM (GRAM) .................................................................................................. 19
7. Timing Generator.............................................................................................................. 19
8. Oscillation Circuit (OSC) ................................................................................................. 20
9. LCD Driver Circuit........................................................................................................... 20
10.Liquid crystal drive power supply circuit ......................................................................... 20
GRAM Address MAP......................................................................................... 21
Instructions ......................................................................................................... 28
Outline ................................................................................................................................... 28
Instructions ............................................................................................................................ 29
Index ...................................................................................................................................... 29
Status Read ............................................................................................................................ 30
Start Oscillation (R00h) ......................................................................................................... 30
Driver Output Control (R01h)................................................................................................ 30
LCD Driving Wave Form Control (R02h)............................................................................. 32
Entry Mode (R03h) Compare Register 1 (R04h) Compare Register 2 (R05h) ..................... 33
Rev.0.12, May.08.2003, page 1 of 156
HD66789
Preliminary
Display Control 1 (R07h)....................................................................................................... 36
Display Control 2 (R08h)....................................................................................................... 38
Display control 3 (R09h) ....................................................................................................... 40
Frame Cycle Control (R0Bh)................................................................................................. 41
External Display Interface Control (R0Ch) ........................................................................... 44
Power Control 1 (R10h) Power Control 2 (R11h) ................................................................. 48
Power Control 3 (R12h) Power Control 4 (R13h) ................................................................. 51
RAM Address Set (R21h)...................................................................................................... 53
Write Data to GRAM (R22h)................................................................................................. 54
RAM Access through RGB-I/F and System I/F..................................................................... 59
Read Data Read from GRAM (R22h).................................................................................... 60
RAM Write Data Mask (R23h) RAM Write Data Mask (R24h) ........................................... 63
γ Control (R30h to R39h)....................................................................................................... 64
Gate Scan Position (R40h)..................................................................................................... 65
Vertical Scroll Control (R41h)............................................................................................... 66
1st-Screen Drive Position (R42h) 2nd-Screen Drive Position (R43h)................................... 66
Horizontal RAM Address Position (R44h) Vertical RAM Address Position (R45h) ............ 67
Instruction List (T.B.D.) ..................................................................................... 68
Reset Function .................................................................................................... 69
Interface Specifications....................................................................................... 71
System Interface.................................................................................................. 73
80-system 18-bit interface...................................................................................................... 74
80-system 16-bit interface...................................................................................................... 75
80-system 9-bit interface........................................................................................................ 76
Data transmission synchronizing in 9-bit bus interface mode................................................ 77
80-system 8-bit interface........................................................................................................ 78
Data transmission synchronizing in 8-bit bus interface mode................................................ 80
Serial Peripheral interface (SPI) ............................................................................................ 81
VSYNC Interface................................................................................................ 84
Conditions on using VSYNC interface .................................................................................. 86
External Display Interface .................................................................................. 88
RGB interface ........................................................................................................................ 88
VLD and ENABLE signals.................................................................................................... 89
RGB interface timing ............................................................................................................. 89
Moving picture display .......................................................................................................... 91
RAM access through system interface in RGB-I/F mode ...................................................... 91
6-bit RGB interface................................................................................................................ 92
Data transmission synchronization in 6-bit RGB interface mode .......................................... 92
16-bit RGB interface.............................................................................................................. 93
18-bit RGB interface.............................................................................................................. 94
Conditions on using external display interface ...................................................................... 95
Rev.0.12, May 09 2003, page 2 of 156
HD66789
Preliminary
Timing Interfacing with Liquid Crystal Panel Signals ....................................... 97
Scan Mode Setting .............................................................................................. 99
High-Speed Burst RAM Write Function ............................................................ 100
Conditions on using high-speed RAM write mode ................................................................ 101
High-Speed RAM Write with Window Address.................................................................... 103
Window Address Function ................................................................................. 105
Graphics Operation Function .............................................................................. 106
Graphics Operation ................................................................................................................ 106
Write-data Mask Function ..................................................................................................... 107
Graphics Operation Processing.............................................................................................. 107
γ-Correction Function ......................................................................................... 111
Configuration of Grayscale Amplifier ................................................................................... 112
γ-Correction Register ............................................................................................................. 114
Ladder resistors and 8-to-1 selector ....................................................................................... 115
Variable resistor..................................................................................................................... 115
Relationship between RAM data and output level................................................................. 121
8-color Display Mode ......................................................................................... 122
System Configuration ......................................................................................... 124
Configuration of Power Generation Circuit........................................................ 125
Specification of External Elements Connected to HD66789 Power Supply ...... 126
Instruction Setting Flow...................................................................................... 127
Power Supply Setting Flow ................................................................................ 129
Pattern Diagram for Voltage Setting................................................................... 130
Oscillation Circuit............................................................................................... 131
n-raster-row Inversion AC Drive ........................................................................ 132
Interlaced Drive .................................................................................................. 133
AC Timing ......................................................................................................... 135
Frame-Frequency Adjustment Function ............................................................. 136
Relationship between Liquid Crystal Drive Duty and Frame Frequency .............................. 136
Screen -split Drive Function ............................................................................... 137
Rev.0.12, May 09 2003, page 3 of 156
HD66789
Preliminary
Conditions on Setting the 1st/2nd Screen Drive Position Register ........................................ 138
Absolute Maximum Values ................................................................................ 140
Electric Characteristics (T.B.D.)......................................................................... 141
DC Characteristics ................................................................................................................. 141
AC Characteristics ................................................................................................................. 142
80-system Bus Interface Timing Characteristics.................................................................... 142
Clock Synchronized Serial Interface Timing Characteristics ................................................ 145
Reset Timing Characteristics (VCC = 1.8 to 3.7 V) ................................................................ 146
RGB interface timing characteristics ..................................................................................... 147
Liquid crystal driver output characteristics............................................................................ 149
Electrical Characteristics Notes ............................................................................................. 149
Load circuits for measuring AC characteristics ..................................................................... 152
80-system Bus Operation ....................................................................................................... 152
Clock Synchronized Serial Interface Operation..................................................................... 153
RESET Operation .................................................................................................................. 153
RGB I/F Operation................................................................................................................. 154
Liquid crystal Driver Output.................................................................................................. 154
Rev.0.12, May 09 2003, page 4 of 156
HD66789
Preliminary
Description
The HD66789 handles 262,144 TFT colors and can drive a TFT color liquid crystal display of 176 RGB x
240 dots with an incorporated RAM compliant to graphics display of 176 RGB x 240 dots at maximum,
and a 528-channel source driver outputs. The HD66789 incorporates a gate driver and a power circuit for
driving liquid crystal display to drive a TFT panel with a single chip.
The HD66789’s bit-operation functions, 8/9/16/18-bit high-speed bus interface, and high-speed RAM-write
functions enable efficient transfer of data and high-speed data update on a graphics RAM. The HD66789’s
6/16/18-bit RGB interface (VSYNC, HSYNC, DOTCLK, ENABLE, and PD 17 to 0) and VSYNC
interface (system interface + VSYNC) provide an interface for moving picture display. With a window
address function that facilitates the moving picture display in an arbitrary area and enables simultaneous
display of moving pictures and the contents of the internal RAM, the HD66789 enables moving picture
display not constrained by the still picture area. Accordingly, the data transmission is reduced to minimum,
thereby saving power consumed by a system as a whole when displaying moving pictures.
The HD66789 supports power-saving operation up to the power supply voltage of 2.4V with a voltage
follower circuit that generate voltage to drive liquid crystal. The HD66789 also incorporates 8-color
display and standby functions that allow precise power control by software. These features make this LSI
the ideal solution for any medium or small-sized portable battery-driven products such as digital cellular
phones supporting WWW browsers or small PDA, where long battery life and board size are major concern.
Rev.0.12, May 09 2003, page 5 of 156
HD66789
Preliminary
Features
•
•
•
•
•
•
•
•
•
Liquid crystal controller/driver for 262,144 TFT-color 176RGB x 240-dot graphics display
Single chip solution for a TFT display panel
System interface
– 8-/9-/16-/18-bit high-speed bus interface
– Serial Peripheral Interface (SPI)
– 8-bit transmission x 3 times (262k/65k color modes)
Interface for moving picture display
– 6-/16-/18-bit RGB interface (VSYNC, HSYNC, DOTCLK, ENABLE, PD17-0)
– VSYNC interface (System interface + VSYNC)
High-speed burst RAM write function
Window address function to write data to the rectangular area of RAM specified by the window
address
– Interface to facilitate moving picture display in an arbitrary area
– Reduce data transmission by transmitting only the data for the moving picture display area
– Simultaneous display of moving pictures and the contents of the internal RAM
Bit unit operations for processing graphics
– Write data mask function by bit
Functions for controlling abundant color displays
– Simultaneous availability of 262,144 colors with γ-correction function
– Line-unit vertical scrolling
Low-power architecture: features for low-power operation
– Vcc = 2.4 ~ 3.3 V (internal logic power supply)
–
–
–
–
–
–
•
•
•
•
•
•
•
IOVcc = 1.8 ~ 3.3 V (interface I/O power supply)
Vci = 2.5 ~ 3.3 V (analogue power supply)
DDVDH = 4.5 ~ 5.5 V (liquid-crystal drive voltage)
Power saving function (standby mode etc.)
Partial liquid crystal drive to display two screens at arbitrary positions
Voltage followers for liquid crystal drive power circuit to fend off the direct current from bleederresistors
Step-up circuit generating liquid crystal drive voltage up to 6-time scale
95,040-byte internal RAM
Incorporated liquid crystal display driver with 582 source outputs and 240 gate outputs
n-raster-row liquid crystal AC drive, enabling polarity inversion by every arbitrary number of rasterrows
Internal oscillation and hardware reset
Reversible direction of signals between RAM and source driver
Exclusive for Cst structure
Rev.0.12, May 09 2003, page 6 of 156
HD66789
Preliminary
Block Diagram
HSYNC
ENABLE
PD0~17
Vcc
7
16
CS*
System Interface
VLD
-18 bits
-16 bits
- 9 bits
- 8 bits
- clock
synchronization
serial (SPI)
- 3-transmission
mode
18
18
18
M
Read data
latch
18
VGH,
VGL
G1
~ G240
18
Voltage
Adjustment
circuit
Step-up
circuit 1
Power supply circuit
Step-up
circuit 2
γ
VREG1
OUT
Vcom
VcomL Vcom
VREG1OUT
VcomH
Rev.0.12, May 09 2003, page 7 of 156
Adjustment circuit
Grayscale voltage
generation circuit
VTEST
VGS VMONI
V0P,V0N,
V31P,V31N
V0-31
LCD driving circuit
Latch circuit
72
Graphics RAM
(GRAM)
95,040 bytes
DDVDH
VLOUT2
VGH
VLOUT3
VGL
VLOUT4
VCL
16
Write data
latch
RESET*
TEST1
TEST2
TS7-0
Vci1
VLOUT1
Timing generation
circuit
Bit operation
M AC driving circuit
18
18
Address
counter
(AC)
Latch circuit
RS
VSYNC, HSYNC, DCLK, ENABLE
PD17-0
Latch circuit
IM3-1,
IM0/ID
CPG
External display interface
Control
register (CR)
LCD driving circuit
(IR)
VciLVL
Vci
VciOUT
OSC1 OSC2
18
Index
WR*/SCL
RD*
DB0/SDI,
DB1/SDO,
~DB17
DOTCLK VSYNC
S1
~ S528
HD66789
Preliminary
Pin Functions
Signals
Number
of Pins
I/O
Connected
to
Functions
IM3~1, IM0/ID
4
I
GND or
IOVcc
Pins to select interfacing mode with MPU.
IM3
IM2
IM1
IM0/ID
MPU-Interface
DB Pin
Mode
GND
GND
GND
GND
Setting disabled
_
GND
GND
GND
IOVcc
Setting disabled
_
GND
GND
IOVcc
GND
GND
GND
IOVcc
IOVcc
80-system 16-bit
DB17~10,
interface
DB8~1
80-system 8-bit
DB17 ~10
interface
GND
IOVcc
GND
ID
Serial Peripheral
DB1~ 0
Interface (SPI)
GND
IOVcc
IOVcc
*
Setting disabled
IOVcc
GND
GND
GND
Setting disabled
IOVcc
GND
GND
IOVcc
Setting disabled
IOVcc
GND
IOVcc
GND
80-system 18-bit
DB17~0
interface
GND
IOVcc
IOVcc
IOVcc
80-system 9-bit
DB17~9
interface
IOVcc
IOVcc
*
*
Setting disabled
When Serial Peripheral Interface is selected, IM0 pin is used for
the device code ID setting.
CS*
1
I
MPU
Select the HD66789.
Low: the HD6678 is selected and accessible
High: the HD66789 is not selected and not accessible
Must be fixed to the GND level while not used.
VLD
1
I
MPU
Indicate whether the data is valid or not during RAM write.
Low: Valid (Write data to RAM)
High: Invalid (Not write data to RAM)
RAM address will be updated irrespective of VLD.
Must be fixed to the GND level while not used.
This signal is available when external display interface is used.
Rev.0.12, May 09 2003, page 8 of 156
CS
VLD
RAM Write
RAM Address
0
0
Valid
Updated
0
1
Invalid
Updated
1
*
Invalid
Hold
HD66789
Preliminary
Signals
Number
of Pins
I/O
Connected
to
Functions
RS
1
I
MPU
Select register.
Low: Index/status, High: Control
Fix to the “IOVcc” or “GND” level while using SPI.
WR*/SCL
1
I
MPU
In 80-system bus interface mode, serves as a write strobe signal.
Data are written at “Low” level.
In Serial Peripheral Interface mode, serves as synchronizing
clock signal.
RD*
1
I
MPU
In 80-system bus interface mode, serves as read-strobe signal.
Data are read at the low level of the signal.
Fix to the “IOVcc” or “GND” level while using SPI.
DB0/SDI
1
I/O
MPU
18-bit parallel bi-directional data bus.
8-bit bus: DB17-DB10
9-bit bus: DB17-DB9
16-bit bus: DB17-DB10 and DB8-DB1
18-bit bus: DB17-DB0
Unused pins must be fixed to the IOVcc or GND level.
Serves as serial data input pin (SDI) in Serial Peripheral
Interface mode, where data are input on the rising edge of SCL
signal.
DB1/SDO
1
I/O
MPU
18-bit parallel bi-directional data bus.
8-bit bus: DB17-DB10
9-bit bus: DB17-DB9
16-bit bus: DB17-DB10 and DB8-DB1
18-bit bus: DB17-DB0
Unused pins must be fixed to the IOVcc or GND level.
Serves as serial data output pin (SDO) in Serial Peripheral
Interface mode, where data are output on the falling edge of the
SCL signal.
DB2~DB17
16
I/O
MPU
18-bit parallel bi-directional data bus.
8-bit bus: DB17-DB10
9-bit bus: DB17-DB9
16-bit bus: DB17-DB10 and DB8-DB1
18-bit bus: DB17-DB0
Unused pins must be fixed to the IOVcc or GND level.
ENABLE
1
I
Rev.0.12, May 09 2003, page 9 of 156
MPU
Indicate whether RAM data are valid or not when RGB interface
is used.
Low: Selected (access enabled)
High: Not selected (access disabled)
Must be fixed to the IOVcc or GND level when not used.
ENABLE signal invert the polarity according to the setting of EPL
resister.
HD66789
Preliminary
Signals
Number
of Pins
I/O
Connected
to
ENABLE
1
I
MPU
Functions
EPL
ENABLE
VLD
RAM Write
RAM Address
0
0
0
Valid
Updated
0
0
1
Invalid
Updated
0
1
*
Invalid
Held
1
0
*
Invalid
Held
1
1
0
Valid
Updated
1
1
1
Invalid
Updated
VSYNC
1
I
MPU
Frame synchronizing signal.
This signal is active low.
Must be fixed at the IOVcc level while not used.
HSYNC
1
I
MPU
Line synchronizing signal.
This signal is active low.
Must be fixed at the IOVcc level while not used.
DOTCLK
1
I
MPU
Dot-clock signal.
This signal is active low.
The timing of data input is determined at the falling edge of the
signal. Must be fixed at the IOVcc level while not used.
PD0~PD17
18
I
MPU
18-bit bus for RGB data.
6-bit bus: PD17-PD12
16-bit bus: PD17-PD13 and PD11-PD1
18-bit bus: PD17-PD0
Fix unused pins to the IOVcc or GND level.
RESET*
1
I
MPU or
reset circuit
Reset pin.
Initializes the LSI at the “Low” level.
Power-on reset required after turning on the power.
S1~S528
528
O
Liquid
Crystal
Output voltage applied to liquid crystal.
The shift direction of segment signals is changeable with SS bit.
For example, if SS = 0, RAM address “0000” is output from S1.
If SS = 1, it is output from S528.
S1, S4, S7, ... display red (R), S2, S5, S8, ... display green (G),
and S3, S6, S9, ... display blue (B) (SS = 0).
G1~G240
Vcom1, Vcom2
240
2
O
O
Liquid
Crystal
Gate output signals.
TFT
common
electrode
Power supply for TFT common electrode.
When gate lines are selected, VGH signals are output. When
gate lines are not selected, VGL are output.
When Vcom AC drive is not selected, the same level of voltage
as VcomL level is output. When Vcom AC drive is selected, the
voltage with the amplitude between VcomH and VcomL is
output. The AC frequency can be set by the M signal.
Connect to the TFT common electrode.
Rev.0.12, May 09 2003, page 10 of 156
HD66789
Preliminary
Signals
Number
of Pins
I/O
Connected
to
Functions
VcomR
1
I
Variable
resistor or
open
Reference voltage for VcomH.
When adjusting VcomH externally, VcomH internal adjusting
circuit must be halted by register setting and place a variable
resistor between VREG1OUT and GND to make an adjustment.
Otherwise, leave open and adjust VcomH by internal register
setting.
VcomH
1
O
Stabilizing
capacitor
High level of Vcom during Vcom AC drive. Connect to a
stabilizing capacitor.
VcomL
1
O
Stabilizing
capacitor
or open
Vcom voltage when Vcom AC drive is not selected.
Low level of Vcom during Vcom AC drive. Voltage can be
adjusted with internal registers. Connect to a stabilizing
capacitor. When VCOMG bit is set to LOW, a stabilizing
capacitor is not necessary because VcomL output is halted.
C11+, C11-
2
-
Step-up
capacitor
Step-up capacitor connection pins for step-up circuit 1. When
the internal step-up circuit is not used, leave open.
C12+, C12-
6
-
Step-up
capacitor
Step-up capacitor connection pins for step-up circuit 2.
Capacitor connection will be necessary depending on the stepup scale. When the internal step-up circuit is not used, leave
open.
OSC1, OSC2
2
I or O
Resistor for
the
oscillator
Connect an external resistor for R-C oscillation. When supplying
clock signals externally, it must be supplied through OSC1 and
leave OSC2 open.
FLM
1
O
MPU or
open
Frame head pulse with amplitude between GND and Vcc.
Power
supply
Power supply for analogue circuits.
Power
supply
Generates a reference voltage (VciOUT, REGP) in accordance
to the ratio set with VC2~0 registers.
C21+, C21C22+, C22-
Vci
VciLVL
1
1
I
I
Use when writing data to RAM in synchronization with FLM.
When FLM is not used, leave open.
In this case, a power supply for the VciOUT amplifier. Connect
an external power supply of 2.5~3.3V.
Connect to the same power supply as the Vci, which has
separate wiring from the VciLVL on the FPC.
REGP
1
I/O
Test pin
Test pin for VREG1OUT. Leave open.
VciOUT
1
I
Stabilizing
capacitor,
Vci1
Internal reference voltage with amplitude between Vci and GND.
Set with VC bit.
Vci1
1
I
VciOUT
Reference voltage for the step-up circuit 1.
Connect to an external power supply of 2.75V or less when the
internal reference voltage is not used.
VLOUT1
1
O
Stabilizing
capacitor,
DDVDH
Output twice stepped-up Vci1 voltage from the step-up circuit 1.
Connect to a stabilizing capacitor. VLOUT1 = 4.0~5.5V
DDVDH
1
I
VLOUT1
Power supply for source driver liquid crystal output portion. A
reference voltage for the step-up circuit 2.
Rev.0.12, May 09 2003, page 11 of 156
HD66789
Preliminary
Signals
Number
of Pins
I/O
Connected
to
Functions
VLOUT2
1
O
Stabilizing
capacitor,
VGH
Output stepped-up DDVDH voltage, which is stepped up to the
level Vci1 x 4~6 from the step-up circuit 2. The step-up scale is
determined with BT bits. Connect to a stabilizing capacitor.
VLOUT2 = max 16.5V
VGH
1
I
VLOUT2
Power supply for TFT gate drive. Connect to VLOUT2.
VLOUT3
1
O
Stabilizing
capacitor,
VGL
Output stepped-up DDVDH voltage, which is stepped up to the
level Vci1 x (- 3) ~ (-5) from the step-up circuit 2. The step-up
scale is determined with BT bits. Connect to a stabilizing
capacitor. VLOUT2 = min -16.5V
VGL
1
I
VLOUT3
Power supply for TFT gate drive. Connect to VLOUT3.
VLOUT4
1
O
Stabilizing
capacitor,
VCL
Output the Vci1 x (-1) voltage from the step-up circuit 2.
Connect to a stabilizing capacitor. VLOUT4 = 0 ~ -3.3V
VCL
1
I
VLOUT4
Power supply for VcomL drive. Connect to VLOUT4.
VREG1OUT
1
I/O
Stabilizing
capacitor
or power
supply
Reference voltage with amplitude between DDVDH and GND,
which is generated from the reference voltage internally
generated with amplitudes between Vci and GND.
The scale of the output voltage can be set with VRH bits.
VREG1OUT becomes (1) a source driver grayscale reference
voltage VDH, (2) a VcomH level reference voltage, or (3) a Vcom
amplitude reference voltage. Connect to a stabilizing capacitor.
VREG1OUT = 3.0 ~ (DDVDH – 0.5)V
Vcc
1
-
Power
supply
Power supply for a logic circuit. Vcc = 2.4~3.3V
IOVcc
1
-
Power
supply
Power supply for interface pins. IOVcc = 1.8~3.3V. IOVcc must
be turned on with the same voltage as the internal logic voltage
Vcc. When it is assembled on COG, connect to Vcc on the FPC
to avoid effects from the noise when IOVcc is used.
RVcc
1
-
Power
supply
Vcc power supply for RAM. Supply with the same potential as
the Vcc.
GND
1
-
Power
supply
Ground for the logic side. GND = 0V
AGND
1
-
Power
supply
Ground for the analog side. AGND = 0V. When assembled on
COG, connect to GND on the FPC to avoid effects from the
noise.
RGND
1
-
Power
supply
Ground for internal RAM. RGND = 0V. When assembled on
COG, connect to GND on the FPC to avoid effects from the
noise.
CGND
1
O
Opposing
GND for
external
parts
GND level output. Available as an opposing GND for external
parts (capacitors, diodes).
TEST1
1
I
GND
Test pin. Fix it to the GND level.
TEST2
1
I
GND
Test pin. Fix it to the GND level.
Rev.0.12, May 09 2003, page 12 of 156
HD66789
Preliminary
Signals
Number
of Pins
I/O
Connected
to
Functions
V0P, V31P
2
I or O
Stabilizing
capacitor
Output from internal positive polarity operational amplifier when
the operational amplifier is ON (SAP2-0 = “001”, “010”, “011”,
“100”, and “101”). Stabilize by connecting to a capacitor.
V0N, V31N
2
I or O
Stabilizing
capacitor
Output from internal negative polarity operational amplifier when
the operational amplifier is ON (SAP2-0 = “001”, “010”, “011”,
“100”, and “101”). Stabilize by connecting to a capacitor.
VGS
1
I
GND or
external
resistor
Reference level for grayscale voltage generation circuit.
open
Test pin. Leave open.
Connect to an external resistor when source driver is used to
adjust grayscale levels for each panel.
VTESTS
1
I/O
TS0~TS7
8
O
open
Test pin. Leave open.
TESTA1
1
I/O
open
Test pin for VcomH. Leave open.
TESTA2
1
I/O
open
Test pin for VcomL. Leave open.
TESTA4
1
I/O
open
Test pin for VcomL. Leave open or connect to a stabilizing
capacitor depending on the display quality.
VMONI
1
O
open
Test pin. Leave open.
IOVccDUM1~4
4
O
Input pin
Internal IOVcc level. When neighboring input pins are fixed to
the IOVcc side, short-circuit them.
IOGNDDUM1~7
7
O
Input pin
Internal GND level. When neighboring input pins are fixed to the
IOVcc side, short-circuit them.
TESTO1~2
2
-
-
Dummy pads. Leave open.
DUMMY
-
-
Dummy pad. Leave open.
DUMMYR
-
-
Dummy pad. Leave open.
Rev.0.12, May 09 2003, page 13 of 156
HD66789
Preliminary
PAD arrangement
VGLDUM4
G1
G3
G5
G7
No.1000
1
1
IOGNDDUM2
(2) 54µm×100µm
Input :
No.2 ~ No.219
(3) 31µm×77µ m
Laced LCD output side :
No.285 ~ No.936
(4) 77µ m×31µm
Laced LCD output side :
No.221 ~ No.283
No.938 ~ No.1000
n Au bump pitch : See PAD coordinate
n Au bump height :15µ m
.
n Numbers in the figure indicates numbers of
PAD coordinate
n Alignment mark
(1) Arrangement : 2 places
Coordinate (X,Y) = (-11164.7, 1110.9)
Coordinate (X,Y)
, = (11164.7, 1110.9)
100µm
40
30
50
30
40
30
(2-a) Coordinate (X,Y) = (-11124, 1264.6)
50µm
(2-b) Coordinate (X,Y) = (11124, 1264.6)
20
50µm
(3-a) Coordinate(X ,,Y) = (-11124, -1264.6)
25
25
10 5
25
5 10
25
70µm
80µm
10 5
5 10
70µm
80µm
(3-b) Coordinate(X ,Y) = (11124, -1264.6)
25
25
10
10
25
70µm
25
10
10
1
1
1
1
1
1
No.221
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
TESTO4
1
1
1
1
1
1
No.936
G125
G127
G129
G131
G233
G235 No.879
G237
G239
VGLDUM3
DUMMY19
DUMMY18
DUMMY17
S1
S2
No.874
S3
S4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
HD667B89
Laced Output
Arrangement
1
1
1
1
1
1
Y
1
1
1
1
1
1
1
1
1
1
X
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Short-circuit
within a chip
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
GATE
Min 33um pich
62 pin
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
No.222
Rev.0.12, May 09 2003, page 14 of 156
1
1
1
1
VGLDUM1
G2
G4
G6
G8
No.220
1
1
1
1
1
1
70µm
1 1
1
1
1
1
1
No.219
TESTO2
No.937
1
1
1
1
1
1
IO
Min 80um pitch
220 pin
100µm
30
50
IM3
IOVccDUM3
DUMMY2
RESET*
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
IOGNDDUM3
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1/SDO
DB0/SDI
IOGNDDUM4
RD*
WR*/SCL
RS
CS*
VLD
IOVccDUM4
VSYNC
HSYNC
DOTCLK
ENABLE
IOGNDDUM5
PD17
PD16
PD15
PD14
PD13
PD12
IOGNDDUM6
PD11
PD10
PD9
PD8
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
FLM
IOVcc
IOVcc
Vcc
Vcc
Vcc
Vcc
RVcc
RVcc
RVcc
RVcc
RVcc
Vci
Vci
Vci
Vci
Vci
Vci
Vci2
RGND
RGND
RGND
RGND
RGND
RGND
AGND
AGND
AGND
AGND
AGND
GND
GND
GND
GND
GND
GND
TEST1
TEST2
OSC1
OSC2
TS7
TS6
TS5
TS4
TS3
TS2
TS1
TS0
IOGNDDUM7
DUMMYR1
DUMMYR2
DUMMYR3
DUMMYR4
DUMMYR5
DUMMYR6
DUMMYR7
DUMMYR8
DUMMYR9
DUMMY3
DUMMY4
DUMMY5
DUMMY6
DUMMY7
DUMMY8
DUMMY9
DUMMY10
DUMMY11
DUMMY12
REGP
VGS
VGS
CGND
CGND
CGND
CGND
CGND
V0P
V0N
VMONI
V31P
V31N
TESTA4
TESTA1
VcomR
VREG1OUT
TESTA2
VTESTS
VcomL
VcomL
VcomL
VcomH
VcomH
VcomH
VCL
VCL
VLOUT4
Vci1
Vci1
Vci1
Vci1
Vci1
Vci1
VciOUT
VciOUT
VciOUT
VciOUT
DDVDH
DDVDH
DDVDH
DDVDH
DDVDH
DDVDH
VLOUT1
VLOUT1
C11C11C11C11C11+
C11+
C11+
C11+
Vcom2
Vcom2
DUMMY13
1
1
1
1
GATE
Min 33um
pitch
62 pin
SOUCE
Min 33um pitch
528pin
n Au bump size :
(1) 80µ m × 80µm
Corner dummy
No.1, No220, No.284, No.937
DUMMY1
Vcom1
Vcom1
VGH
VGH
VLOUT2
C22+
C22+
C22C22C21+
C21+
C21C21C12+
C12+
C12+
C12+
C12C12C12C12VLOUT3
VGL
VGL
VGL
VGL
CGND
CGND
CGND
CGND
CGND
IOVccDUM1
IM0/ID
IOGNDDUM1
IM1
IOVccDUM2
IM2
No.938
1
1
1
1
GATE
Min 33um pich
58 pin
n Chip size : 22.7mm × 2.80mm (T.B.D.)
.
n Chip thickness : 400µm (typ.)
n PAD coordinate : PAD center
n Coordinate origin : Chip center
1
1
1
1
GATE
Min 33um pitch
58 pin
1
1
S525
S526
No.347
S527
S528
DUMMY16
DUMMY15
DUMMY14
VGLDUM2
G240
G238
No.342
G236
G234
G132
G130
G128
G126
No.285
1
1
1
1
1
1
1 1
1
TESTO3
No.284
G118
G120
G122
G124
TESTO1
No.2
G117
G119
G121
G123
No.999
No.1
No.283
HD66789
Preliminary
PAD Coordinate
pad No
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
pad name
TESTO1
DUMMY1
Vcom1
Vcom1
VGH
VGH
VLOUT2
C22+
C22+
C22C22C21+
C21+
C21C21C12+
C12+
C12+
C12+
C12C12C12C12VLOUT3
VGL
VGL
VGL
VGL
CGND
CGND
CGND
CGND
CGND
IOVccDUM1
IM0/ID
IOGNDDUM1
IM1
IOVccDUM2
IM2
IOGNDDUM2
IM3
IOVccDUM3
DUMMY2
RESET*
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
IOGNDDUM3
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1/SDO
DB0/SDI
IOGNDDUM4
RD*
WR*/SCL
RS
CS*
VLD
IOVccDUM4
VSYNC
HSYNC
DOTCLK
ENABLE
IOGNDDUM5
PD17
PD16
PD15
PD14
PD13
PD12
IOGNDDUM6
PD11
PD10
PD9
PD8
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
FLM
IOVcc
IOVcc
Vcc
Vcc
Vcc
Vcc
RVcc
RVcc
RVcc
RVcc
RVcc
Vci
Vci
Vci
Vci
Vci
Vci
VciLVL
RGND
RGND
RGND
RGND
RGND
RGND
AGND
AGND
AGND
AGND
AGND
GND
GND
GND
GND
GND
GND
X
-11214.0
-10888.2
-10782.3
-10702.1
-10569.1
-10489.0
-10387.5
-10227.4
-10147.2
-10067.1
-9986.9
-9906.8
-9826.6
-9746.5
-9666.3
-9527.9
-9447.7
-9367.6
-9287.4
-9149.0
-9068.9
-8988.7
-8908.6
-8775.6
-8642.6
-8562.4
-8482.3
-8402.1
-8269.1
-8189.0
-8108.8
-8028.7
-7948.5
-7815.5
-7698.2
-7553.7
-7436.4
-7291.9
-7174.6
-7030.1
-6912.8
-6768.3
-6635.3
-6512.5
-6372.9
-6292.7
-6212.6
-6132.4
-6052.3
-5972.1
-5892.0
-5811.8
-5731.7
-5587.2
-5469.9
-5389.7
-5309.6
-5229.4
-5149.3
-5069.1
-4989.0
-4908.8
-4828.7
-4684.2
-4566.9
-4486.7
-4406.6
-4326.4
-4246.3
-4101.8
-3984.5
-3904.3
-3824.2
-3744.0
-3599.6
-3482.2
-3402.1
-3321.9
-3241.8
-3161.6
-3081.5
-2937.0
-2819.7
-2739.5
-2659.4
-2579.2
-2499.1
-2418.9
-2338.8
-2258.6
-2178.5
-2098.3
-2018.2
-1938.0
-1857.9
-1702.6
-1622.4
-1478.6
-1398.4
-1307.4
-1227.3
-1083.4
-1003.3
-912.3
-832.1
-752.0
-608.1
-528.0
-447.8
-367.7
-287.5
-207.4
-57.7
86.6
166.8
246.9
327.1
407.2
487.4
620.4
700.5
780.7
860.8
941.0
1074.0
1154.1
1287.1
1367.3
1447.4
1527.6
Y
-1264.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
pad No
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
pad name
TEST1
TEST2
OSC1
OSC2
TS7
TS6
TS5
TS4
TS3
TS2
TS1
TS0
IOGNDDUM7
DUMMYR1
DUMMYR2
DUMMYR3
DUMMYR4
DUMMYR5
DUMMYR6
DUMMYR7
DUMMYR8
DUMMYR9
DUMMY3
DUMMY4
DUMMY5
DUMMY6
DUMMY7
DUMMY8
DUMMY9
DUMMY10
DUMMY11
DUMMY12
REGP
VGS
VGS
CGND
CGND
CGND
CGND
CGND
V0P
V0N
VMONI
V31P
V31N
TESTA4
TESTA1
VcomR
VREG1OUT
TESTA2
VTESTS
VcomL
VcomL
VcomL
VcomH
VcomH
VcomH
VCL
VCL
VLOUT4
Vci1
Vci1
Vci1
Vci1
Vci1
Vci1
VciOUT
VciOUT
VciOUT
VciOUT
DDVDH
DDVDH
DDVDH
DDVDH
DDVDH
DDVDH
VLOUT1
VLOUT1
C11C11C11C11C11+
C11+
C11+
C11+
Vcom2
Vcom2
DUMMY13
TESTO2
VGLDUM1
G2
G4
G6
G8
G10
G12
G14
G16
G18
G20
G22
G24
G26
G28
G30
G32
G34
G36
G38
G40
G42
G44
G46
G48
G50
G52
G54
G56
G58
G60
G62
G64
G66
G68
G70
G72
G74
G76
G78
Rev.0.12, May 09 2003, page 15 of 156
X
1679.2
1759.4
1899.0
1979.2
2118.8
2199.0
2279.1
2359.3
2439.4
2519.6
2599.7
2679.9
2824.3
2984.5
3064.6
3144.8
3224.9
3305.1
3385.2
3465.4
3545.5
3625.7
3705.8
3786.0
3866.1
3946.3
4026.4
4106.6
4186.7
4266.9
4347.0
4427.2
4571.4
4747.5
4873.3
5017.6
5097.8
5177.9
5258.1
5338.2
5482.5
5608.3
5734.1
5860.0
5985.8
6135.5
6418.2
6544.0
6669.9
6795.7
6921.5
7071.2
7249.7
7428.2
7572.1
7750.6
7929.1
8067.5
8150.3
8230.4
8368.9
8449.0
8529.2
8609.3
8689.5
8769.6
8849.8
8929.9
9010.1
9090.2
9234.1
9314.2
9394.4
9474.5
9554.7
9634.8
9778.7
9858.8
10002.7
10082.8
10163.0
10243.1
10323.3
10403.4
10483.6
10563.7
10702.1
10782.3
10888.2
11214.0
11215.5
11098.5
11215.5
11098.5
11215.5
11098.5
11215.5
11098.5
11215.5
11098.5
11215.5
11098.5
11215.5
11098.5
11215.5
11098.5
11215.5
11098.5
11215.5
11098.5
11215.5
11098.5
11215.5
11098.5
11215.5
11098.5
11215.5
11098.5
11215.5
11098.5
11215.5
11098.5
11215.5
11098.5
11215.5
11098.5
11215.5
11098.5
11215.5
11098.5
Y
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1254.0
-1264.0
-1118.7
-1050.6
-1017.5
-984.5
-951.4
-918.3
-885.2
-852.2
-819.1
-786.0
-752.9
-719.9
-686.8
-653.7
-620.6
-587.6
-554.5
-521.4
-488.3
-455.3
-422.2
-389.1
-356.0
-323.0
-289.9
-256.8
-223.7
-190.7
-157.6
-124.5
-91.4
-58.4
-25.3
7.8
40.9
73.9
107.0
140.1
173.2
206.2
pad No
pad name
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
G80
G82
G84
G86
G88
G90
G92
G94
G96
G98
G100
G102
G104
G106
G108
G110
G112
G114
G116
G118
G120
G122
G124
TESTO3
G126
G128
G130
G132
G134
G136
G138
G140
G142
G144
G146
G148
G150
G152
G154
G156
G158
G160
G162
G164
G166
G168
G170
G172
G174
G176
G178
G180
G182
G184
G186
G188
G190
G192
G194
G196
G198
G200
G202
G204
G206
G208
G210
G212
G214
G216
G218
G220
G222
G224
G226
G228
G230
G232
G234
G236
G238
G240
VGLDUM2
DUMMY14
DUMMY15
DUMMY16
S528
S527
S526
S525
S524
S523
S522
S521
S520
S519
S518
S517
S516
S515
S514
S513
S512
S511
S510
S509
S508
S507
S506
S505
S504
S503
S502
S501
S500
S499
S498
S497
S496
S495
S494
S493
S492
S491
S490
S489
S488
S487
S486
S485
X
11215.5
11098.5
11215.5
11098.5
11215.5
11098.5
11215.5
11098.5
11215.5
11098.5
11215.5
11098.5
11215.5
11098.5
11215.5
11098.5
11215.5
11098.5
11215.5
11098.5
11215.5
11098.5
11215.5
11214.0
10958.4
10925.3
10892.3
10859.2
10826.1
10793.0
10760.0
10726.9
10693.8
10660.7
10627.7
10594.6
10561.5
10528.4
10495.4
10462.3
10429.2
10396.1
10363.1
10330.0
10296.9
10263.8
10230.8
10197.7
10164.6
10131.5
10098.5
10065.4
10032.3
9999.2
9966.2
9933.1
9900.0
9866.9
9833.9
9800.8
9767.7
9734.6
9701.6
9668.5
9635.4
9602.3
9569.3
9536.2
9503.1
9470.0
9437.0
9403.9
9370.8
9337.7
9304.7
9271.6
9238.5
9205.4
9172.4
9139.3
9106.2
9073.1
9005.1
8937.0
8868.9
8800.8
8732.8
8699.7
8666.6
8633.5
8600.5
8567.4
8534.3
8501.2
8468.2
8435.1
8402.0
8368.9
8335.9
8302.8
8269.7
8236.6
8203.6
8170.5
8137.4
8104.3
8071.3
8038.2
8005.1
7972.0
7939.0
7905.9
7872.8
7839.7
7806.7
7773.6
7740.5
7707.4
7674.4
7641.3
7608.2
7575.1
7542.1
7509.0
7475.9
7442.8
7409.8
7376.7
7343.6
7310.5
Y
239.3
272.4
305.5
338.5
371.6
404.7
437.8
470.8
503.9
537.0
570.1
603.1
636.2
669.3
702.4
735.4
768.5
801.6
834.7
867.7
900.8
933.9
967.0
1264.0
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1265.5
1265.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
pad No
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
pad name
S484
S483
S482
S481
S480
S479
S478
S477
S476
S475
S474
S473
S472
S471
S470
S469
S468
S467
S466
S465
S464
S463
S462
S461
S460
S459
S458
S457
S456
S455
S454
S453
S452
S451
S450
S449
S448
S447
S446
S445
S444
S443
S442
S441
S440
S439
S438
S437
S436
S435
S434
S433
S432
S431
S430
S429
S428
S427
S426
S425
S424
S423
S422
S421
S420
S419
S418
S417
S416
S415
S414
S413
S412
S411
S410
S409
S408
S407
S406
S405
S404
S403
S402
S401
S400
S399
S398
S397
S396
S395
S394
S393
S392
S391
S390
S389
S388
S387
S386
S385
S384
S383
S382
S381
S380
S379
S378
S377
S376
S375
S374
S373
S372
S371
S370
S369
S368
S367
S366
S365
S364
S363
S362
S361
S360
S359
S358
S357
S356
S355
X
7277.5
7244.4
7211.3
7178.2
7145.2
7112.1
7079.0
7045.9
7012.9
6979.8
6946.7
6913.6
6880.6
6847.5
6814.4
6781.3
6748.3
6715.2
6682.1
6649.0
6616.0
6582.9
6549.8
6516.7
6483.7
6450.6
6417.5
6384.4
6351.4
6318.3
6285.2
6252.1
6219.1
6186.0
6152.9
6119.8
6086.8
6053.7
6020.6
5987.5
5954.5
5921.4
5888.3
5855.2
5822.2
5789.1
5756.0
5722.9
5689.9
5656.8
5623.7
5590.6
5557.6
5524.5
5491.4
5458.3
5425.3
5392.2
5359.1
5326.0
5293.0
5259.9
5226.8
5193.7
5160.7
5127.6
5094.5
5061.4
5028.4
4995.3
4962.2
4929.1
4896.1
4863.0
4829.9
4796.8
4763.8
4730.7
4697.6
4664.5
4631.5
4598.4
4565.3
4532.2
4499.2
4466.1
4433.0
4399.9
4366.9
4333.8
4300.7
4267.6
4234.6
4201.5
4168.4
4135.3
4102.3
4069.2
4036.1
4003.0
3970.0
3936.9
3903.8
3870.7
3837.7
3804.6
3771.5
3738.4
3705.4
3672.3
3639.2
3606.1
3573.1
3540.0
3506.9
3473.8
3440.8
3407.7
3374.6
3341.5
3308.5
3275.4
3242.3
3209.2
3176.2
3143.1
3110.0
3076.9
3043.9
3010.8
Y
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
HD66789
Preliminary
pad No
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
pad name
S354
S353
S352
S351
S350
S349
S348
S347
S346
S345
S344
S343
S342
S341
S340
S339
S338
S337
S336
S335
S334
S333
S332
S331
S330
S329
S328
S327
S326
S325
S324
S323
S322
S321
S320
S319
S318
S317
S316
S315
S314
S313
S312
S311
S310
S309
S308
S307
S306
S305
S304
S303
S302
S301
S300
S299
S298
S297
S296
S295
S294
S293
S292
S291
S290
S289
S288
S287
S286
S285
S284
S283
S282
S281
S280
S279
S278
S277
S276
S275
S274
S273
S272
S271
S270
S269
S268
S267
S266
S265
S264
S263
S262
S261
S260
S259
S258
S257
S256
S255
S254
S253
S252
S251
S250
S249
S248
S247
S246
S245
S244
S243
S242
S241
S240
S239
S238
S237
S236
S235
S234
S233
S232
S231
S230
S229
S228
S227
S226
S225
X
2977.7
2944.6
2911.6
2878.5
2845.4
2812.3
2779.3
2746.2
2713.1
2680.0
2647.0
2613.9
2580.8
2547.7
2514.7
2481.6
2448.5
2415.4
2382.4
2349.3
2316.2
2283.1
2250.1
2217.0
2183.9
2150.8
2117.8
2084.7
2051.6
2018.5
1985.5
1952.4
1919.3
1886.2
1853.2
1820.1
1787.0
1753.9
1720.9
1687.8
1654.7
1621.6
1588.6
1555.5
1522.4
1489.3
1456.3
1423.2
1390.1
1357.0
1324.0
1290.9
1257.8
1224.7
1191.7
1158.6
1125.5
1092.4
1059.4
1026.3
993.2
960.1
927.1
894.0
860.9
827.8
794.8
761.7
728.6
695.5
662.5
629.4
596.3
563.2
530.2
497.1
464.0
430.9
397.9
364.8
331.7
298.6
265.6
232.5
199.4
166.3
133.3
100.2
67.1
34.0
-34.0
-67.1
-100.2
-133.3
-166.3
-199.4
-232.5
-265.6
-298.6
-331.7
-364.8
-397.9
-430.9
-464.0
-497.1
-530.2
-563.2
-596.3
-629.4
-662.5
-695.5
-728.6
-761.7
-794.8
-827.8
-860.9
-894.0
-927.1
-960.1
-993.2
-1026.3
-1059.4
-1092.4
-1125.5
-1158.6
-1191.7
-1224.7
-1257.8
-1290.9
-1324.0
Y
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
pad No
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
pad name
S224
S223
S222
S221
S220
S219
S218
S217
S216
S215
S214
S213
S212
S211
S210
S209
S208
S207
S206
S205
S204
S203
S202
S201
S200
S199
S198
S197
S196
S195
S194
S193
S192
S191
S190
S189
S188
S187
S186
S185
S184
S183
S182
S181
S180
S179
S178
S177
S176
S175
S174
S173
S172
S171
S170
S169
S168
S167
S166
S165
S164
S163
S162
S161
S160
S159
S158
S157
S156
S155
S154
S153
S152
S151
S150
S149
S148
S147
S146
S145
S144
S143
S142
S141
S140
S139
S138
S137
S136
S135
S134
S133
S132
S131
S130
S129
S128
S127
S126
S125
S124
S123
S122
S121
S120
S119
S118
S117
S116
S115
S114
S113
S112
S111
S110
S109
S108
S107
S106
S105
S104
S103
S102
S101
S100
S99
S98
S97
S96
S95
Rev.0.12, May 09 2003, page 16 of 156
X
-1357.0
-1390.1
-1423.2
-1456.3
-1489.3
-1522.4
-1555.5
-1588.6
-1621.6
-1654.7
-1687.8
-1720.9
-1753.9
-1787.0
-1820.1
-1853.2
-1886.2
-1919.3
-1952.4
-1985.5
-2018.5
-2051.6
-2084.7
-2117.8
-2150.8
-2183.9
-2217.0
-2250.1
-2283.1
-2316.2
-2349.3
-2382.4
-2415.4
-2448.5
-2481.6
-2514.7
-2547.7
-2580.8
-2613.9
-2647.0
-2680.0
-2713.1
-2746.2
-2779.3
-2812.3
-2845.4
-2878.5
-2911.6
-2944.6
-2977.7
-3010.8
-3043.9
-3076.9
-3110.0
-3143.1
-3176.2
-3209.2
-3242.3
-3275.4
-3308.5
-3341.5
-3374.6
-3407.7
-3440.8
-3473.8
-3506.9
-3540.0
-3573.1
-3606.1
-3639.2
-3672.3
-3705.4
-3738.4
-3771.5
-3804.6
-3837.7
-3870.7
-3903.8
-3936.9
-3970.0
-4003.0
-4036.1
-4069.2
-4102.3
-4135.3
-4168.4
-4201.5
-4234.6
-4267.6
-4300.7
-4333.8
-4366.9
-4399.9
-4433.0
-4466.1
-4499.2
-4532.2
-4565.3
-4598.4
-4631.5
-4664.5
-4697.6
-4730.7
-4763.8
-4796.8
-4829.9
-4863.0
-4896.1
-4929.1
-4962.2
-4995.3
-5028.4
-5061.4
-5094.5
-5127.6
-5160.7
-5193.7
-5226.8
-5259.9
-5293.0
-5326.0
-5359.1
-5392.2
-5425.3
-5458.3
-5491.4
-5524.5
-5557.6
-5590.6
-5623.7
Y
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
pad No
pad name
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
S94
S93
S92
S91
S90
S89
S88
S87
S86
S85
S84
S83
S82
S81
S80
S79
S78
S77
S76
S75
S74
S73
S72
S71
S70
S69
S68
S67
S66
S65
S64
S63
S62
S61
S60
S59
S58
S57
S56
S55
S54
S53
S52
S51
S50
S49
S48
S47
S46
S45
S44
S43
S42
S41
S40
S39
S38
S37
S36
S35
S34
S33
S32
S31
S30
S29
S28
S27
S26
S25
S24
S23
S22
S21
S20
S19
S18
S17
S16
S15
S14
S13
S12
S11
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
DUMMY17
DUMMY18
DUMMY19
VGLDUM3
G239
G237
G235
G233
G231
G229
G227
G225
G223
G221
G219
G217
G215
G213
G211
G209
G207
G205
G203
G201
G199
G197
G195
G193
G191
G189
G187
G185
G183
G181
G179
G177
X
-5656.8
-5689.9
-5722.9
-5756.0
-5789.1
-5822.2
-5855.2
-5888.3
-5921.4
-5954.5
-5987.5
-6020.6
-6053.7
-6086.8
-6119.8
-6152.9
-6186.0
-6219.1
-6252.1
-6285.2
-6318.3
-6351.4
-6384.4
-6417.5
-6450.6
-6483.7
-6516.7
-6549.8
-6582.9
-6616.0
-6649.0
-6682.1
-6715.2
-6748.3
-6781.3
-6814.4
-6847.5
-6880.6
-6913.6
-6946.7
-6979.8
-7012.9
-7045.9
-7079.0
-7112.1
-7145.2
-7178.2
-7211.3
-7244.4
-7277.5
-7310.5
-7343.6
-7376.7
-7409.8
-7442.8
-7475.9
-7509.0
-7542.1
-7575.1
-7608.2
-7641.3
-7674.4
-7707.4
-7740.5
-7773.6
-7806.7
-7839.7
-7872.8
-7905.9
-7939.0
-7972.0
-8005.1
-8038.2
-8071.3
-8104.3
-8137.4
-8170.5
-8203.6
-8236.6
-8269.7
-8302.8
-8335.9
-8368.9
-8402.0
-8435.1
-8468.2
-8501.2
-8534.3
-8567.4
-8600.5
-8633.5
-8666.6
-8699.7
-8732.8
-8800.8
-8868.9
-8937.0
-9005.1
-9073.1
-9106.2
-9139.3
-9172.4
-9205.4
-9238.5
-9271.6
-9304.7
-9337.7
-9370.8
-9403.9
-9437.0
-9470.0
-9503.1
-9536.2
-9569.3
-9602.3
-9635.4
-9668.5
-9701.6
-9734.6
-9767.7
-9800.8
-9833.9
-9866.9
-9900.0
-9933.1
-9966.2
-9999.2
-10032.3
-10065.4
-10098.5
Y
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1265.5
1265.5
1265.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
pad No
pad name
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
G175
G173
G171
G169
G167
G165
G163
G161
G159
G157
G155
G153
G151
G149
G147
G145
G143
G141
G139
G137
G135
G133
G131
G129
G127
G125
TESTO4
G123
G121
G119
G117
G115
G113
G111
G109
G107
G105
G103
G101
G99
G97
G95
G93
G91
G89
G87
G85
G83
G81
G79
G77
G75
G73
G71
G69
G67
G65
G63
G61
G59
G57
G55
G53
G51
G49
G47
G45
G43
G41
G39
G37
G35
G33
G31
G29
G27
G25
G23
G21
G19
G17
G15
G13
G11
G9
G7
G5
G3
G1
VGLDUM4
Alignment Mark
L-type (Positive)
L-type (Negative)
Circle (Positive)
Circle (Negative)
Cross
X
-10131.5
-10164.6
-10197.7
-10230.8
-10263.8
-10296.9
-10330.0
-10363.1
-10396.1
-10429.2
-10462.3
-10495.4
-10528.4
-10561.5
-10594.6
-10627.7
-10660.7
-10693.8
-10726.9
-10760.0
-10793.0
-10826.1
-10859.2
-10892.3
-10925.3
-10958.4
-11214.0
-11215.5
-11098.5
-11215.5
-11098.5
-11215.5
-11098.5
-11215.5
-11098.5
-11215.5
-11098.5
-11215.5
-11098.5
-11215.5
-11098.5
-11215.5
-11098.5
-11215.5
-11098.5
-11215.5
-11098.5
-11215.5
-11098.5
-11215.5
-11098.5
-11215.5
-11098.5
-11215.5
-11098.5
-11215.5
-11098.5
-11215.5
-11098.5
-11215.5
-11098.5
-11215.5
-11098.5
-11215.5
-11098.5
-11215.5
-11098.5
-11215.5
-11098.5
-11215.5
-11098.5
-11215.5
-11098.5
-11215.5
-11098.5
-11215.5
-11098.5
-11215.5
-11098.5
-11215.5
-11098.5
-11215.5
-11098.5
-11215.5
-11098.5
-11215.5
-11098.5
-11215.5
-11098.5
-11215.5
X
-11124.0
11124.0
-11124.0
11124.0
-11164.7
11164.7
Y
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1148.5
1265.5
1264.0
967.0
933.9
900.8
867.7
834.7
801.6
768.5
735.4
702.4
669.3
636.2
603.1
570.1
537.0
503.9
470.8
437.8
404.7
371.6
338.5
305.5
272.4
239.3
206.2
173.2
140.1
107.0
73.9
40.9
7.8
-25.3
-58.4
-91.4
-124.5
-157.6
-190.7
-223.7
-256.8
-289.9
-323.0
-356.0
-389.1
-422.2
-455.3
-488.3
-521.4
-554.5
-587.6
-620.6
-653.7
-686.8
-719.9
-752.9
-786.0
-819.1
-852.2
-885.2
-918.3
-951.4
-984.5
-1017.5
-1050.6
-1118.7
Y
-1264.6
-1264.6
1264.6
1264.6
1110.9
1110.9
HD66789
Preliminary
BUMP Arrangements
31
35
BUMP
77
S1 ~ S528
G1 ~ G240
40
117
77
33
33
2
S=2387um
Unit: um
54
I/O pins
100
Min.80
2
S=5400um
Unit: um
80
TESTO1 ~ 4
80
2
S=6400um
Unit: um
Rev.0.12, May 09 2003, page 17 of 156
HD66789
Preliminary
Block Function
1.
System Interface
The HD66789 has five high-speed system interfaces: 80-system 18-/16-/9-/8-bit bus and Serial Peripheral
Interface (SPI) port. The interface mode is selected with IM3-0 pins.
The HD66789 has three registers: 16-bit index register (IR), 18-bit write-data register (WDR), and 18-bit
read-data register (RDR). The IR stores index information from control registers and GRAM. The WDR
temporarily stores data to write into the control registers and GRAM, and the RDR temporarily stores data
read from GRAM. Data written into GRAM from the MPU is first written into the WDR and then
automatically written into GRAM by internal operation. Since data are read through the RDR from GRAM,
the data read out first are invalid data and the ensuing data are read out normally.
The execution time for instructions other than oscillation start is 0-clock cycle, which enables consecutively
writing instructions.
Register Selection (8/9/16/18 Parallel Interfaces)
80-system Bus
WR*
RD*
RS
Operation
0
1
0
Write index to IR
1
0
0
Read internal status
0
1
1
Write to the control registers or GRAM through WDR
1
0
1
Read from GRAM through RDR
Values of CS and VLD during RAM Write
CS*
VLD
Operations
0
0
Write data to GRAM. RAM address is updated.
1
0
Not write data to GRAM. RAM address is not updated.
0
1
Not write data to GRAM. RAM address is updated.
1
1
Not write data to GRAM. RAM address is not updated.
Note 1) The VLD setting is only effective with RAM write instructions.
Register Selection (Serial Peripheral Interface)
Start bytes
R/W
RS
Operations
0
0
Write index to IR
1
0
Read internal status
0
1
Write into control register and GRAM through WDR
1
1
Read from GRAM through RDR
Rev.0.12, May 09 2003, page 18 of 156
HD66789
2.
Preliminary
External Display Interface
The HD66789 incorporates RGB and VSYNC interfaces as an external interface for displaying moving
pictures. When RGB-I/F is selected, the display operation is executed in synchronization with the
externally supplied signals, VSYNC, HSYNC, and DOTCLK. The display data (PD17-0) are written
according to the values of the data enable signal (ENABLE) and data valid signal (VLD) in synchronization
with VSYNC, HSYNC, and DOTCLK signals. This data write method allows flicker-free screen update.
When VSYNC-I/F is selected, operations other than the frame synchronization by VSYNC signal are
synchronized with internal clocks. The display data are written to GRAM through a system interface. In
this case, there are constraints on the timing and methods of RAM update. See the “External Display
Interface” section for more details.
Switching between conventional system interfaces and external display interfaces is made through
instructions. An optimum interface is selected whether the screen is displaying moving or still pictures.
All data written through RGB-I/F are written to GRAM. Therefore, data is transmitted only when the
screen is being updated, which reduces the amount of data transmission, thereby saving power when
moving pictures are being displayed.
3.
Bit Operations
The HD66789 supports a write data mask function that selects and writes data into GRAM by bit, and
performs logical operation or conditional rewrite on the contents of compare registers and the data to write
to GRAM. For details, see the “Graphics Operation Functions” section.
4.
Address Counter (AC)
The address counter (AC) assigns address to GRAM. When an address set instruction is written into the IR,
the address information is sent from the IR to the AC.
After writing data into GRAM, the AC is automatically updated plus or minus 1. The AC is not updated
when the data are read from GRAM. Window address function enables data write only in the rectangular
area of GRAM specified by the window address.
5.
Graphics RAM (GRAM)
GRAM is a graphics RAM that stores bit-pattern data of 176 x 240 bytes with 18 bits per pixel.
6.
Gray scale power supply voltage generating circuit
The grayscale voltage generation circuit generates liquid crystal drive voltage according to the grayscale
data set in the γ-correction register, enabling 262,144-color display. For details, see the “γ-Correction
Register” section.
7.
Timing Generator
The timing generator generates timing signals for the operation of internal circuits such as GRAM. The
timing for display operation such as RAM read and the internal operation timing such as access from MPU
are generated in a way to avoid mutual interfere. The interface signals (M, FLM, CL1, EQ, DCCLK,
Rev.0.12, May 09 2003, page 19 of 156
HD66789
Preliminary
DISPTMG, and SFTCLK) are generated internally, and a part of the signals is output through a level
transforming circuit.
8.
Oscillation Circuit (OSC)
The HD66789 can provide R-C oscillation simply by placing an external oscillation-resistor between OSC1
and OSC2 pins. An appropriate oscillation frequency for operating voltage, display size, and frame
frequency can be obtained by adjusting the external-resistor value. Clock pulses can be supplied externally.
Since R-C oscillation is halted during the standby mode, current consumption will be reduced. For details,
see the “Oscillation Circuit” section.
9.
LCD Driver Circuit
The LCD driver circuit of HD66789 consists of a 528-output source driver (S1 ~ S528) and a 240-output
gate driver (G1 ~ G240). Display pattern data are latched when 528-bit data arrive. The latched data
controls source driver and generates drive waveforms. The gate driver, which operates display scan, selects
either VGH or VGL level to output. The shift direction of outputting 528 bits from source driver is
changeable with the SS bit. The shift direction of gate driver scan is changeable with the GS bit. The scan
mode of gate driver is changeable with SM bit. Select an appropriate shift direction and mode for an
assembly.
10. Liquid crystal drive power supply circuit
The LCD drive power supply circuit of HD66789 generates voltage, V0, V31P, V31N, VGH, and Vcom
required for driving LCD.
Rev.0.12, May 09 2003, page 20 of 156
HD66789
Preliminary
……
"0801"H
"0901"H
"EA01"H
"EB01"H
"EC01"H
"ED01"H
"EE01"H
"EF01"H
"0802"H
"0902"H
"EA02"H
"EB02"H
"EC02"H
"ED02"H
"EE02"H
"EF02"H
"0803"H
"0903"H
"EA03"H
"EB03"H
"EC03"H
"ED03"H
"EE03"H
"EF03"H
PD
PD
17 … 0
"00AD"H
"01AD"H
"02AD"H
"03AD"H
"04AD"H
"05AD"H
"06AD"H
"07AD"H
"08AD"H
"09AD"H
"0AAD"H
"0BAD"H
"0CAD"H
"0DAD"H
"0EAD"H
"0FAD"H
"10AD"H
"11AD"H
"12AD"H
"13AD"H
S528
S527
S526
S525
PD
PD
17 … 0
"00AE"H
"01AE"H
"02AE"H
"03AE"H
"04AE"H
"05AE"H
"06AE"H
"07AE"H
"08AE"H
"09AE"H
"0AAE"H
"0BAE"H
"0CAE"H
"0DAE"H
"0EAE"H
"0FAE"H
"10AE"H
"11AE"H
"12AE"H
"13AE"H
…………
…………
…………
…………
…………
…………
…………
…………
"E8AC"H
"E9AC"H
"EAAC"H
"EBAC"H
"ECAC"H
"EDAC"H
"EEAC"H
"EFAC"H
"E8AD"H
"E9AD"H
"EAAD"H
"EBAD"H
"ECAD"H
"EDAD"H
"EEAD"H
"EFAD"H
"E8AE"H
"E9AE"H
"EAAE"H
"EBAE"H
"ECAE"H
"EDAE"H
"EEAE"H
"EFAE"H
"E8AF"H
"E9AF"H
"EAAF"H
"EBAF"H
"ECAF"H
"EDAF"H
"EEAF"H
"EFAF"H
GRAM address and display panel position (SS =”0”)
Rev.0.12, May 09 2003, page 21 of 156
S524
S523
S522
S521
S520
S519
S518
……
……
"0800"H
"0900"H
"EA00"H
"EB00"H
"EC00"H
"ED00"H
"EE00"H
"EF00"H
……
……
G8
G7
G6
G5
G4
G3
G2
G1
…………
…………
…………
…………
…………
…………
…………
…………
…………
…………
…………
…………
…………
…………
…………
…………
…………
…………
…………
…………
PD
PD
17 … 0
"00AC"H
"01AC"H
"02AC"H
"03AC"H
"04AC"H
"05AC"H
"06AC"H
"07AC"H
"08AC"H
"09AC"H
"0AAC"H
"0BAC"H
"0CAC"H
"0DAC"H
"0EAC"H
"0FAC"H
"10AC"H
"11AC"H
"12AC"H
"13AC"H
……
……
G233
G234
G235
G236
G237
G238
G239
G240
S517
S12
S11
S9
S10
S8
S7
S6
S5
S4
S3
……
G240
G239
G238
G237
G236
G235
G234
G233
G232
G231
G230
G229
G228
G227
G226
G225
G224
G223
G222
G221
……
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
G12
G13
G14
G15
G16
G17
G18
G19
G20
PD
PD PD
PD PD
PD PD
PD
17 … 0 17 … 0 17 … 0 17 … 0
"0000"H
"0001"H
"0002"H
"0003"H
"0100"H
"0101"H
"0102"H
"0103"H
"0200"H
"0201"H
"0202"H
"0203"H
"0300"H
"0301"H
"0302"H
"0303"H
"0400"H
"0401"H
"0402"H
"0403"H
"0500"H
"0501"H
"0502"H
"0503"H
"0600"H
"0601"H
"0602"H
"0603"H
"0700"H
"0701"H
"0702"H
"0703"H
"0800"H
"0801"H
"0802"H
"0803"H
"0900"H
"0901"H
"0902"H
"0903"H
"0A00"H
"0A01"H
"0A02"H
"0A03"H
"0B00"H
"0B01"H
"0B02"H
"0B03"H
"0C00"H
"0C01"H
"0C02"H
"0C03"H
"0D00"H
"0D01"H
"0D02"H
"0D03"H
"0E01"H
"0E02"H
"0E03"H
"0E00"H
"0F00"H
"0F01"H
"0F02"H
"0F03"H
"1000"H
"1001"H
"1002"H
"1003"H
"1100"H
"1101"H
"1102"H
"1103"H
"1200"H
"1201"H
"1202"H
"1203"H
"1300"H
"1301"H
"1302"H
"1303"H
…………
……
GS=0 GS=1
S2
SG pin
S1
GRAM Address MAP
PD
PD
17 … 0
"00AF"H
"01AF"H
"02AF"H
"03AF"H
"04AF"H
"05AF"H
"06AF"H
"07AF"H
"08AF"H
"09AF"H
"0AAF"H
"0BAF"H
"0CAF"H
"0DAF"H
"0EAF"H
"0FAF"H
"10AF"H
"11AF"H
"12AF"H
"13AF"H
HD66789
Preliminary
80-System 18-Bit Interface
GRAM Data
DB
17
DB
16
DB DB
15 14
DB
13
DB
12
DB
11
DB
10
DB
9
DB DB
8
7
DB
6
DB
5
DB DB
4
3
DB
2
DB
1
DB
0
RGB
Arrangement
R5
R4
R3 R2
R1
R0
G5
G4
G3
G2
G0
B5
B4
B2
B1
B0
Output pin
S (3n + 1)
G1
B3
S (3n + 2)
S (3n + 3)
Note: n = lower eight bits of address (0 to 175)
80-System 16-Bit Interface
GRAM Data
DB
17
DB
16
DB DB
15 14
DB
13
DB
12
DB
11
DB
10
RGB
Arrangement
R5
R4
R3 R2
R1
R0
G5
G4
S (3n + 1)
Output pin
G3
DB DB
8
7
DB
6
DB
5
DB DB
4
3
DB
2
DB
1
G2
G0
B5
B4
B2
B1
G1
B3
S (3n + 2)
B0
S (3n + 3)
Note: n = lower eight bits of address (0 to 175)
80-System 9-Bit Interface
1st Transmission
2nd Transmission
GRAM Data
DB
17
DB
16
DB
15
DB DB
14 13
DB
12
DB
11
DB
10
DB DB
9
17
DB
16
DB
15
DB
14
DB
13
DB
12
DB
11
DB DB
10 9
RGB
Arrangement
R5
R4
R3
R2
R0
G5
G4
G3
G1
G0
B5
B4
B3
B2
B1
R1
S (3n + 1)
Output pin
G2
S (3n + 2)
B0
S (3n + 3)
Note: n = lower eight bits of address (0 to 175)
80-System 8-Bit Interface/SPI (2 transmissions/pixel)
1st Transmission
GRAM Data
DB
17
DB
16
RGB
Arrangement
R5
R4
Output pin
2nd Transmission
DB DB
15 14
DB
13
DB
12
DB
11
DB
10
R3 R2
R1
R0
G5
G4
S (3n + 1)
G3
DB
17
DB
16
DB DB
15 14
DB
13
G2
G1
G0
B4
S (3n + 2)
B5
DB
12
DB
11
DB
10
B3
B2
B1
B0
S (3n + 3)
Note: n = lower eight bits of address (0 to 175)
GRAM data and RGB assignment (SS = “0”, BGR = “0”)
Rev.0.12, May 09 2003, page 22 of 156
HD66789
Preliminary
18-bit RGB interface
GRAM Data
RGB
Arrangement
PD PD PD PD PD PD
17 16 15 14 13 12
PD PD PD PD PD PD PD PD PD PD
11 10 9
8
7
6
5
4
3
2
PD PD
1
0
R5
G5
B1
R4
R3
R2
R1
R0
G4
G3
S (3n + 1)
Output pin
G2
G1
G0
B5
B4
S (3n + 2)
B3
B2
B0
S (3n + 3)
16-bit RGB interface
GRAM Data
RGB
Arrangement
PD PD PD PD PD
17 16 15 14 13
R5
R4
R3
R2
R1
R0
PD PD PD PD PD PD PD PD PD PD
11 10 9
8
7
6
5
4
3
2
PD
1
G5
B1
S (3n + 1)
Output pin
G4
G3
G2
G1
G0
B5
B4
S (3n + 2)
B3
B2
B0
S (3n + 3)
6-bit RGB interface
1st Transmission
GRAM Data
RGB
Arrangement
Output pin
2nd Transmission
3rd Transmission
PD
17
PD PD PD
16 15 14
PD PD
13 12
PD PD PD PD PD
17 16 15 14 13
PD PD
12 17
PD PD PD
16 15 14
PD PD
13 12
R5
R4
R1
G5
G0
B4
B1
R3
R2
S (3n + 1)
R0
G4
G3
G2
S (3n + 2)
G1
B5
B3
B2
S (3n + 3)
GRAM data and RGB assignment (SS = “0”, BGR = “0”)
Rev.0.12, May 09 2003, page 23 of 156
B0
"E8AE"H
"E9AE"H
"EAAE"H
"EBAE"H
"ECAE"H
"EDAE"H
"EEAE"H
"EFAE"H
"E8AD"H
"E9AD"H
"EAAD"H
"EBAD"H
"ECAD"H
"EDAD"H
"EEAD"H
"EFAD"H
"E8AC"H
"E9AC"H
"EAAC"H
"EBAC"H
"ECAC"H
"EDAC"H
"EEAC"H
"EFAC"H
S528
S527
"0802"H
"0902"H
"EA02"H
"EB02"H
"EC02"H
"ED02"H
"EE02"H
"EF02"H
"0801"H
"0901"H
"EA01"H
"EB01"H
"EC01"H
"ED01"H
"EE01"H
"EF01"H
"0800"H
"0900"H
"EA00"H
"EB00"H
"EC00"H
"ED00"H
"EE00"H
"EF00"H
GRAM address and display panel position (SS =”1”, BGR “1”)
Rev.0.12, May 09 2003, page 24 of 156
S526
S525
S524
S523
S522
S521
S520
S519
S518
S517
………… "0803"H
………… "0903"H
………… "EA03"H
………… "EB03"H
………… "EC03"H
………… "ED03"H
………… "EE03"H
………… "EF03"H
……
"E8AF"H
"E9AF"H
"EAAF"H
"EBAF"H
"ECAF"H
"EDAF"H
"EEAF"H
"EFAF"H
……
G8
G7
G6
G5
G4
G3
G2
G1
……
G233
G234
G235
G236
G237
G238
G239
G240
PD
PD PD
PD PD
PD PD
PD
17 … 0 17 … 0 17 … 0 17 … 0
"0003"H
"0002"H
"0001"H
"0000"H
"0103"H
"0102"H
"0101"H
"0100"H
"0203"H
"0202"H
"0201"H
"0200"H
"0303"H
"0302"H
"0301"H
"0300"H
"0403"H
"0402"H
"0401"H
"0400"H
"0503"H
"0502"H
"0501"H
"0500"H
"0603"H
"0602"H
"0601"H
"0600"H
"0703"H
"0702"H
"0701"H
"0700"H
"0803"H
"0802"H
"0801"H
"0800"H
"0903"H
"0902"H
"0901"H
"0900"H
"0A03"H
"0A02"H
"0A01"H
"0A00"H
"0B03"H
"0B02"H
"0B01"H
"0B00"H
"0C03"H
"0C02"H
"0C01"H
"0C00"H
"0D03"H
"0D02"H
"0D01"H
"0D00"H
"0E03"H
"0E02"H
"0E01"H
"0E00"H
"0F03"H
"0F02"H
"0F01"H
"0F00"H
"1003"H
"1002"H
"1001"H
"1000"H
"1103"H
"1102"H
"1101"H
"1100"H
"1203"H
"1202"H
"1201"H
"1200"H
"1303"H
"1302"H
"1301"H
"1300"H
……
S12
S11
……
S9
S10
S8
S7
……
S6
S5
S4
……
S3
PD
PD
17 … 0
"00AF"H
"01AF"H
"02AF"H
"03AF"H
"04AF"H
"05AF"H
"06AF"H
"07AF"H
"08AF"H
"09AF"H
"0AAF"H
"0BAF"H
"0CAF"H
"0DAF"H
"0EAF"H
"0FAF"H
"10AF"H
"11AF"H
"12AF"H
"13AF"H
……
…………
…………
…………
…………
…………
…………
…………
…………
…………
…………
…………
…………
…………
…………
…………
…………
…………
…………
…………
…………
G240
G239
G238
G237
G236
G235
G234
G233
G232
G231
G230
G229
G228
G227
G226
G225
G224
G223
G222
G221
……
PD
PD
17 … 0
"00AD"H
"01AD"H
"02AD"H
"03AD"H
"04AD"H
"05AD"H
"06AD"H
"07AD"H
"08AD"H
"09AD"H
"0AAD"H
"0BAD"H
"0CAD"H
"0DAD"H
"0EAD"H
"0FAD"H
"10AD"H
"11AD"H
"12AD"H
"13AD"H
PD
PD
17 … 0
"00AC"H
"01AC"H
"02AC"H
"03AC"H
"04AC"H
"05AC"H
"06AC"H
"07AC"H
"08AC"H
"09AC"H
"0AAC"H
"0BAC"H
"0CAC"H
"0DAC"H
"0EAC"H
"0FAC"H
"10AC"H
"11AC"H
"12AC"H
"13AC"H
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
G12
G13
G14
G15
G16
G17
G18
G19
G20
GS=0 GS=1
PD
PD
17 … 0
"00AE"H
"01AE"H
"02AE"H
"03AE"H
"04AE"H
"05AE"H
"06AE"H
"07AE"H
"08AE"H
"09AE"H
"0AAE"H
"0BAE"H
"0CAE"H
"0DAE"H
"0EAE"H
"0FAE"H
"10AE"H
"11AE"H
"12AE"H
"13AE"H
…………
……
SG pin
S2
Preliminary
S1
HD66789
HD66789
Preliminary
80-system 18-bit interface
GRAM Data
DB
17
DB
16
DB
15
DB
14
DB
13
DB
12
DB
11
DB
10
DB
9
DB
8
DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
DB
0
RGB
Arrangement
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
S (528 - 3n)
Output pin
S (527 - 3n)
S (526 - 3n)
Note: n = lower eight bits of address (0 to 175)
80-system 16-bit interface
GRAM Data
RGB
Arrangement
DB
17
DB
16
DB
15
DB
14
DB
13
DB
12
DB
11
DB
10
R5
R4
R3
R2
R1
R0
G5
G4
DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
G2
G1
G0
B5
B4
B3
B2
B1
S (527 - 3n)
S (528 - 3n)
Output pin
G3
DB
8
B0
S (526 - 3n)
Note: n = lower eight bits of address (0 to 175)
80-system 9-bit interface
1st Transmission
GRAM Data
RGB
Arrangement
DB
17
DB
16
R5
R4
2nd Transmission
DB
15
DB
14
DB
13
DB
12
DB
11
DB
10
R3
R2
R1
R0
G5
G4
S (528 - 3n)
Output pin
DB DB
9
17
DB
16
DB
15
DB
14
DB
13
G3
G1
G0
B5
B4
G2
DB
12
DB
11
DB
10
DB
9
B3
B2
B1
B0
S (527 - 3n)
S (526 - 3n)
Note: n = lower eight bits of address (0 to 175)
80-system 8-bit interface/SPI (2 transmissions/pixel)
1st Transmission
GRAM Data
DB
17
DB
16
RGB
Arrangement
R5
R4
Output pin
2nd Transmission
DB
15
DB
14
DB
13
DB
12
DB
11
DB
10
R3
R2
R1
R0
G5
G4
S (528 - 3n)
G3
DB
17
DB
16
DB
15
DB
14
DB
13
G2
G1
G0
B5
B4
S (527 - 3n)
DB
12
DB
11
DB
10
B3
B2
B1
B0
S (526 - 3n)
Note: n = lower eight bits of address (0 to 175)
GRAM data and RGB assignment (SS = “1”, BGR = “1”)
Rev.0.12, May 09 2003, page 25 of 156
HD66789
Preliminary
80-system 8 -bit interface (3 transmissions / pixel, 262k color mode : TRI = 1, DFM1 - 0 =10)
1st Transmission
GRAM Data PD PD PD PD
17 16 15 14
RGB
Arrangement
R5
R4
R3 R2
2nd Transmission
PD PD
17 16
PD PD
15 14
PD PD PD PD PD PD
13 12 17 16 15 14
PD PD
13 12
R1
G5
G3
G1
B1
R0
G4
S (528 - 3n)
Output pin
3rd Transmission
PD PD
13 12
G2
G0
B5
B4
S (527 - 3n)
B3
B2
B0
S (526 - 3n)
Note : n = Lower 8 bits of address (0 ~175)
80-system 8-bit interface (3 transmissions/pixel, 65k color mode : TRI = 1, DFM1 - 0 = 11)
1st Transmission
GRAM Data PD PD
17 16
RGB
Arrangement
R5
Output pin
R4
2nd Transmission
3rd Transmission
PD PD
15 14
PD PD
13 12
PD PD
17 16
PD PD PD PD PD PD
15 14 13 12 17 16
PD PD
15 14
PD PD
13 12
R3 R2
R1
G5
G3
B3
B1
S (528 - 3n)
R0
G4
G2
G1
S (527 - 3n)
G0
B5
B4
B2
B0
S (526 - 3n)
Note : n = Lower 8 bits of address (0 ~175)
GRAM data and RGB assignment (SS = “1”, BGR = “1”)
Rev.0.12, May 09 2003, page 26 of 156
HD66789
Preliminary
18- bit RGB interface
GRAM Data PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD
17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RGB R5
Arrangement
R4
Output
pin
R3 R2
R1
R0
G5
G4
S (528 - 3n)
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
S (526 - 3n)
S (527 - 3n)
Note : n = Lower 8 bits of address (0 ~ 175)
16- bit RGB interface
GRAM Data
RGB
Arrangement
PD PD PD PD PD
17 16 15 14 13
R5
R4
R3 R2
R1
R0
PD PD PD PD PD PD PD PD PD PD
11 10
9
8
7
6
5
4
3
2
PD
1
G5
B1
G4
S (528 – 3n)
Output
pin
G3
G2
G1
G0
B5
S (527 – 3n)
B4
B3
B2
B0
S (526 – 3n)
Note : n = Lower 8 bits of address (0 ~ 175)
6- bit RGB interface
1st Transmission
2nd Transmission
GRAM Data PD PD PD PD PD PD
17 16 15 14 13 12
RGB
Arrangement
Output
pin
R5
R4
R3 R2
R1
S (528 - 3n)
R0
3rd Transmission
PD PD PD PD
17 16 15 14
PD PD PD PD PD PD PD PD
13 12 17 16 15 14 13 12
G5
G1
G4
G3
G2
S (527 - 3n)
G0
B5
B4
B3
B2
B1
B0
S (526 - 3n)
Note : n = Lower 8 bits of address (0 ~ 175)
GRAM data and RGB assignment (SS = “1”, BGR = “1”)
Rev.0.12, May 09 2003, page 27 of 156
HD66789
Preliminary
Instructions
Outline
The HD66789 adapts 18-bit bus architecture that enables high-speed interfacing with a high-performance
microcomputer. Data sent from external (18/16/9/8 bits) are stored temporarily in the instruction register
(IR) and the data register (DR) to store control information before internal operation starts. Since internal
operation is decided according to the signal sent from the microcomputer, register selection signal (RS),
read/write signal (R/W), and internal 16-bit data bus signal (DB15 to DB0) are called instruction. GRAM
is accessed through internal 18-bit data bus. There are eight categories of instructions:
1.
2.
3.
4.
Specify index
Read status
Control display
Control power management
5.
6.
7.
8.
Process graphics data
Set internal GRAM address
Transfer data to and from internal GRAM
Set grayscale level for internal grayscale γ-adjustment
Normally, the 7th instruction to write display data is executed the most frequently. The address of internal
GRAM is updated automatically after data are written to the internal GRAM. With the window address
function, this reduces the amount of data transmission to minimum and thereby lightens the load on the
program in the microcomputer. Since instructions are executed in 0 cycle, it is possible to write
instructions consecutively.
As the following figure shows, the assignment to the 16 instruction bits (IB15-0) varies according to the
interface in use. An instruction must adopt the data format for each interface.
Rev.0.12, May 09 2003, page 28 of 156
HD66789
Preliminary
80-system 18-bit interface
GRAM Data DB
17
DB
16
DB DB
15 14
DB
13
DB
12
DB
11
DB
10
IB
15
IB
14
IB
13
IB
11
IB
10
IB
9
IB
8
DB
13
DB
12
DB
11
DB
10
IB
11
IB
10
IB
9
Instruction Bit (IB)
IB
12
DB
9
DB DB
8
7
IB
7
IB
6
DB
6
DB
5
IB IB
5 4
DB DB
4
3
DB
2
DB
1
IB
3
IB
1
IB
0
IB
2
DB
0
80-system 16-bit interface
GRAM Data DB
17
DB
16
IB
15
IB
14
Instruction Bit (IB)
DB DB
15 14
IB
13
IB
12
DB DB
8
7
DB
6
DB
5
DB DB
4
3
DB
2
DB
1
IB
8
IB
7
IB
6
IB
5
IB
4
IB
3
IB
2
IB
1
IB
0
DB DB
9 17
DB
16
DB DB
15 14
DB
13
DB
12
DB
11
DB
10
IB
7
IB
6
IB
5
IB
3
IB
2
IB
1
IB
0
80-system 9-bit interface
1st Transmission
2nd Transmission
GRAM Data DB
17
DB
16
DB DB
15 14
DB
13
DB
12
DB
11
DB
10
IB
15
IB
14
IB
13
IB
11
IB
10
IB
9
IB
8
Instruction Bit (IB)
IB
12
IB
4
DB
9
80-system 8-bit interface / SPI(2/3 transmissions)
1st Transmission
GRAM Data DB
17
DB
16
IB
15
IB
14
Instruction Bit (IB)
DB DB
15 14
IB
13
IB
12
2nd Transmission
DB
13
DB
12
DB
11
DB
10
DB
17
DB
16
DB DB
15 14
DB
13
DB
12
DB
11
DB
10
IB
11
IB
10
IB
9
IB
8
IB
7
IB
6
IB
5
IB
3
IB
2
IB
1
IB
0
IB
4
Instruction bits
Instructions
The following are detail explanations of instructions with illustrations of instruction bits (IB15-0) assigned
to each interface.
Index
The index instruction specifies the index (R00h to R4Fh) of control register and RAM control. It sets the
register number from 0000000 to 1111111 in binary form. Do not try to access to the register to which the
index is not assigned.
R/W
RS
W
0
IB15 IB14 IB13 IB12 IB11 IB10 IB9
IB8
IB7
∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗
Rev.0.12, May 09 2003, page 29 of 156
IB6
ID6
IB5
ID5
IB4
ID4
IB3
IB2
IB1
IB0
ID3
ID2
ID1
ID0
HD66789
Preliminary
Status Read
The status read instruction reads the internal status of the HD66789.
L7–0: Indicate the position of raster-row driving liquid crystal.
R/W
RS
R
0
IB15 IB14 IB13 IB12 IB11 IB10 IB9
L7
L6
L5
L4
L3
L2
L1
IB8
IB7
IB6
IB5
IB4
IB3
IB2
IB1
IB0
L0
0
0
0
0
0
0
0
0
Start Oscillation (R00h)
The start oscillation instruction restarts the oscillator in a halt state during the standby mode. After
executing this instruction, wait at least 10 ms for stabilizing oscillation before issuing a next instruction.
For details, see the “Standby Mode” section.
“0789”H is read out, if this register is forced to read out.
R/W
RS
W
1
R
1
IB15 IB14 IB13 IB12 IB11 IB10 IB9
IB8
IB7
IB6
IB5
IB4
IB3
IB2
IB1
∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗
IB0
1
1
1
1
0
0
0
1
0
0
1
IB15 IB14 IB13 IB12 IB11 IB10 IB9
IB8
IB7
IB6
IB5
IB4
IB3
IB2
IB1
IB0
SS
0
0
0
0
0
0
0
0
1
Driver Output Control (R01h)
R/W
RS
W
1
0
VSPL HSPL
DPL
EPL
SM
GS
NL4 NL3 NL2 NL1 NL0
SS: Select the shift direction of outputs from the source driver. When SS = 0, the shift direction of outputs
is from S1 to S528. When SS = 1, the shift direction of outputs is from S528 to S1. In addition to the shift
direction, the settings for both SS and BGR bits are required to change the assignment of R, G, B dots to
the source driver pins. To assign R, G, B dots to the source driver pins interchangeably from S1, set SS = 0,
BGR = 0. To assign R, G, B dots to the source driver pins interchangeably from S528, set SS = 1, BGR = 1.
GS: Select the shift direction of outputs from the gate driver. The scan order is changeable in accordance
to the scan mode by the gate driver. Select an optimum shift direction for the assembly.
SM: Set the scan order by the gate driver. Select an optimum scan order for the assembly. For details, see
“Scan Mode Setting”.
Rev.0.12, May 09 2003, page 30 of 156
HD66789
Preliminary
EPL: Set the polarity of ENABLE pin while using the RGB interface.
EPL = “0”
: ENABLE = “Low” / Write data to PD17-0.
: ENABLE = “High” / Data write invalid.
: ENABLE = “High” / Write data to PD17-0.
: ENABLE = “Low” / Data write invalid.
EPL =”1”
The following table shows the relationship between EPL, ENABLE, VLD and RAM access.
EPL
ENABLE
VLD
RAM write
RAM address
0
0
0
Valid
Updated
0
0
1
Invalid
Updated
0
1
*
Invalid
Hold
1
0
*
Invalid
Hold
1
1
0
Valid
Updated
1
1
1
Invalid
Updated
VSPL: Invert the polarity of signal for VSYNC pin.
VSPL = ”0”
VSPL = ”1”
: Low active.
: High active.
HSPL: Invert the polarity of signal for HSYNC pin.
HSPL = ”0”
HSPL = ”1”
: Low active.
: High active.
DPL: Invert the polarity of signal for DOTCLK pin.
DPL = ”0”
DPL = ”1”
: Data are read in synchronization with the rising edge of the DOTCLK.
: Data are read in synchronization with the falling edge of the DOTCLK.
NL4-0: Specify the number of LCD drive raster-rows. The number of drive raster-rows is changeable by 8
multiples. The GRAM address mapping is independent of this setting. Select a number of raster-rows so
that the display size covers the size of a panel.
Rev.0.12, May 09 2003, page 31 of 156
HD66789
Preliminary
NL bits
NL4
NL3
NL2
NL1
NL0
Display Size
Liquid crystal
drive
raster-rows
Gate driver lines
Used
0
0
0
0
0
Setting disabled
Setting disabled
Setting disabled
0
0
0
0
1
528 x 16 dots
16
G1–G16
0
0
0
1
0
528 x 24 dots
24
G1–G24
0
0
0
1
1
528 x 32 dots
32
G1–G32
0
0
1
0
0
528 x 40 dots
40
G1–G40
0
0
1
0
1
528 x 48 dots
48
G1–G48
0
0
1
1
0
528 x 56 dots
56
G1–G56
0
0
1
1
1
528 x 64 dots
64
G1–G64
0
1
0
0
0
528 x 72 dots
72
G1–G72
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
1
1
0
0
0
528 x 200 dots
200
G1–G200
1
1
0
0
1
528 x 208 dots
208
G1–G208
1
1
0
1
0
528 x 216 dots
216
G1–G216
1
1
0
1
1
528 x 224 dots
224
G1–G224
1
1
1
0
0
528 x 232 dots
232
G1–G232
1
1
1
0
1
528 x 240 dots
240
G1–G240
Note 1) A front porch period (set in the FP register) and a back porch period (set in the BP register) will be
inserted as a blank period before and after driving all gate lines
LCD Driving Wave Form Control (R02h)
R/W
RS
W
1
IB15 IB14 IB13 IB12 IB11 IB10 IB9
0
0
0
0
FLD1 FLD0 B/C
IB8
EOR
IB7
IB6
0
0
IB5
IB4
IB3
IB2
IB1
IB0
NW5 NW4 NW3 NW2 NW1 NW0
FLD1-0: Specify the number of fields during n-field interlaced drive. For details, see the “interlaced drive”
section.
This function is not available when an external display interface is selected. In the external display
interface mode, make sure FLD1-0= “01”
Rev.0.12, May 09 2003, page 32 of 156
HD66789
Preliminary
FLD1-0
FLD1
FLD0
Number of Fields
0
0
Setting disabled
0
1
1 field
1
0
Setting disabled
1
1
3 fields
NW5-0: Specify n, the number of raster-rows from 1 to 64 to alternate every n+1 raster-rows when Cpattern waveform is generated (B/C = 1).
EOR: When EOR = 1 and a C-pattern waveform is generated (B/C =1), an odd/even frame select signal
and an n-raster-row inversion signal are AC-driven. This instruction is available when liquid crystal AC
drive is not made depending on the combination of numbers of LCD drive raster-rows and the value of “n”
of n-raster-row inversion AC drive. For details, see “n-raster-row inversion AC drive”.
B/C: When B/C =0, a field AC waveform is generated. Alternation occurs every frame when driving liquid
crystal. When B/C=1, alternation occurs every n raster-row. For details, see the “n-raster-row Inversion
AC Drive” section.
Entry Mode (R03h)
Compare Register 1 (R04h)
Compare Register 2 (R05h)
R/W
RS
IB15 IB14 IB13 IB12 IB11 IB10 IB9
W
1
W
1
0
0
W
1
0
0
TRI DFM1 DFM0 BGR
0
CP11 CP10 CP9
0
0
0
IB8
IB7
IB6
0
0
IB5
IB4
IB3
IB2
IB1
IB0
I/D1 I/D0
AM
LG2 LG1 LG0
CP3
CP2
0
HWM
0
CP8
CP7
CP6
0
0
CP5
0
0
0
0
0
CP17 CP16 CP15 CP14 CP13 CP12
CP4
CP1
CP0
The HD66789 modifies write data sent from the microcomputer before writing to GRAM. This enables
high-speed GRAM data update, and reduces the load on the microcomputer software. For details, see the
“Graphics Operation Function” section.
TRI: RAM write data are transmitted in 3 times through 8-bit interface when TRI = 1. When 8-bit
interface mode is not selected, set TRI to 0.
DFM1-0: Specify the data format for the RAM write data transmission when TRI = 1 (8-bit interface mode
only).
DFM1-0 = “10” : 262k mode (6bit x 3 transmissions)
DFM1-0 = “11” : 65k mode (5,6,5 bits transmissions)
Rev.0.12, May 09 2003, page 33 of 156
HD66789
Preliminary
HWM: When HWM=1, data are written to GRAM in high speed. In high-speed write mode, 4 words are
written to GRAM in a single operation after executing 4 RAM write operations. If RAM write is
terminated before it is executed 4 times, the last data will not be written. Make sure that RAM write is
executed 4 times. For this reason, the lower 2 bits must be set to “0” when setting the RAM address. For
details, see “High-Speed RAM Write Mode” section.
I/D1-0: The address counter is automatically incremented by 1, after data are written to GRAM when I/D10 = “1”. The address counter is automatically decremented by 1, after data are written to GRAM when
I/D1-0 = “0”. An independent setting for the increment or decrement of the address counter can be made to
the upper (AD15-8) and the lower (AD7-0) bits of the address. The address transition direction when data
are written to GRAM is set with AM bits.
AM: Set the direction of updating address counter automatically after data are written to GRAM. When
AM = “0”, the address counter is updated in the horizontal direction. When AM = “1”, the address counter
is updated in the vertical direction. When the window address is specified, data are written to the GRAM
area specified by the window address in the manner specified with I/D1-0, AM bits.
TRI
DFM1 DFM0
8-bit interface data format
First transmission
Second transmission
DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10
0
0
DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10
0
R5
0
*
*
1
0
*
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
Setting disabled
Setting disabled
First transmission
Second transmission
Third transmission
DB17 DB16 DB15 DB14 DB13 DB12 DB17 DB16 DB15 DB14 DB13 DB12 DB17 DB16 DB15 DB14 DB13 DB12
1
1
0
R5
R4
R3
R2
R1
R0
G5
G4
First transmission
G3
G2
G1
G0
B5
B4
Second transmission
B3
B2
B1
B0
Third transmission
DB17 DB16 DB15 DB14 DB13 DB12 DB17 DB16 DB15 DB14 DB13 DB12 DB17 DB16 DB15 DB14 DB13 DB12
1
1
1
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
8-bit interface data format
Rev.0.12, May 09 2003, page 34 of 156
G0
B5
B4
B3
B2
B1
B0
HD66789
Preliminary
I/D1-0="10”
horizontal : decrement
vertical : increment
I/D1-0="01”
horizontal : increment
vertical : decrement
I/D1-0="00”
horizontal : decrement
vertical : decrement
0000h
0000h
I/D1-0="11”
horizontal : increment
vertical : increment
0000h
0000h
AM="0”
horizontal
EFAFh
EFAFh
EFAFh
EFAFh
0000h
0000h
0000h
0000h
AM="1”
vertical
EFAFh
EFAFh
EFAFh
EFAFh
Note : Data are written only on the GRAM area specified with the window
addresses when window addresses are set.
Address transition direction
LG2–0: Rewrite data to GRAM after comparing the data that are written by the microcomputer to GRAM
with the values in the compare registers (CP17–0) and performing logical operation. For details, see the
“Graphics Operation function”
CP17–0: Set the value for the compare register, with which the data read out from GRAM or data written
to GRAM by the microcomputer are compared. This function is not available with the external display
interface mode. In the external display interface mode, make sure LG2-0 = “000”.
BGR: Reverse the order from R, G, B to B, G, R to the 18-bit data to write to GRAM. When setting BGR
= 1, CP17-0 and WM17-0 bits will be automatically changed to the same effect.
18 bits
Write data to GRAM
Note 1)
0
0
0
0
0
0
0
1
1
1
0
0
1
1
1
0
Conversion between RGB and BGR (BGR)
Logical/compare operation
(LG2-0)
Logical operation (write data)
LG2-0 = 000: Replacement
Write data to
GRAM (WM17-0) Note 2)
Compare operation (with compare register)
LG2-0 = 110: Replacement of matched write data
LG2-0 = 111: Replacement of unmatched write data
Write data mask (WM17-0)
GRAM
Note 1) Data write to GRAM is executed by 18 bits. Logical operation is also executed by 18 bits.
As to the assignment of bits, see the description regarding each bit data bus interface.
Note 2) Write data mask (WM17-0) is set with the RAM write data mask register.
Logic/Compare Operation
Rev.0.12, May 09 2003, page 35 of 156
HD66789
Preliminary
Display Control 1 (R07h)
R/W
RS
W
1
IB15 IB14 IB13 IB12 IB11 IB10 IB9
0
0
0
PT1
IB8
PT0 VLE2 VLE1 SPT
IB7
IB6
0
0
IB5
IB4
GON DTE
IB3
CL
IB2
REV
IB1
IB0
D1
D0
PT1-0: Determine the kind of source output in a non-display area in the partial display mode. For details,
see the “Screen-split drive function” section.
PT1-0 bits
Source Output for Non-display Area
PT1
PT0
Positive Polarity
Negative Polarity
0
0
V31
V0
0
1
V31
V0
1
0
GND
GND
1
1
High impedance
High impedance
VLE2–1: When VLE1 = 1, the first screen is scrolled in the vertical direction. When VLE2 = 1, the second
screen is scrolled in the vertical direction. The first and second screens cannot be scrolled simultaneously.
This function is not available with the external display interface mode. In this case, make sure VLE2-1 = 0.
VLE Bits
VLE2
VLE1
Image on 2nd Screen
Image on 1st Screen
0
0
Stationary
Stationary
0
1
Stationary
Scrolled
1
0
Scrolled
Stationary
1
1
Setting disabled
Setting disabled
CL: When CL = 1, 8-color display mode is selected. For details, see the “8-Color Display Mode” section.
CL Bit
CL
Colors
0
262,144
1
8
SPT: When SPT = 1, liquid crystal is driven with 2 split screens. For details, see the “Screen Split Drive
Function” section. This function is not available in the external display interface mode. In this case, make
sure SPT = 0.
Rev.0.12, May 09 2003, page 36 of 156
HD66789
Preliminary
REV: When REV = 1, a reverse display is shown. Inverting the grayscale levels allows the display of
same data on both normally white and normally black panels. The source output during front, back porch
periods and blank periods during the 2-split-screen display is made in accordance with settings with PT1-0
bits.
Source Output in the Display Area
Source Output in the Display Area*
REV
GRAM Data
Positive Polarity
Negative Polarity
18’h00000
V31
V0
18’h3FFFF
V0
V31
18’h00000
V0
V31
18’h3FFFF
V31
V0
0
1
Note: The output on the source lines during the front and back porch periods and blanking of the partial
display is determined with PT1-0 bits.
GON: When GON = 0, the gate-off level is GND.
DTE: When DTE = 0, the DISPTMG output is fixed to GND.
GON Bit
DTE Bit
GON
Gate Output
DTE
DISPTMG Output
0
VGH/GND
0
Halt (GND)
1
VGH/VGL
1
Operation (Vcc/GND)
D1–0: The graphics display is on when D1 = 1, and off when D1 = 0. When setting D1 = 0, the data are
retained in GRAM. This means the graphics is instantly redisplayed when setting D1 to 1. When D1 is 0
(i.e., the display is off) all the source outputs are set to the GND level. This reduces the charged/discharged
current on LCD, accompanied by the liquid crystal AC drive.
When D1-0 = 01, the HD66789 continues the internal display operation, even while the external display is
off. When D1-0 = 00, both the internal display operations and the external display operation are halted.
In combination with GON and DTE bits, D1-0 bits control ON/OFF of display. For details, see the
“Instruction Setting Flow” section.
Rev.0.12, May 09 2003, page 37 of 156
HD66789
Preliminary
D1-0
D1
0
D0
Source Output
HD67789
Internal Operations
Gate-Driver Control Signals
(CL1, FLM, and M)
0
GND
Halt
Halt
0
1
GND
Operate
Operate
1
0
Unlit display
Operate
Operate
1
1
Display
Operate
Operate
Note 1) Data are written to GRAM from the microcomputer irrespective of the setting of D1-0 bits.
Note 2) In the standby mode, D1-0 = "00". However, the D1-0 register setting before entering standby
modes is retained.
Display Control 2 (R08h)
R/W
RS
W
1
IB15 IB14 IB13 IB12 IB11 IB10 IB9
0
0
0
0
FP3
FP2
FP1
IB8
FP0
IB7
IB6
IB5
IB4
IB3
IB2
0
0
0
0
BP3
BP2
IB1
IB0
BP1 BP0
FP3-0/BP3-0: Make settings for blank periods (the front and back porches), which are placed at the
beginning and end of the display. FP3-0 and BP3-0 bits specify the number of raster-rows for the front and
back porch respectively. When making this setting, make sure:
BP + FP = <16 raster-rows
FP >= 2 raster-rows
BP >= 2 raster-rows
In the external display interface mode, the back porch (BP) starts on the falling edge of VSYNC signal,
followed by display operation. After displaying the number of raster-rows set with NL bits, the front porch
starts. After the front porch, a blank period ensues until an input of next VSYNC signal.
Rev.0.12, May 09 2003, page 38 of 156
HD66789
Preliminary
FP and BP
FP3
FP2
FP1
FP0
Number of lines for the Front Porch
BP3
BP2
BP1
BP0
Number of lines for the Back Porch
0
0
0
0
Setting disabled
0
0
0
1
Setting disabled
0
0
1
0
2
0
0
1
1
3
0
1
0
0
4
⋅
⋅
⋅
⋅
1
1
0
0
12
1
1
0
1
13
1
1
1
0
14
1
1
1
1
Setting disabled
VSYNC
Back porch
Display area
Front porch
Note: The output timing to the LCD panels is delayed two rasterrows from the input of synchronization signal.
External display interface
Rev.0.12, May 09 2003, page 39 of 156
HD66789
Preliminary
BP3-0, FP3-0 Setting
Set BP3-0, FP3-0 bits as follows each in the following operation modes.
Operation of
internal clock
FLD1-0 = 01
BP>= 2 lines
FP >= 2 lines
FLD1-0 = 11
FP +BP <= 16 lines
BP = 3 lines
FP = 5 lines
RGB interface
BP >= 2 lines
FP >= 2 lines
FP +BP <= 16 lines
VSYNC interface
BP >= 2 lines
FP >= 2 lines
FP +BP = 16 lines
Display control 3 (R09h)
R/W
RS
W
1
IB15 IB14 IB13 IB12 IB11 IB10 IB9
0
0
0
0
0
0
0
IB8
IB7
IB6
0
0
0
IB5
IB4
IB3
IB2
IB1
IB0
PTG1 PTG0 ISC3 ISC2 ISC1 ISC0
PTG1-0: Set the gate scan mode when non-display area is driven.
PTG1
PTG0
Gate output in non-display
area
Source output in non-display
area
Vcom output
0
0
normal scan
PT setting
VcomH/VcomL amplitude
0
1
VGL (fixed)
PT setting
VcomH/VcomL amplitude
1
0
interval scan
PT setting
VcomH/VcomL amplitude
1
1
setting disabled
_
_
Rev.0.12, May 09 2003, page 40 of 156
HD66789
Preliminary
ISC 3-0: Set the frequency of gate scan when the gate scan mode in the non-display area is set to the
interval scan mode with PTG bits. The scan frequency always occurs per odd frames, which is set with ISC
bits, and inverted polarity is applied as the gate line is scanned.
Gate scan frequency
ISC3
ISC2
ISC1
ISC0
Scan frequency
(f FLM) = 60Hz
0
0
0
0
0 frame
_
0
0
0
1
3 frames
50 mS
0
0
1
0
5frames
84 mS
0
0
1
1
7 frames
117 mS
0
1
0
0
9 frames
150 mS
0
1
0
1
11 frames
184 mS
0
1
1
0
13 frames
217 mS
0
1
1
1
15 frames
251 mS
1
0
0
0
17 frames
284 mS
1
0
0
1
19 frames
317 mS
1
0
1
0
21 frames
351 mS
1
0
1
1
23 frames
384 mS
1
1
0
0
25 frames
418 mS
1
1
0
1
27 frame
451 mS
1
1
1
0
29 frame
484 mS
1
1
1
1
31 frame
518 mS
Frame Cycle Control (R0Bh)
R/W
RS
W
1
IB15 IB14 IB13 IB12 IB11 IB10 IB9
IB8
NO1 NO0 SDT1 SDT0 EQ1 EQ0 DIV1 DIV0
IB7
IB6
IB5
IB4
0
0
0
0
RTN3-0: Set the 1H (1 raster-row) period.
RTN3
RTN2
RTN1
RTN0
Clock Cycles per Raster-row
0
0
0
0
16 clocks
0
0
0
1
17 clocks
0
0
1
0
18 clocks
1
1
1
0
30 clocks
1
1
1
1
31 clocks
:
:
Rev.0.12, May 09 2003, page 41 of 156
IB3
IB2
IB1
IB0
RTN3 RTN2 RTN1 RTN0
HD66789
Preliminary
DIV1-0: Set the division ratio of clocks for internal operations (DIV1-0). Internal operations are in
synchronization with the clock, the frequency of which is divided according to the DIV1-0 setting. Frame
frequency can be adjusted in combination with the adjustment of 1H period (RTN 3-0). When changing the
number of drive raster-rows, adjust the frame frequency too. For details, see “Frame Frequency
Adjustment Function”. When the RGB interface is selected, this function is not available.
DIV Bits and Division Ratio
DIV1
DIV0
Division Ratio
Internal Operating Clock Frequency
0
0
1
fosc / 1
0
1
2
fosc / 2
1
0
4
fosc / 4
1
1
8
fosc / 8
fosc = R-C oscillation frequency
Formula for the frame frequency
fosc
Frame frequency
=
[Hz]
Clock cycles per raster-row × division ratio × (Line + BP + FP)
fosc: R-C oscillation frequency
Line: number of drive raster-rows (NL bit)
Division ratio: DIV bit
Clock cycles per raster-row: RTN bit
FP : the number of raster-rows in the front porch
BP : the number of raster-rows in the back porch
EQ1-0: Equalizing period is prolonged as the number of clocks specified with EQ1-0 bits. The
equalization signal is output only with the alternating current.
EQ Bits
Equalizing period
EQ1
EQ0
Internal Operation
RGB I/F Operation
(synchronized with the internal operating clock)
(synchronized with DOTCLK )
0
0
Not equalized
Not equalized
0
1
1 clock
8 clocks
1
0
2 clocks
16 clocks
1
1
3 clocks
24 clocks
SDT1-0: Determine the amount of delay for the source output from the falling edge of the gate output.
Rev.0.12, May 09 2003, page 42 of 156
HD66789
Preliminary
SDT Bits
Delay Time for Source Signal
SDT1
SDT0
Internal Operation
RGB I/F Operation
(synchronized with the internal operating clock)
(synchronized with DOTCLK)
0
0
1 clock
8 clocks
0
1
2 clocks
16 clocks
1
0
3 clocks
24 clocks
1
1
4 clocks
32 clocks
Note 1) The amount of delay for the source output is measured from the falling edge of the CL1.
1H period
1H period
CL1
M
Gn
Sn
EQ
Source output delay
equalizing period
Source output delay and equalize period
Note 1) In internal operation and VSYNC interface modes, the reference clock is the internal operating clock.
In RGB interface modes, the reference clock is DOTCLK.
NO1-0: Specify the amount of non-overlap time for the gate output.
In the internal operation and VSYNC interface modes, the reference clock is the internal operating clock.
In the RGB interface mode, the reference clock is DOTCLK.
NO Bits
Non-overlap time
NO1
NO0
Internal Operation
RGB I/F Operation
(synchronized with the internal operating clock)
(synchronized with DOTCLK)
0
0
0 clock
0 clock
0
1
4 clocks
32 clocks
1
0
6 clocks
48 clocks
1
1
8 clocks
64 clocks
Note 1) The amount of non-overlap time is defined from the falling edge of the CL1.
Rev.0.12, May 09 2003, page 43 of 156
HD66789
Preliminary
1H period
1H period
CL1
Gn
Non-overlap period
Gn + 1
Non-overlap period
External Display Interface Control (R0Ch)
R/W
RS
W
1
IB15 IB14 IB13 IB12 IB11 IB10 IB9
0
0
0
0
0
0
0
IB8
RM
IB7
IB6
0
0
IB5
IB4
DM1 DM0
IB3
IB2
0
0
IB1
IB0
RIM1 RIM0
RIM1–0: Specify the RGB I/F mode when the RGB interface is selected. Specifically, this setting
specifies the RGB interface mode when it is selected by setting DM and RM bits. The setting must be
made before the display operation through the external display interface. Do not make a setting during
display.
RIM Bits
RIM1
RIM0
RGB Interface Mode
0
0
18-bit RGB interface (one-time transfer/pixel)
0
1
16-bit RGB interface (one-time transfer/pixel)
1
0
6-bit RGB interface (three-time transfers/pixel)
1
1
Setting disabled
Note 1) The instruction register setting is possible only through a system interface.
Note 2) Data transmission and input of DOTCLK in the 6-bit RGB interface mode should be executed by
RGB.
Rev.0.12, May 09 2003, page 44 of 156
HD66789
Preliminary
DM1–0:Specify the display operation mode. The interface through which display operation is executed is
selected with DM1-0 bits. This setting enables switching between internal clock operation and external
display interface. Switching within the external display interface modes (between RGB-I/F and VSYNCI/F) cannot be made.
DM Bits
DM1
DM0
Display Interface
0
0
Internal clock operation
0
1
RGB interface
1
0
VSYNC interface
1
1
Setting disabled
RM: Specify the interface for RAM accesses. RAM is accessible only through the interface specified with
RM bit. When the display data is written through RGB-I/F, set RM = 1. The RM-bit setting can be made
irrespective of the display operation mode. This means the display data can be updated through a system
interface even during the display period through RGB interface by setting RM = 0.
RM Bit
RM
Interface for RAM Access
0
System interface/VSYNC interface
1
RGB interface
Rev.0.12, May 09 2003, page 45 of 156
HD66789
Preliminary
Setting for external display interface control allows selecting an optimum interface for the kind of display
as follows. When displaying a moving picture (RGB-I/F/VSYNC-I/F), the display data must be written in
the high-speed mode (HWM = 1) which enables high-speed RAM access with low power consumption.
Display state and interfaces
Display State
Operation Mode
RAM Access
(RM)
Display Operation Mode (DM1-0)
Still pictures
Internal clock
operation
System interface
(RM = 0)
Internal clock operation
(DM1-0 = 00)
Moving pictures
RGB interface (1)
RGB interface
(RM = 1)
RGB interface
(DM1-0 = 01)
Rewrite still picture
area while displaying
moving pictures.
RGB interface (2)
System interface
(RM = 0)
RGB interface
(DM1-0 = 01)
Moving pictures
VSYNC interface
System interface
(RM = 0)
VSYNC interface
(DM1-0 = 10)
Note 1) The instruction register setting is made only through a system interface.
Note 2) Switching between RGB-I/F and VSYNC-I/F cannot be made.
Note 3) The RGB-I/F mode settings is not changeable during RGB I/F operation.
Note 4) For details on the transition flow between operation modes, see the “External Display Interface”
section.
Note 5) Use the high-speed write mode (HWM = 1) during the write operation in RGB-I/F and VSYNC-I/F
modes.
Internal clock operation mode
All display operations are controlled by signals generated by the internal clock in internal clock operation
mode. All inputs through the external display interface are invalid. The internal RAM is accessible only
through a system interface.
RGB interface mode (1)
Display operation is controlled by the frame synchronization clock (VSYNC), line synchronizing signal
(VSYNC), and dot clock (DOTCLK) in the RGB interface mode. These signals must be supplied
throughout the display operation in this mode.
All display data are stored in the internal RAM, transmitted with PD17-0 bits by pixel. The combination
with the high-speed write mode and window address function enables simultaneous display of both moving
picture areas and the internal RAM area. The data are transmitted only when the screen is being updated,
thereby reducing the overall data transmission to minimum.
The periods of the front (FP) and back (BP) porches and the display period (NL) are automatically
generated in the HD66782 by counting the clock of line synchronizing signal (HSYNC) in accordance to
the frame synchronizing signal (VSYNC). Transmit pixel data with PD 17-0 bits in accordance with the
setting specified above.
Rev.0.12, May 09 2003, page 46 of 156
HD66789
Preliminary
RGB interface mode (2)
When RGB-I/F is selected, RAM data are changeable through the system interface. This write operation
must be performed while display data are not being transmitted through the RGB-I/F (ENABLE = High).
When reverting from the system interface mode to the data transmission through the RGB interface, make a
new setting for the address set and index (R22h) after changing the aforementioned settings.
VSYNC interface mode
The internal display operation is synchronized with the frame-synchronizing signal (VSYNC) in the
VSYNC interface mode. By writing data to RAM at a fixed speed on the falling edge of VSYNC, it
enables moving pictures display with a system interface. In this case, there are some constraints in the
RAM write speed and methods. For details, see the “External Display Interface” section.
In the VSYNC-I/F mode, only VSYNC input is valid. Other input signals for the external display interface
are invalid.
The front porch (FP), back porch (BP) periods and display period (NL) are automatically generated in
accordance to the frame synchronizing signal (VSYNC) according to the register setting of HD66789.
Rev.0.12, May 09 2003, page 47 of 156
HD66789
Preliminary
Power Control 1 (R10h)
Power Control 2 (R11h)
R/W
RS
IB15 IB14 IB13 IB12 IB11 IB10 IB9
W
1
0
W
1
0
SAP2 SAP1 SAP0
0
0
0
IB8
IB7
IB6
IB5
IB4
IB3
IB2
IB1
IB0
SLP STB
0
BT2 BT1 BT0
0
AP2 AP1
AP0
0
DK
0
DC12 DC11 DC10
0
DC02 DC01 DC00
0
VC2 VC1 VC0
SAP2-0: Adjust the amount of fixed current from the fixed current source of operational amplifier for the
source driver. When the amount of fixed current is set large, the operational amplifier will stabilize, while
the current consumption will increase. Select an optimum amount of current taking both the display quality
and the current consumption into account. During non-display operation, set SAP2-0 = “000” to halt the
operation of operational amplifier, to reduce the current consumption.
SAP Bits and the amount of current for the Op-amp
SAP2
SAP1
SAP0
Op-amp Current
SAP2
SAP1
SAP0
Op-amp Current
0
0
0
Halt
1
0
0
1 (fixed)
0
0
1
Setting disabled
1
0
1
1.25 (fixed)
0
1
0
0.62 (fixed)
1
1
0
1.43 (fixed)
0
1
1
0.71 (fixed)
1
1
1
Setting disabled
BT2–0: Change the step-up scale of the step-up circuit. Adjust the scale according to the voltage. Smaller
scale consumes lesser current.
DC02–00: Select the operating frequency for the step-up circuit 1. The higher frequency enhances the
drive capacity of step-up circuit as well as the display quality, while the current consumption will increase.
Adjust the frequency taking both the display quality and the current consumption into consideration.
DC12–10: Select the operating frequency for the step-up circuit 2. The higher frequency enhances the
drive capacity of step-up circuit as well as the display quality, while the current consumption will increase.
Adjust the frequency taking both the display quality and the current consumption into consideration.
AP2–0: Adjust the amount of fixed current from the fixed current source of operational amplifier for the
liquid crystal drive power supply. When the amount of fixed current is set large, the liquid crystal drive
capacity will be enhanced and the display quality will improve, while the current consumption will increase.
Select an optimum amount of current taking both the display quality and the current consumption into
account. During non-display operation, set AP2-0 = “000” to halt the operation of operational amplifier to
reduce current consumption.
DK: Control the operation of the step-up circuit 1. When turning on the power supply, stop the start up of
VLOUT1 for a moment, and wait for an enough time until VLOUT2 is stabilized before starting up
VLOUT1. For details, see the “Power Supply Setting Flow” section.
Rev.0.12, May 09 2003, page 48 of 156
HD66789
Preliminary
SLP: When SLP = 1, the HD66789 enters into the sleep mode. In the sleep mode, internal display
operation is halted except the R-C oscillator to reduce current consumption. Only power control
instructions
(BT2–0, DC2–0, AP2–0, SLP, STB, VC2-0, VRH4-0, VCOMG, VDV4-0, and VCM4-0 bits) are executed
during the sleep mode. No change is made to the GRAM data or instructions during the sleep mode,
although it is retained.
STB: When STB = 1, the HD66789 enters into the standby mode. In the standby mode, display operation
is completely halted, and all internal operation including the internal R-C oscillator and reception of
external clock pulse, is halted. For details, see the “Standby Mode” section. Only instructions to release
the standby mode (STB = 0) and to start oscillation are accepted during the standby mode. Changes in the
GRAM data or instructions during the standby mode are susceptible to destruction. These changes should
be made after releasing the standby mode.
VC2-0: Adjust the reference voltage for VLEG1OUT, VciOUT voltages to the optimum ratio of Vci.
AP2
AP1
AP0
Amount of current in operational amplifier
0
0
0
halt
0
0
1
setting disabled
0
1
0
0.5 (fixed)
0
1
1
0.75 (fixed)
1
0
0
1 (fixed)
1
0
1
1.25 (fixed)
1
1
0
1.5 (fixed)
1
1
1
setting disabled
DC02
DC01
DC00
Step-up circuit 1
step-up frequency
DC12
DC11
DC10
Step-up circuit 2
step-up frequency
0
0
0
oscillation clock/8
0
0
0
oscillation clock/16
0
0
1
oscillation clock/16
0
0
1
oscillation clock/32
0
1
0
oscillation clock/32
0
1
0
oscillation clock/64
0
1
1
oscillation clock/64
0
1
1
oscillation clock/128
1
0
0
oscillation clock/128
1
0
0
oscillation clock/256
1
0
1
setting disabled
1
0
1
setting disabled
1
1
0
setting disabled
1
1
0
setting disabled
1
1
1
setting disabled
1
1
1
setting disabled
Rev.0.12, May 09 2003, page 49 of 156
HD66789
Preliminary
BT2
BT1
BT0
VLOUT1
output
(DDVDH)
VLOUT4
output
(VCL)
VLOUT2 output
(VGH)
VLOUT3 output
(VGL)
Capacitor
connection pins
0
0
0
Vci1 x 2
[x2]
Vci1 x -1
[x-1]
DDVDH x 3
[x 6]
- (Vci1+DDVDH x 2)
[x –5]
DDVDH, VGH, VGL, VCL,
0
0
1
↑
↑
DDVDH x 3
[x 6]
- (DDVDH x 2)
[x –4]
DDVDH, VGH, VGL, VCL,
C11±, C12±, C21±, C22±,
C11±, C12±, C21±, C22±,
0
1
0
↑
↑
DDVDH x 3
[x 6]
- (Vci1+DDVDH)
[x –3]
DDVDH, VGH, VGL, VCL,
0
1
1
↑
↑
Vci1 +DDVDH x 2
[x 5]
- (Vci1+DDVDH x 2)
[x –5]
DDVDH, VGH, VGL, VCL,
Vci1 +DDVDH x 2
[x 5]
- (DDVDH x 2)
[x –4]
DDVDH, VGH, VGL, VCL,
Vci1 +DDVDH x 2
[x 5]
- (Vci1+DDVDH)
[x –3]
DDVDH, VGH, VGL, VCL,
DDVDH x 2
[x 4]
- (DDVDH x 2)
[x –4]
DDVDH, VGH, VGL, VCL,
DDVDH x 2
[x 4]
- (Vci1+DDVDH)
[x –3]
DDVDH, VGH, VGL, VCL,
1
1
1
1
0
0
1
1
↑
0
↑
↑
1
↑
↑
0
↑
↑
1
↑
C11±, C12±, C21±, C22±,
C11±, C12±, C21±, C22±,
C11±, C12±, C21±, C22±,
C11±, C12±, C21±, C22±,
C11±, C12±, C21±, C22±,
C11±, C12±, C21±
Note 1) The numerals in the bracket [ ] show the step-up scale from Vci1.
Note 2) The capacitor connection pins are step-up capacitors which are necessary for DDVDH, VCL, VGH,
VGL voltages.
Note 3) Set the voltage within the following range: DDVDH = 5.5 V (Max.), VCL = - 3.3 V (Min.),
VGH = 16.5 V (Max.), VGL = -16.5 V (Min.)
VC2
VC1
VC0
Step-up circuit 1
step-up frequency
DK
Operation of
step-up circuit 1
0
0
0
Vci
0
Operation
0
0
1
0.92 x Vci
1
Halt
0
1
0
0.87 x Vci
0
1
1
0.83 x Vci
1
0
0
0.76 x Vci
1
0
1
0.73 x Vci
1
1
0
setting disabled
1
1
1
setting disabled
Rev.0.12, May 09 2003, page 50 of 156
HD66789
Preliminary
Power Control 3 (R12h)
Power Control 4 (R13h)
R/W
RS
IB15 IB14 IB13 IB12 IB11 IB10 IB9
W
1
0
0
W
1
0
0
0
0
0
0
0
IB8
IB7
IB6
IB5
0
0
0
0
PON VRH3 VRH2 VRH1 VRH0
0
VCM4 VCM3 VCM2 VCM1 VCM0
VCO
VDV4 VDV3 VDV2 VDV1 VDV0
MG
0
0
IB4
IB3
IB2
IB1
IB0
PON: Start operation of VLOUT3. To stop operation, set PON = 0. To start operation, set PON = 1.
VRH3-0: Set the scale for amplifying VLOUT1 voltage (the reference voltage for VCOM and grayscale
voltage). REGP voltage is amplified by 1.33 ~ 2.775 times.
VCOMG: When VCOMG = 1, VcomL outputs a negative voltage (1.0V ~ -Vci+0.5V Max.). When
VCOMG = 0, the amplifiers for the negative voltage is halted, thereby saving power consumption. When
VCOMG = 0, settings with VDV4-0 bits are invalid. In this case, to adjust AC amplitude of Vcom, make
settings with VCM4-0 bits (VcomH setting). VCOMG = 1 is valid when PON = 1.
VDV4-0: Set the AC amplitude of Vcom during Vcom AC drive. The amplitude can be specified within
the range of 0.6 ~ 1.23 times of VREG1OUT. When VCOMG = 0, this setting is invalid.
VCM4-0: Set the VcomH voltage (The higher voltage during Vcom AC drive). The voltage can be
specified within the range of 0.4 ~ 0.98 times of VREG1OUT. When VCM4-0 = “11111”, the internal
volume adjustment operation is halted, and the VcomH voltage can be adjust by placing an external resistor
from VcomR.
Rev.0.12, May 09 2003, page 51 of 156
HD66789
Preliminary
VRH3
VRH2
VRH1
VRH0
VREG1OUT voltage
0
0
0
0
REGP x 1.33
0
0
0
1
REGP x 1.45
0
0
1
0
REGP x 1.55
0
0
1
1
REGP x 1.65
0
1
0
0
REGP x 1.75
0
1
0
1
REGP x 1.80
0
1
1
0
REGP x 1.85
0
1
1
1
halt
1
0
0
0
REGP x 1.90
1
0
0
1
REGP x 2.175
1
0
1
0
REGP x 2.325
1
0
1
1
REGP x 2.475
1
1
0
0
REGP x 2.625
1
1
0
1
REGP x 2.700
1
1
1
0
REGP x 2.775
1
1
1
1
halt
Rev.0.12, May 09 2003, page 52 of 156
HD66789
Preliminary
VCM4
VCM3
VCM2
VCM1
VCM0
VcomH
VDV4
VDV3
VDV2
VDV1
VDV0
Vcom amplitude
0
0
0
0
0
VREG1OUT x 0.40
0
0
0
0
0
VREG1OUT x 0.60
0
0
0
0
1
VREG1OUT x 0.42
0
0
0
0
1
VREG1OUT x 0.63
0
0
0
1
0
VREG1OUT x 0.44
0
0
0
1
0
VREG1OUT x 0.66
:
:
:
:
:
:
:
:
:
:
:
:
0
1
1
0
0
VREG1OUT x 0.64
0
1
1
0
0
VREG1OUT x 0.96
0
1
1
0
1
VREG1OUT x 0.66
0
1
1
0
1
VREG1OUT x 0.99
0
1
1
1
0
VREG1OUT x 0.68
0
1
1
1
0
VREG1OUT x 1.02
0
1
1
1
1
Halt internal volume.
Adjust with a variable
external resistor from
VcomR.
0
1
1
1
1
Setting disabled
1
0
0
0
0
VREG1OUT x 0.70
1
0
0
0
0
VREG1OUT x 1.05
1
0
0
0
1
VREG1OUT x 0.72
1
0
0
0
1
VREG1OUT x 1.08
1
0
0
1
0
VREG1OUT x 0.74
1
0
0
1
0
VREG1OUT x 1.11
:
:
:
:
:
:
1
0
0
1
1
VREG1OUT x 1.14
1
1
1
0
0
VREG1OUT x 0.94
1
0
1
0
0
VREG1OUT x 1.17
1
1
1
0
1
VREG1OUT x 0.96
1
0
1
0
1
VREG1OUT x 1.20
1
1
1
1
0
VREG1OUT x 0.98
1
0
1
1
0
1
Halt internal volume.
Adjust with a variable
external resistor from
VcomR.
1
1
1
1
1
0
1
1
1
1
*
*
VREG1OUT x 1.23
Setting disabled
Setting disabled
*
Note 1) Adjust VREG1OUT and VCM0-4 to set VcomH the same level as VDH or less.
Note 2) Adjust VREG1OUT and VDV0-4 to set the amplitude of Vcom 0.6V or less.
RAM Address Set (R21h)
R/W
W
RS
1
IB15 IB14 IB13 IB12 IB11 IB10
AD
15
AD
14
AD
13
AD
12
AD
11
AD
10
IB9
AD
9
IB8
AD
8
IB7 IB6
IB5
AD
7
AD
5
AD
6
IB4
AD
4
IB3 IB2
AD
3
AD
2
IB1
AD
1
IB0
AD
0
AD15–0: Make the initial setting of GRAM address in the address counter (AC). After GRAM data are
written, the address counter is automatically updated according to the settings with AM, I/D bits and the
setting for a new GRAM address is not required in the address counter. Therefore, data are written
consecutively without resetting the address. The address counter is not automatically updated when data
are read out from GRAM.
GRAM address setting can not be made during the standby mode. An address set should be made within
the area specified with the window address.
When the RGB interface is selected (RM = 1), the setting of the address for AD15-0 is made every frame at
the falling edge of VSYNC. When the internal clock operation or VSYNC interface is selected (RM = 0),
the setting of the address is made when the instruction is executed.
Rev.0.12, May 09 2003, page 53 of 156
HD66789
Preliminary
GRAM Address Range
AD15–AD0
GRAM Setting
“0000”H – “00AF”H
Bitmap data for G1
“0100”H – “01AF”H
Bitmap data for G2
“0200”H – “02AF”H
Bitmap data for G3
“0300”H – “03AF”H
Bitmap data for G4
:
:
“EC00”H – “ECAF”H
Bitmap data for G237
“ED00”H – “EDAF”H
Bitmap data for G238
“EE00”H – “EEAF”H
Bitmap data for G239
“EF00”H – “EFAF”H
Bitmap data for G240
Write Data to GRAM (R22h)
R/W
RS
W
1
RAM write data (WD17-0) The pin assignment for DB17-0 varies for each interface (see below).
PD17 PD16 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6
RGB-I/F
mode:
WD
17
WD WD
16 15
WD
14
WD
13
WD
12
WD
11
WD
10
WD
9
WD
8
WD
7
WD
6
PD5
WD
5
PD4
WD
4
PD3 PD2 PD1 PD0
WD WD
2
3
WD
1
WD
0
WD17–0: All data are expanded into 18 bits internally before written to GRAM. Each interface has its
own way of expanding data to 18 bits.
The grayscale level is selected according to GRAM data. The address is automatically updated according
to the setting with the AM and I/D bits after data are written to GRAM. During the standby mode, no
access is allowed to GRAM. When 8 or 16 bit interface modes is selected, the data in the MSB of R and B
pixels are also written to the LSB of R and B pixels respectively to expand the 8/16- bit data into the 18bit
data internally.
During the RGB interface mode, when writing data to RAM through a system interface, make sure to avoid
conflicts between writing through the RGB interface and writing through the system interface.
When the 18-bit RGB interface is selected, the18-bit data in PD17-0 bits are written, and 262,144 colors are
available. When the 16-bit RGB interface is selected, the data in the MSB of R and B pixels are also
written to the LSB of R and B pixels respectively, and 65,536 colors are available.
Rev.0.12, May 09 2003, page 54 of 156
HD66789
Preliminary
18-bit interface(262,144 colors)
INPUT
Write Data
to GRAM
RGB
Assignment
DB
17
DB
16
DB
15
DB
14
DB
13
DB
12
DB
11
DB
10
DB
9
DB
8
DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
DB
0
WD
17
WD
16
WD
15
WD
14
WD
13
WD
12
WD
11
WD
10
WD
9
WD
8
WD
7
WD
6
WD
5
WD
4
WD
3
WD
2
WD
1
WD
0
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
one pixel
16-bit interface(65,536 colors)
INPUT
DB
17
DB
16
DB
15
DB
14
DB
13
DB
12
DB
11
DB
10
Write Data
to GRAM
WD
17
WD
16
WD
15
WD
14
WD
13
WD
12
WD
11
WD
10
RGB
Assignment
R5
R4
R3
R2
R1
R0
G5
G4
DB
8
DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
WD
9
WD
8
WD
7
WD
6
WD
5
WD
4
WD
3
WD
2
WD
1
WD
0
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
one pixel
9-bit interface (262,144 colors)
1st Transmission (Upper)
2nd Transmission (Lower)
INPUT
DB
17
DB
16
DB
15
DB
14
DB
13
DB
12
DB
11
DB
10
DB
9
DB
17
DB
16
DB
15
DB
14
DB
13
DB
12
DB
11
DB
10
DB
9
Write Data
to GRAM
WD
17
WD
16
WD
15
WD
14
WD
13
WD
12
WD
11
WD
10
WD
9
WD
8
WD
7
WD
6
WD
5
WD
4
WD
3
WD
2
WD
1
WD
0
RGB
Assignment
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
one pixel
Write data to GRAM: Bit assignment
Rev.0.12, May 09 2003, page 55 of 156
HD66789
Preliminary
8-bit interface (65,536 colors) TRI = 0, DFM1-0 = 00
1st Transmission (Upper)
2nd Transmission (Lower)
INPUT
DB
17
DB
16
DB
15
DB
14
DB
13
DB
12
DB
11
DB
10
Write Data
to GRAM
WD
17
WD
16
WD
15
WD
14
WD
13
WD
12
WD
11
WD
10
RGB
Assignment
R5
R4
R3
R2
R1
R0
G5
G4
DB
17
DB
16
DB
15
DB
14
DB
13
DB
12
DB
11
DB
10
WD
9
WD
8
WD
7
WD
6
WD
5
WD
4
WD
3
WD
2
WD
1
WD
0
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
one pixel
8-bit interface (262,144 colors) TRI =1, DFM1-0 = 10
1st Transmission
INPUT
Write Data
to GRAM
RGB
Assignment
2nd Transmission
DB DB DB DB DB DB DB
17 16 15 14 13
12 17
DB
16
DB DB
15 14
3rd Transmission
DB DB
13 12
DB DB DB
17 16 15
DB DB
14 13
DB
12
WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD
0
17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
R5
R4
R3 R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
One pixel
8-bit interface (65,536 colors) TRI =1, DFM1-0 = 11
1st Transmission
INPUT
Write Data
to GRAM
RGB
Assignment
2nd Transmission
DB DB DB DB DB DB DB
17 16 15 14 13
12 17
DB
16
DB DB
15 14
3rd Transmission
DB DB
13 12
DB DB DB
17 16 15
DB DB
14 13
DB
12
WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD
0
17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
R5
R4
R3 R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
One pixel
Write data to GRAM: Bit assignment
Rev.0.12, May 09 2003, page 56 of 156
B4
B3
B2
B1
B0
HD66789
Preliminary
18-bit RGB interface (262,144 colors)
INPUT
PD PD PD PD PD PD
17 16 15 14 13 12
Write Data
to GRAM
RGB
Assignment
PD
11
PD
10
PD PD
9
8
PD PD
7
6
PD
5
PD
4
PD
3
PD PD
2
1
PD
0
WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD
0
17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
R5
R4
R3 R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
One pixel
The index register should be set when data is written in RGB-I/F mode.
16-bit RGB interface (65,563 colors)
INPUT
PD PD PD PD PD
17 16 15 14 13
PD PD
11 10
Write Data
to GRAM
WD WD WD WD WD
17 16 15 14 13
WD WD WD WD WD WD WD WD WD WD WD
11 10
9
8
7
6
5
4
3
2
1
RGB
Assignment
R5
R4
R3 R2
R1
R0
G5
G4
PD PD
9
8
G3
G2
PD PD
7
6
G1
G0
PD
5
B5
PD PD
4
3
B4
B3
PD PD
2
1
B2
B1
B0
One pixel
The index register should be set when data is written in RGB-I/F mode.
6-bit RGB interface (262,144 colors)
1st Transmission
INPUT
Write Data
to GRAM
RGB
Assignment
2nd Transmission
PD PD PD PD PD PD PD
17 16 15 14 13
12 17
PD
16
PD PD
15 14
3rd Transmission
PD PD
13 12
PD PD PD PD PD
17 16 15 14 13
PD
12
WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD
0
17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
R5
R4
R3 R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
One pixel
The index register should be set when data is written in RGB-I/F mode.
Write data to GRAM (RGB interface): Bit assignment
Rev.0.12, May 09 2003, page 57 of 156
HD66789
Preliminary
GRAM data settings
Grayscale
RGB
Negative
GRAM data settings
Positive
RGB
Grayscale
Negative
Positive
000000
V0
V31
100000
V16
V15
000001
(V0-V1)/2
(V30-V31)/2
100001
(V16-V17)/2
(V14-V15)/2
000010
V1
V30
100010
V17
V14
000011
(V1-V2)/2
(V29-V30)/2
100011
(V17-V18)/2
(V13-V14)/2
000100
V2
V29
100100
V18
V13
000101
(V2-V3)/2
(V28-V29)/2
100101
(V18-V19)/2
(V12-V13)/2
000110
V3
V28
100110
V19
V12
000111
(V3-V4)/2
(V27-V28)/2
100111
(V19-V20)/2
(V11-V12)/2
001000
V4
V27
101000
V20
V11
001001
(V4-V5)/2
(V26-V27)/2
101001
(V20-V21)/2
(V10-V11)/2
001010
V5
V26
101010
V21
V10
001011
(V5-V6)/2
(V25-V26)/2
101011
(V21-V22)/2
(V9-V10)/2
001100
V6
V25
101100
V22
V9
001101
(V6-V7)/2
(V24-V25)/2
101101
(V22-V23)/2
(V8-V9)/2
001110
V7
V24
101110
V23
V8
(V7-V8)/2
001111
(V7-V8)/2
(V23-V24)/2
101111
(V23-V24)/2
010000
V8
V23
110000
V24
V7
010001
(V8-V9)/2
(V22-V23)/2
110001
(V24-V25)/2
(V6-V7)/2
010010
V9
V22
110010
V25
V6
010011
(V9-V10)/2
(V21-V22)/2
110011
(V25-V26)/2
(V5-V6)/2
010100
V10
V21
110100
V26
V5
010101
(V10-V11)/2
(V20-V21)/2
110101
(V26-V27)/2
(V4-V5)/2
010110
V11
V20
110110
V27
V4
010111
(V11-V12)/2
(V19-V20)/2
110111
(V27-V28)/2
(V3-V4)/2
011000
V12
V19
111000
V28
V3
011001
(V12-V13)/2
(V18-V19)/2
111001
(V28-V29)/2
(V2-V3)/2
011010
V13
V18
111010
V29
V2
011011
(V13-V14)/2
(V17-V18)/2
111011
(V29-V30)/2
(V1-V2)/2
011100
V14
V17
111100
V30
V1
011101
(V14-V15)/2
(V16-V17)/2
111101
(V30-V31)/2
(V0-V1)/2
(V0-V1)/3
V0
011110
V15
V16
111110
(V30-V31)/3
011111
(V15-V16)/2
(V15-V16)/2
111111
V31
GRAM data and LCD output level
Rev.0.12, May 09 2003, page 58 of 156
HD66789
Preliminary
RAM Access through RGB-I/F and System I/F
The HD66789 writes all display data on the screens to the internal RAM. This enables the transfer of only
the data for the moving picture area as well as for the frames for updating screens through the RGB
interface. By writing data in the high speed write mode (HWM = 1) and with the window address function,
the HD66789 enables a high-speed access to RAM with low power consumption while displaying moving
pictures. In the frames other than the moving picture screen update, the display data in the area other than
the moving picture area can be updated through a system interface.
The RAM access is also possible through a system interface even in the RGB-I/F mode. In the RGB
interface mode, data are written to RAM in synchronization with the DOTCLK during ENABLE = “Low”.
When writing data in the RGB-I/F mode through the system interface, it is necessary to set the ENABLE
“High” to stop writing through the RGB interface. After accessing to RAM through the system interface,
wait an enough time for the write/read bus cycle before starting accessing to RAM through the RGB
interface. When RAM accesses through the RGB and system interfaces conflict, there will be no guarantee
that data are properly written to RAM.
Updating
(both panels)
Updating
(both panels)
VSYNC
ENABLE
DOTCLK
PD17-0
Setting of index
System interface
Index
R22
RM=0
Updating or moving
picture area
Setting
of
address
Index
R22
Updating of area
other than moving
picture area
RM=1
Updating still picture area*1
Setting
of
address
Index
R22
Updating or moving
picture area
Note 1) When RGB-I/F is selected, the address setting is made at every falling edge of VSYNC.
Note 2) The address set and the index set must be made before the RAM access throught the RGB interface.
Note 3) The high-speed write mode should be used in RGB-I/F and VSYNC-I/F modes.
2001/01/01 00:00
Still picture area
Moving picture area
Updating Still Picture Area during Displaying a Moving Picture
Rev.0.12, May 09 2003, page 59 of 156
HD66789
Preliminary
Read Data Read from GRAM (R22h)
R/W
RS
R
1
RAM Read data (RD17-0) The pin assignment for DB17-0 varies for each interface (see below).
RD17–0: Read 18-bit data from GRAM. The bit assignment for the data that are read out from GRAM is
different according to the interface.
When data are read out from GRAM to the microcomputer, the first word read immediately after GRAM
address set are latched in the internal read-data latch, and thereby the data in the data bus (DB17–0) are
nullified. The second word is read as valid data. When the HD66789 performs an internal bit processing,
such as logical operation, the data latched in the read-data latch are used to complete it by single read out
operation. The data are expanded internally into 18 bits before going through the logical operation. When
the 8-/16-bit interfaces are selected, GRAM data in the LSBs of R and B pixels are not read out. This
function is not available in the RGB interface mode.
18-bit interface
GRAM data
R5
R4
R3 R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
One pi xel
Read
data
Output
RD RD RD RD
17 16 15 14
RD RD RD RD RD RD RD
13 12 11 10
9
8
7
RD RD RD RD
6
5
4
3
RD RD RD
2
1
0
DB
17
DB
13
DB
6
DB
2
DB
16
DB DB
15 14
DB
12
DB
11
DB
10
DB
9
DB DB
8
7
DB
5
DB DB
4
3
Read data from GRAM: Bit assignment
Rev.0.12, May 09 2003, page 60 of 156
DB
1
DB
0
HD66789
Preliminary
16-bit interface
GRAM
data
R5
R4
R3 R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
One pixel
Read RD RD RD RD
data 17 16 15 14
Output
DB
17
DB
16
RD RD RD RD RD RD RD
13 12 11 10
9
8
7
DB DB
15 14
DB
13
DB
12
DB
11
DB
10
R3 R2
R1
R0
G5
G4
RD RD RD RD
6
5
4
3
RD RD RD
2
1
0
DB
8
DB
7
DB DB
6
5
DB
4
DB
3
DB
2
DB
1
G2
G1
G0
B4
B3
B2
B1
9-bit interface
GRAM
data
R5
R4
G3
B5
B0
One pixel
Read
data
RD RD RD RD
17 16 15 14
RD RD RD RD RD RD RD
13 12 11 10
9
8
7
RD RD RD RD
6
5
4
3
RD RD RD
2
1
0
Output
DB
17
DB
13
DB DB
15 14
DB
11
DB
16
DB DB
15 14
DB
12
DB
11
DB
10
DB DB
9 17
DB
16
1st Transmission
(Upper)
DB
13
DB
12
DB
10
DB
9
B1
B0
2nd Transmission
(Lower)
8-bit interface / SPI
GRAM
data
R5
R4
R3 R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
One pixel
Read
data
Output
RD RD RD RD
17 16 15 14
DB
17
DB
16
DB DB
15 14
RD RD RD RD RD RD RD
13 12 11 10
9
8
7
DB
13
DB
12
DB
11
1st Transmission
(Upper)
DB
10
DB
17
DB
16
RD RD RD RD
6
5
4
3
DB DB
15 14
DB
13
DB
11
2nd Transmission
(Lower)
Read data from GRAM: Bit assignment
Rev.0.12, May 09 2003, page 61 of 156
DB
12
RD RD RD
0
2
1
DB
10
HD66789
Preliminary
Set the I/D, AM, HSA/HSE, and
VSA/VEA bits
Set the I/D, AM, HSA/HSE, and
VSA/VEA bits
Address: N set
Address: N set
First word
Dummy read (invalid data)
GRAM Read-data latch
Second word
Read (data of address n)
Read-data latch DB17-0
First word
Second word
Address: M set
Dummy read (invalid data)
GRAM Read-data latch
Write (data of address n)
DB17-0 GRAM
Automatic address update: N +α
First word
Dummy read (invalid data)
GRAM Read-data latch
First word
Dummy read (invalid data)
GRAM Read-data latch
Second word
Read (data of address n)
Read-data latch DB17-0
Second word
Write(data of address n)
DB17-0 GRAM
i) Read data to the microcomputer
ii) Logical arithmetic operacion inside HD66789
GRAM read sequence
Rev.0.12, May 09 2003, page 62 of 156
HD66789
Preliminary
RAM Write Data Mask (R23h)
RAM Write Data Mask (R24h)
R/W
RS
IB15 IB14 IB13 IB12 IB11 IB10 IB9
IB8
IB7
WM WM WM WM WM WM
11
10
9
8
7
6
W
1
0
0
W
1
0
0
0
0
0
1
1
1
IB6
IB5
IB4
IB3
IB2
IB1
IB0
0
0
WM WM
5
4
0
1
WM WM WM WM WM WM
17
16
15
14
13
12
WM WM WM WM
3
2
1
0
WM17–0: Write-mask the data when they are written to GRAM by bit. For example, if WM17 = 1, the
WM17 write-mask the MSB of the data to write to GRAM so that the data in the MSB are not written to
GRAM. The rest of WM16-0 bits also write-mask the data in the corresponding bits when these bits are set
to “1”. For details, see the “Graphics Operation Function” section.
The WM17-0 bits write-mask the data to write to GRAM, which are expanded, if necessary, into 18 bits.
This function is not available in the RGB-I/F mode.
Write mask
Write data to
GRAM
WM WM WM WM WM WM WM WM WM WM WM WM WM WM WM WM WM WM
17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
R5
R4
R3 R2
R1
R0
G5
G4
G3
G2
G1
One pixel
RAM write data mask
Rev.0.12, May 09 2003, page 63 of 156
G0
B5
B4
B3
B2
B1
B0
HD66789
Preliminary
γ Control (R30h to R39h)
R/W
RS
IB15 IB14 IB13 IB12 IB11 IB10 IB9
IB8
IB7 IB6
IB5
IB4
IB2
IB1 IB0
R30
W
1
0
0
0
0
0
R31
W
1
0
0
0
0
0
PKP PKP PKP
32
31 30
0
0
0
0
0
PKP PKP PKP
22
21
20
R31
W
1
0
0
0
0
0
PKP PKP PKP
52
51 50
0
0
0
0
0
PKP PKP PKP
42
41
40
R33
W
1
0
0
0
0
0
PRP PRP PRP
12
11 10
0
0
0
0
0
PRP PRP PRP
02
01
00
R34
W
1
0
0
0
0
0
PKN PKN PKN
12
11 10
0
0
0
0
0
PKN PKN PKN
02
01 00
R35
W
1
0
0
0
0
0
PKN PKN PKN
32
31 30
0
0
0
0
0
PKN PKN PKN
22
21
20
R36
W
1
0
0
0
0
0
PKN PKN PKN
52
51 50
0
0
0
0
0
PKN PKN PKN
42
41
40
R37
W
1
0
0
0
0
0
PRN PRN PRN
12
11 10
0
0
0
0
0
PRN PRN PRN
02
01
00
R38
W
1
0
0
0
VRP VRP VRP VRP VRP
14
13
12
11
10
0
0
0
0
VRP VRP VRP VRP
03 02
01
00
W
1
0
0
0
VRN VRN VRN VRN VRN
11
10
14
13 12
0
0
0
0
VRN VRN VRN VRN
03
02
01 00
R39
0
0
0
0
0
PKP PKP PKP
02
01
00
γ Control Instructions
PKP52-00
PRP12-00
PKN52-00
PRN12-00
VRP14-00
VRN14-00
IB3
PKP PKP PKP
12
11 10
: The γ fine adjustment registers for positive polarity.
: The γ gradient adjustment registers for positive polarity.
: The γ fine adjustment registers for negative polarity.
: The γ gradient adjustment registers for negative polarity.
: The amplitude adjustment registers for positive polarity.
: The amplitude adjustment registers for negative polarity.
For details, see the “γ adjustment” section.
Rev.0.12, May 09 2003, page 64 of 156
HD66789
Preliminary
Gate Scan Position (R40h)
R/W
RS
W
1
IB15 IB14 IB13 IB12 IB11 IB10
0
0
0
0
0
IB9
IB8
IB7
0
0
0
0
IB6
IB5
0
0
IB4
IB3
IB2
IB1
IB0
SCN4 SCN3 SCN2 SCN1 SCN0
SCN4-0: Specify the position where the gate driver scan starts. Make an optimum setting for the gate
driver in use.
SC Bits and Gate scan start position
Scan Start Position
SCN4
SCN3
SCN2
SCN1
SCN0
GS = 0
GS = 1
0
0
0
0
0
G1
G240
0
0
0
0
1
G9
G232
0
0
0
1
0
G17
G224
.
.
.
.
.
.
.
.
.
.
.
.
.
.
1
1
0
1
0
G209
G32
1
1
0
1
1
G217
G24
1
1
1
0
0
G225
G16
G1
G1
G57
G176
G240
G232
GS = 0
GS = 0
NL = 10101
NL = 10101
SCM4-0 = 00000
SCM4-0 = 00111
Note: Set the value “NL + end position of the gate scan” does not exceed 240 raster-rows or more.
Rev.0.12, May 09 2003, page 65 of 156
HD66789
Preliminary
Vertical Scroll Control (R41h)
R/W
RS
W
1
IB15 IB14 IB13 IB12 IB11 IB10
0
0
0
0
0
IB9
IB8
0
0
0
IB7
IB6
IB5
IB4
IB3
IB2
IB1
IB0
VL7 VL6 VL5 VL4 VL3 VL2 VL1 VL0
VL7–0: Specify the number of raster-rows that are scrolled and control smooth scrolling in the vertical
direction. The number of raster-rows is specified from 0 to 240. The raster-rows of the specified number
are scrolled during display. When the 240th raster-row is displayed, the scrolling display starts afresh from
the 1st raster-row. The number of raster-rows that are scrolled (VL7–0) can be specified when the first
screen vertical scroll enable bit VLE1 = 1 or the second screen vertical scroll enable bit VLE2 = 1. The
number of raster-rows is fixed (not changeable) when VLE2-1 = 00. This function is not available in the
external display interface mode.
VL Bits and Display-start Raster-row
VL7
VL6
VL5
VL4
VL3
VL2
VL1
VL0
Amount of Scrolling (Number of raster-row)
0
0
0
0
0
0
0
0
0 raster-row
0
0
0
0
0
0
0
1
1 raster-row
0
0
0
0
0
0
1
0
2 raster-rows
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
1
1
1
0
1
1
1
0
238 raster-rows
1
1
1
0
1
1
1
1
239 raster-rows
Note: When setting the number of raster-rows for scrolling, it must be 239 or less.
1st-Screen Drive Position (R42h)
2nd-Screen Drive Position (R43h)
R/W
RS
IB15 IB14 IB13 IB12 IB11 IB10 IB9
IB8
IB7
IB6
IB5
IB4
IB3
IB2
IB1
IB0
W
1
SE17 SE16 SE15 SE14 SE13 SE12 SE11 SE10 SS17 SS16 SS15 SS14 SS13 SS12 SS11 SS10
W
1
SE27 SE26 SE25 SE24 SE23 SE22 SE21 SE20 SS27 SS26 SS25 SS24 SS23 SS22 SS21 SS20
SS17–10: Specify the start position for driving the first screen by line. The liquid crystal is driven by from
the gate driver of “the set value + 1”.
SE17–10: Specify the end position for driving the first screen by line. The liquid crystal is driven by to the
gate driver of “the set value + 1”. For instance, when SS17–10 = “07”H and SE17–10 = “10”H, the liquid
crystal is driven from G8 to G17, and black display is driven from G1 to G7, and G18 thereafter. Make
sure that SS17–10 ≤ SE17–10 ≤ “EF”H. For details, see the “Screen-split Drive Function” section.
Rev.0.12, May 09 2003, page 66 of 156
HD66789
Preliminary
SS27–20: Specify the start position for driving the second screen by line. The liquid crystal is driven by
from the gate driver of “the set value + 1”. The second screen is driven when SPT = 1.
SE27–20: Specify the end position for driving the second screen by line. The liquid crystal is driven by to
the gate driver of “the set value + 1”. For instance, when SPT = 1, and SS27–20 = “20”H, SE27–20 =
“4F”H, the liquid crystal is driven from G33 to G80. Make sure that SS17–10 ≤ SE17–10 < SS27–20 ≤
SE27–20 ≤ “EF”H. For details, see the “Screen-split Drive Function” section.
Horizontal RAM Address Position (R44h)
Vertical RAM Address Position (R45h)
R/W
RS
IB15 IB14 IB13 IB12 IB11 IB10
IB9
IB8
IB7
IB6
IB5
IB4
IB3
IB2
IB1
IB0
W
1
HEA7 HEA6 HEA5 HEA4 HEA3 HEA2 HEA1 HEA0 HSA7 HSA6 HSA5 HSA4 HSA3 HSA2 HSA1 HSA0
W
1
VEA7 VEA6 VEA5 VEA4 VEA3 VEA2 VEA1 VEA0 VSA7 VSA6 VSA5 VSA4 VSA3 VSA2 VSA1 VSA0
HSA7-0/HEA7-0: Specify the start/end positions of the window-address range in the horizontal direction
by address. Data are written to GRAM within the area determined by the addresses specified by HEA7-0
and HSA7-0. These addresses must be set before RAM write. In setting these bits, make sure that “00”h ≤
HSA7-0 ≤ HEA7-0 ≤ “AF”h.
VSA7-0/VEA7-0: Specify the start/end positions of the window-address range in the vertical direction by
address. Data are written to GRAM within the area determined by the addresses specified by VEA7-0 and
VSA7-0. These addresses must be set before RAM write. In setting these bits, make sure that “00”h ≤
VSA7-0 ≤ VEA7-0 ≤ “EF”h.
HSA
HEA
0000h
VSA
Window Address
Window address setting area
“00”h=< HSA7-0=<HEA7-0=<“AF”h
“00”h=<VSA7-0=<VEA7-0=<“EF”h
VEA
GRAM address space
EFAFh
Note 1) The window address area is set within the GRAM address space.
Note 2) In the high-speed write mode, data are written to the GRAM every four words.
Therefore, depending on the window address setting, dummy write operations
are required. For details, see the "High-Speed Burst RAM Write Function" section.
Note 3) The address set must be within the window address area. In the high-speed
write mode, dummy write area must also be within the window address area.
GRAM address area and window-address range
Rev.0.12, May 09 2003, page 67 of 156
HD66789
Preliminary
Instruction List (T.B.D.)
Main Category
Upper
Index
SR
0*
Sub Category
Index
Index
Status Read
Display Control
3*
4*
RAM Access
γ Control
Coordination
Control
IB12
IB11
IB10
IB9
IB8
IB7
IB6
IB5
IB4
IB3
IB2
IB1
IB0
*
L3
*
0
EPL
(0)
FLD
(0)
*
L2
*
1
SM
(0)
FLD0
(1)
*
L0
*
1
SS
(0)
EOR
(0)
ID6
0
*
0
ID5
0
*
0
0
*
L4
*
0
DPL
(0)
*
0
*
1
Driver Output Control
*
L5
*
0
HSPL
(0)
0
0
0
0
0
0
0
CP6
(0)
0
0
0
0
NW5
(0)
ID1
(1)
CP5
(0)
CP17
(0)
ID4
0
*
0
NL4
(1)
NW4
(0)
ID0
(1)
CP4
(0)
CP16
(0)
ID3
0
*
1
NL3
(1)
NW3
(0)
AM
(0)
CP3
(0)
CP15
(0)
ID2
0
*
0
NL2
(1)
NW2
(0)
LG2
(0)
CP2
(0)
CP14
(0)
ID21
0
*
0
NL1
(0)
NW1
(0)
LG1
(0)
CP1
(0)
CP13
(0)
ID0
0
1
1
NL0
(1)
NW0
(0)
LG0
(0)
CP0
(0)
CP12
(0)
0
0
GON
0
DTE
(0)
0
0
0
0
0
0
PTG1
(0)
PTG0
(0)
CL
(0)
BP3
(1)
ISC3
(0)
REV
(0)
BP2
(0)
ISC2
(0)
D1
(0)
BP1
(0)
ISC1
(0)
D0
(0)
BP0
(0)
ISC0
(0)
0
0
0
0
RTN3
(0)
RTN2
(0)
0
0
DM1
(0)
DM0
(0)
0
0
RTN1
(0)
RIM1
(0)
RTN0
(0)
RIM0
(0)
AP2
(0)
DC02
(0)
AP1
(0)
DC01
(0)
LCD AC driving Control
0
0
0
0
Entry Mode
TRI
(0)
DFM1
(0)
DFM0
(0)
CP11
(0)
BGR
(0)
CP10
(0)
0
0
CP9
(0)
CP8
(0)
04h
Compare Register (1)
0
0
05h
Compare Register (2)
0
0
0
0
0
0
0
0
PT0
(0)
FP3
(1)
VLE2
(0)
FP2
(0)
VLE1
(0)
FP1
(0)
SPT
(0)
FP0
(0)
06h
Setting Disabled
07h
Display Control (1)
0
0
0
PT1
(0)
08h
Display Control (2)
0
0
0
0
09h
Display Control (3)
0Ah
0Dh
0Eh
0Fh
Setting Disabled
Frame Cycle Adjustment
Control
External Display Interface
Control
Setting Disabled
Setting Disabled
Setting Disabled
10h
11h
0
0
0
0
0
0
0
0
NO1
(0)
NO0
(0)
SDT1
(0)
SDT0
(0)
EQ1
(0)
EQ0
(0)
DIV1
(0)
0
0
0
0
0
0
0
DIV0
(0)
RM
(0)
Power Control (1)
0
SAP2
(0)
SAP1
(0)
SAP0
(0)
0
Power Control (2)
0
0
0
0
0
BT2
(0)
DC12
(0)
BT1
(0)
DC11
(0)
0
0
12h
Power Control (3)
0
0
Power Control (4)
0
0
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
Setting Disabled
Setting Disabled
Setting Disabled
Setting Disabled
Setting Disabled
Setting Disabled
Setting Disabled
Setting Disabled
Setting Disabled
Setting Disabled
Setting Disabled
Setting Disabled
Setting Disabled
AD15
(0)
21h
RAM Address Set
RAM data Write/Read
23h
RAM Write Data Mask (1)
24h
RAM Write Data Mask (2)
25h
26h
27h
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
Setting Disabled
Setting Disabled
Setting Disabled
Setting Disabled
Setting Disabled
Setting Disabled
Setting Disabled
Setting Disabled
Setting Disabled
Setting Disabled
Setting Disabled
VCOM VDV4
(0)
G
AD14
(0)
AD13
(0)
AD12
(0)
RAM
BT0
(0)
DC10
(0)
0
0
0
0
0
0
0
VDV2
(0)
VDV1
(0)
VDV0
(0)
0
0
0
0
0
0
0
0
0
31h
γ
Control (2)
0
0
0
32h
γ
Control (3)
0
0
0
33h
γ
Control (4)
0
0
0
34h
γ
Control (5)
0
0
0
35h
γ
Control (6)
0
0
0
36h
γ
Control (7)
0
0
0
37h
γ
Control (8)
0
0
0
38h
γ
Control (9)
39h
γ
Control (10)
AD10
(0)
AD9
(0)
0
0
AD8
(0)
AD7
(0)
AD6
(0)
AD5
(0)
AD4
(0)
AD3
(0)
AD2
(0)
AD1
(0)
0
WM9
(0)
WM8
(0)
WM7
(0)
WM6
(0)
0
0
0
0
0
0
PKP12
(0)
PKP32
(0)
PKP52
0
0
(0)
PRP12
0
0
(0)
PKN12
0
0
(0)
PKN32
0
0
(0)
PKN52
0
0
(0)
PRN12
0
0
(0)
VRP14 VRP13 VRP12
(0)
(0)
(0)
VRN14 VRN13 VRN12
(0)
(0)
(0)
0
0
0
0
PKP11
(0)
PKP31
(0)
PKP51
(0)
PRP11
(0)
PKN11
(0)
PKN31
(0)
PKN51
(0)
PRN11
(0)
VRP11
(0)
VRN11
(0)
PKP10
(0)
PKP30
(0)
PKP50
(0)
PRP10
(0)
PKN10
(0)
PKN30
(0)
PKN50
(0)
PRN10
(0)
VRP10
(0)
VRN10
(0)
40h
Gate Scan Start Position
0
0
0
0
0
0
0
0
Vertical Scroll Control
0
0
0
0
0
0
0
0
42h
First Screen Driving Position
SE17
(1)
SE27
(1)
HEA7
(1)
VEA7
(1)
SE16
(1)
SE26
(1)
HEA6
(0)
VEA6
(1)
SE15
(1)
SE25
(1)
HEA5
(1)
VEA5
(1)
SE14
(1)
SE24
(1)
HEA4
(0)
VEA4
(0)
SE13
(1)
SE23
(1)
HEA3
(1)
VEA3
(1)
SE12
(1)
SE22
(1)
HEA2
(1)
VEA2
(1)
SE11
(1)
SE21
(1)
HEA1
(1)
VEA1
(1)
SE10
(1)
SE20
(1)
HEA0
(1)
VEA0
(1)
Second Screen Driving
Position
Horizontal RAM Address
Position
Vertical RAM Address
Position
Setting Disabled
Setting Disabled
Setting Disabled
Setting Disabled
Setting Disabled
Setting Disabled
Setting Disabled
Setting Disabled
Setting Disabled
Setting Disabled
Setting Disabled
Setting Disabled
Setting Disabled
AD0
(0)
0
(RD17-0)
41h
46h
47h
48h
49h
4Ah
4Bh
4Ch
4Dh
4Eh
4Fh
*
*
*
AP0
SLP
STB
DK
0
(0)
(1)
(0)
(0)
VC2
DC00
VC1
VC0
0
(0)
(0)
(0)
(0)
PON VRH3 VRH2 VRH1 VRH0
(0)
(0)
(0)
(0)
(0)
VCM4 VCM3 VCM2 VCM1 VCM0
(0)
(0)
(0)
(0)
(0)
0
WM5 WM4 WM3 WM2 WM1 WM0
(0)
(0)
(0)
(0)
(0)
(0)
WM17 WM16 WM15 WM14 WM13 WM12
(0)
(0)
(0)
(0)
(0)
(0)
T.B.D.
0
Control (1)
45h
0
0
AD11
(0)
WM11 WM10
(0)
(0)
γ
44h
0
VDV3
(0)
WD17-0 /RAM
30h
Setting Disabled
Setting Disabled
Setting Disabled
Setting Disabled
Setting Disabled
Setting Disabled
789
0
0
0
0
0
0
0
0
0
0
0
22h
3Ah
3Bh
3Ch
3Dh
3Eh
3Fh
0
Note
0
13h
43h
5*
6*
7*
IB13
*
L6
*
0
VSPL
(0)
02h
0Ch
2*
IB14
*
L7
*
0
03h
00h
0Bh
Power Control
IB15
Index
Status Read
Oscillation Start
Device Code Read
*
L1
*
1
GS
(0)
B/C
(0)
HWM
(0)
CP7
(0)
01h
1*
Lower Code
Upper Code
Command
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VL7
(0)
SS17
(0)
SS27
(0)
HSA7
(0)
VSA7
(0)
VL6
(0)
SS16
(0)
SS26
(0)
HSA6
(0)
VSA6
(0)
VL5
(0)
SS15
(0)
SS25
(0)
HSA5
(0)
VSA5
(0)
SCN4
(0)
VL4
(0)
SS14
(0)
SS24
(0)
HSA4
(0)
VSA4
(0)
PKP02
(0)
PKP22
(0)
PKP42
0
(0)
PRP02
0
(0)
PKN02
0
(0)
PKN22
0
(0)
PKN42
0
(0)
PRN02
0
(0)
VRP03 VRP02
(0)
(0)
VRN03 VRN02
(0)
(0)
PKP01
(0)
PKP21
(0)
PKP41
(0)
PRP01
(0)
PKN01
(0)
PKN21
(0)
PKN41
(0)
PRN01
(0)
VRP01
(0)
VRN01
(0)
PKP00
(0)
PKP20
(0)
PKP40
(0)
PRP00
(0)
PKN00
(0)
PKN20
(0)
PKN40
(0)
PRN00
(0)
VRP00
(0)
VRN00
(0)
SCN3
(0)
VL3
(0)
SS13
(0)
SS23
(0)
HSA3
(0)
VSA3
(0)
SCN1
(0)
VL1
(0)
SS11
(0)
SS21
(0)
HSA1
(0)
VSA1
(0)
SCN0
(0)
VL0
(0)
SS10
(0)
SS20
(0)
HSA0
(0)
VSA0
(0)
0
0
SCN2
(0)
VL2
(0)
SS12
(0)
SS22
(0)
HSA2
(0)
VSA2
(0)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Note 1) The numerals in parenthesis in the bit cells are initialized value.
Note 2) Do not access to the"Setting Disabled" indexes.
Rev.0.12, May 09 2003, page 68 of 156
HD66789
Preliminary
Reset Function
The HD66789 makes internal initialization with RESET input. During RESET, the HD66789 is in a busy
state, and no instruction from the MPU and access to GRAM are accepted. The time required for the
RESET input is at least 1ms. In case of power-on reset, wait at least 10ms after the power is turned on until
the R-C oscillation frequency becomes stabilized. While waiting, do not make an initial setting for the
instruction set or an access to GRAM.
Initial State of Instructions
a.
b.
c.
d.
e.
f.
g.
h.
i.
j.
k.
l.
m.
n.
o.
p.
q.
r.
s.
t.
u.
v.
w.
Start oscillation
Driver output control (NL4–0 = “11101”, SS = “0”, SM = “0”, EPL = “0”, DPL = “0”, HSPL = “0”,
VSPL = “0”, GS = “0”, SM = “0”)
Liquid crystal AC drive control (FLD1-0 = “01”, B/C = “0”, EOR = “0”, NW5–0 = “00000”)
Entry mode set (HWM = “0”, I/D1-0 = “11”: Increment by 1, AM = “0” : Horizontal direction,
LG2–0 = “000” : Replace mode, BGR = “0”, TRI = “0”, DFM1-0 = “00”)
Compare register (CP17–0 : “00 0000 0000 0000 0000”)
Display control 1 (PT1-0 = “00”, VLE2-1 = “00” : No vertical scroll, SPT = “0”, FRCP = “0”,
DTE = “0”, CL = “0” : 65,536-color mode, REV = “0”, D1-0 = “00” : Display OFF, GON = 0)
Display control 2 (BP3-0 = “1000”, FP3-0 = “1000”)
Display control 3 (PTG1-0 = “00”, ISC3-0 = “0000”
Frame cycle control (NO1-0 = “00”, SDT1-0 = “00”, EQ1-0 = “00” : No equalization,
DIV1-0 = “00”: clock/1, RTN3-0 = “0000” : 16 clocks in 1H period)
External display interface (RIM1-0 = “00” : 18-bit RGB interface,
DM1-0 = “00” : internal clock operation, RM = “0” : System interface)
Power control 1 (SAP2-0 = “000”, BT2-0 = “000”, AP2–0 = “000”: liquid crystal power supply off,
DK = “1” : DCDC1 off, SLP = “0”, STB = “0” : Standby mode off)
Power control 2 (DC12-0 = “000”, DC02-00 = “000”, VC2-0 = “000”)
Power control 3 (PON = “0”, VRH3-0 = “00000”)
Power control 4 (VCOMG = “0”, VDV4-0 = “00000”, VCM4-0 = “00000”)
RAM address set (AD15–0 = “0000”H)
RAM write data mask (WM17–0 = “18’h00000”: No mask)
γ control
(PKP02-00 = “000”, PKP12-10 = “000”, PKP22-20 = “000”, PKP32-30 = “000”,
PKP42-40 = “000”, PKP52-50 = “000”, PRP02-00 = “000”, PRP12-10 = “000”)
(PKN02-00 = “000”, PKN12-10 = “000”, PKN22-20 = “000”, PKN32-30 = “000”,
PKN42-40 = “000”, PKN52-50 = “000”, PRN02-00 = “000”, PRN12-10 = “000”)
(VRP14-10 = “00000”, VRP03-00 = “0000”, VRN14-10 = “00000”, VRN12-10 = “000”)
Gate scan starting position (SCN4-0 = “00000”)
Vertical scroll (VL7–0 = “00000000”)
1st split-screen (SE17-10 = “11111111”, SS17-10 = “00000000”)
2nd split-screen (SE27-20 = “11111111”, SS27-20 = “00000000”)
Horizontal RAM address position (HEA7-0 = “10000011”, HSA7-0 = “00000000”)
Vertical RAM address position (VEA7-0 = “10101111”, VSA7-0 = “00000000”)
Rev.0.12, May 09 2003, page 69 of 156
HD66789
Preliminary
GRAM Data Initialization
The data in GRAM are not initialized by the RESET input. Initialize through software during the display
OFF (D1–0 = “00”).
Initial state of Output Pins
a.
b.
Liquid crystal driver output pins (source outputs): Output GND level
Oscillator output pin (OSC2): Outputs oscillation signal
Rev.0.12, May 09 2003, page 70 of 156
HD66789
Preliminary
Interface Specifications
The HD66789 incorporates a system interface to make settings for instructions, and an external display
interface to display moving pictures. By selecting an optimum interface for display (moving or still picture,
or both), data are transmitted efficiently.
The external display interfaces are RGB-I/F and VSYNC-I/F. Through these interfaces, the data can be
updated without flickering the moving picture on the display.
In the RGB-I/F mode, the display operation is performed in synchronization with the signals (VSYNC,
HSYNC, and DOTCLK). The display data are written according to the values of the data enable signal
(ENABLE), data valid signal (VLD) and PD17-0 bits in synchronization with VSYNC, HSYNC, and
DOTCLK signals. The display data are written to GRAM to reduce the data transmission to minimum, i.e.
only when the displays are being updated. With the window address function, only the RAM area used for
moving picture display is overwritten, and therefore the simultaneous display of moving picture area, which
is overwritten, and the RAM data in the area other than the moving picture area, which is not overwritten, is
possible. In the RGB and VSYNC interface modes, write data to GRAM in the high speed write mode
(HWM = 1) while displaying moving pictures to make an access to GRAM in high speed with low power
consumption.
In the VSYNC interface mode, internal display operations are synchronized with the frame-synchronizing
signal (VSYNC). By writing data in synchronization with the falling edge of VSYNC at a fixed speed to
GRAM through a system interface, it enables moving pictures display with a system interface. In this case,
there are some constraints in the RAM writing speed and method.
The HD66789 handles the following 4 operational modes for the type of display. The setting can be made
through an external display interface. A transition between the modes must follow the transition flow.
Rev.0.12, May 09 2003, page 71 of 156
HD66789
Preliminary
Operation modes and interfaces
Operation Mode
RAM Access Setting
(RM)
Display Operation Mode
(DM1-0)
Internal operating clock only
(Displaying still pictures)
System interface
(RM = 0)
Internal operating clock
(DM1-0 = 00)
RGB interface (1)
(Displaying moving pictures)
RGB interface
(RM = 1)
RGB interface
(DM1-0 = 01)
RGB interface (2)
(Rewriting still pictures while
displaying moving pictures)
System interface
(RM = 0)
RGB interface
(DM1-0 = 01)
VSYNC interface
(Displaying moving pictures)
System interface
(RM = 0)
VSYNC interface
(DM1-0 = 10)
Note 1) the instruction register setting can be made only through a system interface.
Note 2) The RGB-I/F and VSYNC-I/F are not compatible with each other.
Note 3) Do not change the setting for RGB-I/F mode (RIM-0) while RGB I/F is in operation.
Note 4) See the “External Display Interface” section for the transition flow of each operation mode.
Note 5) In the RGB-I/F and VSYNC-I/F modes, write data in the high speed write mode (HWM = 1).
CSn*
RS
WR*
(RD*)
System interface
DB17-0
18/16/9/8
System
VLD
ENABLE
VSYNC
HSYNC
RGB interface
DOTCLK
PD17-0
18/16/6
Interfaces and HD66789
Rev.0.12, May 09 2003, page 72 of 156
HD66789
HD66789
Preliminary
System Interface
The following shows the kinds of system interfaces and the IM pins setting for selecting an interface. The
instruction setting and RAM access are made through a system interface.
IM bits setting and the type of system interface
IM3
IM2
IM1
IM0
MPU-Interface Mode
0
0
0
0
Setting disabled
0
0
0
1
Setting disabled
DB Pin
0
0
1
0
80-system 16-bit interface
DB17 to 10 and 8-to-1
0
0
1
1
80-system 8-bit interface
DB17 to 10
0
1
0
*
Serial peripheral interface (SPI)
SDI, SDO
0
1
1
*
Setting disabled
1
0
0
0
Setting disabled
1
0
0
1
Setting disabled
1
0
1
0
80-system 18-bit interface
DB17 to 0
1
0
1
1
80-system 9-bit interface
DB17 to 9
1
1
*
*
Setting disabled
Rev.0.12, May 09 2003, page 73 of 156
HD66789
Preliminary
80-system 18-bit interface
80-system 18-bit parallel data transmission becomes operable by setting IM3/2/1/0 pins to
IOVcc/GND/IOVcc/GND levels respectively.
CSn*
A1
HWR*
(RD*)
MPU
CS*
RS
WR*
HD66789
(RD*)
DB17-0
D31-0
18
18-bit microcomputer and HD66789
Instruction
Input
Instruction
DB DB DB
17 16 15
DB DB
14 13
DB
12
DB DB
11 10
IB
15
IB
12
IB
10
IB
9
IB
14
IB
13
IB
11
DB
9
IB
8
DB
8
IB
7
DB DB
7
6
IB
6
DB
5
DB
4
DB
3
IB
4
IB
3
IB
2
IB
1
IB
0
IB
5
DB DB
2
1
DB
0
Instruction code
RAM data write
Input
Write data to
GRAM
DB
17
DB
16
DB
15
DB
14
DB
13
DB
12
DB DB DB
12 10
9
DB
8
DB
7
DB DB
6
5
DB
4
DB
3
DB
2
DB
1
DB
0
R5
R4
R3 R2
R1
R0
G5
G2
G1
G0
B4
B3
B2
B1
B0
G4
G3
B5
One pixel
262,144 colors are available in 18-bit system interface
Data format for 18-bit interface
Rev.0.12, May 09 2003, page 74 of 156
HD66789
Preliminary
80-system 16-bit interface
The 80-system 16-bit parallel data transmission becomes operable by setting IM3/2/1/0 pins to
GND/GND/IOVcc/GND levels respectively.
CSn*
A1
H8/2245 HWR*
(RD*)
CS*
RS
WR*
(RD*)
HD66789
DB17-10, 8-1
D15-0
16
16-bit microcomputer and HD66789
Input
Instruction
DB
17
DB
16
DB
15
DB
14
DB
13
DB
12
DB
11
DB
10
DB
8
DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
IB
15
IB
14
IB
13
IB
12
IB
11
IB
10
IB
9
IB
8
IB
7
IB
6
IB
5
IB
4
IB
3
IB
2
IB
1
IB
0
Instruction code
Input
DB
17
DB
16
DB
15
DB
14
DB
13
DB
12
DB
11
DB
10
GRAM R5
write data
R4
R3 R2
R1
R0
G5
G4
G3
DB
8
DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
G2
G1
G0
B5
B4
B3
B2
B1
One pixel
66,536 colors are available in 16-bit system interface.
Data format for 16-bit interface
Rev.0.12, May 09 2003, page 75 of 156
B0
HD66789
Preliminary
80-system 9-bit interface
The 80-system 9-bit parallel data transmission becomes operable by setting IM3/2/1/0 pins to
IOVcc/GND/IOVcc/IOVcc levels respectively. When transmitting a 16-bit instruction, it is divided into
upper and lower 8 bits (the LSB is not used) and the upper 8 bits are transmitted first. The RAM data is
also divided into the upper and lower 9 bits, and the upper bits are transmitted first. The unused pins
DB8-0 must be fixed to either IOVcc or GND level. When writing into the index register, the upper byte (8
bits) must be written.
CSn*
A1
HWR*
(RD*)
H8/2254
CS*
RS
WR*
HD66789
(RD*)
DB17-9
D15-0
9
DB8-0
9
GND
9-bit microcomputer and HD66789
Instructions
1st Transfer (Upper)
Input
Instruction
2nd Transfer (Lower)
DB DB
17 16
DB
15
DB
14
DB
13
DB DB
12 11
DB
10
IB
15
IB
13
IB
12
IB
11
IB
10
IB
8
IB
14
IB
9
DB
9
DB
17
DB DB
16 15
DB
14
DB
13
DB
12
DB DB
11 10
IB
7
IB
6
IB
4
IB
3
IB
2
IB
1
IB
5
DB
9
IB
0
Instruction code
RAM data write
1st Transmission (Upper)
Input
Write data to
GRAM
2nd Transmission (Lower)
DB DB
17 16
DB
15
DB
14
DB
13
DB DB
12 11
DB
10
DB
9
DB
17
DB DB
16 15
DB
14
DB
13
DB
12
DB DB
11 10
DB
9
R5
R3 R2
R1
R0
G4
G3
G2
G1
B5
B4
B3
B2
B0
R4
G5
G0
B1
One pixel
262,144 colors are available in the 9 - bit system interface.
Data format for 9-bit interface
Rev.0.12, May 09 2003, page 76 of 156
HD66789
Preliminary
Data transmission synchronizing in 9-bit bus interface mode
The HD66789 supports a data transmission synchronizing function, which resets the upper/lower counter
that counts the number of transmission of upper/lower 9-bit data in the 9-bit bus interface mode. When a
discrepancy occurs in the upper/lower 9-bit data transmission due to effects from noise and so on, the “00”
H instruction is written 4 times consecutively to forcibly reset the upper/lower counter so that data
transmission restarts with an upper 9-bit data transmission. The excursion can be recovered by executing
the synchronizing function periodically.
RS
RD
WR
DB17-9
Upper
Lower
00H
00H
00H
00H
(1)
(2)
(3)
(4)
Upper
Lower
(9-bit transmission synchronization)
9-bit data transmission synchronization
Rev.0.12, May 09 2003, page 77 of 156
HD66789
Preliminary
80-system 8-bit interface
The 80-system 8-bit parallel data transmission becomes operable by setting IM3/2/1/0 pins to
GND/GND/IOVcc/IOVcc levels respectively. When transmitting a 16-bit instruction, it is divided into
upper and lower 8 bits and the upper 8 bits are transmitted first. The RAM data is also divided into the
upper and lower 8 bits, and the upper bits are transmitted first. The data to write to RAM are expanded into
18 bits internally. The unused pins DB9-0 must be fixed to either IOVcc or GND level. When writing into
the index register, the upper byte (8 bits) must be written.
H8/2245
CS *
RS
WR*
(RD*)
CSn*
A1
HWR*
(RD*)
D15-0
HD6
66789
DB17-10
8
DB9-0
10
GND
8-bit microcomputer and HD66789
Rev.0.12, May 09 2003, page 78 of 156
HD66789
Preliminary
Instruction
1st Transfer (Upper)
Input
Instruction
2nd Transfer (Lower)
DB DB
17 16
DB DB DB
15 14 13
DB DB
12 11
DB
10
DB
17
IB
15
IB
13
IB
10
IB
8
IB
7
IB
14
IB
12
IB
11
IB
9
DB DB
16 15
IB
6
DB DB DB
14 13 12
IB
5
IB
4
IB
3
DB DB
11 10
IB
2
IB
1
IB
0
Instruction code
RAM data write
1st Transfer (Upper)
Input
Write data to
GRAM
DB DB
17 16
DB
15
R5
R3 R2
R4
DB
14
2nd Transfer (Lower)
DB DB
13 12
DB
11
DB
10
R1
G5
G4
R0
G3
DB DB DB
17 16 15
DB DB
14 13
DB
12
DB DB
11 10
G2
B5
B3
B2
One pixel
G1
G0
B4
B1
B0
65,536 colors are available in 8 - bit system interface.
RAM data write : TRI =1, DFM1-0 = 10
1st Transmission
INPUT
RGB
Assignment
2nd Transmission
3rd Transmission
DB DB DB DB DB DB DB
17 16 15 14 13
12 17
DB
16
DB DB
15 14
DB DB
13 12
DB DB DB
17 16 15
DB DB
14 13
DB
12
R5
G4
G3
G1
B5
B2
B0
R4
R3 R2
R1
R0
G5
G2
One pixel
G0
B4
B3
B1
262,144 colors are available in 8 - bit system interface.
RAM data write : TRI =1, DFM1-0 = 11
1st Transmission
INPUT
RGB
Assignment
2nd Transmission
3rd Transmission
DB DB DB DB DB DB DB
17 16 15 14 13
12 17
DB
16
DB DB
15 14
DB DB
13 12
DB DB DB
17 16 15
DB DB
14 13
DB
12
R5
G4
G3
G1
B5
B2
B0
R4
R3 R2
R1
R0
G5
G2
One pixel
G0
B3
B1
65,636 colors are available in 8 - bit system interface.
Data format for 8-bit interface
Rev.0.12, May 09 2003, page 79 of 156
B4
HD66789
Preliminary
Data transmission synchronizing in 8-bit bus interface mode
The HD66789 supports a data transmission synchronizing function, which resets the upper/lower counter
that counts the number of transmission of upper/lower 8-bit data in the 8-bit bus interface mode. When a
discrepancy occurs in the transmission of upper/lower 8-bit data due to effects from noise and so on, the
“00” H instruction is written 4 times consecutively to forcibly reset the upper/lower counter so that data
transmission restarts with the upper 8-bit transmission. The excursion can be recovered by executing the
synchronizing function periodically.
RS
RD
WR
DB17-10
Upper/
Lower
00H
00H
00H
00H
(1)
(2)
(3)
(4)
Upper
(8-bit transfer synchronization)
8-bit data transmission synchronization
Rev.0.12, May 09 2003, page 80 of 156
Lower
HD66789
Preliminary
Serial Peripheral interface (SPI)
The Serial Peripheral Interface (SPI) becomes operable by setting IM3/2/1 pins to GND/IOVcc/GND levels
respectively. The SPI is available through the chip select line (CS*), serial transfer clock line (SCL), serial
data input (SDI), and serial data output (SDO). In the SPI mode, the IM0/ID pin functions as ID pin. In the
SPI mode, the unused DB15-2 pins must be fixed at either IOVcc or GND level.
The HD66789 recognizes the start of data transfer at the falling edge of CS* input to initiate the transfer of
start byte. It recognizes the end of data transfer at the rising edge of CS* input. The HD66789 is selected
when the 6-bit chip address in the start byte transferred from the transmission device and the 6-bit device
identification code assigned to the HD66789 are compared and both 6-bit data correspond. When selected,
the HD66789 starts taking in the subsequent data string. The setting for the least significant bit of the
identification code is made with the ID pin. The five upper bits of the identification code must be 01110.
Two different chip addresses must be assigned to the HD66789 because the seventh bit of the start byte is
assigned to a register select bit (RS). When RS = 0, index register write or status read is executed. When
RS = 1, instruction write or RAM read/write is executed. The eighth bit of the start byte is to specify read
or write (R/W bit). The data are received when the R/W bit is 0, and are transmitted when the R/W bit is 1.
In the SPI mode, the data are written to GRAM after two-byte data transmission. The data are expanded
into 18 bits by adding one bit (the same data as the MSB of RB) next to the LSB of RB data.
After receiving the start byte, the HD66789 starts to transmit or receive data by byte. The data transmission
adopts a format by which the MSB is first transmitted. All HD66789 instructions consist of 16 bits and
they are executed internally after two bytes are transmitted with the MSB first (DB15 to 0). The data to
write to RAM are expanded into 18-bit data. After the start byte is received, the first byte is always fetched
as the upper eight bits of the instruction and the second byte is fetched as the lower eight bits of the
instruction. The 4-byte data that are read from RAM right after the start byte are made invalid. The
HD66789 reads as valid data from the 5th-byte data.
Start Byte Format
Transmitted bits
S
1
Start byte format
Transmission
start
Device ID code
0
Note 1) ID bit is selected with the IM0/ID pin.
RS and R/W Bit Function
RS
R/W
Function
0
0
Set index register
0
1
Read status
1
0
Write instruction or RAM data
1
1
Read instruction or RAM data
Rev.0.12, May 09 2003, page 81 of 156
2
1
3
1
4
1
5
0
6
ID
7
8
RS
R/W
HD66789
Preliminary
1st Transmission (Upper)
Input
Instruction
2nd Transmission (Lower)
D15 D14 D13 D12 D11 D10 D9
IB
15
IB
14
IB
13
IB
12
IB
11
IB
10
IB
9
D8
D7
D6
D5
D4
D3
D2
D1
D0
IB
8
IB
7
IB
6
IB
5
IB
4
IB
3
IB
2
IB
1
IB
0
Instruction code
1st Transmission (Upper)
Input
Write data to
GRAM
2nd Transmission (Lower)
D15 D14 D13 D12 D11 D10 D9
D8
R5
G4
R4
R3 R2
R1
R0
G5
G3
D7
D6
D5
D4
D3
D2
D1
D0
G2
G1
G0
B5
B4
B3
B2
B1
One pixel
Data format for SPI
Rev.0.12, May 09 2003, page 82 of 156
66,536 colors are available in serial interface.
B0
HD66789
Preliminary
A)Basic data transmission through SPI
Data transmission start
Data transmission end
CS*
(Input)
1
SCL
(Input)
SDI
(Input)
2
3
4
5
6
7
8
9 10
11 12
13 14 15 16
17 18 19 20 21 22 23
MSB
“0” “1” “1” “1” “0”
ID
Device ID code
RS
RW
RS
RW
LSB
D15 D14 D13 D12 D11 D10
Start byte
24
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D3
D2
D1
D0
Index register setting, instruction, RAM data write
SDO
(Output)
D15 D14 D13 D12 D11 D10
D9
D8
D7
D6
D5
D4
Status read, instruction read, RAM data read
B)Consecutive data transmission through SPI
CS*
(Input)
1
2 3 4
5
6 7
8
9 10 1112 13 14 15 16
17 18 19 20 21 22 23 24
25 26 27 28 29 30 31 32
SCL
(Input)
Start byte
SDI
(Input)
Instruction1:
upper eight bits
Instruction1:
lower eight bits
Instruction2:
upper eight bits
Instruction1:
execution time
Start
End
Note: The first byte after the start byte is always the upper eight bits.
C) RAM data read transmission
CS*
(Input)
SCL
(Input)
Start byte
RS = 1,
R/W = 1
SDI
(Input)
SDO
(Output)
Dummy
Read 1
Dummy
Read 2
Dummy
Read 3
Dummy
Read 4
Dummy
Read 5
RAM read
Upper 8
bits
RAM read
Lower 8
bits
Start
End
Note: Five bytes of invalid dummy data are read after the start byte.
The valid data are read from the 6th byte.
D) Status read / instruction read
CS*
(Input)
SCL
(Input)
Start byte
RS = 1,
R/W = 1
SDI
(Input)
SDO
(Output)
Dummy read 1
Status read:
upper eight bits
Start
Status read:
lower eight bits
End
Note: One byte of invalid dummy data are read after the start byte.
The valid data are read from the second byte.
Data transmission through Clock-Synchronized Serial Bus Interface
Rev.0.12, May 09 2003, page 83 of 156
HD66789
Preliminary
VSYNC Interface
The HD66789 incorporates a VSYNC-I/F, which enables moving picture display with only a system
interface and the frame-synchronizing signal (VSYNC). This interface enables moving picture display with
minimum modification to a conventional system.
VSYNC
HD66789
LCDC/
MPU
CS*
RS
WR*
16
DB17-10, 8-1
VYSNC interface
The VSYNC-I/F becomes operable by setting DM1-0 = 10 and RM = 0. In the VSYNC I/F mode, the
internal display operations are synchronized with VSYNC. By writing data to RAM through a system
interface in a speed that is higher for more than a fixed speed than the internal display operation speed, it
enables moving picture display through a system interface, while preventing flickers while the screens are
being updated.
Display operations are executed by the internal clock generated by the internal oscillator and VSYNC input.
All display data are stored in RAM. This enables moving picture display only by transmitting data that are
written over, thereby minimizing the number of data transmission while displaying moving picture. The
high-speed write mode (HWM = 1) enables RAM access in high speed with low power consumption.
VSYNC
RAM write via
system interface
Updating screen
Updating screen
Display operation in
synchronization with
the internal clock
Note: Data must be written in the high-speed write mode (HWM = 1) in VSYNC-I/F mode.
Moving picture data transmission through VSYNC interface
Rev.0.12, May 09 2003, page 84 of 156
HD66789
Preliminary
The VSYNC-I/F has limits on the minimum speed for RAM write through a system interface and the
frequency of the internal clock. It requires RAM write speed more than the result that is calculated from
the following formula.
•
Internal clock frequency (fosc) [Hz] = Frame frequency × (Display line (NL) + Front porch (FP) + Back
porch (BP)) × 16 clocks × Fluctuation
•
Minimum speed for RAM write (min.)[Hz] > 176 × Display line (NL) / {((Back porch (BP) +
Display raster-row (NL) - Margin) × 16 clocks) / fosc}
Note 1) When RAM write does not start right after the falling edge of VSYNC, the time between the falling
edge of VSYNC and the start of RAM write must also be taken into account.
An example of the RAM write speed and the frequency of the internal clock in the VSYNC interface mode
is as follows.
[Example]
Display size
Display line
Back/front porch
Frame frequency
176 RGB × 240 lines
240 lines (NL = 11110)
14/2 lines (BP = 1110/FP = 0010)
60 Hz
Internal clock frequency (fosc) [Hz] = 60 Hz × (240 + 2 + 14) × 16 Clock × 1.1 / 0.9 = 300 kHz
When calculating the internal clock frequency, possible causes of fluctuations must also be taken into
consideration. The allowance for this fluctuation is ± 10 % from the center value, and the range of the
frequency must be within VSYNC period.
As the causes of fluctuations, the above example takes the variation in the LSI fabrication and the room
temperature into account. Other possible causes of fluctuations, such as variation in the external resistors
or the voltage change are not considered in the above example. It is necessary to make a setting with
enough margins to include the allowances for these factors.
Minimum speed for RAM writing [Hz]
> 176 × 240 / {((14 + 240 - 2) raster-rows × 16 clock) / 300 kHz} = 3.14 MHz
In this case, RAM write is performed in synchronization with the falling edge of VSYNC.
When the data for one frame are written to RAM completely, there must be more than 2 raster-rows of
margin before the raster-rows driven for the display.
By writing data to RAM on the falling edge of VSYNC at the speed of 3.14 MHz or more, the data for the
whole screen on RAM are overwritten before the display operation starts. Accordingly, the flicker due to
updating moving picture data can be avoided while displaying a moving picture.
Rev.0.12, May 09 2003, page 85 of 156
HD66789
Preliminary
VSYNC
Display
(240 raster-rows)
Display operation
The number of driven raster-rows
Back porch
(14 raster-rows)
Display
operation
Front porch
(2 raster-rows)
R-C oscillation
10%
RAM write at 10MHz
44240 times
Raster-row
240
RAM write
RAM write
at 3.15 MHz
Display
operation
[ms]
0
4.22
13.41
16.74
13.55
Blanking period
60Hz
Back-porch 14H
VSYNC
Operation through VSYNC interface
Notes to the VSYNC interface
1.
The aforementioned example of calculation is just a result of calculation. In the actual settings, causes
for the fluctuations of internal clocks and so on should be taken into consideration. It is necessary to
make a setting for the RAM write speed with enough margins.
2.
The aforementioned example of calculation is the value in case of writing over the entire screen.
Limiting the area for the moving picture display will create more margins for the RAM write speed.
R-C oscillation
10%
Raster-row
240
220
VSYNC
The number of driven raster-rows
Back porch
(14 raster-rows)
(20 raster-rows)
Moving picture area
(200 raster-rows)
Display operation
RAM write
at 3.15 MHz
Display
operation
20
0
(20 raster-rows)
Front porch
(2 raster-rows)
4.22
[ms]
11.17
13.52 16.74
13.55
Back-porch 14H
60Hz
VSYNC
Limiting moving picture display area
3.
A front porch period continues after the completion of 1 frame display and until the next input of
VSYNC.
4.
The transition between the internal clock operation mode (DM1-0 = 00) and the VSYNC interface
mode becomes effective after displaying one frame made during instruction setting.
5.
In the VSYNC interface mode, the partial display, vertical scroll, and interlaced drive functions are not
available.
6.
In the VSYNC interface mode, set AM to 0 to transmit display data in the aforementioned method.
7.
In the VSYNC interface mode, write display data to RAM in the high speed write mode (HWM = 1)
Rev.0.12, May 09 2003, page 86 of 156
HD66789
Preliminary
Internal Clock Operation to VSYNC Interface
VSYNC interface operation
Internal clock operation
HWM = 1, AM = 0
Address Setting
VSYNC interface mode
setting (DM1-0 = 0, RM = 0)
VSYNC Interface to Internal Clock Operation
Display operation
in synchronization with
the internal clock
The values set in DM1-0 and RM
become valid after completion of
1-frame display.
Internal clock mode setting
(DM1-0 = 0, RM = 0)
Display operation
in synchronization with
VSYNC
The values set in DM1-0 and RM
become valid after completion of
1-frame display.
Wait more than 1 frame
Internal clock operation
Display operation
in synchronization with
the internal clock
Index register set (R22h)
Note: When switching into the internal clock mode,the VSYNC signal
must be kept continuously supplied for more than 1 frame
after it is switched into the internal clock mode.
Wait more than 1 frame
VSYNC interface
Write data to RAM
VSYNC interface
operation
Displa y operation
in synchronization with
VSYNC
Internal clock mode setting
(DM1-0 =00, RM = 0)
Wait more than 1 frame
Internal clock operation
Note: When t he interface mode is switched, VSYNC should be
input before setting of DM1-0 and RM.
Transition flow between VSYNC and internal clock operation modes
Rev.0.12, May 09 2003, page 87 of 156
HD66789
Preliminary
External Display Interface
The following interfaces are available as the external display interface (RGB interface). The interface is
selected by setting RIM1-0 bits. RAM is accessible through the RGB interface.
RIM bits setting and RGB interface
RIM1
RIM0
RGB Interface
PD Pin
0
0
18-bit RGB interface
PD17-0
0
1
16-bit RGB interface
PD17-13, 11-1
1
0
6-bit RGB interface
PD17-12
1
1
Setting disabled
Note 1) The use of multiple interfaces simultaneously is not possible.
RGB interface
Through the RGB-I/F, the display operation is performed in synchronization with VSYNC, HSYNC, and
DOTCLK. The RGB interface enables data transmission with low power consumption by overwriting the
area that needs update in high-speed write mode in combination with the window address function. The
front and back porches must be set before and after the display period.
VSYNC
Back porch period (BP3-0)
Display area for RAM data
Display area
for moving pictures
Display period (NL4-0)
Front porch period (FP3-0)
HSYNC
Note 1) The front porch period continues until the next input
of VSYNC signal.
DOTCLK
Note 2) The DOTCLK signal must be supplied consecutively.
ENABLE
VLD
PD17-0
VSYNC: Frame synchronization signal
HSYNC: Raster-row synchronization signal
DOTCLK: Dot clock
ENABLE: Data enable signal
VLD: Data valid signal
PD17-0: Display data for RGB (6:6:6)
Back porch period (BPP):14H>=BP3-0>=2H
Front porch period (FPP):14H>=FP3-0>=2H
FPP + BPP =<16H
Display operation period: NL4-0 =< 240H
The number of raster-rows of 1 frame: FPP + DP + BPP
Note 3) In RGB interface mode, VSYNC, HSYNC, and DOTCLK more than to achieve the LCD resolution must be supplied.
RGB interface
Rev.0.12, May 09 2003, page 88 of 156
HD66789
Preliminary
VLD and ENABLE signals
The relationship with the VLD and ENABLE signals is as follows. With the ENABLE signal, the
addresses are not updated during data write, while with the VLD signal, the addresses are updated during
data write when the ENABLE is “Low”. The polarity of the ENABLE signal is inverted by the setting of
EPL bit.
EPL
ENABLE
VLD
RAM Write
RAM Address
0
0
0
Valid
Updated
0
0
1
Invalid
Updated
0
1
*
Invalid
Unchanged
1
0
*
Invalid
Unchanged
1
1
0
Valid
Updated
1
1
1
Invalid
Updated
RGB interface timing
The timing chart of 16/18-bit RGB interfaces is as follows.
1 frame
Back porch period
Front porch period
VSYNC
HSYNC
DOTCLK
C
ENABLE
VLD
PD17-0
>=1H
VSYNC
1H
HLW >= 1CLK
HSYNC
1 clock
DOTCLK
DTST >=HLW
ENABLE
VL
D
PD17-0
Valid data
VLW: the period in which VSYNC is low level
HLW: the period in which HSYNC is low level
DTST: the set up time for data transmission
Note: Data to be displayed must be written in the high-speed write mode (HWM = 1) in
RGB I/F mode.
16-/18-bit RGB Interface Timing
Rev.0.12, May 09 2003, page 89 of 156
HD66789
Preliminary
The timing chart of 6-bit RGB interface is as follows.
1 frame
Back porch period
Front porch period
VSYNC
HSYNC
DOTCLK
ENABLE
VLD
PD17-0
>= 1H
VSYNC
1H
HLW>=3CLK
HSYNC
1 clock
DOTCLK
DTST >= HLW
ENABLE
VLD
RGB RGB RGB
RGB RGB
PD17-0
Valid data
VLW: the period in which VSYNC is low level
HLW: the period in which HSYNC is low level
DTST: the set up time for data transmission
Note 1) In 6-bit interface.mode, one pixel, which consists of R,G, and B, must be transmitted in synchronization
with 3 DOTCLKs.
Note 2) VSYNC, HSYNC, EVABLE, DOTCLK, VLD, and PD17-2 should be all transmitted by three clocks.
Note 3) Data to be displayed must be written in the high-speed write mode (HWM =1) in RGB I/F mode.
6-bit RGB Interface Timing
Rev.0.12, May 09 2003, page 90 of 156
HD66789
Preliminary
Moving picture display
The HD66789 incorporates the RGB interface to display moving pictures and RAM to store display data,
which provides the following merits in displaying moving pictures.
•
•
•
•
•
The window address function enables the transfer of only data for the moving picture area.
The high-speed write mode enables high-speed access to RAM with low power consumption
Only transmitting data that are written over the moving picture area.
Reduced transmission contributes to the reduction of power consumption of the entire system.
In combination with a system interface, the still picture area, such as an icon, can be updated while
displaying moving pictures.
RAM access through system interface in RGB-I/F mode
RAM is accessible through a system interface in the RGB-I/F mode. In the RGB interface mode, data are
being written to RAM in synchronization with the DOTCLK input while the ENABLE is “Low”. When
writing data to RAM through the system interface, it is necessary to set ENABLE to “High” to stop data
write through the RGB-I/F. Setting RM = 0 allows RAM access through the system interface. When
reverting to the RGB interface mode, wait a write/read bus cycle. Then, set RM = 1 and the index to R22h
to start RAM access though the RGB-I/F. When the RAM writes through the RGB and system interface
conflicts, it is not guaranteed that the data are properly written to RAM.
The following is an example of moving picture display through the RGB-I/F and updating still picture area
through the system interface.
Updating screen
Updating screen
VSYNC
ENABLE
DOTCLK
PD17-0
*Note 2
Index set
System interface
Index
R22
RM=0
Updating moving
picture area
Setting
of
address
Index
R22
Updating of area
other than moving
picture area
Setting
of
address
Updating of still picture area
RM=1
Index
R22
* Note 1
Updating moving
picture area
Note 1) In the RGB interface mode, the address is set at every falling edge of VSYNC.
Note 2) Set the address and the index (R22h) before RAM access starts through the RGB interface mode.
Note 3) In the RGB interface mode write data in the high-speed write mode (HWM = 1).
2001/01/01 00:00
Still picture area
Moving picture area
Updating Still Picture Area during Displaying Moving Picture
Rev.0.12, May 09 2003, page 91 of 156
HD66789
Preliminary
6-bit RGB interface
The 6-bit RGB interface is selected by setting RIM1-0 bits to 10. The display operation is synchronized
with VSYNC, HSYNC, and DOTCLK signals. Display data are transmitted to RAM in synchronization
with the display operation through 6-bit RGB data bus (PD17-12) according to data valid signal (VLD),
and the data enable signal (ENABLE). Unused pins (PD11 to 0) must be fixed to either IOVcc or GND
level.
The instructions are set only through a system interface.
VSYNC
HSYNC
DOTCLK
LCDC
VLD
ENABLE
HD66789
PD17-12
6
PD11-0
12
GND
6-bit RGB interface
RAM data write
1st Transmission
INPUT
Write Data
to GRAM
PD
17
PD
16
PD
15
R5
R4
R3 R2
PD
14
2nd Transmission
3rd Transmission
PD
13
PD PD
12 17
PD PD
16 15
PD
14
PD
13
PD PD PD PD PD PD PD
12 17 16 15 14 13 12
R1
R0
G4
G2
G1
G0
G5
G3
One Pixel
B5
B4
B3
B2
B1
B0
262,144 colors are available in 6-bit system interface.
Data format for 6-bit interface
Data transmission synchronization in 6-bit RGB interface mode
The HD66789 incorporates a transmission counter to count the first, second, third data transmissions in the
6-bit RBG interface mode. The transmission counter is reset to the first transmission on the falling edge of
VSYNC. When a discrepancy occurs in the transmission of first, second and third data, the counter is reset
so that a first data transmission will be made at the start of each frame (on the falling edge of VSYNC) and
the data transmission restarts in the correct order from the next frame. In case of displaying moving
pictures, which requires consecutive data transfer, this function minimizes the effect from the discrepancy
in the data transmission and makes it easy to return to the normal display.
The internal display operation is executed by pixel. Note that each DOTCLK input must correspond to a
pixel. Otherwise data transmission discrepancies will occur and affect the displays of the current and
ensuing frames.
Rev.0.12, May 09 2003, page 92 of 156
HD66789
Preliminary
VSYNC
ENABLE
DOTCLK
PD17-0
2nd
Transmission
2nd
3rd
1st
2nd
3rd
1st
Trans- Trans- Trans- Trans- Trans- Transmission mission mission mission mission mission
Transfer synchronization
6-bit data transmission synchronization
16-bit RGB interface
The 16-bit RGB interface is selected by setting RIM1-0 bits to 01. The display operation is synchronized
with VSYNC, HSYNC, and DOTCLK signals. Display data are transmitted to RAM in synchronization
with the display operation through 16-bit RGB data bus (PD17-13, 11-1) according to the data valid signal
(VLD), and the data enable signal (ENABLE).
The instructions are set only through a system interface.
VSYNC
HSYNC
DOTCLK
C
LCDC
HD66789
VLD
ENABLE
PD17-13,11- 1
16
PD12,0
2
GND
16-bit RGB interface
RAM data Write
Input
Write data to
GRAM
PD PD PD PD PD
17 16 15 14 13
R5
R4
R3 R2
R1
R0
PD PD PD PD PD
11 10
9
8
7
PD PD PD PD PD PD
6
5
4
3
2
1
G5
G0
G4
G3
G2
G1
One pixel
Data format for 16-bit interface
Rev.0.12, May 09 2003, page 93 of 156
B5
B4
B3
B2
B1
B0
HD66789
Preliminary
18-bit RGB interface
The 18-bit RGB interface is selected by setting RIM1-0 bits to 00. The display operation is synchronized
with VSYNC, HSYNC, and DOTCLK signals. Display data are transmitted to RAM in synchronization
with the display operation through 18-bit RGB data bus (PD17-0) according to the data valid signal (VLD),
and the data enable signal (ENABLE).
The instructions are set only through a system interface.
VSYNC
HSYNC
DOTCLK
LCDC
HD66789
VLD
ENABLE
PD17-0
18
18-bit RGB interface
RAM data Write
Input
Write data to
GRAM
PD PD PD PD PD PD
17 16 15 14 13 12
PD PD PD PD PD
11 10
9
8
7
PD PD PD PD PD PD
6
5
4
3
2
1
PD
0
R5
G5
G0
B0
R4
R3 R2
R1
R0
G4
G3
G2
One pixel
G1
B5
B3
B2
B1
262,144 colors available in 18-bit RGB interface.
Data format for 18-bit interface
Rev.0.12, May 09 2003, page 94 of 156
B4
HD66789
Preliminary
Notes to the external display interface
1.
While an external display interface is selected, the following functions are not available.
Function
External Display Interface
Internal Display Operation
Partial display
Not available
Available
Scroll function
Not available
Available
Interlaced drive
Not available
Available
Graphics operation function
Not available
Available
2.
The VSYNC, HSYNC, and DOTCLK signals must be supplied consecutively during display
operation through the RGB-I/F.
3.
When setting NO1-0, SDT1-0, and EQ1-0 bits in the RGB-I/F mode, the reference clock is the
DOTCLK, not the internal operation clock.
4.
In the 6-bit RGB-I/F mode, RGB (pixels) data are transmitted by three clocks. The data transmission,
therefore, should be made by RGB.
5.
In the 6-bit RGB-I/F mode, the interface signals, VSYNC, HSYNC, DOTCL, ENABLE, VLD, and
PD17-0, should be set by RGB (pixels) in convenience for transmitting RGB pixels.
6.
The transitions between the internal operation mode and external display interface should be made
according to the mode switching sequence below.
7.
In the RGB-I/F mode, the front porch period continues after displaying one frame data until the next
VSYNC signal input.
8.
In the RGB-I/F mode, the data must be written in the high-speed write mode (HWM = 1).
9.
In the RGB-I/F mode, the address is set every frame on the falling edge of VSYNC.
Rev.0.12, May 09 2003, page 95 of 156
HD66789
Preliminary
Internal Clock Operation to RGB I/F (1)
RGB I/F (1) to Internal Clock Operation
RGB I/F operation
Internal clock operation
HWM = 1, AM = 0
Address Setting
RGB I/F Setting
(DM1-0=01, RM=1)
Index resister
setting (R22h)
Display operation
in synchronization with
the internal clock
The value set in DM1-0 and RM
become valid after the completion
of 1-frame display.
The value set in DM1-0 and RM bits
become valid after the completion of
1-frame display.
Wait more than 1 frame
Internal clock operation
Display operation
in synchronization with
the internal clock
Note: When switching into the internal clock mode from RGB I/F,
keep RGB I/F signals (VSYNC, HSYNC, DOTCLK, ENABLE)
input for more than 1 frame after the mode has been switched.
Wait more than 1 frame
RGB I/F
Writing RAM Data
Internal clock mode setting
(DM1-0 = 00, RM=0)
Display operation in
synchronization with the RGB
signals ( VSYNC , HSYNC,
DOTCLK)
Display operation in
synchronization
with the RGB signal
RGB interface operation
Note: When switching into the RGB interface mode, the RGB
interface signals, VSYNC, HSYNC, DOTCLK, and ENABLE,
must be input before the setting of DM1-0 and RM bits.
Transition between the Internal Clock Operation Mode and RGB Interface Mode
From RGB I/F (1) to RGB I/F (2)
From RGB I/F (2) to RGB I/F (1)
RGB I/F Operation
RGB I/F mode setting
(DM1-0=01, RM=0)
System I/F
Writing RAM Data
HWM=1/0
HWM=1, AM=0
Address Setting
Address Setting
Index resister setting (R22h)
RGB I/F mode
(DM1-0=01, RM=1)
System I/F
Writing RAM Data
Index resister setting (R22h)
RGB I/F Operation
RAM data write sequence through system interface in RGB-I/F mode
Rev.0.12, May 09 2003, page 96 of 156
HD66789
Preliminary
Timing Interfacing with Liquid Crystal Panel Signals
The relationship between RGB I/F signals and the liquid crystal panel signals in the RGB I/F mode is as
follows.
1 frame
Back porch period (BP)
Front porch period (BP)
Back porch period (BP)
>=1H
VSYNC
1H
HSYNC
DOTCLK
ENABLE
VLD
PD17-0
1 2 3 4 5
236 237 238 239 240
1
Note 1)
5DOTCLK
Note 1)
5DOTCLK
1H
FLM
CLW2-0
CL1
SHW1-0
STG2-0
SFTCLK
DISPTMG
NO1-0
G1
G2
G240
S1-528
SDT1-0
1 2 3 4 5
236 237 238 239 240
EQ1-0
EQ
M (VCOM)
Note 1) 15 clocks in case of 6-bit RGB I/F mode.
Note 2) FLM, CL1, SFTCLK, DISPTMG, EQ, M are internal signals.
Relationship between RGB I/F signal and the liquid crystal panel signal
Rev.0.12, May 09 2003, page 97 of 156
HD66789
Preliminary
The timing interfacing with the liquid crystal panel signals in the internal clock operation mode is as
follows.
1-frame
Front porch period (FP) +Back porch period(BP) =8H
1H
FLM
CLW2-0
CL1
SHW1-0
STG2-0
SFTCLK
DISPTMG
NO1-0
G1
G2
G240
S1-528
SDT1-0
1 2 3 4 5
236 237 238 239 240
1
EQ1-0
EQ
M (VCOM)
Note 1) FLM, CL1, SFTCLK, DISPTMG, EQ, and M are internal signals.
Interfacing with the liquid crystal panel signals in the internal clock operation mode
Rev.0.12, May 09 2003, page 98 of 156
HD66789
Preliminary
Scan Mode Setting
The shift direction of gate signal is changeable by the combination of SM and GS bit settings. This allows
various ways of connecting a liquid crystal panel and the HD66789.
SM
Scan direction
GS
raster-rows of
odd number
G1
G2
raster-rows of
even number
TFT panel
0
0
G239
G1
G240
G1, G2, G3, G4,….
G237, G238, G239, G240
G239 G240
G2
HD66789
raster-rows of
odd number
G1
G2
raster-rows of
even number
TFT panel
0
1
G239
G1
G240, G239, G238, G237,….
G4, G3, G2, G1
G240
G239 G240
G2
HD66789
G1
G239
TFT panel
G2
1
0
G1, G3, G5,….
G237, G239,
G2, G4, G6,….
G238, G240
G240
G1
G239
G240
G2
HD66789
G1
TFT panel
G239
1
G2
G240, G238, G236,….
G236,
G4, G2,
G2
G239, G237, G235,….
G235
G3, G1
G240
1
G1
G239 G240
HD66789
Scan mode setting
Rev.0.12, May 09 2003, page 99 of 156
G2
HD66789
Preliminary
High-Speed Burst RAM Write Function
The HD66789 incorporates high-speed burst RAM-write function, which writes data to RAM in one-fourth
the access time required for a standard RAM-write operation. This function is especially useful for
applications which require the high-speed rewrite of the display data such as display of colored moving
picture and so on.
In the high-speed RAM write mode (HWM), data to write to RAM is temporarily stored to the internal
register of HD66789. The data storage in the register is executed by word. When the data storage
operation is executed 4 times, all data stored in the register are written to RAM at once. While the data is
being written from the register to RAM, another set of data is being written to the register. This function
enables high-speed and consecutive RAM write, which are required in displaying moving pictures and so
on.
Microcomputer
18
Address
counter
(AC)
Register 1
Register 2
Register 3
Register 4
72
16
“0001H”
“0000H”
“0002H”
“0003H”
GRAM
Operational flow of High-Speed Burst RAM Write
CS*
(input)
1
2
3
4
1
2
3
4
1
2
3
4
RAM
data
2
RAM
data
3
RAM
data
4
RAM
data
5
RAM
data
6
RAM
data
7
RAM
data
8
RAM
data
9
RAM
data
10
RAM
data
11
RAM
data
12
E
(input)
DB15-0
(input/output)
RAM
Index RAM
data
data
1
(R22)
1
RAM write
execution time
RAM write data
(72 bits)
RAM address
(AC15 to 0)
RAM data 1 to 4
“0000”H
RAM write
execution time
RAM data 5 to 8
“0004”H
Index
(R22)
RAM write
execution time
RAM data 9 to 12
“0008”H
“000A”H
The lower two bits of the address must be set as follows in the high-speed write mode.
When ID0 = 0, set the lower two bits of the address to 11.
When ID1 = 1, set the lower two bits of the address to 00.
Note : When terminating the high-speed RAM write, wait for the time required for the RAM write execution
(bus cycle line (tCYC) in the normal write mode) before executing the next instruction.
High-Speed Consecutive Write to RAM
Rev.0.12, May 09 2003, page 100 of 156
HD66789
Preliminary
CS*
(input)
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
E
(input)
DB15-0
(input/output)
Index
(R22)
RAM
data
1
Upper
RAM
data
1
lower
RAM
data
2
Upper
RAM
data
2
lower
RAM
data
3
Upper
RAM
data
3
lower
RAM
data
4
Upper
RAM
data
4
lower
RAM
data
1
Upper
RAM
data
1
lower
RAM
data
2
Upper
RAM
data
2
lower
RAM
data
3
Upper
RAM address
(AC15 to 0)
RAM data 1 to 4
“0000”H
RAM
data
4
Upper
RAM
data
4
lower
RAM write
execution time *Note
RAM write
execution time
RAM write data
(64 its)
RAM
data
3
lower
RAM data 5 to 8
“0004”H
“The lower two bits of the address must be set as follows in high-speed write mode.
When ID0 = 0, set the lower two bits of the address to 11.
When ID1 = 1, set the lower two bits of the address to 00.
Note : In the high-speed mode (HWM), data are written to the RAM every 4 words. This means in the 8-bit interface mode,
data are written to the RAM for every eight write operation.
Operation of High-Speed Consecutive Writing to RAM (8-Bit Interface)
Notes to the high-speed RAM write mode
1.
The logical/compare operations are not available.
2.
The RAM write operation is executed every four words. Set the lower 2 bits of the addresses as
follows when setting the address.
*When ID0=0, the lower two bits in the address must be set to 11 before RAM write.
*When ID0=1, the lower two bits in the address must be set to 00 before RAM write.
3.
The RAM write operation is executed every four words. If the RAM write operation is terminated
before all four-word data is written to RAM, the last data will not be written to RAM.
4.
When the index register is set to R22H (RAM data write), the first RAM write operation is always
executed. In this case, the RAM data read is not operable simultaneously. During RAM read, set the
HWM to 0.
5.
The high-speed RAM write mode is not compatible with the normal RAM write mode. When the
mode must be switched to the other, make a new address set before starting RAM write.
6.
When writing data in the high speed RAM write mode within the range specified with the window
address, some window-address range may require dummy write operation. See “High-Speed RAM
Write with Window Address Function”.
Rev.0.12, May 09 2003, page 101 of 156
HD66789
Preliminary
Comparison between Normal and High-Speed RAM Write Operations
Normal RAM Write
(HWM=0)
High-Speed RAM Write (HWM=1)
Logical operation function
Available
Not available
Compare operation function
Available
Not available
BGR function
Available
Available
Write mask function
Available
Available
RAM address set
Specified by one
word
ID0 bit=0: Set the lower two bits to 11
ID0 bit=1: Set the lower two bits to 00
RAM read
Read by one word
Not available
RAM write
Write by one word
Dummy write operations may be required depending
on the specified window-address range
Window address
Set by one word
Horizontal range(HSA/HSE): more than four words
Number of horizontal writing : 4N (N>=2)
External display interface
Available
Available
AM Setting
AM = 1/0
AM = 0
Rev.0.12, May 09 2003, page 102 of 156
HD66789
Preliminary
High-Speed RAM Write with Window Address
To rewrite the data in an arbitrary rectangular area of RAM consecutively in high speed, the number of
RAM access should be made 4 multiple times. Accordingly some window-address range may require
dummy write operation to make the RAM access 4 multiple times. The number of dummy write is set
when setting the window address as follows.
The horizontal window-address range specifying bits (HSA1-0, HEA1-0) specify the number of dummy
write operations executed at the start and end of the data to write to RAM. The total RAM access must be
4 multiple times per line.
Number of Dummy Write Operations in High-Speed RAM Write (HSA Bits)
HSA1
HSA0
Number of Dummy Write Operations
inserted
0
0
0
0
1
1
1
0
2
1
1
3
Number of Dummy Write Operations in High-Speed RAM Write (HEA Bits)
HEA1
HEA0
Number of Dummy Write Operations
inserted
0
0
3
0
1
2
1
0
1
1
1
0
The number of RAM access when writing data in the horizontal direction must be made 4 × N times by
including the dummy writes.
Horizontal RAM write = start dummy write + write data + end dummy write = 4 × N (times)
An example of RAM write in high speed RAM write mode with the window address is as follows.
The RAM data in the specified window-address range is written over consecutively in high speed by
inserting two dummy writes at the start of the line and three dummy writes at the end of the line. The
number of dummy writes is specified with the window-address range specifying bits. In this case, set
HSA1-0 to 10, HEA1-0 to 00.
Rev.0.12, May 09 2003, page 103 of 156
HD66789
Preliminary
Writing data in the horizontal direction
AM = 0, ID0 = 1
h0000
GRAM address map
h0812
Window address range setting
HSA = h12, HEA = h30
VSA = h08, VEA = hA0
High-speed RAM write mode setting
HWM = 1
Specified window address
range (rewrite area)
Address set
AD = h0810 *Note
hA030
hEFAF
Dummy RAM write X 2
RAM write X 31
Window address range setting
HAS = h12, HEA = h30
VSA = h08, VEA = hA0
X 153
Dummy RAM write X 3
Note: In the high-speed RAM write mode, the address set must be either 00 or 11
in ID0 bit setting. Only the RAM address range specified by window addresses
will be overwritten.
High-Speed RAM Write with Window Address Function
Rev.0.12, May 09 2003, page 104 of 156
HD66789
Preliminary
Window Address Function
The window address function enables consecutive data write within the rectangular window-address area
on the on-chip GRAM, which is specified with horizontal address registers (start: HSA7-0, end: HEA 7-0)
and vertical address registers (start: VSA7-0, end: VEA7-0).
The address transition direction is determined with AM bits (either increment or decrement). Accordingly,
the data, including picture data, are written consecutively without taking the data wrap position into
consideration.
The window-address range must be specified within the GRAM address area. An address set must be set
within the window-address range.
[Condition on setting window-address range]
(horizontal direction)
00H ≤ HSA7-0 ≤ HSA7-0 ≤ AFH
(vertical direction)
00H ≤ VSA7-0 ≤ VEA7-0 ≤ EFH
[Condition on making an address set within the window-address range]
(RAM address)
HSA7-0 ≤ AD7 -0 ≤ HEA7-0
VSA7-0 ≤ AD15-8 ≤ VEA7-0
Note: In high-speed RAM write mode , the lower two bits of the address must be set as follows.
ID0=0: The lower two bits of the address must be set to 11.
ID0=1: The lower two bits of the address must be set to 00.
GRAM address map
“00AF”H
“0000”H
Window address area
“2010”H
“202F”H
“2110”H
“212F”H
“5F10”H
“5F2F”H
“EF00”H
“EFAF”H
Window address range specification area
HSA7-0 = “10”H, HSE7-0 = “2F”H
I/D = 1 (increment)
VSA7-0 = “20”H, VEA7-0 = “5F”H
AM = 0 (horizontal writing)
Address transition direction in specified window-address range
Rev.0.12, May 09 2003, page 105 of 156
HD66789
Preliminary
Graphics Operation Function
The HD66789 greatly reduces the load on the graphics-processing software in the microcomputer with the
18-bit bus architecture and the graphics bit operation. The graphics bit operation includes:
1. The write data mask function that selectively rewrites some of the 18-bit write data.
2. The conditional rewrite function that compares the write data and the compare bit data and writes
the data sent from the microcomputer only when the conditions are satisfied.
The graphics bit operation is controlled by setting bits in the entry mode register and RAM-write-data mask
register, and the write operation from the microcomputer.
Graphics Operation
Bit Setting
Operation Mode
I/D
AM
LG2–0
Operation and Usage
Write mode 1
0/1
0
000
Horizontal data replacement
Write mode 2
0/1
1
000
Vertical data replacement
Write mode 3
0/1
0
110 111
Conditional horizontal data replacement
Write mode 4
0/1
1
110 111
Conditional vertical data replacement
Microcomputer
18
Write data latch
18
+1/-1
+256
3
Address
counter
(AC)
Logical/Compare operation (LG2-0)
000: replacement
110: replacement with matched write
111: replacement with unmatched write
Logical operation bit
(LG2-0)
18
Compare bit (CP17-0)
18
18
Write bit mask
16
Graphics RAM (GRAM)
Graphics operation flow
Rev.0.12, May 09 2003, page 106 of 156
Write-mask register
(WM17-0)
HD66789
Preliminary
Write-data Mask Function
The HD66789 expands the 16-bit data sent from the microcomputer into the 18-bit data. In the18-bit
interface mode, data are not expanded. The write data mask function of the HD66789 controls the write
operation of the 18-bit data from the microcomputer to GRAM by bit. The write data mask function write
data in the bits whose corresponding bits in the write data mask resister (WM17–0) are assigned with “0”.
It does not write data in the bits whose corresponding bits in the write data mask register (WM17–0) are
assigned with “1”, and the corresponding data in GRAM are not overwritten but retained. This function is
useful when only one-pixel data are rewritten or a particular color in the display is selectively changed.
DB0
DB17
Data from
the microcomputer
R05 R04 R03 R02 R01 R00 G05 G04 G03 G02 G02 G01 G00 B05 B04 B03 B02 B01 B00
WM17
Write data mask
1
WM0
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
17
GRAM data
0
0
0
* * * * * *
G05 G04 G03 G02 G02 G01 G00
* * * *
B01 B00
Note : Data are expanded into 18 bits in the 8/16-bit system interface and the 16 RGB interface modes.
Write data mask function
Graphics Operation Processing
1. Write mode 1: AM = 0, LG2–0 = 000
This mode is used when data are horizontally written in high-speed mode. It is also used to initialize the
graphics RAM (GRAM) or to draw a line horizontally. The write-data mask function (WM17–0) is also
available with this mode. After writing, the address counter (AC) automatically increments by 1 (I/D = 1)
or decrements by 1 (I/D = 0), and jumps to the counter at the opposing edge of the next one-raster-row
below after when the counter reaches either left or right edge of GRAM.
Operation example
1) I/D = "1", AM = "0", LG2-0 = "000"
2) WM17-0 = "00FFF"H
3) AC = "0000"H
WM17
Write-data mask:
WM0
0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1
DB17
Write-data (1)
1 0 0 1 1 1 1 1 1 1 0 0 1 0 1 0 0 0
Write-data (2)
1 1 0 0 0 1 0 0 0 0 0 1 1 0 0 0 0 0
“0000”H
*Write-mask <G>, <B> planes.
DB0
Data are expanded into 18 bits in 8/16-bit system
interface, and 16-bit RGB interface modes.
“ 0002”H
“ 0001” H
100111 * * * * * * * * * * * * 110001 * * * * * * * * * * * *
Write data (1)
Write data (2)
GRAM
Write Mode 1
Rev.0.12, May 09 2003, page 107 of 156
Note : The bits in the GRAM with “"*"
are not overwritten.
HD66789
2.
Preliminary
Write mode 2: AM = 1, LG2–0 = 000
This mode is used when data are vertically written in high-speed mode. It is also used to initialize the
graphics RAM (GRAM), develop font patterns or draw a line vertically. The write-data mask function
(WM17–0) is also available with this mode. After writing, the address counter (AC) automatically
increments by 256, and automatically jumps to the counter either at the top of the next right row (ID = 1) or
at the top of the next left row (I/D = 0) according to the setting in the I/D bit, when the address reaches the
bottom of GRAM.
Operation example
1) I/D = "1", AM = "1", LG2-0 = "000"
2) WM17-0 = "00FFF"H
3) AC = "0000"H
WM17
Write-data mask:
WM0
000000111111111111
DB17
DB0
Write-data (1):
100111111100101000
Write-data (2):
110001000001100000
Write-data (3):
011110100010000011
Data are expanded into 18 bits in 8/16-bit system
interface, and 16-bit RGB interface modes.
“0000”H
100111 * * * * * * * * * * * *
Write-data (1)
“0001”H
110001 * * * * * * * * * * * *
Write-data (2)
“0002”H
011110 * * * * * * * * * * * *
Write-data (3)
GRAM
Note 1) The bits in the GRAM with “*”are not overwritten.
Note 2) After writing data to the address "EF00"H, the address counter jumps to
"0001"H.
Write Mode 2
Rev.0.12, May 09 2003, page 108 of 156
HD66789
Preliminary
3. Write mode 3: AM = 0, LG2–0 = 110/111
This mode is used when data are horizontally written with comparing the write data and the value set in the
compare register (CP17–0) by R, G, B pixel. When the result of the comparison satisfies a condition, the
write data sent from the microcomputer are written to GRAM. The write-data mask function (WM17–0) is
also available with this mode. After writing, the address counter (AC) automatically increments by 1 (I/D
= 1) or decrements by 1 (I/D = 0), and jumps to the counter at the opposing edge of the next one-raster-row
below after when the counter reaches either left or right edge of GRAM.
Operation example
1) I/D = "1", AM = "0", LG2-0 = "110" (matched writing)
2)CP17-0 = "050C0"H
3)WM17-0 = "00000"H
4) AC = "0000"H
WM0
WM17
Write-data mask:
000000000000000000
Compare register:
000101000011000000
CP0
CP17
DB17
Write-data (1):
(Matched)
Compare operation
DB0
Conditional replacement
000101000011000000 C
R
Write-data (2):
000000111111000000
000101000011000000
Replacement
Compare
operation
Conditional replacement
C
R
**** ******* *******
Data are expanded into 18 bits in 8/16-bit system
interface, and 16-bit RGB interface modes.
"0000"H
"0001"H
000101000011000000 * * * * * * * * * * * * * * * * * *
write data (1)
matched
replacement
GRAM
Write Mode 3
Rev.0.12, May 09 2003, page 109 of 156
HD66789
Preliminary
4. Write mode 4: AM = 1, LG2–0 = 110/111
This mode is used when data are horizontally written with comparing the write data and the value set in the
compare register (CP17–0) by R, G, B pixel. When the result of the comparison satisfies a condition, the
write data sent from the microcomputer are written to GRAM. The write-data mask function (WM17–0) is
also available with this mode. After writing, the address counter (AC) automatically increments by 256,
and automatically jumps to the counter either at the top of the next right row (ID = 1) or at the top of the
next left row (I/D = 0) according to the setting in the I/D bit, when the address reaches the bottom of
GRAM.
Operation example
1) I/D = "1", AM = "1", LG2-0 = "111" (unmatched writing)
2)CP17-0 = "0A0C0"H
3)WM17-0 = "00000"H
4) AC = "0000"H
WM0
WM17
Write-data mask:
000000000000000000
Compare register:
001010000011000000
CP0
CP17
DB17
Write-data (1):
( Unmatched)
DB0
Conditional replacement
100111001100111111 C
(Matched)
Write-data (2):
Compare operation
R
001010000011000000
100111001100111111
Replacement
Compare
operation
Conditional replacement
C
R
**** ******* *******
Data are expanded into 18 bits in 8/16-bit system
interface, and 16-bit RGB interface modes.
"0100"H
"0000"H
"0000"H 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1 Write-data (1)
"0100"H
******************
Write-data (2)
GRAM
"EF00"H
Note 1) The bits in the GRAM with “*”are not overwritten.
Note 2) After writing data to the address "EF00"H, the address counter jumps to
"0001"H.
Write Mode 4
Rev.0.12, May 09 2003, page 110 of 156
HD66789
Preliminary
γ-Correction Function
The HD66789 incorporates γ-correction function to simultaneously display 262,144 colors, by which 8level grayscale is determined by the gradient-adjustment and fine-adjustment registers. Select either
positive or negative polarity of the registers according to the characteristics of a liquid crystal panel.
Graphics RAM(GRAM)
MSB
Display
data
R5
R4
R3
R2
R1
R0
G 5 G4
G3
G2
G1
LSB
G0
B5
B4
B3
B2
B1
PKP 02 PKP 01 PKP 00
PKP 12 PKP 11 PKP 10
Positive
Polarity
Register
PKP 22 PKP 21 PKP 20
PKP 32 PKP 31 PKP 30
PKP 42 PKP 41 PKP 40
PKP 52 PKP 51 PKP 50
PRP 02 PRP 01 PRP 00
V0
VRP 03 VRP 02 VRP 01 VRP00
VRP 14 VRP 13 VRP 12 VRP 11 VRP10
PKN 02 PKN 01 PKN 00
PKN 12 PKN 11 PKN 10
Negative
Polarity
Register
8
Grayscale Amplifier
PRP 12 PRP 11 PRP 10
6
6
6
V1
32-level grayscale
control
<R>
32
32-level grayscale
control
<G>
32-level grayscale
control
<B>
FRC control
FRC control
FRC control
LCD driver
LCD driver
LCD driver
V31
PKN 22 PKN 21 PKN 20
PKN 32 PKN 31 PKN 30
PKN 42 PKN 41 PKN 40
PKN 52 PKN 51 PKN 50
PRN 02 PRN 01 PRN 00
PRN 12 PRN 11 PRN 10
VRN 03 VRN 02 VRN01 VRN00
R G B
LCD
VRN14 VRN13 VRN12 VRN11 VRN10
Grayscale control
Rev.0.12, May 09 2003, page 111 of 156
B0
HD66789
Preliminary
Configuration of Grayscale Amplifier
The eight levels (VIN0-7) of grayscale are determined by the gradient adjustment and fine adjustment
registers. The 8 levels are then divided into 32 levels (V0-31) by the ladder resistors placed between each
level.
Gradient
Adjustment
Register
PRP/N0 PRP/N1
3
3
Amplitude
Adjustment
Register
Fine Adjustment Registers (6 x 3bits)
PKP/N0
3
PKP/N1
3
PKP/N2
3
PKP/N3
3
PKP/N4 PKP/N5
3
3
VRP/N0
4
VRP/N1
5
VREG1OUT
VINP0/VINN0
V0
VINP1/VINN1
V1
8 to 1
Selector
V2
V3
VINP2/VINN2
8 to 1
Selector
VINP3/VINN3
VINP4/VINN4
8 to 1
Selector
8 to 1
Selector
Grayscale Amplifier
8 to 1
Selector
Ladder Resistors
V9
VINP5/VINN5
V16
V17
V19
V20
V24
V25
V26
VINP6/VINN6
8 to 1
Selector
VINP7/VINN7
VGS
Grayscale amplifier
Rev.0.12, May 09 2003, page 112 of 156
V8
V30
V31
HD66789
Preliminary
VDH
VRP0[3:0]
VRP0
0 ~30R
5R
KVP0
RP3
RP4
RP5
RP6
RP7
VRHP
0 ~28R
1R
5R
RP8
KVP11
KVP12
RP11
RP12
KVP13
KVP14
KVP15
KVP16
16R
1R
RP19
RP20
RP21
RP22
4R
PKP1[2:0]
VRHN
0 ~28R
VIINP 2
1R
PKP2[2:0]
KVP17
KVP18
KVP19
KVP20
KVP21
KVP22
KVP23
KVP24
5R
8 to 1
SE
LL
VIINP3
1R
PKP3[2:0]
RP24
RP25
KVP25
KVP26
KVP27
RP26
RP27
KVP28
KVP29
RP28
RP29
KVP30
KVP31
KVP32
RN0
RN1
RN2
KVN2
KVN3
RN3
RN4
RN5
RN6
RN7
KVN4 8 to 1
KVN5 SE
LL
KVN6
KVN7
16R
VIINP4
1R
KVN9
KVN10
KVN11
KVN12
KVN13
KVN14
KVN15
KVN16
RN8
RN9
RN10
RN11
RN12
RN13
RN14
RN17
RN18
RN19
RN20
RN21
RN22
KVN21 8 to 1
KVN22 SE
LL
KVN23
KVN24
VRLP
0~28R
PKN3[2:0]
RN23
KVN25
KVN26
KVN27
KVN28
KVN29
KVN30
KVN31
KVN32
RN26
RN27
4R
5R
RP42
RP43
RP44
RP45
KVP47
KVP48
PKP5[2:0]
8 to 1
SE
LL
VIINP 6
VRLN
0 ~28R
VRP1[4:0]
4R
PKN4[2:0]
KVN36 8 to 1
KVN37 SE
LL
KVN38
KVN39
PKN5[2:0]
KVN41
KVN42
KVN43
KVN44
KVN45
KVN46
8 to 1
SE
LL
VINN6
KVN47
KVN48
RN46
KVN49
VRN
0~31R
VRN1[4:0]
RN47
Ladder Resistors and 8-to-1 Selector
Rev.0.12, May 09 2003, page 113 of 156
VINN5
KVN40
PRN1[2:0]
VIINP 7
8R
RP47
VINN4
KVN34
KVN35
RN39
RN40
RN41
RN42
RN43
RN44
RN45
5R
RP46
VRP1
0~31R
8R
VIINP 5
KVP41
KVP42
KVP49
VGS
8 to 1
SE
LL
KVP40
KVP43
KVP44
KVP45
KVP46
RP40
RP41
8 to 1
SE
LL
RN31
RN32
RN33
RN34
RN35
RN36
RN37
RN38
KVP38
KVP39
PRP1[2:0]
RP39
VINN3
KVN33
KVP34
KVP35
KVP36
KVP37
VINN2
PKN2[2:0]
KVP33
1R
8 to 1
SE
LL
KVN17
KVN18
KVN19
KVN20
RN30
5R
PKN1[2:0]
RN15
RN28
RN29
PKP4[2:0]
VINN1
KVN8
PRN0[2:0]
RN24
RN25
8 to 1
SE
LL
RP31
RP32
RP33
RP34
RP35
RP36
RP37
RP38
VINN0
PKN0[2:0]
RN16
RP23
RP30
5R
8 to 1
SE
LL
RP15
RP17
RP18
VIiNP1
KVP8
RP9
RP10
RP16
1R
8 to 1
SE
LL
KVP6
KVP7
KVP9
KVP10
KVN0
KVN1
PRP0[2:0]
RP13
RP14
5R
KVP1
KVP2
KVP3
KVP4
KVP5
VRN0[3:0]
VRN0
0 ~30R
PKP0[2:0]
RP0
RP1
RP2
4R
VIiNP 0
VINN7
HD66789
Preliminary
γ-Correction Register
Grayscale number
Glayscale voltage
Glayscale voltage
Glayscale voltage
The γ-adjustment register is a group of registers to set an appropriate grayscale voltage for the γcharacteristics of a liquid crystal panel. The register group is categorized into the ones adjusting gradient,
amplitude, and fine-tuning in relation to grayscale number and grayscale voltage characteristics. Each
register can make an independent setting for the positive/negative polarity. The reference value and RGB
are common to both polarities.
Grayscale number
Gradient adjustment
Amplitude adjustment
Grayscale number
Fine adjustment
Gradient, Amplitude, Fine Adjustments
1. Gradient adjustment registers
The gradient adjustment registers are used to adjust the gradient around the middle of the grayscale number
and voltage characteristics without changing a dynamic range. To adjust a gradient, the values of the
variable resistors (VRHP (N)/VRLP (N)) in the middle of the ladder resistor block for grayscale voltage
generation are controlled. The registers incorporate separate registers for positive and negative polarities to
be compatible with asymmetric drive.
2. Amplitude adjustment registers
The amplitude adjustment registers are used to adjust the amplitude of the grayscale voltage. To adjust the
amplitude, the values of the variable resistors (VRP(N)1/0) in the bottom of the ladder resistor block for
grayscale voltage generation are adjusted. Same with the gradient registers, the amplitude adjustment
registers also incorporate separate registers for positive and negative polarities.
3. Fine adjustment registers
The fine adjustment register is to fine-adjust the grayscale voltage level. To fine-adjust the grayscale
voltage level, each level of 8-level reference voltages generated from the ladder registers is controlled by 8to-1 selector. Same with the other registers, the fine-adjustment registers also incorporate separate registers
for positive and negative polarities.
Rev.0.12, May 09 2003, page 114 of 156
HD66789
Preliminary
γ-Correction Registers
Register
Groups
Positive
Polarity
Negative
Polarity
Description
Gradient
adjustment
PRP0 2 to 0
PRN0 2 to 0
Variable resistor VRHP (N)
PRP1 2 to 0
PRN1 2 to 0
Variable resistor VRLP (N)
Amplitude
adjustment
VRP0 3 to 0
VRN0 3 to 0
Variable resistor VRP (N)0
VRP1 4 to 0
VRN1 4 to 0
Variable resistor VRP (N)1
Fine adjustment
PKP0 2 to 0
PKN0 2 to 0
8-to-1 selector (voltage level of grayscale 1)
PKP1 2 to 0
PKN1 2 to 0
8-to-1 selector (voltage level of grayscale 8)
PKP2 2 to 0
PKN2 2 to 0
8-to-1 selector (voltage level of grayscale 20)
PKP3 2 to 0
PKN3 2 to 0
8-to-1 selector (voltage level of grayscale 43)
PKP4 2 to 0
PKN4 2 to 0
8-to-1 selector (voltage level of grayscale 55)
PKP5 2 to 0
PKN5 2 to 0
8-to-1 selector (voltage level of grayscale 62)
Ladder resistors and 8-to-1 selector
Block configuration
The block diagram of page 112 consists of two ladder resistors including variable resistors, and 8-to-1
selectors which select the voltage generated by the ladder resistors to output a reference voltage for the
grayscale voltage. The variable resistors and the 8-to-1 selectors are controlled by the γ correction registers.
Pins that are connected to a variable resistor are provided to compensate the variation among the panels.
Variable resistor
There are three kinds of variable resistors for the gradient adjustment (VRHP(N)/VRLP(N)), the amplitude
adjustment (1) (VRP(N)0), and the amplitude adjustment (2) (VRP(N)1). The resistance is determined by
the gradient adjustment and amplitude adjustment registers as is shown below.
Gradient adjustment
Amplitude adjustment (1)
Amplitude adjustment (2)
Contents of Register
PRP(N) 0/1[2:0]
Resistance
VRHP(N)
VRLP(N)
Contents of Register
VRP(N)0[3:0]
Resistance
VRP(N)0
Contents of Register
VRP(N)1[4:0]
Resistance
VRP(N)1
000
0R
0000
0R
00000
0R
001
4R
0001
2R
00001
1R
010
8R
011
12R
100
16R
0010
•
•
•
•
4R
•
•
•
•
00010
•
•
•
•
2R
•
•
•
•
101
20R
1101
26R
11101
29R
110
24R
1111
28R
11110
30R
111
28R
1111
30R
11111
31R
Rev.0.12, May 09 2003, page 115 of 156
HD66789
Preliminary
8-to-1 selector
The 8-to-1 selectors select a voltage level generated by the ladder resistors according to the fine adjustment
registers, and output six kinds of reference voltage, VIN1 to VIN 6. The relationship between the fine
adjustment register and the selected voltage is as follows.
Fine adjustment registers and selected voltage
The value of Register
Selected Voltage
PKP(N)[2:0]
VINP(N)1
VINP(N)2
VINP(N)3
VINP(N)4
VINP(N)5
VINP(N)6
000
KVP(N)1
KVP(N)9
KVP(N)17
KVP(N)25
KVP(N)33
KVP(N)41
001
KVP(N)2
KVP(N)10
KVP(N)18
KVP(N)26
KVP(N)34
KVP(N)42
010
KVP(N)3
KVP(N)11
KVP(N)19
KVP(N)27
KVP(N)35
KVP(N)43
011
KVP(N)4
KVP(N)12
KVP(N)20
KVP(N)28
KVP(N)36
KVP(N)44
100
KVP(N)5
KVP(N)13
KVP(N)21
KVP(N)29
KVP(N)37
KVP(N)45
101
KVP(N)6
KVP(N)14
KVP(N)22
KVP(N)30
KVP(N)38
KVP(N)46
110
KVP(N)7
KVP(N)15
KVP(N)23
KVP(N)31
KVP(N)39
KVP(N)47
111
KVP(N)8
KVP(N)16
KVP(N)24
KVP(N)32
KVP(N)40
KVP(N)48
Rev.0.12, May 09 2003, page 116 of 156
HD66789
Preliminary
The grayscale levels (V0-V31) are calculated according to the following formulas.
Formulas for calculating voltage (Positive polarity) (1)
Pin
Formula
KVP0
VREG1OUT - ∆ V*VRP0/SUMRP
KVP1
KVP2
KVP3
KVP4
KVP5
KVP6
KVP7
KVP8
KVP9
KVP10
KVP11
KVP12
KVP13
KVP14
KVP15
KVP16
KVP17
KVP18
KVP19
KVP20
KVP21
KVP22
KVP23
KVP24
KVP25
KVP26
KVP27
KVP28
KVP29
KVP30
KVP31
KVP32
KVP33
KVP34
KVP35
KVP36
KVP37
KVP38
KVP39
KVP40
KVP41
KVP42
KVP43
KVP44
KVP45
KVP46
KVP47
KVP48
KVP49
VREG1OUT
VREG1OUT
VREG1OUT
VREG1OUT
VREG1OUT
VREG1OUT
VREG1OUT
VREG1OUT
VREG1OUT
VREG1OUT
VREG1OUT
VREG1OUT
VREG1OUT
VREG1OUT
VREG1OUT
VREG1OUT
VREG1OUT
VREG1OUT
VREG1OUT
VREG1OUT
VREG1OUT
VREG1OUT
VREG1OUT
VREG1OUT
VREG1OUT
VREG1OUT
VREG1OUT
VREG1OUT
VREG1OUT
VREG1OUT
VREG1OUT
VREG1OUT
VREG1OUT
VREG1OUT
VREG1OUT
VREG1OUT
VREG1OUT
VREG1OUT
VREG1OUT
VREG1OUT
VREG1OUT
VREG1OUT
VREG1OUT
VREG1OUT
VREG1OUT
VREG1OUT
VREG1OUT
VREG1OUT
VREG1OUT
- ∆ V* VRP0+5R)/SUMRP
- ∆ V* VRP0+9R)/SUMRP
- ∆ V* VRP0+13R)/SUMRP
- ∆ V* VRP0+17R)/SUMRP
- ∆ V* VRP0+21R)/SUMRP
- ∆ V* VRP0+25R)/SUMRP
- ∆ V* VRP0+29R)/SUMRP
- ∆ V* VRP0+33R)/SUMRP
- ∆ V*(VRP0+33R+VRHP)/SUMRP
- ∆ V*(VRP0+34R+VRHP)/SUMRP
- ∆ V*(VRP0+35R+VRHP)/SUMRP
- ∆ V*(VRP0+36R+VRHP)/SUMRP
- ∆ V*(VRP0+37R+VRHP)/SUMRP
- ∆ V*(VRP0+38R+VRHP)/SUMRP
- ∆ V*(VRP0+39R+VRHP)/SUMRP
- ∆ V*(VRP0+40R+VRHP)/SUMRP
- ∆ V*(VRP0+45R+VRHP)/SUMRP
- ∆ V*(VRP0+46R+VRHP)/SUMRP
- ∆ V*(VRP0+47R+VRHP)/SUMRP
- ∆ V*(VRP0+48R+VRHP)/SUMRP
- ∆ V*(VRP0+49R+VRHP)/SUMRP
- ∆ V*(VRP0+50R+VRHP)/SUMRP
- ∆ V*(VRP0+51R+VRHP)/SUMRP
- ∆ V*(VRP0+52R+VRHP)/SUMRP
- ∆ V*(VRP0+68R+VRHP)/SUMRP
- ∆ V*(VRP0+69R+VRHP)/SUMRP
- ∆ V*(VRP0+70R+VRHP)/SUMRP
- ∆ V*(VRP0+71R+VRHP)/SUMRP
- ∆ V*(VRP0+72R+VRHP)/SUMRP
- ∆ V*(VRP0+73R+VRHP)/SUMRP
- ∆ V*(VRP0+74R+VRHP)/SUMRP
- ∆ V*(VRP0+75R+VRHP)/SUMRP
- ∆ V*(VRP0+80R+VRHP)/SUMRP
- ∆ V*(VRP0+81R+VRHP)/SUMRP
- ∆ V*(VRP0+82R+VRHP)/SUMRP
- ∆ V*(VRP0+83R+VRHP)/SUMRP
- ∆ V*(VRP0+84R+VRHP)/SUMRP
- ∆ V*(VRP0+85R+VRHP)/SUMRP
- ∆ V*(VRP0+86R+VRHP)/SUMRP
- ∆ V*(VRP0+87R+VRHP)/SUMRP
- ∆ V*(VRP0+87R+VRHP+VRLP)/SUMRP
- ∆ V*(VRP0+91R+VRHP+VRLP)/SUMRP
- ∆ V*(VRP0+95R+VRHP+VRLP)/SUMRP
- ∆ V*(VRP0+99R+VRHP+VRLP)/SUMRP
- ∆ V*(VRP0+103R+VRHP+VRLP)/SUMRP
- ∆ V*(VRP0+107R+VRHP+VRLP)/SUMRP
- ∆ V*(VRP0+111R+VRHP+VRLP)/SUMRP
- ∆ V*(VRP0+115R+VRHP+VRLP)/SUMRP
- ∆ V*(VRP0+120R+VRHP+VRLP)/SUMRP
SUMRP : Sum of positive ladder resistors = 128R+VRHP+VRLP+VRP0+VRP1
SUMRN : Sum of negative ladder resistors = 128R+VRHN+VRLN+VRN0+VRN1
∆V : Voltage difference between VREG1OUT and VGS
Rev.0.12, May 09 2003, page 117 of 156
Fine adjustment register value
PKP02-00 = "000"
PKP02-00 = "001"
PKP02-00 = "010"
PKP02-00 = "011"
PKP02-00 = "100"
PKP02-00 = "101"
PKP02-00 = "110"
PKP02-00 = "111"
PKP12-10 = "000"
PKP12-10 = "001"
PKP12-10 = "010"
PKP12-10 = "011"
PKP12-10 = "100"
PKP12-10 = "101"
PKP12-10 = "110"
PKP12-10 = "111"
PKP22-20 = "000"
PKP22-20 = "001"
PKP22-20 = "010"
PKP22-20 = "011"
PKP22-20 = "100"
PKP22-20 = "101"
PKP22-20 = "110"
PKP22-20 = "111"
PKP32-30 = "000"
PKP32-30 = "001"
PKP32-30 = "010"
PKP32-30 = "011"
PKP32-30 = "100"
PKP32-30 = "101"
PKP32-30 = "110"
PKP32-30 = "111"
PKP42-40 = "000"
PKP42-40 = "001"
PKP42-40 = "010"
PKP42-40 = "011"
PKP42-40 = "100"
PKP42-40 = "101"
PKP42-40 = "110"
PKP42-40 = "111"
PKP52-50 = "000"
PKP52-50 = "001"
PKP52-50 = "010"
PKP52-50 = "011"
PKP52-50 = "100"
PKP52-50 = "101"
PKP52-50 = "110"
PKP52-50 = "111"
-
Reference
Voltage
VINP0
VINP1
VINP2
VINP3
VINP4
VINP5
VINP6
VINP7
HD66789
Preliminary
Formulas for calculating voltage (Positive polarity) (2)
Grayscale
Voltage
V0
V1
V2
V3
V4
V5
V6
V7
V8
V9
V10
V11
V12
V13
V14
V15
V16
V17
V18
V19
V20
V21
V22
V23
V24
V25
V26
V27
V28
V29
V30
V31
Formula
VINP0
V4+(VINP1-V4)*(15/24)
V4+(VINP1-V4)*(8/24)
V4+(VINP1-V4)*(4/24)
VINP2
V10+(V4-V10)*(20/24)
V10+(V4-V10)*(16/24)
V10+(V4-V10)*(12/24)
V10+(V4-V10)*(8/24)
V20+(V8-V20)*(4/24)
VINP3
V21+(V10-V21)*(21/24)
V21+(V10-V21)*(19/24)
V21+(V10-V21)*(17/24)
V21+(V10-V21)*(15/24)
V21+(V10-V21)*(13/24)
V21+(V10-V21)*(11/24)
V21+(V10-V21)*(9/24)
V21+(V10-V21)*(7/24)
V21+(V10-V21)*(5/24)
V21+(V10-V21)*(3/24)
VINP4
V27+(V21-V27)*(20/24)
V27+(V21-V27)*(16/24)
V27+(V21-V27)*(12/24)
V27+(V21-V27)*(8/24)
V27+(V21-V27)*(4/24)
VINP5
VINP6+(V27-VINP6)*(20/24)
VINP6+(V27-VINP6)*(16/24)
VINP6+(V27-VINP6)*(9/24)
VINP7
Note : Make sure DDVDH - V0 > 0.5V
DDVDH - V4 > 1.1V
Rev.0.12, May 09 2003, page 118 of 156
HD66789
Preliminary
Formulas for calculating voltage (Negative polarity) (1)
Pin
Formula
KVP0
VREG1OUT - ∆ V*VRN0/SUMRN
KVN1
KVN2
KVN3
KVN4
KVN 5
KVN 6
KVN 7
KVN 8
KVN9
KVN10
KVN 11
KVN 12
KVN13
KVN 14
KVN 15
KVN 16
KVN 17
KVN 18
KVN19
KVN 20
KVN 21
KVN22
KVN 23
KVN 24
KVN25
KVN 26
KVN 27
KVN28
KVN 29
KVN30
KVN31
KVN 32
KVN33
KVN34
KVN 35
KVN36
KVN37
KVN38
KVN 39
KVN40
KVN41
KVN42
KVN43
KVN44
KVN45
KVN46
KVN47
KVN48
KVN49
VREG1OUT - ∆ V* VRN0+5R)/SUMRN
VREG1OUT - ∆ V* VRN0+9R)/SUMRN
VREG1OUT - ∆ V* VRN0+13R)/SUMRN
VREG1OUT - ∆ V* VRN0+17R)/SUMRN
VREG1OUT - ∆ V* VRN0+21R)/SUMRN
VREG1OUT - ∆ V* VRN0+25R)/SUMRN
VREG1OUT - ∆ V* VRN0+29R)/SUMRN
VREG1OUT - ∆ V* VRN0+33R)/SUMRN
VREG1OUT - ∆ V*(VRN0+33R+VRHN)/SUMRN
VREG1OUT - ∆ V*(VRN0+34R+VRHN)/SUMRN
VREG1OUT - ∆ V*(VRN0+35R+VRHN)/SUMRN
VREG1OUT - ∆ V*(VRN0+36R+VRHN)/SUMRN
VREG1OUT - ∆ V*(VRN0+37R+VRHN)/SUMRN
VREG1OUT - ∆ V*(VRN0+38R+VRHN)/SUMRN
VREG1OUT - ∆ V*(VRN0+39R+VRHN)/SUMRN
VREG1OUT - ∆ V*(VRN0+40R+VRHN)/SUMRN
VREG1OUT - ∆ V*(VRN0+45R+VRHN)/SUMRN
VREG1OUT - ∆ V*(VRN0+46R+VRHN)/SUMRN
VREG1OUT - ∆ V*(VRN0+47R+VRHN)/SUMRN
VREG1OUT - ∆ V*(VRN0+48R+VRHN)/SUMRN
VREG1OUT - ∆ V*(VRN0+49R+VRHN)/SUMRN
VREG1OUT - ∆ V*(VRN0+50R+VRHN)/SUMRN
VREG1OUT - ∆ V*(VRN0+51R+VRHN)/SUMRN
VREG1OUT - ∆ V*(VRN0+52R+VRHN)/SUMRN
VREG1OUT - ∆ V*(VRN0+68R+VRHN)/SUMRN
VREG1OUT - ∆ V*(VRN0+69R+VRHN)/SUMRN
VREG1OUT - ∆ V*(VRN0+70R+VRHN)/SUMRN
VREG1OUT - ∆ V*(VRN0+71R+VRHN)/SUMRN
VREG1OUT - ∆ V*(VRN0+72R+VRHN)/SUMRN
VREG1OUT - ∆ V*(VRN0+73R+VRHN)/SUMRN
VREG1OUT - ∆ V*(VRN0+74R+VRHN)/SUMRN
VREG1OUT - ∆ V*(VRN0+75R+VRHN)/SUMRN
VREG1OUT - ∆ V*(VRN0+80R+VRHN)/SUMRN
VREG1OUT - ∆ V*(VRN0+81R+VRHN)/SUMRN
VREG1OUT - ∆ V*(VRN0+82R+VRHN)/SUMRN
VREG1OUT - ∆ V*(VRN0+83R+VRHN)/SUMRN
VREG1OUT - ∆ V*(VRN0+84R+VRHN)/SUMRN
VREG1OUT - ∆ V*(VRN0+85R+VRHN)/SUMRN
VREG1OUT - ∆ V*(VRN0+86R+VRHN)/SUMRN
VREG1OUT - ∆ V*(VRN0+87R+VRHN)/SUMRN
VREG1OUT - ∆ V*(VRN0+87R+VRHN+VRLP)/SUMRN
VREG1OUT - ∆ V*(VRN0+91R+VRHN+VRLP)/SUMRN
VREG1OUT - ∆ V*(VRN0+95R+VRHN+VRLP)/SUMRN
VREG1OUT - ∆ V*(VRN0+99R+VRHN+VRLP)/SUMRN
VREG1OUT - ∆ V*(VRN0+103R+VRHN+VRLP)/SUMRN
VREG1OUT - ∆ V*(VRN0+107R+VRHN+VRLP)/SUMRN
VREG1OUT - ∆ V*(VRN0+111R+VRHN+VRLP)/SUMRN
VREG1OUT - ∆ V*(VRN0+115R+VRHN+VRLP)/SUMRN
VREG1OUT - ∆ V*(VRN0+120R+VRHN+VRLP)/SUMRN
Fine adjustment register value
PKN 02-00 = "000"
PKN 02-00 = "001"
PKN 02-00 = "010"
PKN 02-00 = "011"
PKN 02-00 = "100"
PKN 02-00 = "101"
PKN 02-00 = "110"
PKN 02-00 = "111"
PKN 12-10 = "000"
PKN 12-10 = "001"
PKN 12-10 = "010"
PKN 12-10 = "011"
PKN 12-10 = "100"
PKN 12-10 = "101"
PKN 12-10 = "110"
PKN 12-10 = "111"
PKN 22-20 = "000"
PKN 22-20 = "001"
PKN 22-20 = "010"
PKN 22-20 = "011"
PKN 22-20 = "100"
PKN 22-20 = "101"
PKN 22-20 = "110"
PKN 22-20 = "111"
PKN 32-30 = "000"
PKN 32-30 = "001"
PKN 32-30 = "010"
PKN 32-30 = "011"
PKN 32-30 = "100"
PKN 32-30 = "101"
PKN 32-30 = "110"
PKN 32-30 = "111"
PKN 42-40 = "000"
PKN 42-40 = "001"
PKN 42-40 = "010"
PKN 42-40 = "011"
PKN 42-40 = "100"
PKN 42-40 = "101"
PKN 42-40 = "110"
PKN 42-40 = "111"
PKN 52-50 = "000"
PKN 52-50 = "001"
PKN 52-50 = "010"
PKN 52-50 = "011"
PKN 52-50 = "100"
PKN 52-50 = "101"
PKN 52-50 = "110"
PKN 52-50 = "111"
-
SUMRP : Sum of positive ladder resistors = 128R+VRHP+VRLP+VRP0+VRP1
SUMRN : Sum of negative ladder resistors = 128R+VRHN+VRLN+VRN0+VRN1
∆V: Voltage difference between VREG1OUT and VGS
Rev.0.12, May 09 2003, page 119 of 156
Reference
Voltage
VINN0
VINN1
VINN2
VINN3
VINN4
VINN5
VINN6
VINN7
HD66789
Preliminary
Formulas for calculating voltage (Negative polarity) (2)
Grayscale
Voltage
Formula
V0
VINN0
V1
V4+(VINN1-V4)*(15/24)
V2
V4+(VINN1-V4)*(8/24)
V3
V4+(VINN1-V4)*(4/24)
V4
VINN2
V10+(V4-V10)*(20/24)
V5
V6
V10+(V4-V10)*(16/24)
V7
V10+(V4-V10)*(12/24)
V8
V10+(V4-V10)*(8/24)
V20+(V8-V20)*(4/24)
V9
VINN3
V10
V11
V21+(V10-V21)*(21/24)
V12
V21+(V10-V21)*(19/24)
V13
V21+(V10-V21)*(17/24)
V21+(V10-V21)*(15/24)
V14
V21+(V10-V21)*(13/24)
V15
V21+(V10-V21)*(11/24)
V16
V21+(V10-V21)*(9/24)
V17
V21+(V10-V21)*(7/24)
V18
V21+(V10-V21)*(5/24)
V19
V20
V21+(V10-V21)*(3/24)
V21
VINN4
V27+(V21-V27)*(20/24)
V22
V27+(V21-V27)*(16/24)
V23
V27+(V21-V27)*(12/24)
V24
V27+(V21-V27)*(8/24)
V25
V27+(V21-V27)*(4/24)
V26
V27
VINN5
V28
VINN6 +(V27-VINN6)*(20/24)
V29
VINN6 +(V27-VINN6)*(16/24)
V30
VINN6 +(V27-VINN6)*(9/24)
VINN7
V31
Note : Make sure DDVDH - V0 > 0.5V
DDVDH - V4 > 1.1V
Rev.0.12, May 09 2003, page 120 of 156
HD66789
Preliminary
Relationship between RAM data and output level
The relationship between the RAM data and the source output level is as follows.
V0
Negative polarity
Positive polarity
111111
000000
V31
RAM data
(Common for each RGB pixel)
RAM data and the output voltage
Sn
Negative polarity
Vcom
Positive polarity
Source output and Vcom
Rev.0.12, May 09 2003, page 121 of 156
HD66789
Preliminary
8-color Display Mode
The HD66789 incorporates 8-color display mode. The available grayscale levels are V0 and V31, and the
voltages for the other levels (V1-V30) are halted to reduce power consumption.
The γ-fine-adjustment registers, PKP0-PKP5 and PKN0-PKN5 are not available in the 8-color display
mode. Since the power supply for the levels V1-V30 are halted, RGB data in GRAM should be set to
either “000000” or “111111” before setting this mode so that V0 or V31 is selected.
Graphics RAM(GRAM)
MSB
Display
data
R5
R4
R3
R2
R1
R0
G 5 G4
G3
G2
G1
LSB
G0
B5
B4
B3
B2
B1
PKP 02 PKP 01 PKP 00
PKP 12 PKP 11 PKP 10
Positive
Polarity
Register
PKP 22 PKP 21 PKP 20
PKP 32 PKP 31 PKP 30
PKP 42 PKP 41 PKP 40
PKP 52 PKP 51 PKP 50
PRP 02 PRP 01 PRP 00
V0
VRP 03 VRP 02 VRP 01 VRP00
VRP 14 VRP 13 VRP 12 VRP 11 VRP10
PKN 02 PKN 01 PKN 00
PKN 12 PKN 11 PKN 10
Negative
Polarity
Register
8
Grayscale Amplifier
PRP 12 PRP 11 PRP 10
2
6
6
6
2 - level grayscale
control
<R>
2 - level grayscale
control
<G>
2 - level grayscale
control
<B>
LCD driver
LCD driver
LCD driver
V31
PKN 22 PKN 21 PKN 20
PKN 32 PKN 31 PKN 30
PKN 42 PKN 41 PKN 40
PKN 52 PKN 51 PKN 50
PRN 02 PRN 01 PRN 00
PRN 12 PRN 11 PRN 10
VRN 03 VRN 02 VRN01 VRN00
R G B
LCD
VRN14 VRN13 VRN12 VRN11 VRN10
Grayscale control
Rev.0.12, May 09 2003, page 122 of 156
B0
HD66789
Preliminary
To switch between the 262, 144-color mode and the 8-color mode, make settings according to the following
sequences.
262,144 to 8 colors
8 to 22,144 colors
Display off
GON = “1”
DTE = “1”
D1-0 = “10”
Display off
GON =”1”
DTE = “1”
D1-0 = “10”
Wait (2 frame or more)
Wait (2 frame or more)
Display off
GON = “1”
DTE = “0”
D1-0 = “10”
Display off
GON = “1”
DTE = “0”
D1-0 = “10”
Wait (2 frame or more)
Wait (2 frame or more)
Display off
GON = “0”
DTE = “0”
D1-0 = “00”
Display off
GON = “0”
DTE = “0”
D1-0 = “00”
Setting of RAM
Setting of RAM
CL = “1”
CL = “0”
Wait (40 msec or more)
Wait (40 msec or more)
Display on
GON = “0”
DTE = “0”
D1-0 = “01”
Display on
GON = “0”
DTE = “0”
D1-0 = “01”
Wait (2 frame or more)
Wait (2 frame or more)
Display on
GON = 1
DTE = 0
D1-0 = 01
Display on
GON =”1”
DTE = “0”
D1-0 = “01”
Display on
GON =”1”
DTE = “0”
D1-0 = “11”
Display on
GON = “1”
DTE = “0”
D1-0 = “11”
Wait (2H or longer)
Wait (2H or longer)
Display on
GON =”1”
DTE = “1”
D1-0 = “11”
Display on
GON =”1”
DTE = “1”
D1-0 = “11”
Displaying
in 8-color mode
Displaying
in 262,144-color mode
Rev.0.12, May 09 2003, page 123 of 156
HD66789
Preliminary
System Configuration
The following figure illustrates an example of configuring a TFT-LCD panel of 176x 240 dots
withHD66789.
176 pixels x 3
G1
G2
α - Si TFT
240
G239
G240
S527 S528
S1S2
Vcom
Source Driver Circuit
Vcom
DCDC
Power Supply
Circuit
HD66789
Gate Driver
Circuit
Vci1 Vci
4
18
RESET DB0~17
3
18
4
Vcc GND
IM2, IM1, VLD PD0~17
IM0/ID
CS*,WR*,
RD*, RS
VSYNC
HSYNC
DOTCLK
ENABLE
System configuration with HD66789
Rev.0.12, May 09 2003, page 124 of 156
HD66789
Preliminary
Configuration of Power Generation Circuit
The internal configuration of power generation circuit of HD66789 is as follows.
VREG1OUT
In case of OCG
assemby, separate
on the FPC.
VciLVL
Voltage
Adjustment
Circuit
Amplifying
Circuit 1
(VDH Adjustment)
Source Driver
S1-S528
REGP
VcomH voltage
adjustment
(in case of
adjusting
with external
variable resistors)
γ Adjustment
Vci
Circuit
VciOUT
VciOUT
Output AMP
γ Adjustment
Circuit
VcomR
Vci1
C11-
In case of using
VciOUT output
amplifier
C11+
Vci
VcomH
adjustment
Circuit
Step-up
Circuit 1
VLOUT1
Grayscale
Voltage
Generation
Circuit
Note 2)
VcomH output
Amplifier
C12C12+
C21-
VcomH
Vcom
C21+
C22-
Vcom amplitude
adjustment Circuit
VcomL output
Amplifier
VcomL
C22+
VLOUT2
V31N
VMONI
DDVDH
Note 2)
V0P
V0N
V31P
Step-up
Circuit 2
VGH
VLOUT3
TESTA1
TESTA2
TESTA4
VGH
VGL
Gate Driver
Note 1)
G1-G240
VGL
Notes 2),3)
Note 4)
VLOUT4
VCL
Vcc
HD66789
GND
Note 1) Connect stabilizing capacitors to the TESTA4 panel as required for the display quality of
the panel and voltage consumption (0.1µF, characteristic B). Otherwise, adopt 1µF, characteristic B.
Note 2) Place a shot-key diode (VF = about 0.4V/20mA, VR >=30V).
Note 3) Wiring from GND or VGL to the shot-key dioode must be 10Ω or less.
Note 4) Capacitors are not required when VCOMG = 0 (VCOML = GND).
Rev.0.12, May 09 2003, page 125 of 156
HD66789
Preliminary
Specification of External Elements Connected to HD66789 Power Supply
The following table shows specifications of external elements connected to HD66789 power supply.
Capacitor
Capacity
Recommended voltage
Connect pins
1 µF (B characteristic)
6V
VREG1OUT, VciOUT, VOUT4, VcomH, VcomL,
C11+/-, C21+/-
10V
VLOUT1, C21+/-, C22+/-
25V
VLOUT2, VLOUT3
6V
V0P, V0N, V31P, V31N, TESTA4
0.1 µF (B characteristic)
Shot-key diode
Feature
Connect pin
VF < 0.4V / 20mA at 25 centigrade, VR>=30V
GND – VGL
(recommended diode : HSC226)
(Vci – VGH)
(Vci – DDVDH)
Variable resistor
Feature
Connect pin
> 200 kΩ
VcomR
Rev.0.12, May 09 2003, page 126 of 156
HD66789
Preliminary
Instruction Setting Flow
Make a setting for each instruction according to the following sequence.
Display ON/OFF
Display off
EQ = 0
Display on
Power supply
setting
Display off
GON = 1
DTE = 1
D1-0 = 10
SAP2-0 Setting
Wait (2 frames or more)
Display on
GON = 0
DTE = 0
D1-0 = 01
Display off
GON = 1
DTE = 0
D1-0 = 10
Wait (2 frames or more)
Display off
GON = 0
DTE = 0
D1-0 = 00
Power supply off
SAP2-0 = “000”
AP2-0 = “000”
PON = “0”
VCOMG = “0”
Wait (2 frames or more)
Display on
GON = 1
DTE = 0
D1-0 = 01
Display on
GON = 1
DTE = 0
D1-0 = 11
Wait (2 frames or more)
Display on
GON = 1
DTE = 1
D1-0 = 11
“Display on”
“Display off”
Display on flow
Display off flow
Rev.0.12, May 09 2003, page 127 of 156
HD66789
Preliminary
Standby and Sleep
Sleep
Standby
Display off flow
Standby
set
Standby set (STB = “1”)
Display off low
Sleep set
Sleep set (SLP = “1”)
Oscillation Start
Wait 10 ms
Standby
cancel
Sleep canceled (SLP = “0”)
Sleep
cancel
Standby canceled (STB = “0”)
Power setting
Power setting
Display on flow
Display on low
Rev.0.12, May 09 2003, page 128 of 156
HD66789
Preliminary
Power Supply Setting
Whenever turning on the power supply, it must be done in accordance to the following procedure.
The stabilization time for the oscillation circuits, step-up circuits, and operational amplifiers depends on the
external resistors and capacitors.
Power supply (Vcc, Vci, IOVcc) ON
Vcc
IOVcc Vci
GND
Vcc(=RVcc)
IOVcc
Vci or
Vcc(=RVcc), IOVcc, Vci Simultaneously
Normal Display
1ms or more
Power ON RESET
& Display OFF
10ms or more
Oscillation Circuit
Stabilization Time
Instructions for
settings before
driving
Power Supply
Power Supply
Instruction
issue (1)
Bits for “Display OFF”
DTE="0”, D1-0="00"
GON="0"
PON="0"
VCOMG="0"
Bits for Initializing
Power Supply Settings
VC2-0 bits setting
VRH3-0 bits setting
VCM4-0 bits setting
VDV4-0 bits setting
PON="0”, DK="1"
Bits for setting
Power Supply Operation Start
BT2-0="000"
DC12-10 bits setting
Bits for “Display ON”
DTE = "1", D1-0="11"
GON = "1"
Display OFF
Sequence
Display OFF
Bits for setting
Power Supply Halt
Power supply
setting
Instruction (2)
SAP2-0="000"
AP2-0="000"
PON="0"
VCOMG="0"
DC02-00 bits setting
AP2-0 bits setting
40ms or more
PON="1"
Power Supply (Vcc, Vci, IOVcc) OFF
Vci IOVcc
Step-up Circuit
Stabilization Time
100ms or more
Operational
Amplifier
Stabilization
Time
Power Supply
Instruction
issue (2)
Bits for setting
Power Supply Operation Start
VCOMG="1"
BT2-0 bits setting
DK="0"
Other mode settings
Instruction issue
Display ON
sequence
Display ON
SAP2-0 bit setting
Bits for “Display ON”
DTE="1", D1-0="11"
GON="1"
Display ON Sequence
Rev.0.12, May 09 2003, page 129 of 156
Vci
IOVcc
Vcc
GND
Vcc(=RVcc) or
Vcc(=RVcc),IOVcc, Vci Simultaneously
Display OFF Sequence
HD66789
Preliminary
Pattern Diagram for Voltage Setting
The following figures are the pattern diagram of voltage setting for the HD66789 and the voltage
waveforms.
VLOUT2
VGH (+9 ~ +16.5V)
BT
VLOUT1
DDVDH (4.5 ~ 5.5V)
VREG1OUT (3.0 ~ (DDVDH-0.5)V)
Vci (2.5 ~ 3.3V)
VC
Vci1
VcomH (3.0 ~ (DDVDH-0.5) V)
VRH
Vcc (2.4 ~ 3.3V)
VDV
IOVcc (1.8 ~ 3.3V)
GND (0V)
VCOMG
VLOUT4
VcomL ((VCL+0.5) ~ 1V)
VCL (0 ~ -3.3)V
BT
VLOUT3
VGL (-4.0 ~ -16.5V)
Pattern diagram for voltage setting
Note 1) Voltage drop occurs in relation to set voltage for each DDVDH, VGH, VGL, VCL output depending
on current consumption required for each output. (DDVDH+VREG1OUT) > 0.5V and
(VcomL – VCL) > 0.5V show the relationship in relation to the actual voltage. When AC frequency of
Vcom1 and Vcom 2 is high (e.g. AC occurs by line), current consumption is also large. In this case,
check voltage before use.
VGH
VDH
VcomH
VcomL
Vcom
Sn(Source driver output of HD66789)
Gate Output
VGL
Applied voltage to the TFT display
Rev.0.12, May 09 2003, page 130 of 156
HD66789
Preliminary
Oscillation Circuit
The HD66789 generates oscillation by internal R-C oscillator with an external oscillation resistor placed
between the OSC1 and OSC2 pins. The oscillation frequency varies depending on the value of external
resistor, the distance of wiring, and the power supply voltage for the oscillation. For example, the
oscillation frequency becomes low when increasing the value of Rf resistor, or lowering the power supply
voltage. See the “Electric Characteristics Notes” section for the relationship between the Rf resistor value
and the oscillation frequency.
OSC1
Rf
OSC2
HD66789
OSC1
Rf
OSC2
HD66789
External Resistor Oscillation Mode
Note 1) Place the Rf resistor as close as to the OSC1, OSC2 pins.
Note 2) Make sure not to arrange other wiring beneath or close to OSC1-OSC2 wiring to avoid effects from
coupling.
Rev.0.12, May 09 2003, page 131 of 156
HD66789
Preliminary
n-raster-row Inversion AC Drive
The HD66789, in addition to LCD inversion AC drive by frame, supports n-raster-row inversion AC drive
where alternation occurs by n raster-rows, where n takes a number between 1 to 64. The n-raster-row
inversion AC drive enables to overcome the problems related to display quality.
In determining n (the value set in the NW bit +1), the number of raster-rows by which alternation occurs,
check the display quality on the actual liquid crystal panel. Setting a small number of raster-rows will raise
the AC frequency of the liquid crystal and increase the charge/discharge current on the liquid crystal cells..
1 frame
Back porch
1
2
3
1 frame
Front porch
4
241242
Back porch
256 1
2
3
Front porch
4
241 242
256 1
2
Frame AC driving
240-raster-row driving
n-raster row driving
240-raster-row driving
3-raster-row reversed
EOR = 1
Note: Make sure that EOR is set to "1" whenever the n-raster-row reverse AC driving to avoid DC bias.
n-raster-rows inversion AC drive
Rev.0.12, May 09 2003, page 132 of 156
HD66789
Preliminary
Interlaced Drive
The HD66789 supports interlaced drive, which divides one frame into n fields and then drives to prevent
flickers.
To determine the number of fields (n: value set in the FLD bits), check the display quality on the actual
liquid crystal panel. The following table shows the gate selection for each number of fields, 1 to 3. The
figure illustrates the output waveforms of the 3-field interlaced drive.
Gate selection
GS = 0
GS = 1
FLD1-0
01
Field
-
11
1
2
FLD1-0
3
Gate
01
Field
11
-
1
G240
O
O
G239
O
G238
O
G237
O
G236
O
G235
O
G234
O
G233
O
G232
O
2
3
Gate
G1
O
G2
O
G3
O
G4
O
G5
O
G6
O
G7
O
G8
O
G9
O
•
•
•
•
•
•
G237
O
G238
O
G239
O
G240
O
O
O
O
O
O
O
O
O
O
•
•
•
•
•
•
•
•
•
O
O
O
Rev.0.12, May 09 2003, page 133 of 156
O
•
•
•
•
•
•
G4
O
G3
O
G2
O
G1
O
O
O
O
O
O
O
O
O
•
•
•
•
•
•
•
•
•
O
O
O
O
HD66789
Preliminary
1 frame
Blank period
Field 1
Field 2
Field 3
Field 1
AC
Polarity
G1
G2
G3
G4
G5
G6
G3n + 1
G3n + 2
G3n + 3
Gate output timing in 3-field interlaced drive
Rev.0.12, May 09 2003, page 134 of 156
HD66789
Preliminary
AC Timing
The AC timings of frame inversion AC drive, 3-field interlaced drive, and n-raster-row inversion drive are
illustrated as follows. In case of frame inversion AC drive, alternation occurs at the completion of drawing
one frame, followed by a blank, which lasts for 16H periods. In this case, all outputs from the gate are
Vgoff outputs. In case of interlaced drive, alternation occurs at the completion of drawing one field,
followed by a blank. The total period of the blanks in one frame amounts to 16H period. In case of nraster-row, a blank lasting 16H period is inserted after drawing a full screen.
During interlaced drive, make the numbers of back and front porches more than that of field.
Frame inversion AC drive
3-field interlaced drive
n-raster-row inversion AC drive
AC timing
Field 1
AC timing
Blank period 1
AC timing
Field 2
Blank period 2
One frame period
One frame period
Frame 1
Field 3
Front porch
AC timing
AC timing
Back porch
AC timing
n-raster-rows
AC timing
n-raster-rows
AC timing
n-raster-rows
AC timing
n-raster-rows
AC timing
n-raster-rows
AC timing
n-raster-rows
AC timing
n-raster-rows
AC timing
AC timing
n-raster-rows
Front porch
Blank period 3
Blank period
= front porch + back porch
= 16H
Blank period
= Blank period 1
+ Blank period 2
+ Blank period 3
= 8H
(BP=3, FP=5)
AC timing
Rev.0.12, May 09 2003, page 135 of 156
Blank period
= 16H
One frame period
AC timing
Back porch
HD66789
Preliminary
Frame-Frequency Adjustment Function
The HD66789 incorporates frame frequency adjustment function. The frame frequency during the liquid
crystal drive is adjusted by the instruction setting (DIV, RTN) while keeping the oscillation frequency fixed.
Setting the oscillation frequency high in advance allows switching the frame frequency in accordance to the
kind of displayed picture (i.e. moving/still picture). When displaying a still picture, set the frame frequency
low to save power consumption, while setting the frame frequency high when displaying a moving picture
which requires high-speed switching of screens.
Relationship between Liquid Crystal Drive Duty and Frame Frequency
The relationship between the liquid crystal drive duty and the frame frequency is calculated by the
following formula. The frame frequency is adjusted through the instruction setting with the 1-H period
adjustment bit (RTN bit) and the operation clock division bit (DIV bit).
(Formula for the frame frequency)
fosc
Frame frequency =
Clock cycles per raster-row × division ratio × (Line+BP+FP)
[Hz]
fosc: R-C oscillation frequency
Line: number of drive raster-rows (NL bit)
Clock cycles per raster-row: RTN bit
Division ratio: DIV bit
The number of raster-rows for the front porch: FP
The number of raster-rows for the back porch: BP
Calculation Example
The maximum frame frequency = 60 Hz
Number of drive raster-rows: 240
1-H period: 16 clock cycles (RTN3-0 = 0000)
Operation clock division ratio: 1 division
fosc = 60 Hz × (0 + 16) clock × 1 division × (240 + 16) lines = 246 (kHz)
In this case, the R-C oscillation frequency becomes 246 kHz. Adjust the external resistor to the R-C
oscillator to 246 kHz.
Rev.0.12, May 09 2003, page 136 of 156
HD66789
Preliminary
Screen -split Drive Function
The HD66789 allows selectively driving two screens at arbitrary positions with the screen-drive position
registers (R42 and R43). Only the raster-rows required to display two screens at arbitrary positions are
selectively driven to reduce power consumption.
The first screen drive position register (R42) specifies the start line (SS17-10) and the end line (SE17-10)
for displaying the first screen. The second screen drive position register (R43) specifies the start line
(SS27-20) and the end line (SE27-20) for displaying the second screen. The second screen control is
effective when the SPT bit is set to 1. The total number of raster-rows driven for displaying the first and
second screens must be less than the number of liquid crystal drive raster-rows.
1st Screen:
7 raster-row
driving
G1
G7
Non-display
ar ea
G26
2nd Screen:
17 raster-row
driving
G42
Non-display
ar ea
The number of driven raster-rows : NL4-0 = “11110” (240 raster-rows)
1st screen setting : SS17-10 = “00”H, SS17-10 = “06”H
2nd screen setting : SS27-20 = “19”H, SS27-20 = “29”H, SPT = “1”
Screen-split Drive
Rev.0.12, May 09 2003, page 137 of 156
HD66789
Preliminary
Notes to the setting of 1st/2nd screen drive position registers
When making settings for the start line (SS17-10) and end line (SE17-10) of the first screen drive position
register (R42), and the start line (SS27-20) and end line (SE27-20) of the second screen drive position
register (R43) with the HD66789, it is necessary to satisfy the following conditions to display screens
correctly.
One-screen Drive (SPT = 0)
Register Settings
Display Operation
(SE17-10) - (SS17-10) = NL
Full screen display
The area of (SE17-10) - (SS17-10) is normally displayed.
(SE17-10) - (SS17-10) < NL
Partial screen display
The area of (SE17-10) - (SS17-10) is normally displayed.
The rest of the area is white display irrespective of data in RAM.
(SE17-10) - (SS17-10) > NL
Setting disabled
Note 1) SS17-10 ≤ SE17-0 ≤ “EF”H
Note 2) Setting disabled for SS27-20 and SE27-20.
Two-screen Drive (SPT = 1)
Register Settings
Display Operation
((SE17-10) - (SS17-10))
+ ((SE27-20) - (SS27-20)) = NL
Full screen display
The area of (SE27-20) - (SS17-10) is normally displayed.
((SE17-10) - (SS17-10))
+ ((SE27-20) - (S27-20)) < NL
Partial screen display
The area of (SE27-10) - (SS17-10) is normally displayed.
The rest of the area is white display irrespective of data in RAM.
((SE17-10) - (SS17-10))
+ ((SE27-20) - (SS27-20)) > NL
Setting disabled
Note 1) Make sure that SS17-10 ≤ SE17-10 < SS27-20 ≤ SE27-20 ≤ EFH.
Note 2) Make sure that ((SE27-20) - (SS17-10)) ≤ NL.
The setting for the driver output in the non-display area during the partial display is changeable according
to the characteristics of the display panel.
Source outputs in non-display area
Source Output for Non-display Area
PT1
PT0
Positive Polarity
Negative Polarity
0
0
V31
V0
0
1
V31
V0
1
0
GND
GND
1
1
High-Z
High-Z
Rev.0.12, May 09 2003, page 138 of 156
HD66789
Preliminary
Full screen display
PT1-0 = 00
Set SS/SE bits
Wait for 2 screen or more
Screen
division drive
set up flow
As required
PT1-0 = 01 or
PT1-0 = 10 or
PT1-0 = 11
Partial display ON
Set SS/SE bits
Full screen display
setting flow
Full screen display
Partial display setting flow
Rev.0.12, May 09 2003, page 139 of 156
HD66789
Preliminary
Absolute Maximum Values
Item
Symbol
Unit
Value
Notes
Power supply voltage (1)
Vcc
V
-0.3 ~ + 4.6
1, 2
Power supply voltage (2)
Vci - GND
V
-0.3 ~ + 4.6
1, 2
Power supply voltage (3)
DDVDH - GND
V
-0.3 ~ + 6.0
1, 2
Power supply voltage (4)
GND -VCL
V
-0.3 ~ + 4.6
1, 2
Power supply voltage (5)
DDVDH - VCL
V
-0.3 ~ + 9.0
1
Power supply voltage (6)
VGH - GND
V
-0.3 ~ + 18.5
1, 2
Power supply voltage (7)
GND - VGL
V
-0.3 ~ + 18.5
1, 2
Input voltage
Vt
V
-0.3 ~ Vcc + 0.3
1
Operating temperature
Topr
°C
-40 ~ + 85
1, 3
Storage temperature
Tstg
°C
-55 ~ + 110
1
Note 1) The LSI may be permanently damaged if it is used under the condition exceeding the above
absolute maximum values. It is also recommended to use the LSI within the limit of its electric
characteristics during normal operation. Exceeding the conditions may lead to malfunction of LSI
and affect its credibility.
Note 2) The voltage from GND.
Note 3) The DC and AC characteristics of chip and wafer products are guaranteed at 85 °C.
Rev.0.12, May 09 2003, page 140 of 156
HD66789
Preliminary
Electric Characteristics (T.B.D.)
DC Characteristics
(VCC = 1.8 to 3.7 V, Ta = –40 to +85°C Note 1 )
Item
Symbol Unit Test Condition
Min
Max
Notes
Input high voltage
VIH
V
VCC = 1.8 to 3.7 V
0.7 VCC —
VCC
2, 3
Input low voltage (1)
(OSC1 pin)
VIL1
V
VCC = 1.8 to 3.7 V
–0.3
—
0.15VCC 2, 3
Input low voltage (2)
(Except OSC1 pin)
VIL2
V
Vcc=1.8V to 2.4V
-0.3

0.15Vc 2,3
c
Vcc=2.4V to 3.7V
-0.3

0.2Vcc 2,3
Output high voltage (1)
(DB0-17 pins)
Output low voltage (1)
(DB0-17 pins)
I/O leakage current
Typ
VOH1
V
IOH = –0.1 mA
0.75VCC —
—
—
0.2 VCC 2
V
VCC = 1.8 to 2.4 V,
IOL = 0.1 mA
—
VOL1
VCC = 2.4 to 3.7 V,
IOL = 0.1 mA
—
—
0.15VCC 2
ILi
Current consumption
IOP
during normal operation
(VCC – GND)
µA
Vin = 0 to VCC
–1
—
1
4
µA
R-C oscillation; fosc =
250kHz (240line)
VCC = 3.0 V,
Ta = 25°C, RAM data
0000h
—
190
300
5,6
Vcc = 3V, Ta<=50°C
—
0.1
5
Vcc = 3V, Ta>50°C
—
—
20
5
Vcc=3V, VLCD=5.5V,
VDH=5.0V, CR
Oscillation;
fosc=250kHz(240line),
Ta=25°C,
RAMdata:0000h,
REV=”0”, SAP=”001”,
VRN4-0=”0”, PKP5200=”0”, PRP12-00=”0”,
VRN4-0=VRP4-0=”0”
—
500
650
5,6
T.B.D
Current consumption
during standby mode
(VCC – GND)
IST
Liquid Crystal Power
Current
ILCD
2
µA
µA
(DDVDH-GND)
PKP52-00=”0”, PRP1200=”0”
Liquid Crystal Drive
Voltage(DDVDH-GND)
VLCD
V

4.5
—
5.5

Output Voltage
deviation
∠Vo
mV


5

7
mV



35
8
Variation of average
output voltage
Rev.0.12, May 09 2003, page 141 of 156
HD66789
Preliminary
AC Characteristics
(VCC = 1.7 to 3.7 V, Ta = –40 to +85°C Note 1)
Clock Characteristics (VCC = 1.8 to 3.7 V)
Item
Symbol
Unit
Test Condition
Min
Typ
Max
Notes
External clock
frequency
fcp
kHz
VCC = 1.8 to 3.3 V
100
270
600
9
External clock duty
ratio
External clock rise time
External clock fall time
R-C oscillation clock
T.B.D.
Duty
%
VCC = 1.8 to 3.3 V
45
50
55
9
trcp
µs
VCC = 1.8 to 3.3 V
—
—
0.2
9
tfcp
µs
VCC = 1.8 to 3.3 V
—
—
0.2
9
fOSC
kHz
Rf = TBD VCC = 3 V
244
305
366
10
80-system Bus Interface Timing Characteristics
Normal Write Mode (HWM=0) (Vcc = 1.8 to 2.4 V)
Item
Symbol
Unit
Test Condition
Min
Typ
Max
Write
tCYCW
ns
Figure 2
600
—
—
Read
tCYCR
ns
Figure 2
800
—
—
Write low-level pulse width
PWLW
ns
Figure 2
90
—
—
Read low-level pulse width
PWLR
ns
Figure 2
350
—
—
Write high-level pulse width
PWHW
ns
Figure 2
300
—
—
Read high-level pulse width
PWHR
ns
Figure 2
400
—
—
Write/Read rise/fall time
tWRr, WRf
ns
Figure 2
Bus cycle time
T.B.D.
Setup time Write (RS to CS*,WR*)
—
—
25
0
—
—
10
—
—
tAS
ns
Figure 2
tAH
ns
Figure 2
5
—
—
tVS
ns
Figure 2
60
—
—
tVH
ns
Figure 2
15
—
—
Write data set up time
tDSW
ns
Figure 2
60
—
—
Write data hold time
tH
ns
Figure 2
15
—
—
Read data delay time
tDDR
ns
Figure 2
—
—
200
Read data hold time
tDHR
ns
Figure 2
5
—
—
Read (RS to CS*, RD*)
Address hold time
VLD setup time
VLD hold time
Rev.0.12, May 09 2003, page 142 of 156
HD66789
Preliminary
High-Speed Write Mode (HWM=1) (Vcc = 1.8 to 2.4 V)
Item
Write
Read
Write low-level pulse width
Read low-level pulse width
Write high-level pulse width
Read high-level pulse width
Write/Read rise/fall time
Write (RS to CS*, WR*)
Set up time
Read (RS to CS*, RD*)
Address hold time
VLD setup time
VLD hold time
Write data set up time
Write data hold time
Read data delay time
Read data hold time
Symbol
Unit
Test Condition
Min
tCYCW
tCYCR
PWLW
PWLR
PWHW
PWHR
tWRr, WRf
ns
ns
ns
ns
ns
ns
ns
Figure 2
Figure 2
Figure 2
Figure 2
Figure 2
Figure 2
Figure 2
tAS
ns
Figure 2
tAH
tVS
tVH
tDSW
tH
tDDR
tDHR
ns
ns
ns
ns
ns
ns
ns
Figure 2
Figure 2
Figure 2
Figure 2
Figure 2
Figure 2
Figure 2
200
800
90
350
90
400
—
0
10
5
60
15
60
15
—
5
Bus cycle time
T.B.D.
Typ
Max
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
25
—
—
—
—
—
—
—
200
—
Normal Write Mode (HWM=0) : Vcc = 2.4 to 3.7 V
Item
Symbol
Unit
Test Condition
Min
Typ
Max
Write
tCYCW
ns
Figure 2
250
—
—
Read
tCYCR
ns
Figure 2
500
—
—
Write low-level pulse width
PWLW
ns
Figure 2
40
—
—
Read low-level pulse width
PWLR
ns
Figure 2
250
—
—
Write high-level pulse width
PWHW
ns
Figure 2
70
—
—
Bus cycle time
T.B.D.
Read high-level pulse width
PWHR
ns
Figure 2
200
—
—
tWRr, WRf
ns
Figure 2
—
—
25
tAS
ns
Figure 2
0
—
—
10
—
—
Address hold time
tAH
ns
Figure 2
2
—
—
VLD set up time
tVS
ns
Figure 2
25
—
—
VLD hold time
tVH
ns
Figure 2
2
—
—
tDSW
ns
Figure 2
25
—
—
Write/Read rise/fall time
Set up time
Write (RS to CS*, WR*)
Read (RS to CS*, WR*)
Write data setup time
Write data hold time
tH
ns
Figure 2
2
—
—
Read data delay time
tDDR
ns
Figure 2
—
—
200
Read data hold time
tDHR
ns
Figure 2
5
—
—
Rev.0.12, May 09 2003, page 143 of 156
HD66789
Preliminary
High-Speed Write Mode (HWM=1) : Vcc = 2.4 to 3.7 V
Item
Bus cycle time
Symbol
Write
tCYCW
Read
tCYCR
Unit
Test Condition
ns
Figure 2
Min
Typ
Max
100
—
—
500
—
—
Write low-level pulse width
PWLw
ns
Figure 2
40
—
—
Read low-level pulse width
PWLR
ns
Figure 2
250
—
—
Write high -level pulse width
PWHW
ns
Figure 2
40
—
—
Read high -level pulse width
PWHR
ns
Figure 2
200
—
—
tWRr, WRf
ns
Figure 2
—
—
—
0
—
25
t WRr, WRf
ns
Figure 2
10
—
—
Write/Read rise/fall time
Set up time
T.B.D.
Write (RS to CS*,
WR*)
Read (RS to CS*, RD*)
Address hold time
tAH
ns
Figure 2
2
—
—
VLD set-up time
tVS
ns
Figure 2
25
—
—
VLD hold time
tVH
ns
Figure 2
2
—
—
tDSW
ns
Figure 2
25
—
—
Write data hold time
tH
ns
Figure 2
2
—
—
Read data delay time
tDDR
ns
Figure 2
—
—
200
Read data hold time
tDHR
ns
Figure 2
5
—
—
Write data set up time
Rev.0.12, May 09 2003, page 144 of 156
HD66789
Preliminary
Clock Synchronized Serial Interface Timing Characteristics
Vcc = 1.8 to 2.4 V
Item
Symbol Unit
Write
tSCYC
(received)
Serial clock cycle time
Read
(transmitted tSCYC
)
Write
tSCH
(received)
Serial clock high-level pulse
Read
width
(transmitted tSCH
)
Write
tSCL
(received)
Serial clock low-level pulse
Read
width
(transmitted
tSCL
)
Serial clock rise/fall time
tscr, tscf
Chip select set up time
tCSU
Chip select hold time
tCH
Serial input data set up time
tSISU
Serial input data hold time
tSIH
Serial input data delay time
tSOD
Serial input data hold time
tSOH
Test Condition
Min
Typ
Max
us
Figure 3
0.1
—
20
us
Figure 3
0.5
—
20
ns
Figure 3
40
—
—
T.B.D.
Figure 3
40
—
—
ns
Figure 3
230
—
—
ns
ns
ns
ns
ns
ns
ns
Figure 3
Figure 3
Figure 3
Figure 3
Figure 3
Figure 3
Figure 3
—
20
60
30
30
—
5
—
—
—
—
—
—
—
20
—
—
—
—
200
—
Symbol
Unit
Test
Condition
Min
Typ
Max
tSCYC
us
Figure 3
0.1
—
20
tSCYC
us
Figure 3
0.35
—
20
tSCH
ns
Figure 3
40
—
—
T.B.D.
ns
Figure 3
230
—
—
ns
Vcc = 2.4 to 3.3 V
Item
Serial clock cycle time
Serial clock high-level pulse
width
Serial clock low-level pulse
width
Write
(receive))
Read
(send)
Write
(receive)
Read
(send)
Write
(receive)
Read
(send)
Serial clock rise/fall time
Chip select set up time
Chip select hold time
Serial input data set up time
Serial input data hold time
Serial output data delay time
Serial output data hold time
Rev.0.12, May 09 2003, page 145 of 156
tSCH
ns
Figure 3
150
—
—
tSCL
ns
Figure 3
40
—
—
tSCL
ns
Figure 3
150
—
—
tscr, scf
tCSU
tCH
tSISU
tSIH
tSOD
tSOH
ns
ns
ns
ns
ns
ns
ns
Figure 3
Figure 3
Figure 3
Figure 3
Figure 3
Figure 3
Figure 3
—
20
60
30
30
—
5
—
—
20
—
—
—
—
130
—
—
—
—
—
—
HD66789
Preliminary
Reset Timing Characteristics (VCC = 1.8 to 3.7 V)
Item
Reset low-level width
Reset rise time
Symbol
Unit
Test
Condition
Figure 4
Figure 4
Min
Typ
T.B.D.
tRES
trRES
Rev.0.12, May 09 2003, page 146 of 156
ms
us
1
—
—
—
Max
—
10
HD66789
Preliminary
RGB interface timing characteristics
18/16 bit RGB interface (HWM =1), Vcc = 1.8V to 2.4V
Item
Symbol
Unit
Test
Condition
min.
typ.
max.
VSYNC/HSYNC Set up time
tSYNCS
clock
Figure 5
0

1
ENABLE Set up time
tENS
ns
Figure 5
20


ENABLE Hold time
tENH
ns
Figure 5
80


VLD Set up time
tVLS
ns
Figure 5
20


VLD Hold time
tVLH
ns
Figure 5
80


DOTCLK “Low” Level pulse
width
PWDL
ns
Figure 5
90


DOTCLK “High” Level pulse
width
PWDH
ns
Figure 5
90


DOTCLK cycle time
tCYCD
ns
Figure 5
200


Data Set up time
tPDS
ns
Figure 5
20


Data Hole time
tPDH
ns
Figure 5
80


DOTCLK, VSYNC, HSYNC
rising and falling time
trgbr, trgbf
ns
Figure 5


25
T.B.D.
18/16 bit RGB interface (HWM = 1), Vcc = 2.4V to 3.7 V
Item
Symbol
Unit
Test
Condition
min.
typ.
max.
VSYNC/HSYNC Set up time
tSYNCS
clock
Figure 5
0

1
ENABLE Set up time
tENS
ns
Figure 5
10


ENABLE Hold time
tENH
ns
Figure 5
20


VLD Set up time
tVLS
ns
Figure 5
10


tVLH
ns
Figure 5
40


DOTCLK “Low” Level pulse
width
PWDL
ns
Figure 5
40


DOTCLK “High” Level pulse
width
PWDH
ns
Figure 5
40


DOTCLK cycle time
tCYCD
ns
Figure 5
100


Data Set up time
tPDS
ns
Figure 5
10


Data Hole time
tPDH
ns
Figure 5
40


DOTCLK, VSYNC, HSYNC
rising and falling time
trgbr, trgbf
ns
Figure 5


25
VLD Hold time
T.B.D.
Rev.0.12, May 09 2003, page 147 of 156
HD66789
Preliminary
6 bit RGB interface (HWM = 1), Vcc = 1.8V to 2.4 V
Item
Symbol
Unit
Test
Condition
min.
typ.
max.
VSYNC/HSYNC Set up time
tSYNCS
clock
Figure 5
0

1
ENABLE Set up time
tENS
ns
Figure 5
20


ENABLE Hold time
tENH
ns
Figure 5
50


VLD Set up time
tVLS
ns
Figure 5
20


tVLH
ns
Figure 5
65


PWDL
ns
Figure 5
50


DOTCLK “High” Level pulse
width
PWDH
ns
Figure 5
50


DOTCLK cycle time
tCYCD
ns
Figure 5
120


Data Set up time
tPDS
ns
Figure 5
20


Data Hold time
tPDH
ns
Figure 5
65


DOTCLK, VSYNC, HSYNC
rising and falling time
trgbr, trgbf
ns
Figure 5


25
VLD Hold time
DOTCLK “Low” Level pulse
width
T.B.D.
6 bit RGB interface (HWM = 1), Vcc = 2.4V to 3.3 V
Item
Symbol
Unit
Test
Condition
min.
typ.
max.
VSYNC/HSYNC Set up time
tSYNCS
clock
Figure 5
0

1
ENABLE Set up time
tENS
ns
Figure 5
10


ENABLE Hold time
tENH
ns
Figure 5
20


VLD Set up time
tVLS
ns
Figure 5
10


Vcc=2,4 to2,7V
tVLH
ns
Figure 5
40


Vcc=2,7 to
3,7V
tVLH
ns
Figure 5
30


PWDL
ns
Figure 5
30


PWDH
ns
Figure 5
30


DOTCLK cycle time
tCYCD
ns
Figure 5
70


Data Set up time
tPDS
ns
Figure 5
10


Vcc=2,4 to
2,7V
tPDH
ns
Figure 5
40


Vcc=2,7 to
3,7V
tPDH
ns
Figure 5
30


trgbr, trgbf
ns
Figure 5


25
VLD Hold time
DOTCLK “Low” Level pulse
width
DOTCLK “High” Level pulse
width
Data Hole time
DOTCLK, VSYNC, HSYNC
rising and falling time
T.B.D.
Rev.0.12, May 09 2003, page 148 of 156
HD66789
Preliminary
Liquid crystal driver output characteristics
Item
Symbol
Unit
Driver output
delay time
tdd
µs
Test conditions
Vcc=3V, VLCD=5.5V, VDH=5.0V,
CR oscillation ;fosc=270kHz(240 lines),
Ta=25℃、REV="0", SAP="001",
VRN4-0="0",VRP4-0="0"
PKP52-00="0",PRP12-00="0"
PKP52-00="0",PRP12-00="0"
All pins changes at the same time from same
grayscale. The time till output level reaches
―35mV when VCOM polarity changes.
Load resistance R=10kΩ、
Load capacity C=20pF
min.
typ.
max.
Note

40

(11)
T.B.D.
Electrical Characteristics Notes
1.
For bare die and wafer products, specified up to 85°C.
2.
The following three circuits are I pin, I/O pin, O pin configurations.
Pins: RESET*, CS*, E/WR, RW/RD, RS,
OSC1, OPOFF, IM2-1, IM0/ID,TEST
Vcc
Vcc
PMOS
PMOS
NMOS
NMOS
GND
GND
T.B.D.
Pins: DB15 -DB2,
DB1/SD0, DB0/SD1
Vcc
PMOS
(Input circuit)
NMOS
Vcc
(Tri-state output circuit)
Output enable
PMOS
Output data
NMOS
GND
3.
The TEST pin must be grounded and the IM2/1 and IM0/ID pins must be grounded or connected to
Vcc.
4.
This applies to the resistor value (RSEG) between VSH, GND pins and segment signal pins.
T.B.D.
Rev.0.12, May 09 2003, page 149 of 156
HD66789
Preliminary
5.
This excludes the current flowing through output drive MOSs. This excludes the current flowing
through the input/output units. The input level must be fixed high or low because through current
increases if the CMOS input is left floating. Even if the CS pin is low or high when an access with the
interface pin is not performed, current consumption does not change.
6.
The following figure shows the relationship between the operation frequency and current consumption.
Vcc = 3V
Vcc = 3V, DDVDH = 5,5V
T.B.D.
ILCD (µF)
lop (µF)
440
600
typ.
400
420
typ.
(
400
380
360
340
200
320
0
100 200
0
300
400
500
600
4.0
R-C, oscillation frequencies: fosc (kHz)
4.5
5.0
VDH (V)
7.
This is a voltage difference for the neighboring outputs under the same display condition. The output
voltage deviation is a reference value.
8.
The fluctuation of average output voltage indicates the difference of average output voltage between
chips. The average output voltage is an average voltage within a chip under the same display
condition.
9.
Applies to the external clock input (figure ).
T.B.D.
T.B.D.
Tl
Th
2kΩ
Oscillator
OSC1
Open
0.7Vcc
0.5Vcc
0.3Vcc
Duty =
Th
Th + Tl x 100%
OSC2
trcp
t fcp
10. Applies to the internal oscillator operations using external oscillation resistor Rf (figure and table).
Rev.0.12, May 09 2003, page 150 of 156
HD66789
Preliminary
T.B.D.
OSC1
Rf
The oscillation frequency may vary
depending on the capacitors for OSC1, OSC2 pins.
Place OSC1 and OSC2 close to each other.
OSC2
External Resistance Value and R-C Oscillation Frequency (Referential Data)
External
Resistance
R-C Oscillation Frequency: fosc
Vcc = 1.8
V
Vcc = 2 V
Vcc = 2.4 V
Vcc = 3 V
Vcc = 3.3 V
110 kΩ
299
333
372
401
411
150 kΩ
234
258
284
305
311
180 kΩ
202
222
243
258
263
186
203
222
235
240
160
173
188
198
202
145
157
169
177
181
132
143
153
161
163
390 kΩ
106
113
121
126
128
430 kΩ
97
104
110
115
116
(Rf)
T.B.D.
200 kΩ
240 kΩ
270 kΩ
300 kΩ
LCD driver output delay time
tDD (µS)
11. Applies to the internal oscillator operations using external oscillation resistor Rf (figure and table).
Reference data
Vcc =3V, VLCD = 5.5V, VDH = 5.0V,
R-C Oscillation; fosc = 270kHz (240line),
Ta = 25 Centigrade, REV = "0", SAP ="001",
VRN4-0 = "0", VRP4-0 = "0",
PKP52-00 = "0", PRP12-00 ="0",
PKN52-00 = "0", PRN12-00 ="0",
All pins chnge at the same time from same grayscale.
The time till output level reaches +/-35mV when VCOM polarity changes.
Load resistance R = 10kΩ/pin
70
60
50
40
30
20
10
T.B.D.
10
20
30
Load Capacity C(pF)
Rev.0.12, May 09 2003, page 151 of 156
HD66789
Preliminary
Load circuits for measuring AC characteristics
T.B.D.
AC characteristic measuring load circuit
LCD driver output characteristic measuring load circuit
Data bus : DB17-DB0, PD17-0
Test Point
LCD output : S1- S528
Test Point
Lord
Resistance R
10kΩ
50pF
Lord
Capacity C
20pF
80-system Bus Operation
RS
VIH
VIH
VIL
VIL
tAS
tAH
VIH
CS*
T.B.D.
VIL
Note 1)
PWHW, PWHR
PWLW, PWLR
WR*
RD*
VIH
VIL
VIL
tWRr
tCYCW, tCYCR
tDSW
VIH
VIL
DB0
to DB15
Wrire data
tDDR
DB0
to DB15
VIH
tWRf
tHWR
VIH
VIL
tDHR
VOH1
VOL1 Read data
VOH1
VOL1
Note 1) PWLW and PWLR is specified in the overlapped period when CS* is low and WR* or RD* is low.
Note 2) Parallel data transfer is enabled on the DB15-8 pins when the 8-bit bus interface is used. Fix the
DB7-0 pins to Vcc or GND.
Rev.0.12, May 09 2003, page 152 of 156
HD66789
Preliminary
Clock Synchronized Serial Interface Operation
Start: S
End : P
CS*
VIH
VIL
VIL
tCSU
tSCYC
tscf
tscr
tSCL
tSCH
tCH
T.B.D.
SCL
VIH
VIH
VIH VIH
VIL
VIL
VIL
VIL
tSIH
tSISU
SDI
VIH
VIL
VIH
VIL
Input data
Input data
tSOD
SDO
tSOH
VOH1
VOL1
Output data
Output data
VOH1
VOL1
RESET Operation
T.B.D.
trRE
S
tRES
RESET *
VIL
Rev.0.12, May 09 2003, page 153 of 156
VIL
VIL
HD66789
Preliminary
RGB I/F Operation
VSYNC
HSYNC
trgbf
trgbf
tSYNCS
VIH
VIH
VIL
VIL
tENS
ENABLE
tENH
VIH
VIH
VIH
VIH
VIL
VIL
VIL
VIL
T.B.D.
tVLS
VLD
VIH
VIH
VIL
VIL
PWDL
VIH
VIL
VIL
PWDH
VIH
VIH
VIL
VIH
VIH
VIL
VIL
VIH
VIL
VIL
tPDS
PD17-0
VIH
trgbf
trgbf
DOTCLK
tVLH
tPDH
Write Data
VIH
VIH
VIL
VIL
Liquid crystal Driver Output
VCOM
T.B.D.
tPDS
S1-528
Ce rta in g ray s ca le v o l t a g e
+/-35mV
Certain grayscale voltage
+/-35mV
Rev.0.12, May 09 2003, page 154 of 156
HD66789
Preliminary
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Keep safety first in your circuit designs!
1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with
them. Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of
nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corporation product best suited to the customer's application; they
do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corporation or a third party.
2. Renesas Technology Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts,
programs, algorithms, or circuit application examples contained in these materials.
3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these
materials, and are subject to change by Renesas Technology Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers
contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor for the latest product information before purchasing a product listed
herein.
The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corporation by various means, including the Renesas Technology Corporation Semiconductor home page
(http://www.renesas.com).
4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information
as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corporation assumes no responsibility for any damage,
liability or other loss resulting from the information contained herein.
5. Renesas Technology Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially
at stake. Please contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor when considering the use of a product contained
herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.
6. The prior written approval of Renesas Technology Corporation is necessary to reprint or reproduce in whole or in part these materials.
7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be
imported into a country other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.
8. Please contact Renesas Technology Corporation for further details on these materials or the products contained therein.
http://www.renesas.com
Copyright © 2003. Renesas Technology Corporation, All rights reserved. Printed in Japan.
Colophon 0.0
Rev.0.12, May 09 2003, page 155 of 156
HD66789
Preliminary
Revision Record
Rev.
Date
Contents of Modification
0.1
2003.05.08
First issue
Rev.0.12, May 09 2003, page 156 of 156
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