HN58X2402SFPIAG HN58X2404SFPIAG Two-wire serial interface 2k EEPROM (256-word × 8-bit) 4k EEPROM (512-word × 8-bit) REJ03C0133-0400 Rev.4.00 Jul.13.2005 Description HN58X24xxSFPIAG series are two-wire serial interface EEPROM (Electrically Erasable and Programmable ROM). They realize high speed, low power consumption and a high level of reliability by employing advanced MNOS memory technology and CMOS process and low voltage circuitry technology. They also have a 8-byte page programming function to make their write operation faster. Features • • • • • • • • • • • Single supply: 1.8 V to 5.5 V Two-wire serial interface (I2CTM serial bus*1) Clock frequency: 400 kHz Power dissipation: Standby: 3 µA (max) Active (Read): 1 mA (max) Active (Write): 3 mA (max) Automatic page write: 8-byte/page Write cycle time: 10 ms (2.7 V to 5.5 V)/15ms (1.8 V to 2.7 V) Endurance: 105 Cycles (Page write mode) Data retention: 10 Years Small size packages: SOP 8-pin Shipping tape and reel: 2,500 IC/reel Lead free products. Note: 1. I2C is a trademark of Philips Corporation. Ordering Information Type No. HN58X2402SFPIAGE HN58X2404SFPIAGE Internal organization Operating voltage Frequency Package 2k bit (256 × 8-bit) 1.8 V to 5.5 V 400 kHz 150 mil 8-pin plastic SOP PRSP0008DF-B (FP-8DBV) 4k bit (512 × 8-bit) Lead free Rev.4.00, Jul.13.2005, page 1 of 16 HN58X2402SFPIAG/HN58X2404SFPIAG Pin Arrangement 8-pin SOP A0 1 8 VCC A1 2 7 WP A2 3 6 SCL VSS 4 5 SDA (Top view) Pin Description Pin name Function A0 to A2 SCL SDA WP VCC VSS Device address Serial clock input Serial data input/output Write protect Power supply Ground Block Diagram High voltage generator A0, A1, A2 SCL Control logic X decoder WP Address generator VSS Memory array Y decoder VCC Y-select & Sense amp. SDA Serial-parallel converter Absolute Maximum Ratings Parameter Symbol Supply voltage relative to VSS VCC Input voltage relative to VSS Vin 1 Operating temperature range* Topr Storage temperature range Tstg Notes: 1. Including electrical characteristics and data retention. 2. Vin (min): −3.0 V for pulse width ≤ 50 ns. 3. Should not exceed VCC + 1.0 V. Rev.4.00, Jul.13.2005, page 2 of 16 Value −0.6 to +7.0 −0.5*2 to +7.0*3 −40 to +85 −65 to +125 Unit V V °C °C HN58X2402SFPIAG/HN58X2404SFPIAG DC Operating Conditions Parameter Symbol VCC VSS Input high voltage VIH Input low voltage VIL Operating temperature Topr Note: 1. VIL (min): −1.0 V for pulse width ≤ 50 ns. Min 1.8 0 VCC × 0.7 −0.3*1 −40 Supply voltage Typ 0 Max 5.5 0 VCC + 1.0 VCC × 0.3 +85 Unit V V V V °C DC Characteristics (Ta = −40 to +85°C, VCC = 1.8 V to 5.5 V) Parameter Input leakage current Output leakage current Standby VCC current Read VCC current Write VCC current Output low voltage Symbol ILI ILO ISB ICC1 ICC2 VOL2 Min Typ 1.0 Max 2.0 20 2.0 3.0 1.0 3.0 0.4 Unit µA µA µA µA mA mA V VOL1 0.2 V Test conditions VCC = 5.5 V, Vin = 0 to 5.5 V (SCL, SDA) VCC = 5.5 V, Vin = 0 to 5.5 V (A0 to A2, WP) VCC = 5.5 V, Vout = 0 to 5.5 V Vin = VSS or VCC VCC = 5.5 V, Read at 400 kHz VCC = 5.5 V, Write at 400 kHz VCC = 4.5 to 5.5 V, IOL = 1.6 mA VCC = 2.7 to 4.5 V, IOL = 0.8 mA VCC = 1.8 to 2.7 V, IOL = 0.4 mA VCC = 1.8 to 2.7 V, IOL = 0.2 mA Capacitance (Ta = +25°C, f = 1 MHz) Parameter Symbol Input capacitance (A0 to A2, SCL, WP) Cin*1 Output capacitance (SDA) CI/O*1 Note: 1. This parameter is sampled and not 100% tested. Rev.4.00, Jul.13.2005, page 3 of 16 Min Typ Max Unit 6.0 6.0 pF pF Test conditions Vin = 0 V Vout = 0 V HN58X2402SFPIAG/HN58X2404SFPIAG AC Characteristics (Ta = −40 to +85°C, VCC = 1.8 to 5.5 V) Test Conditions • Input pules levels: VIL = 0.2 × VCC VIH = 0.8 × VCC • Input rise and fall time: ≤ 20 ns • Input and output timing reference levels: 0.5 × VCC • Output load: TTL Gate + 100 pF Max Unit Clock frequency fSCL 400 Clock pulse width low tLOW 1200 Clock pulse width high tHIGH 600 Noise suppression time tI 50 Access time tAA 100 900 Bus free time for next mode tBUF 1200 Start hold time tHD.STA 600 Start setup time tSU.STA 600 Data in hold time tHD.DAT 0 Data in setup time tSU.DAT 100 Input rise time tR 300 Input fall time tF 300 Stop setup time tSU.STO 600 Data out hold time tDH 50 Write protect hold time tHD.WP 1200 Write protect setup time tSU.WP 0 Write cycle time VCC = 2.7 V to 5.5 V tWC 10 VCC = 1.8 V to 2.7 V tWC 15 Notes: 1. This parameter is sampled and not 100% tested. 2. tWC is the time from a stop condition to the end of internally controlled write cycle. Parameter kHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms Rev.4.00, Jul.13.2005, page 4 of 16 Symbol Min Typ Notes 1 1 1 2 2 HN58X2402SFPIAG/HN58X2404SFPIAG Timing Waveforms Bus Timing tF tHIGH 1/fSCL tLOW tR SCL tSU.STA tHD.DAT tSU.DAT tHD.STA tSU.STO SDA (in) tBUF tAA tDH SDA (out) tSU.WP tHD.WP WP Write Cycle Timing Stop condition Start condition SCL SDA D0 in Write data (Address (n)) Rev.4.00, Jul.13.2005, page 5 of 16 ACK tWC (Internally controlled) HN58X2402SFPIAG/HN58X2404SFPIAG Pin Function Serial Clock (SCL) The SCL pin is used to control serial input/output data timing. The SCL input is used to positive edge clock data into EEPROM device and negative edge clock data out of each device. Maximum clock rate is 400 kHz. Serial Input/Output data (SDA) The SDA pin is bidirectional for serial data transfer. The SDA pin needs to be pulled up by resistor as that pin is opendrain driven structure. Use proper resistor value for your system by considering VOL, IOL and the SDA pin capacitance. Except for a start condition and a stop condition which will be discussed later, the SDA transition needs to be completed during the SCL low period. Data Validity (SDA data change timing waveform) SCL SDA Data change Note: Data change High-to-low and low-to-high change of SDA should be done during the SCL low period. Rev.4.00, Jul.13.2005, page 6 of 16 HN58X2402SFPIAG/HN58X2404SFPIAG Device Address (A0, A1, A2) UP to eight devices for 2k, four devices for 4k, can be addressed on the same bus by setting the levels on these pins to different combinations. The levels on these pins are compared with the device address code which are input through the SDA pin. The device is selected if the compare is successfully done. These pins are internally pulled-down to VSS. The device read these pins as Low if unconnected. As for 4k, it is unnecessary for the A0 pin to be connected because the corresponding device address code is used as memory address a8. Pin Connections for A0 to A2 Memory size Max connect number Pin connection A2 A1 A0 Notes 2k bit 8 VCC/VSS*1 VCC/VSS VCC/VSS 4k bit 4 VCC/VSS VCC/VSS ×*2 Use A0 for memory address a8 Notes: 1. “VCC/VSS” means that the device address pins are connected to VCC or VSS. These pins are VSS if unconnected. 2. × = Don’t care (Open is also approval.) Write Protect (WP) When the Write Protect pin (WP) is high, the write protections feature is enabled and operates as shown in the following table. When the WP is low, write operations for all memory array are allowed. The read operation is always activated irrespective of the WP pin status. The WP pin is internally pull-down to VSS. Write operations for all memory array are allowed if unconnected. Write Protect Area WP pin status VIH VIL Rev.4.00, Jul.13.2005, page 7 of 16 Write protect area 2k bit 4k bit Entire (2k bit) Entire (4k bit) Normal read/write operation HN58X2402SFPIAG/HN58X2404SFPIAG Functional Description Start Condition A high-to-low transition of the SDA with the SCL high is needed in order to start read, write operation. (See start condition and stop condition) Stop Condition A low-to-high transition of the SDA with the SCL high is a stop condition. The stand-by operation starts after a read sequence by a stop condition. In the case of write operation, a stop condition terminates the write data inputs and place the device in a internally-timed write cycle to the memories. After the internally-timed write cycle which is specified as tWC, the device enters a standby mode. (See write cycle timing) Start Condition and Stop Condition SCL SDA (in) Start condition Rev.4.00, Jul.13.2005, page 8 of 16 Stop condition HN58X2402SFPIAG/HN58X2404SFPIAG Acknowledge All addresses and data words are serially transmitted to and from in 8-bit words. The receiver sends a zero to acknowledge that it has received each word. This happens during ninth clock cycle. The transmitter keeps bus open to receive acknowledgment from the receiver at the ninth clock. In the write operation, EEPROM sends a zero to acknowledge after receiving every 8-bit words. In the read operation, EEPROM sends a zero to acknowledge after receiving the device address word. After sending read data, the EEPROM waits acknowledgment by keeping bus open. If the EEPROM receives zero as an acknowledge, it sends read data of next address. If the EEPROM receives acknowledgment "1" (no acknowledgment) and a following stop condition, it stops the read operation and enters a stand-by mode. If the EEPROM receives neither acknowledgment "0" nor a stop condition, the EEPROM keeps bus open without sending read data. Acknowledge Timing Waveform SCL SDA IN SDA OUT Rev.4.00, Jul.13.2005, page 9 of 16 1 2 8 9 Acknowledge out HN58X2402SFPIAG/HN58X2404SFPIAG Device Addressing The EEPROM device requires an 8-bit device address word following a start condition to enable the chip for a read or a write operation. The device address word consists of 4-bit device code, 3-bit device address code and 1-bit read/write(R/W) code. The most significant 4-bit of the device address word are used to distinguish device type and this EEPROM uses “1010” fixed code. The device address word is followed by the 3-bit device address code in the order of A2, A1, A0. The device address code selects one device out of all devices which are connected to the bus. This means that the device is selected if the inputted 3-bit device address code is equal to the corresponding hard-wired A2-A0 pin status. As for the 4kbit EEPROMs, some bits of their device address code may be used as the memory address bits. For example, A0 is used as a8 of memory address for the 4kbit. The eighth bit of the device address word is the read/write(R/W) bit. A write operation is initiated if this bit is low and a read operation is initiated if this bit is high. Upon a compare of the device address word, the EEPROM enters the read or write operation after outputting the zero as an acknowledge. The EEPROM turns to a stand-by state if the device code is not “1010” or device address code doesn’t coincide with status of the correspond hard-wired device address pins A0 to A2. Device Address Word Device address word (8-bit) Device code (fixed) Device address code*1 2k 1 0 1 0 A2 A1 A0 4k 1 0 1 0 A2 A1 a8 Notes: 1. A2 to A0 are device address and a8 are memory address. 2. R/W=“1” is read and R/W = “0” is write. Rev.4.00, Jul.13.2005, page 10 of 16 R/W code*2 R/W R/W HN58X2402SFPIAG/HN58X2404SFPIAG Write Operations Byte Write: A write operation requires an 8-bit device address word with R/W = “0”. Then the EEPROM sends acknowledgment "0" at the ninth clock cycle. After these, EEPROMs receive 8-bit memory address word. Upon receipt of this memory address, the EEPROM outputs acknowledgment "0" and receives a following 8-bit write data. After receipt of write data, the EEPROM outputs acknowledgment "0". If the EEPROM receives a stop condition, the EEPROM enters an internally-timed write cycle and terminates receipt of SCL, SDA inputs until completion of the write cycle. The EEPROM returns to a standby mode after completion of the write cycle. 2k, 4k 1010 Memory address (n) Write data (n) D7 D6 D5 D4 D3 D2 D1 D0 Device address a7 a6 a5 a4 a3 a2 a1 a0 Byte Write Operation W ACK R/W Start ACK ACK Stop Page Write: The EEPROM is capable of the page write operation which allows any number of bytes up to 8 bytes to be written in a single write cycle. The page write is the same sequence as the byte write except for inputting the more write data. The page write is initiated by a start condition, device address word, memory address(n) and write data(Dn) with every ninth bit acknowledgment. The EEPROM enters the page write operation if the EEPROM receives more write data(Dn+1) instead of receiving a stop condition. The a0 to a2 address bits are automatically incremented upon receiving write data(Dn+1). The EEPROM can continue to receive write data up to 8 bytes. If the a0 to a2 address bits reaches the last address of the page, the a0 to a2 address bits will roll over to the first address of the same page and previous write data will be overwritten. Upon receiving a stop condition, the EEPROM stops receiving write data and enters internally-timed write cycle. 1010 Start Rev.4.00, Jul.13.2005, page 11 of 16 W Write data (n) ACK R/W ACK ACK Write data (n+m) D5 D4 D3 D2 D1 D0 2k, 4k Memory address (n) D7 D6 D5 D4 D3 D2 D1 D0 Device address a7 a6 a5 a4 a3 a2 a1 a0 Page Write Operation Stop ACK HN58X2402SFPIAG/HN58X2404SFPIAG Acknowledge Polling: Acknowledge polling feature is used to show if the EEPROM is in a internally-timed write cycle or not. This feature is initiated by the stop condition after inputting write data. This requires the 8-bit device address word following the start condition during a internally-timed write cycle. Acknowledge polling will operate when the R/W code = “0”. Acknowledgment “1” (no acknowledgment) shows the EEPROM is in a internally-timed write cycle and acknowledgment “0” shows that the internally-timed write cycle has completed. See Write Cycle Polling using ACK. Write Cycle Polling using ACK Send write command Send stop condition to initiate write cycle Send start condition Send device address word with R/W = 0 ACK returned No Yes Next operation is addressing the memory No Yes Proceed write operation Send memory address Send start condition Proceed random address read operation Send stop condition Rev.4.00, Jul.13.2005, page 12 of 16 Send stop condition HN58X2402SFPIAG/HN58X2404SFPIAG Read Operation There are three read operations: current address read, random read, and sequential read. Read operations are initiated the same way as write operations with the exception of R/W = “1”. Current Address Read: The internal address counter maintains the last address accessed during the last read or write operation, with incremented by one. Current address read accesses the address kept by the internal address counter. After receiving a start condition and the device address word(R/W is “1”), the EEPROM outputs the 8-bit current address data from the most significant bit following acknowledgment “0”. If the EEPROM receives acknowledgment “1” (no acknowledgment) and a following stop condition, the EEPROM stops the read operation and is turned to a standby state. In case the EEPROM has accessed the last address of the last page at previous read operation, the current address will roll over and returns to zero address. In case the EEPROM has accessed the last address of the page at previous write operation, the current address will roll over within page addressing and returns to the first address in the same page. The current address is valid while power is on. The current address after power on will be indefinite. The random read operation described below is necessary to define the memory address. Current Address Read Operation Device address 1010 R Start Note: 1. Don‘t care bit for 4k. Rev.4.00, Jul.13.2005, page 13 of 16 D7 D6 D5 D4 D3 D2 D1 D0 *1 2k, 4k Read data (n+1) ACK R/W No ACK Stop HN58X2402SFPIAG/HN58X2404SFPIAG Random Read: This is a read operation with defined read address. A random read requires a dummy write to set read address. The EEPROM receives a start condition, device address word(R/W=0) and memory address sequentially. The EEPROM outputs acknowledgment “0” after receiving memory address then enters a current address read with receiving a start condition. The EEPROM outputs the read data of the address which was defined in the dummy write operation. After receiving acknowledgment “1”(no acknowledgment) and a following stop condition, the EEPROM stops the random read operation and returns to a standby state. Random Read Operation 1010 @@@ Device address a7 a6 a5 a4 a3 a2 a1 a0 2k, 4k Memory address (n) W R Start ACK ACK R/W Start 1010 Read data (n) # # # Dummy write D7 D6 D5 D4 D3 D2 D1 D0 Device address ACK No ACK Stop R/W Currect address read Note: 1. 2nd device address code (#) should be same as 1st (@). Sequential Read: Sequential reads are initiated by either a current address read or a random read. If the EEPROM receives acknowledgment “0” after 8-bit read data, the read address is incremented and the next 8-bit read data are coming out. This operation can be continued as long as the EEPROM receives acknowledgment “0”. The address will roll over and returns address zero if it reaches the last address of the last page. The sequential read can be continued after roll over. The sequential read is terminated if the EEPROM receives acknowledgment “1” (no acknowledgment) and a following stop condition. Sequential Read Operation ACK R/W Rev.4.00, Jul.13.2005, page 14 of 16 ACK ACK ACK D5 D4 D3 D2 D1 D0 R Read data (n+1) Read data (n+2) Read data (n+m) D7 D6 D5 D4 D3 D2 D1 D0 Start 1010 Read data (n) D7 D6 D5 D4 D3 D2 D1 D0 2k, 4k D7 D6 D5 D4 D3 D2 D1 D0 Device address No ACK Stop HN58X2402SFPIAG/HN58X2404SFPIAG Notes Data protection at VCC On/Off When VCC is turned on or off, noise on the SCL and SDA inputs generated by external circuits (CPU, etc) may act as a trigger and turn the EEPROM to unintentional program mode. To prevent this unintentional programming, this EEPROM has a power on reset function. Be careful of the notices described below in order for the power on reset function to operate correctly. • SCL and SDA should be fixed to VCC or VSS during VCC on/off. Low to high or high to low transition during VCC on/off may cause the trigger for the unintentional programming. • VCC should be turned off after the EEPROM is placed in a standby state. • VCC should be turned on from the ground level(VSS) in order for the EEPROM not to enter the unintentional programming mode. • VCC turn on speed should be longer than 10 µs. Write/Erase Endurance and Data retention Time The endurance is 105 cycles in case of page programming and 104 cycles in case of byte programming (1% cumulative failure rate). The data retention time is more than 10 years when a device is page-programmed less than 104 cycles. Noise Suppression Time This EEPROM have a noise suppression function at SCL and SDA inputs, that cut noise of width less than 50 ns. Be careful not to allow noise of width more than 50 ns. Rev.4.00, Jul.13.2005, page 15 of 16 HN58X2402SFPIAG/HN58X2404SFPIAG Package Dimensions HN58X2402SFPIAGE / HN58X2404SFPIAGE (PRSP0008DF-B / Previous Code: FP-8DBV) JEITA Package Code P-SOP8-3.9x4.89-1.27 RENESAS Code PRSP0008DF-B *1 Previous Code FP-8DBV D 8 MASS[Typ.] 0.08g NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. F 5 *2 c E HE bp Reference Symbol Index mark Terminal cross section ( Ni/Pd/Au plating ) Dimension in Millimeters Min Nom Max D 4.89 5.15 E 3.90 A2 1 Z 4 e *3 A1 bp x 0.14 L1 0.35 0.40 0.45 0.15 0.20 0.25 6.02 6.20 b1 c A c A1 θ L y Detail F 0.254 1.73 bp 1 θ 0° HE 5.84 8° 1.27 e x 0.25 y 0.10 Z 0.69 0.406 L L Rev.4.00, Jul.13.2005, page 16 of 16 0.102 A M 1 0.60 1.06 0.889 Revision History Rev. Date 1.0 2.00 Mar. 30, 2001 Oct. 24, 2003 3.00 Dec.14.2004 Contents of Modification Page Description Initial issue Change format issued by Renesas Technology Corp. Ordering Information 2 Addition of HN58X2402SFPIAGE, HN58X2404SFPIAGE Package Dimensions FP-8DB to FP-8DB, FP-8DBV 17 2 17 4.00 Jul.13.2005 HN58X2402SFPIAG/HN58X2404SFPIAG Data Sheet 1 4 5 16 Ordering Information Deletion of HN58X2402SFPIAG, HN58X2404SFPIAG Package Dimensions Deletion of FP-8DB Ordering Information Addition of Renesas package codes AC Characteristics Addition of tHD.WP Addition of tSU.WP Timing Waveforms Addition of WP Package Dimensions Addition of Renesas package codes Changed to Renesas formats Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. 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