RENESAS HN58W241000I

HN58W241000I
Two-wire serial interface
1M EEPROM (128-kword × 8-bit)
REJ03C0138-0300
Rev.3.00
Jul.12.2005
Description
HN58W241000I is the two-wire serial interface EEPROM (Electrically Erasable and Programmable ROM). It realizes
high speed, low power consumption and a high level of reliability by employing advanced MNOS memory technology
and CMOS process and low voltage circuitry technology. It also has a 256-byte page programming function to make
it’s write operation faster.
Note: Renesas Technology’s serial EEPROM are authorized for using consumer applications such as cellular phone,
camcorders, audio equipment. Therefore, please contact Renesas Technology’s sales office before using
industrial applications such as automotive systems, embedded controllers, and meters.
Features
•
•
•
•
•
•
•
•
•
•
•
•
Single supply: 2.5 V to 3.6 V
Two-wire serial interface (I2CTM serial bus*1)
Clock frequency: 1 MHz
Power dissipation:
 Standby: 1 µA (max)
 Active (Read): 1 mA (max)
 Active (Write): 4 mA (max)
Automatic page write: 256-byte/page
Write cycle time: 5.0 ms (max)
Endurance: 105 Cycles
Data retention: 10 Years
Small size packages: SOP-8pin (200 mil-wide)
Shipping tape and reel: 1,500 IC/reel
Temperature range: −40 to +85°C
Lead free products.
Note: 1. I2C is a trademark of Philips Corporation.
Ordering Information
Type No.
HN58W241000FPIE
Rev.3.00,
Internal organization
Operating voltage
1M bit
2.5 V to 3.6 V
(131,072 × 8-bit)
Jul.12.2005,
page 1 of 18
Frequency
1 MHz
Package
200 mil 8-pin plastic SOP
PRSP0008DG-B
(FP-8DFV)
Lead free
HN58W241000I
Pin Arrangement
8-pin SOP
NC
1
8
VCC
A1
2
7
WP
A2
3
6
SCL
GND
4
5
SDA
(Top view)
Pin Description
Pin name
Function
A1, A2
SCL
SDA
WP
VCC
VSS
Device address
Serial clock input
Serial data input/output
Write protect
Power supply
Ground
NC
No connection
Block Diagram
High voltage generator
Control
logic
A1, A2
SCL
X decoder
WP
Address generator
VSS
Memory array
Y decoder
VCC
Y-select & Sense amp.
SDA
Serial-parallel converter
Absolute Maximum Ratings
Parameter
Symbol
Supply voltage relative to VSS
VCC
Input voltage relative to VSS
Vin
Operating temperature range*1
Topr
Storage temperature range
Tstg
Notes: 1. Including electrical characteristics and data retention.
2. Vin (min): −3.0 V for pulse width ≤ 50 ns.
3. Should not exceed VCC + 1.0 V.
Rev.3.00,
Jul.12.2005,
page 2 of 18
Value
−0.6 to +7.0
−0.5*2 to +7.0*3
−40 to +85
−65 to +125
Unit
V
V
°C
°C
HN58W241000I
DC Operating Conditions
Parameter
Symbol
VCC
VSS
Input high voltage
VIH
Input low voltage
VIL
Operating temperature
Topr
Notes: 1. VIL (min): −1.0 V for pulse width ≤ 50 ns.
2. VIH (max): VCC + 1.0 V for pulse width ≤ 50 ns.
Min
2.5
0
VCC × 0.7
−0.3*1
−40
Supply voltage
Typ

0



Max
3.6
0
VCC + 0.5*2
VCC × 0.3
+85
Unit
V
V
V
V
°C
DC Characteristics (Ta = −40 to +85°C, VCC = 2.5 V to 3.6 V)
Parameter
Input leakage current
Symbol
ILI
Min

Typ

Max
2.0
Unit
µA
Test conditions
VCC = 3.6 V, Vin = 0 to 3.6 V
(SCL, SDA)


20
µA
VCC = 3.6 V, Vin = 0 to 3.6 V
(A1, A2, WP)
VCC = 3.6 V, Vout = 0 to 3.6 V
Vin = VSS or VCC
VCC = 3.6 V, Read at 1 MHz
VCC = 3.6 V, Write at 1 MHz
Output leakage current
Standby VCC current
Read VCC current
Write VCC current
ILO
ISB
ICC1
ICC2








2.0
1.0
1.0
4.0
µA
µA
mA
mA
Output low voltage
VOL


0.4
V
VCC = 2.5 to 3.6 V, IOL = 0.8 mA
Capacitance (Ta = +25°C, f = 1 MHz)
Parameter
Symbol
Input capacitance (A1 to A2, SCL, WP)
Cin*1
Output capacitance (SDA)
CI/O*1
Note: 1. This parameter is sampled and not 100% tested.
Rev.3.00,
Jul.12.2005,
page 3 of 18
Min
Typ
Max
Unit
Test
conditions




6.0
6.0
pF
pF
Vin = 0 V
Vout = 0 V
HN58W241000I
AC Characteristics (Ta = −40 to +85°C, VCC = 2.5 to 3.6 V)
Test Conditions
• Input pules levels:
 VIL = 0.2 × VCC
 VIH = 0.8 × VCC
• Input rise and fall time: ≤ 20 ns
• Input and output timing reference levels: 0.5 × VCC
• Output load: TTL Gate + 100 pF
VCC = 2.5 to 3.6 V
Symbol
Min
Typ
Max
Clock frequency
fSCL


1000
Clock pulse width low
tLOW
600


Clock pulse width high
tHIGH
400


Noise suppression time
tI


50
Access time
tAA
100

550
Bus free time for next mode
tBUF
500


Start hold time
tHD.STA
250


Start setup time
tSU.STA
250


Data in hold time
tHD.DAT
0


Data in setup time
tSU.DAT
100


Input rise time
tR


300
Input fall time
tF


100
Stop setup time
tSU.STO
250


Data out hold time
tDH
50


Write protect hold time
tHD.WP
1000


Write protect setup time
tSU.WP
0


Write cycle time
tWC


5.0
Notes: 1. This parameter is sampled and not 100% tested.
2. tWC is the time from a stop condition to the end of internally controlled write cycle.
Parameter
Rev.3.00,
Jul.12.2005,
page 4 of 18
Unit
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
Notes
1
1
1
2
HN58W241000I
Timing Waveforms
Bus Timing
tF
tHIGH
1/fSCL
tLOW
tR
SCL
tSU.STA
tHD.DAT
tSU.DAT
tHD.STA
tSU.STO
SDA
(in)
tBUF
tAA
tDH
SDA
(out)
tSU.WP
tHD.WP
WP
Write Cycle Timing
Stop condition
Start condition
SCL
D0 in
SDA
Write data
(Address (n))
Rev.3.00,
Jul.12.2005,
page 5 of 18
ACK
tWC
(Internally controlled)
HN58W241000I
Pin Function
Serial Clock (SCL)
The SCL pin is used to control serial input/output data timing. The SCL input is used to positive edge clock data into
EEPROM device and negative edge clock data out of each device. Maximum clock rate is 1 MHz.
Serial Input/Output Data (SDA)
The SDA pin is bidirectional for serial data transfer. The SDA pin needs to be pulled up by resistor as that pin is opendrain driven structure. Use proper resistor value for your system by considering VOL, IOL and the SDA pin capacitance.
Except for a start condition and a stop condition, which will be discussed later, the SDA transition needs to be
completed during the SCL low period.
Data Validity (SDA data change timing waveform)
SCL
SDA
Data
change
Note:
Data
change
High-to-low and low-to-high change of SDA should be done during the SCL low period.
Rev.3.00,
Jul.12.2005,
page 6 of 18
HN58W241000I
Device Address (A1, A2)
Up to four devices can be addressed on the same bus by setting the levels on these pins to different combinations. The
levels on these pins are compared with the device address code which are inputted thought the SDA pin. These
device is selected if the compare is successfully done. These pins are internally pulled down to VSS. The device read
these pins as low if unconnected.
Pin Connections for A1, A2
Pin connection
Memory size Max connect number
A2
A1
Note
1M bit
4
VCC/VSS
VCC/VSS
1
Note: 1. “VCC/VSS” means that device address pin should be connected to VCC or VSS. The A1 and A2 are read as VSS,
if left unconnected.
Write Protect (WP)
When the Write Protect pin (WP) is high, the write protection feature is enabled and operates as shown in the following
table. When the WP is low, write operation for all memory arrays are allowed. The read operation is always
activated irrespective of the WP pin status. When left unconnected, the WP input is read as VIL because the WP pin is
internally pulled down to VSS.
Write Protect Area
WP pin status
VIH
VIL
Rev.3.00,
Write protect area
Full (1M bit)
Normal read/write operation
Jul.12.2005,
page 7 of 18
HN58W241000I
Functional Description
Start Condition
A high-to-low transition of the SDA with the SCL high is needed in order to start read, write operation. (See start
condition and stop condition)
Stop Condition
A low-to-high transition of the SDA with the SCL high is a stop condition. The stand-by operation starts after a read
sequence by a stop condition. In the case of write operation, a stop condition terminates the write data inputs and place
the device in a internally-timed write cycle to the memories. After the internally-timed write cycle which is specified
as tWC, the device enters a standby mode. (See write cycle timing)
Start Condition and Stop Condition
SCL
SDA
(in)
Start condition
Rev.3.00,
Jul.12.2005,
page 8 of 18
Stop condition
HN58W241000I
Acknowledge
All addresses and data words are serially transmitted to and from in 8-bit words. The receiver sends a zero to
acknowledge that it has received each word. This happens during ninth clock cycle. The transmitter keeps bus open
to receive acknowledgment from the receiver at the ninth clock. In the write operation, EEPROM sends a zero to
acknowledge after receiving every 8-bit words. In the read operation, EEPROM sends a zero to acknowledge after
receiving the device address word. After sending read data, the EEPROM waits acknowledgment by keeping bus open.
If the EEPROM receives zero as an acknowledge, it sends read data of next address. If the EEPROM receives
acknowledgment "1" (no acknowledgment) and a following stop condition, it stops the read operation and enters a
stand-by mode. If the EEPROM receives neither acknowledgment "0" nor a stop condition, the EEPROM keeps bus
open without sending read data.
Acknowledge Timing Waveform
SCL
1
SDA IN
Jul.12.2005,
8
9
Acknowledge
out
SDA OUT
Rev.3.00,
2
page 9 of 18
HN58W241000I
Device Addressing
The EEPROM device requires an 8-bit device address word following a start condition to enable the chip for a read or a
write operation. The device address word consists of 4-bit device code, 3-bit device address code and 1-bit
read/write(R/W) code. The most significant 4-bit of the device address word are used to distinguish device type and
this EEPROM uses “1010” fixed code. The device address word is followed by the 2-bit device address code. The
device address code selects one device out of all devices which are connected to the bus. This means that the device is
selected if the inputted 3-bit device address code is equal to the corresponding hard-wired A2 to A1 pin status. The
third bit of the device address code is used as memory address. The eighth bit of the device address word is the
read/write(R/W) bit. A write operation is initiated if this bit is low and a read operation is initiated if this bit is high.
Upon a compare of the device address word, the EEPROM enters the read or write operation after outputting the zero
as an acknowledge. The EEPROM turns to a stand-by state if the device code is not “1010” or device address code
doesn’t coincide with status of the correspond hard-wired device address pins A1 to A2.
Device Address Word
Device code (fixed)
1M
1
0
1
Notes: 1. R/W=“1” is read and R/W = “0” is write.
Rev.3.00,
Jul.12.2005,
page 10 of 18
Device address word (8-bit)
Device address code
0
A2
A1
a16
R/W code*1
R/W
HN58W241000I
Write Operations
Byte Write:
A write operation requires an 8-bit device address word with R/W = “0”. Then the EEPROM sends acknowledgment
"0" at the ninth clock cycle. After these, the EEPROM receives 2 sequence 8-bit memory address words. Upon receipt
of this memory address, the EEPROM outputs acknowledgment "0" and receives a following 8-bit write data. After
receipt of write data, the EEPROM outputs acknowledgment "0". If the EEPROM receives a stop condition, the
EEPROM enters an internally-timed write cycle and terminates receipt of SCL, SDA inputs until completion of the
write cycle. The EEPROM returns to a standby mode after completion of the write cycle.
Start
Rev.3.00,
Jul.12.2005,
2nd Memory
address (n)
Write data (n)
D7
D6
D5
D4
D3
D2
D1
D0
W
1st Memory
address (n)
a7
a6
a5
a4
a3
a2
a1
a0
1010
a16
Device
address
a15
a14
a13
a12
a11
a10
a9
a8
Byte Write Operation
ACK
R/W
page 11 of 18
ACK
ACK
Stop
HN58W241000I
Page Write:
The EEPROM is capable of the page write operation which allows any number of bytes up to 256 bytes to be written in
a single write cycle. The page write is the same sequence as the byte write except for inputting the more write data.
The page write is initiated by a start condition, device address word, memory address(n) and write data (Dn) with every
ninth bit acknowledgment. The EEPROM enters the page write operation if the EEPROM receives more write data
(Dn+1) instead of receiving a stop condition. The a0 to a7 address bits are automatically incremented upon receiving
write data (Dn+1). The EEPROM can continue to receive write data up to 256 bytes. If the a0 to a7 address bits
reaches the last address of the page, the a0 to a7 address bits will roll over to the first address of the same page and
previous write data will be overwritten. Upon receiving a stop condition, the EEPROM stops receiving write data and
enters internally-timed write cycle.
Page Write Operation
Rev.3.00,
Jul.12.2005,
page 12 of 18
ACK
ACK
Write data (n+m)
D5
D4
D3
D2
D1
D0
Write data (n)
D7
D6
D5
D4
D3
D2
D1
D0
ACK
R/W
2nd Memory
address (n)
a7
a6
a5
a4
a3
a2
a1
a0
Start
W
a15
a14
a13
a12
a11
a10
a9
a8
1010
1st Memory
address (n)
a16
Device
address
ACK
ACK
Stop
HN58W241000I
Acknowledge Polling:
Acknowledge polling feature is used to show if the EEPROM is in a internally-timed write cycle or not. This feature
is initiated by the stop condition after inputting write data. This requires the 8-bit device address word following the
start condition during a internally-timed write cycle. Acknowledge polling will operate when the R/W code = “0”.
Acknowledgment “1” (no acknowledgment) shows the EEPROM is in a internally-timed write cycle and
acknowledgment “0” shows that the internally-timed write cycle has completed. See Write Cycle Polling using ACK.
Write Cycle Polling Using ACK
Send
write command
Send
stop condition
to initiate write cycle
Send
start condition
Send
device address word
with R/W = 0
ACK
returned
No
Yes
Next operation is
addressing the memory
No
Yes
Proceed write operation
Rev.3.00,
Jul.12.2005,
Send
memory address
Send
start condition
Proceed random address
read operation
Send
stop condition
page 13 of 18
Send
stop condition
HN58W241000I
Read Operation
There are three read operations: current address read, random read, and sequential read. Read operations are initiated
the same way as write operations with the exception of R/W = “1”.
Current Address Read:
The internal address counter maintains the last address accessed during the last read or write operation, with
incremented by one. Current address read accesses the address kept by the internal address counter. After receiving a
start condition and the device address word (R/W is “1”), the EEPROM outputs the 8-bit current address data from the
most significant bit following acknowledgment “0” If the EEPROM receives acknowledgment “1” (no
acknowledgment) and a following stop condition, the EEPROM stops the read operation and is turned to a standby state.
In case the EEPROM has accessed the last address of the last page at previous read operation, the current address will
roll over and returns to zero address. In case the EEPROM has accessed the last address of the page at previous write
operation, the current address will roll over within page addressing and returns to the first address in the same page.
The current address is valid while power is on. The current address after power on will be indefinite. The random
read operation described below is necessary to define the memory address.
Current Address Read Operation
Device
address
Start
Rev.3.00,
Jul.12.2005,
page 14 of 18
R
D7
D6
D5
D4
D3
D2
D1
D0
1 0 10
Read data (n+1)
ACK
R/W
No ACK
Stop
HN58W241000I
Random Read:
This is a read operation with defined read address. A random read requires a dummy write to set read address. The
EEPROM receives a start condition, device address word (R/W=0) and memory address 2 × 8-bit sequentially. The
EEPROM outputs acknowledgment “0” after receiving memory address then enters a current address read with
receiving a start condition. The EEPROM outputs the read data of the address which was defined in the dummy write
operation. After receiving acknowledgment “1”(no acknowledgment) and a following stop condition, the EEPROM
stops the random read operation and returns to a standby state.
Random Read Operation
Start
ACK
R/W
ACK
Device
address
1010#
Start
ACK
Dummy write
Notes: 1. 2nd device address code (#) should be same as 1st (@).
2. Don't care bit.
Rev.3.00,
Jul.12.2005,
page 15 of 18
*2
Read data (n)
#
0
R/W
ACK
R
D7
D6
D5
D4
D3
D2
D1
D0
W
2nd Memory
address (n)
a7
a6
a5
a4
a3
a2
a1
a0
@
a15
a14
a13
a12
a11
a10
a9
a8
1 0 1 [email protected]
1st Memory
address (n)
a16
Device
address
No ACK
Stop
Currect address read
HN58W241000I
Sequential Read:
Sequential reads are initiated by either a current address read or a random read. If the EEPROM receives
acknowledgment “0” after 8-bit read data, the read address is incremented and the next 8-bit read data are coming out.
This operation can be continued as long as the EEPROM receives acknowledgment “0”. The address will roll over
and returns address zero if it reaches the last address of the last page. The sequential read can be continued after roll
over. The sequential read is terminated if the EEPROM receives acknowledgment “1” (no acknowledgment) and a
following stop condition.
Sequential Read Operation
Rev.3.00,
Jul.12.2005,
ACK
R/W
page 16 of 18
ACK
ACK
ACK
D5
D4
D3
D2
D1
D0
Read data (n+1) Read data (n+2) Read data (n+m)
D7
D6
D5
D4
D3
D2
D1
D0
Start
R
D7
D6
D5
D4
D3
D2
D1
D0
1010
Read data (n)
D7
D6
D5
D4
D3
D2
D1
D0
Device
address
No ACK
Stop
HN58W241000I
Notes
Data Protection at VCC On/Off
When VCC is turned on or off, noise on the SCL and SDA inputs generated by external circuits (CPU, etc) may act as a
trigger and turn the EEPROM to unintentional program mode. To prevent this unintentional programming, this
EEPROM has a power on reset function. Be careful of the notices described below in order for the power on reset
function to operate correctly.
• SCL and SDA should be fixed to VCC or VSS during VCC on/off. Low to high or high to low transition during VCC
on/off may cause the trigger for the unintentional programming.
• VCC should be turned off after the EEPROM is placed in a standby state.
• VCC turn on speed (tr) should be longer than 10 us (tr > 10 µs).
Write/Erase Endurance and Data Retention Time
The endurance for programming is 105 cycles (1% cumulative failure rate). The data retention time is more than 10
years.
Noise Suppression Time
This EEPROM have a noise suppression function at SCL and SDA inputs, that cut noise of width less than 50 ns. Be
careful not to allow noise of width more than 50 ns.
Rev.3.00,
Jul.12.2005,
page 17 of 18
HN58W241000I
Package Dimensions
HN58W241000FPIE (PRSP0008DG-B / Previous Code:
JEITA Package Code
P-SOP8-5.3x5.65-1.27
RENESAS Code
PRSP0008DG-B
*1
Previous Code
FP-8DFV
D
8
FP-8DFV)
MASS[Typ.]
0.153g
F
NOTE)
1. DIMENSIONS"*1 (Nom)"AND"*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
5
c
*2
E
HE
bp
Reference
Symbol
Terminal cross section
( Ni/Pd/Au plating )
Index mark
Dimension in Millimeters
Min
Nom
Max
D
5.65
5.85
E
5.30
A2
A1
1
Z
*3
bp
M
c
A1
A
θ
L
Detail F
y
0.35
0.40
0.45
0.15
0.20
0.25
8.10
8.20
page 18 of 18
1
θ
0°
HE
8.00
e
10°
1.27
x
0.25
y
0.1
Z
1.02
0.40
L
L
Jul.12.2005,
0.254
b1
x
c
Rev.3.00,
0.14
1.73
bp
4
e
0.102
A
L1
1
0.60
1.40
0.80
Revision History
Rev.
Date
0.0
1.00
Jul. 10, 2002
Nov.12, 2003
Page



2
19
2.00
Dec.13.2004
2
19
3.00
Jul.12.2005
1
4
5
18
HN58W241000I Data Sheet
Contents of Modification
Description
Initial issue
Change format issued by Renesas Technology Corp.
Deletion of Preliminary
Ordering Information
Addition of HN58W241000FPIE
Package Dimensions
FP-8DF to FP-8DF, FP-8DFV
Ordering Information
Deletion of HN58W241000FPI
Package Dimensions
Deletion of FP-8DF
Ordering Information
Addition of Renesas package codes
AC Characteristics
Addition of tHD.WP
Addition of tSU.WP
Timing Waveforms
Addition of WP
Package Dimensions
Addition of Renesas package codes
Changed to Renesas formats
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
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may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary
circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
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2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data,
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The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor
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