MIC24421 DATA SHEET (11/09/2015) DOWNLOAD

MIC24420/MIC24421
2.5A Dual Output PWM Synchronous
Buck Regulator IC
General Description
Features
The MIC24420/MIC24421 are synchronous PWM dual
output step down converters with internal 2.5A high-side
switches. The MIC24420/MIC24421 has an integrated lowside gate driver for synchronous step-down conversion by
connecting an external N-channel MOSFET to achieve
high efficiencies in low duty-cycle applications.
The MIC24420 switching frequency is 1MHz and the
MIC24421 switching frequency is 500kHz. A patented
control scheme allows the use of a wide range of output
capacitance from small ceramic capacitors to large
electrolytic types with only one compensation component.
A 2% output voltage tolerance over the temperature range
allows the maximum level of system performance. The
MIC24420/MIC24421 power good signal allows full control
for sequencing the output voltages with minimum external
components.
An adjustable current limit allows the use of smaller
inductors in lower current applications.
The MIC24420/MIC24421 is available in a ePad 24-pin
®
4mm x 4mm MLF package, and has an operating junction
temperature range of –40°C to +125°C.
•
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4.5V to 15V input voltage range
Adjustable output voltages down to 0.7V
2.5A per channel
180° out of phase operation
Pre-biased output startup capability
Low-side driver for synchronous operation
2% output voltage accuracy (over temperature)
500kHz (MIC24421) and 1MHz (MIC24420) switching
frequency
Output voltage sequencing
Programmable max current limit
Power good output
Ramp Control™ provides soft-start
Low-side current sensing allows very low duty-cycle
Works with ceramic output capacitors
24-pin 4mm x 4mm MLF® package
Junction temperature range of –40°C to +125°C
Applications
• Multi-output power supplies with sequencing
• DSP, FPGA, CPU and ASIC power supplies
• Telecom and networking equipment, servers
_________________________________________________________________________________________________________________________
Typical Application
MIC24420 Dual Output Buck Converter
Ramp Control is a trademark of Micrel, Inc.
MLF and MicroLeadFrame are registered trademarks of Amkor Technology, Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
June 2012
M9999-062012-C
Micrel, Inc.
MIC24420/MIC24421
Ordering Information
Part Number
Voltage
MIC24420YML
Adj
MIC24421YML
Adj
Switching
Frequency
Temperature Range
1MHz
500kHz
Package
Lead Finish
-40°C to +125°C
24-Pin 4mm x 4mm MLF
®
Pb-Free
-40°C to +125°C
24-Pin 4mm x 4mm MLF®
Pb-Free
Notes:
®
1. MLF is GREEN RoHS compliant package. Lead finish is NiPdAu. Mold compound is Halogen Free.
®
2. MLF z= Pin 1 identifier
Pin Configuration
24-Pin 4mm x 4mm MLF (ML)
Pin Description
Pin Number
Pin Name
Pin Description
1
BST1
Boost 1 (Input): Provides voltage for high-side internal MOSFET for channel 1. Connect a
0.01µF capacitor from SW1 to BST1 pin and a diode to PVDD.
2
LSD1
Low-side Drive 1 (Output): External low-side N-Channel MOSFET driver. Use 4.5V rated
MOSFETs.
3
PGND1
4
CS1
Current Sense 1 (Input): Place a resistor from SW1 to this pin to program the current limit point
from 0.5A to 2.7A.
5
PG1
Power Good 1 (Output): Open drain. Device is in the OFF state. i.e. high when output is within
90% of regulation.
6
EN/DLY1
Enable/Delay 1 (Input): This pin can be used to disable VOUT1. When used to disable VOUT1, this
pin must be pulled down to ground in less than 1µs for proper operation. It is also used for softstart of the output. Soft start capacitor range is 4.7nF to 22nF. See Functional Description
section for additional information.
7
COMP1
8
FB1
9
AVDD
10
AGND
11
FB2
12
COMP2
June 2012
Power Ground 1 (Input).
Compensation 1 (Input): Pin for external compensation, Channel 1.
Feedback 1 (Input): Input to Ch1 error amplifier. Regulates to 0.7V.
5V Internal Linear Regulator (Output): Connect to an external 4.7µF bypass capacitor. When
VIN is <6V, this regulator operates in drop-out mode. Connect AVDD to VIN when VIN <6V.
Analog Ground (Input): Control section ground. Connect to PGND.
Feedback 2 (Input): Input to Channel 2 error amplifier. Regulates to 0.7V.
Compensation 2 (Input): Pin for external compensation, Channel 2.
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MIC24420/MIC24421
Pin Description (Continued)
Pin Number
Pin Name
Pin Description
Enable/Delay 2 (Input): This pin can be used to disable VOUT2. When used to disable VOUT2, this
pin must be pulled down to ground in less than 1µs for proper operation. It is also used for softstart of the output. Soft start capacitor range is 4.7nF to 22nF. See Functional Description
section for additional information.
13
EN/DLY2
14
PG2
Power Good 2 (Output) Open drain. Device is in the OFF state. i.e. high when output is within
90% of regulation
15
CS2
Current Sense 2 (Input) Place a resistor from SW2 to this pin to program the current limit point
from 0.5A to 2.7A
16
PGND2
17
LSD2
Low-side Drive 2 (Output): External low-side N-Channel MOSFET driver. Use 4.5V rated
MOSFETs.
18
BST2
Boost 2 (Input): Provides voltage for high-side internal MOSFET for Channel 2. Connect a
0.01µF capacitor from SW2 to BST2 pin and a diode to PVDD.
19
SW2
Switch Node 2 (Output): Source of internal high-side power MOSFET.
20
VIND2
Supply voltage (Input): For the drain of internal high-side power MOSFET 4.5V to 13.2V.
21
PVDD
5V VDD input (input): Power connection to the internal MOSFET drivers. Connect to AVDD
through an RC filter
22
VIN
23
VIND1
Power Ground 2 (Input)
Supply voltage (Input): For the internal 5V linear regulator. 4.5V to 13.2V.
Supply voltage (Input): For the drain of internal high-side power MOSFET 4.5V to 13.2V.
24
SW1
Switch Node 1 (Output): Source of internal high-side power MOSFET.
EP
ePad
Exposed thermal pad for package only. Connect to ground. Must make a full connection to the
ground plane to maximize thermal performance of the package.
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MIC24420/MIC24421
Absolute Maximum Ratings(1)
Operating Ratings(2)
VIN to PGND .................................................... –0.3V to 16V
VIND1, VIND2 to PGND........................................ –0.3V to 16V
VDD to PGND ..................................................... –0.3V to 6V
VSW1, VSW2 to PGND ............................ –0.7V to (VIN + 0.3V)
VCS1, VCS2 to PGND ............................. –0.7V to (VIN + 0.3V)
VBST1 to VSW1, VBST2 to VSW2 ............................... –0.3V to 6V
VBST1, VBST2 to PGND................................. –0.3V to VSW+6V
VEN/DLY, VCOMP, VFB, VPG to PGND ....–0.7V to (VAVDD + 0.3V)
PGND1, PGND2 to AGND ........................... –0.3V to +0.3V
Junction Temperature ................................................ 150°C
Storage Temperature ...............................–65°C to +150°C
Lead Temperature (soldering, 10 sec.)...................... 260°C
ESD Rating (3) ................................................ ESD Sensitive
Supply Voltage (VIN)...................................... +4.5V to +15V
Output Voltage Range (VOUT)……………......0.7V to 0.7*VIN
Maximum Output Current (IOUT)…………….. ................2.5A
Junction Temperature (TJ) ........................ –40°C to +125°C
Junction Thermal Resistance
4mmx4mm MLF-24L (θJC) .................................14°C/W
4mmx4mm MLF-24L (θJA) .................................35°C/W
Electrical Characteristics(4)
VIN = 12V; VEN=5V; VOUT=1.8V; ILOAD=10mA; TA = 25°C, bold values indicate –40°C≤ TJ ≤ +125°C, unless noted.
Parameter
Condition
Min
Typ
Max
Units
15
V
Power Input Supply
Input Voltage Range (VIN)
4.5
Quiescent Supply Current
VFB = 0.8V, IOUT = 0A; Both outputs not switching
2.6
7
mA
Shutdown Current
VEN1 = VEN2 = 0V
25
50
µA
VIN UVLO Turn-On Threshold
VIN Rising, VDD = VIN
4.1
4.45
V
VIN UVLO Hysteresis
VDD = VIN
3.6
400
mV
VDD Supply
Internal Bias Voltages AVDD
VFB = 0.8V, IAVDD = 50mA
4.7
5.1
5.45
V
686
700
714
mV
Reference (Each Channel)
Feedback Reference Voltage
FB Bias Current
VFB = 0.7V
5
nA
FB Line Regulation
VIN = 6V to 15V, IOU T = 10mA
0.005
%/V
Output Voltage Line Regulation
VIN = 6V to 15V , VOUT = 1.8V, IOU T = 1A; each channel
0.005
%/V
Output Voltage Load Regulation
VOUT = 1.8V, IOU T = 0A to 2A; each channel
0.15
%
Output Voltage Total Regulation
VIN = 6V to 15V , IOU T = 0.25A to 2A, VOUT = 1.8V ; each
channel
0.1
%
External Current Sense, Adjustable
Current Limit Trip Point Current
Sourcing current
Current Limit Temperature
Coefficient
TJ = -40°C to 125°C
175
225
750
Current Limit Comparator Offset
June 2012
200
-20
4
0
µA
ppm/°C
10
mV
M9999-062012-C
Micrel, Inc.
MIC24420/MIC24421
Electrical Characteristics(4) (Continued)
Parameter
Condition
Min
Typ
Max
MIC24420
MIC24421
0.8
1
1.2
0.4
0.5
0.6
MIC24420
70
76
MIC24421
85
90
Units
Oscillator / PWM
Switching Frequency
Maximum Duty Cycle
Minimum On-Time
MHz
%
ILOAD > 200mA (5)
60
ns
IFET = 1A, VFB=0.8V
150
mΩ
Pull Up, ISOURCE = 10mA
4
Ω
Pull Down; ISINK = 10mA
2.5
Ω
Rising Into 1000pF
12
ns
Falling Into 1000pF
9
ns
(Adaptive)
25
ns
High-side Internal MOSFET
On Resistance RDS(ON)
Low-side MOSFET Driver
DH On-Resistance
DH Transition Time
Driver Non-overlap Dead Time
EN/DLY and Soft-start Control
EN/DLY Pull-up Current
VEN/DLY1= VEN/DLY2 = 0V
7
8.5
AVDD Threshold
AVDD turns on
Soft-start Begins Threshold
Channel soft-start begins
0.4
0.58
0.65
V
1.1
1.35
1.8
V
Soft-start Ends Threshold
Channel soft-start ends
2
2.4
2.8
V
PG Threshold Voltage
VOUT Rising (% of VOUT nominal)
85
PG Output Low Voltage
VFB = 0V, IPG = 1mA
90
95
%Nom
0.08
0.3
V
PG Leakage Current
VFB = 800mV, VPG = 5.5V
5.5
µA
Power Good
5
nA
165
°C
22
°C
Thermal Protection
Over-temperature Shutdown
TJ Rising
Over-temperature Shutdown
Hysteresis
Notes:
1. Exceeding the absolute maximum rating may damage the device.
2. The device is not guaranteed to function outside its operating rating.
3. Devices are ESD sensitive. Handling precautions recommended. Human body model, 1.5kΩ in series with 100pF.
4. Specification for packaged product only.
5. Minimum on-time before automatic cycle skipping begins. See applications section.
June 2012
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MIC24420/MIC24421
Typical Characteristics
45
40
4.15
35
1.6
UVLO rising
4.1
4.05
UVLO falling
4
3.95
30
25
20
15
MIC24421
10
3.9
-20
0
20
40
60
80
100
120
140
0.6
0.4
VDD off
6
8
10
12
14
4
16
-10
-15
VIN = 12V
3.4
3.40
3.38
3.38
3.36
3.36
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
-5
3.34
3.32
3.3
3.28
3.26
3.24
VOUT = 3.3V
3.22
-20
60
80
100 120 140
5
7
TEMPERATURE (°C)
100%
90%
80%
80%
EFFICIENCY (%)
70%
60%
50%
VOUT = 0.7V
VOUT = 1.2V
40%
30%
VOUT = 3.3V
20%
VIN
= 5V
11
13
0.5
1
1.5
2
OUTPUT CURRENT (A)
June 2012
3.32
3.30
3.28
3.26
3.24
VOUT = 3.3V
VIN
2.5
= 12V
0
0.5
1
1.5
2
OUTPUT CURRENT (A)
Current Sense Source Current
vs Temperature
225
205
60%
50%
VOUT = 3.3V
40%
30%
195
185
VOUT = 5V
VOUT = 0.7V
VOUT = 1.2V
175
VIN
VIN
= 12V
= 12V
165
0%
0
3.34
15
70%
10%
0%
16
215
20%
10%
9
Efficiency vs. Load
VIN = 12V
100%
90%
14
Regulation vs. Load
VIN = 12V
INPUT VOLTABE (V)
Efficiency vs. Load
VIN = 5V
12
3.20
ICS (uA)
40
10
3.22
3.2
20
8
VIN (V)
Regulation vs. Input Voltage
0
0
6
Input Voltage (V)
5
-20
VDD on
0.8
0
4
Current Limit trip Voltage vs
Temperature
-60 -40
SW on
1
0
-40
Temperature (°C)
VCS TRIP (mV)
1.2
0.2
VOUT1/2 = 1.2V/3.3V
No Load
5
3.85
-60
EFFICIENCY (%)
1.4
MIC24420
VEN THRESHOLD (V)
4.2
Input Current (mA)
UVLO voltage (V)
4.25
10
Enable and Switching Start
Thresholds vs. VIN
Operating Current vs Input
Voltage (O/P regulating)
UVLO vs Temperature
0
0.5
1
1.5
2
OUTPUT CURRENT (A)
6
2.5
-60 -40 -20
0
20
40
60
80
100 120 140
TEMPERATURE (°C)
M9999-062012-C
Micrel, Inc.
MIC24420/MIC24421
Functional Characteristics
June 2012
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MIC24420/MIC24421
Functional Characteristics (Continued)
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MIC24420/MIC24421
Functional Characteristics (Continued)
50
180
50
180
40
144
40
144
30
108
30
108
20
72
20
72
10
36
10
36
0
GAIN (dB)
0
0
-10
-36
-20
-72
-20
-108
-30
Gain
-30
Phase
-40
-50
1
10
100
-144
-40
-180
-50
1000
-36
-72
Gain
-108
Phase
-144
-180
1
FREQUENCY (kHz)
June 2012
0
-10
PHASE (°)
Bode Plot MIC24421
(12V to 5V @ 1.5A)
PHASE (°)
GAIN (dB)
Bode Plot MIC24420
(12V to 5V @ 1.5A)
10
100
1000
FREQUENCY (kHz)
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Micrel, Inc.
MIC24420/MIC24421
Functional Diagram
PWM Core
MIC24420 Block Diagram
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MIC24420/MIC24421
A 4.7µF ceramic capacitor should be used to decouple
AVDD to ground.
Functional Description
The MIC24420/MIC24421 are dual output, synchronous
buck regulators. Output regulation is performed using a
fixed frequency, voltage mode control scheme. The fixed
frequency clock drives the two sections 180° out of
phase, which reduces input ripple current.
EN/DLY pin
The EN/DLY pins are used to turn on, turn off and softstart the outputs. The pins can be controlled with an
open collector or open drain device as shown in Figure
1. It must not be actively driven high or damage will
result. When disabling the output with an external
device, the enable pin turn-off time must be less than
1µs.
Oscillator
An internal oscillator provides a clock signal to each of
the two sides. The clock signals are 180° out of phase
with the other. Each phase is used to generate a ramp
for the PWM comparator and a clock pulse that
terminates the switching cycle. The MIC24420 &
MIC24421 oscillator frequencies are nominally 1MHz
and 500 kHz respectively.
UVLO
The UVLO monitors voltage on the VIN pin. The circuit
controls both regulators (side1 and side2). It disables the
output drivers and discharges the EN/DLY capacitor
when VIN is below the UVLO threshold. As VIN rises
above the threshold, the internal high-side FET drivers
and external low-side drives are enabled and the
EN/DLY pins are released.
A low impedance source should be used to supply input
voltage to the MIC24420/MIC24421. When VIN drops
below the UVLO threshold and the outputs turn off, the
change in input current will cause VIN to rise. The
output voltage will momentarily turn back on if the rise in
VIN is greater than the UVLO hysteresis.
The preferred method is to use the EN/DLY pins, as
shown in Figure 1, for startup and shutdown of the
outputs. This avoids the possibility of glitching during
startup and shutdown. If an external control signal is not
available, the circuit in Figure 1A may be used to set a
higher turn-on and turn-off threshold than the internal
UVLO circuit. Moreover, the hysteresis is adjustable and
can accommodate a wider input source impedance
range. Please refer to the MIC841 datasheet for
additional information on selecting the resistor values.
Figure 1. Enable and soft-start circuit
Figure 1A. Adjustable UVLO startup circuit
Minimum Output Load when Disabled
When one output is disabled and the other enabled, the
disabled output requires a minimum output load to
prevent its output voltage from rising. Typically a 2kΩ
load on the output will keep the output voltage below
100mV. The output setting voltage divider resistors may
be used for the 2kΩ load if the total resistance is set low
enough. A separate output resistor should be used for
lower output voltages since the voltage divider
resistance becomes impractically low.
Regulator/Reference
The internal regulator generates an AVDD pin voltage
that powers the internal analog circuit blocks of the low
level analog and digital sections. The AVDD voltage is
also used by the bandgap to generate a nominal 700mV
for the error amplifier reference. The output undervoltage
and power good circuits use the bandgap for their
references. PVDD powers the high-side MOSFET and
low-side gate drive circuits.
The dropout of the internal regulator causes AVDD to
drop when VIN is below 6V. When operating below 6V,
the AVDD pin must be jumpered to VIN. This bypasses
the internal LDO and prevents AVDD from dropping out.
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MIC24420/MIC24421
can be connected to another regulator’s EN/DLY pin for
sequencing of the outputs. A pull-up resistor is not used
when the power good pin is connected to another
regulators EN/DLY pin.
Soft-start
Enable and soft-start waveforms are shown in Figure 2.
Output Sequencing
Sequencing of the outputs can be easily implemented as
shown in Figure 3. The power good pin is used to
disable VOUT2 until the VOUT1 reaches regulation.
Sequencing waveforms are shown in Figure 4.
Figure 2. Soft-start Timing Diagram
A capacitor, CSS, is connected to the EN/DLY pin. The
CSS capacitor range is 4.7nF to 22nF. Releasing the pin
allows an internal current source to charge the capacitor.
The delay (tD) between the EN/DLY pin release and
when VOUT starts to rise can be calculated by the
equation below.
tD =
C SS × VThreshold_ Start
Figure 3. Output Sequencing
ISS
Where:
CSS is the soft-start capacitor.
ISS is the internal soft-start current (7µA nominal).
VThreshold_start is the EN/DLY pin voltage where the output
starts to rise (1.35V nominal).
The output voltage starts to rise when voltage on the
EN/DLY pin reaches the start threshold. The output
voltage reaches regulation when the EN/DLY pin voltage
reaches the end threshold. The output voltage rise time
(tR) can be calculated by the equation below:
tR =
C SS × (VThreshold_End − VThreshold_Start )
I SS
Where:
VThreshold_End is the EN/DLY pin voltage where the output
reaches regulation (2.4V nominal).
As the MIC24420/MIC24421 uses a fold-back, hiccup
mode current limit, care should be taken to select tR to
ensure startup. See application information for details.
Figure 4. Output Sequencing Waveforms
Power Good
Power good is an open drain signal that asserts when
VOUT exceed the power good threshold. The circuit
monitors the FB pin. The internal FET is turned on while
the FB voltage is below the FB threshold. When voltage
on the FB in exceeds the FB threshold, the FET is
turned off. A pull-up resistor can be connected to PVDD
or an external source. The external source voltage must
not exceed the maximum rating of the pin. The PG pin
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MIC24420/MIC24421
discharging the gate through the LSD pin. The return
path is through the PGND pin and back to the
MOSFET’s Source pin. These circuit paths must be kept
short to minimize noise. See the layout section for
additional information.
Driving the low-side MOSFET on and off dissipates
power in the MIC24420/21 regulator. The power can be
calculated by the equation below:
High-side Drive
The internal high-side drive circuit is designed to switch
the internal N-channel MOSFET. Figure 5 shows a
diagram of the high-side MOSFET, gate drive and
bootstrap circuit. D2 and CBST comprise the bootstrap
circuit, which supplies drive voltage to the high-side
MOSFET. Bootstrap capacitor CBST is charged through
diode D2 when the low-side MOSFET turns on and pulls
the SW pin voltage to ground. When the high-side
MOSFET driver is turned on, energy from CBST charges
the MOSFET gate, turning it on. Voltage on the SW pin
increases to approximately VIN. Diode D2 is reversed
biased and CBST flies high while maintaining gate voltage
on the high-side MOSFET.
A resistor should be added in series with the BST1 and
BST2 pins. This will slow down the turn-on time of the
high-side MOSFET while leaving the turn-off time
unaffected. Slowing down the MOSFET risetime will
reduce the turn-on overshoot at the switch node, which
is important when operating with an input voltage close
to the maximum operating voltage.
The recommended capacitor for CBST is a 0.01µF
ceramic capacitor. The recommended value for RBST is
20Ω to 60Ω.
PDRIVER = QG × VIN × fS
Where:
PDRIVER is the power dissipated in the regulator by
switching the MOSFET on and off.
QG is the total Gate charge of the MOSFET at VGS =
PVDD.
VIN is the input voltage to the internal AVDD regulator.
fS is the switching frequency of the regulator
(1MHz/500kHz nominal).
dV/dt Induced Turn-on of the Low-side MOSFET
As the high-side MOSFET turns on, the rising dv/dt on
the switch-node forces current through CGD of the lowside MOSFET causing a glitch on its gate. Figure 6
demonstrates the basic mechanism causing this issue. If
the glitch on the gate is greater than the MOSFET’s turnon threshold, it may cause an unwanted turn-on of the
low-side MOSFET while the high-side MOSFET is on. A
short circuit between input and ground would
momentarily occur, which lowers efficiency and
increases power dissipation in both MOSFETs.
Additionally, turning on the low-side MOSFET during the
off-time could interfere with overcurrent sensing.
Figure 5. High-side Drive Circuitry
Low-side Drive Output
The LSD pin is used to drive an external MOSFET. This
MOSFET is driven out of phase with the internal highside MOSFET to conduct inductor current during the
high-side MOSFETs off-time. Circuitry internal to the
regulator prevents short circuit “shoot-through” current
from flowing by preventing the high-side and low-side
MOSFETs conducting at the same time.
The low-side MOSFET gate voltage is supplied from
PVDD. Turn off of the MOSFET is accomplished by
June 2012
Figure 6. dV/dt induced turn-on of the low-side MOSFET
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MIC24420/MIC24421
The following steps can be taken to lower the gate drive
impedance, minimize the dv/dt induced current and
lower the MOSFET’s susceptibility to the induced glitch:
•
Choose a low-side MOSFET with a high
CGS/CGD ratio and a low internal gate resistance.
•
Do not put a resistor between the LSD output
and the gate.
•
Ensure both the gate drive and return etch are
short, low inductance connections.
•
Use a 4.5V VGS rated MOSFET. It’s higher gate
threshold voltage is more immune to glitches
than a 2.5V or 3.3V rated MOSFET. MOSFETs
that are rated for operation at less than 4.5 VGS
should not be used.
•
Figure 7. Over-current Circuit
Inductor current, IL, flows from the lower MOSFET
source to the drain during the off-time, causing the drain
voltage to become negative with respect to ground. This
negative voltage is proportional to the instantaneous
inductor current times the MOSFET RDS(ON). The lowside MOSFET voltage becomes even more negative as
the output current increases.
The over-current circuit operates by passing a known
fixed current source through a resistor RCS. This sets up
an offset voltage (ICS x RCS) that is compared to the VDS
of the low-side MOSFET. When ISD (source-to-drain
current) x RDS(ON) is equal to this voltage the soft-start
circuit is reset and a hiccup current mode is initiated to
protect the power supply and load from excessive
current during short circuits. Fold back current limiting is
recommended to protect the switch devices during short
circuit faults. For more information on this, see the
application information section.
Add a resistor in series with the BST pin. This
will slow down the turn-on time of the high-side
MOSFET while leaving the turn-off time
unaffected.
Pre-biased output protection:
It is desirable in synchronous step down converters such
as MIC24420/MIC24421, to prevent the low-side
MOSFET from switching during startup or short periods
in an idle state, since during these times it is possible
that a voltage exists on the output of the converter. If the
low-side switch is allowed to operate, uncontrolled in this
state, large transient voltages can be created at the
switching nodes by ‘open-loop boost’ operation. To
prevent this unwanted operation, the MIC24420/24421
will gradually increase switching cycles on the low-side
MOSFET in ratio to the soft start ramping waveform. Full
operation of the low-side driver is achieved when the
ramp reaches the soft start end threshold (nominally
2.4V) when output voltage is at its nominal level.
Current Limit Calculations and Maximum Peak Limit
Proper current limiting requires careful selection of the
inductor value and saturation current. If a short circuit
occurs during the off-time, the overcurrent circuit will
take up to a full cycle to detect the overcurrent once it
exceeds the over-current limit. The worst case occurs if
the output current is 0A and a hard short is applied to the
output. The short circuit causes the output voltage to fall,
which increases the pulse width of the regulator. It may
take 3 or 4 cycles for the current to build up in the
inductor before current limit forces the part into hiccup
mode. The wider pulse width generates a larger peak to
peak inductor current which can saturate the inductor.
For this reason, the minimum inductor values for the
MIC24420/MIC24421 are 10µH/22µH respectively and
the maximum peak current limit set-point is 2.7A. The
saturation current for each of these inductors should be
at least 1.5A higher than the overcurrent limit setting.
Current Limit
The MIC24420/MIC24421 use the synchronous (lowside) MOSFET’s RDS(ON) to sense an over-current
condition. The low-side MOSFET is used because it
displays lower parasitic oscillations after switching than
the upper MOSFET. Additionally, reduces false tripping
at lower voltage outputs and narrow duty cycles since
the off-time increases as duty cycle decreases. Figure 7
shows how over-current protection is performed using
the low-side MOSFET.
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MIC24420/MIC24421
Voltage Setting Components
The regulator requires two external resistors to set the
output voltage as shown in Figure 8.
Thermal Protection
The internal temperature of the regulator is monitored to
prevent damage to the device. Both outputs are inhibited
from switching if the over-temperature threshold is
exceeded. Hysteresis in the circuit allows the regulator
to cool before turning back on.
Figure 8. Setting the Output Voltage
The output voltage is determined by the equation below.
R1 ⎞
⎛
VOUT = VREF × ⎜1 +
⎟
R2
⎝
⎠
Where: VREF is 0.7V nominal.
If the voltage divider resistance is used to provide the
minimum load (see EN/DLY section) then R1 should be
low enough to provide the necessary impedance.
Once R1 is selected, R2 can be calculated with the
following formula.
R2 =
VREF × R1
VOUT − VREF
And
R2 + R1 < 2k Ω
Minimum Pulse Width
Output voltage is regulated by adjusting the on-time
pulse width of the high-side MOSFET. This is
accomplished by comparing the error amplifier output
with a sawtooth waveform (see block diagram). The
pulse width output of the comparator becomes smaller
as the error amplifier voltage decreases. Due to
propagation delay and other circuit limitations, there is a
minimum pulse width at the output of the comparator. If
the error amplifier voltage drops any further, the output
of the comparator will be low.
The PWM circuit will skip pulses if a smaller duty cycle is
required to maintain output voltage regulation. This
effectively cuts the output frequency in half.
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MIC24420/MIC24421
usually available from the magnetics vendor.
Application Information
Input Capacitor
A 10μF ceramic is suggested on each of the VIN pins for
bypassing. X5R or X7R dielectrics are recommended for
the input capacitor. Y5V dielectrics should not be used.
Besides losing most of their capacitance over
temperature, they also become resistive at high
frequencies, which reduce their ability to filter out high
frequency noise.
Component Selection
Inductor
The value of inductance is determined by the peak-topeak inductor current. Higher values of inductance
reduce the inductor current ripple at the expense of a
larger inductor. Smaller inductance values allow faster
response to output current transients but increase the
output ripple voltage and require more output
capacitance.
The inductor value and saturation current are also
controlled by the method of overcurrent limit used (see
explanation in the previous section). The minimum value
of inductance for the MIC24420/MIC24421 is
10µH/22µH.
The peak-to-peak ripple current may be calculated using
the formula below.
IPP =
Output Capacitor
The MIC24420/MIC24421 regulator is designed for
ceramic output capacitors although tantalum and
Aluminum Electrolytic may also be used.
Output ripple voltage is determined by the magnitude of
inductor current ripple, the output capacitor’s ESR and
the value of output capacitance. When using ceramic
output capacitors, the primary contributor to output ripple
is the value of capacitance. Output ripple using ceramic
capacitors may be calculated using the equation below:
VOUT ⋅ (η ⋅ VIN(max) − VOUT )
η ⋅ VIN(max) ⋅ f S ⋅ L
C OUT ≥
Where:
IPP is the peak-to-peak inductor ripple current
L is the value of inductance
fS is the switching frequency of the regulator
η is the efficiency of the power supply
Efficiency values from the Functional Characteristics
section can be use for these calculations.
The peak inductor current in each channel is equal to the
average output current plus one half of the peak to peak
inductor ripple current.
2
ΔVOUT
2
The RMS inductor current is used to calculate the I R
losses in the inductor.
1 ⎛⎜ IPP ⎞⎟
⎟
3 ⎜I
⎝ OUT ⎠
2
⎡
⎤
I PP
2
= ⎢
⎥ + [I PP ⋅ R ESR ]
⎣ 8 ⋅ C OUT ⋅ 2 ⋅ f S ⎦
The output capacitor RMS current is calculated below:
ICOUTRMS =
Maximizing efficiency requires the proper selection of
core material and minimizing the winding resistance. The
high frequency operation of the MIC24420/MIC24421
requires the use of ferrite materials. Lower cost iron
powder cores may be used but the increase in core loss
will reduce the efficiency of the power supply. This is
especially noticeable at low output power. The inductor
winding resistance decreases efficiency at the higher
output current levels. The winding resistance must be
minimized although this usually comes at the expense of
a larger inductor.
The power dissipated in the inductor equals the sum of
the core and copper losses. Core loss information is
June 2012
8 ⋅ ΔVOUT ⋅ 2 ⋅ f S
Where:
ΔVOUT is the peak-to-peak output voltage ripple
IPP is the peak-to-peak ripple current as see by the
capacitors
fS is the switching frequency (1MHz nominal).
When using tantalum or aluminum electrolytic
capacitors, both the capacitance and ESR contribute to
output ripple. The total ripple is calculated below:
IPK = IOUT + 0.5 × IPP
IINDUCTORRMS = IOUT ⋅ 1 +
IPP
IPP
12
The power dissipated in the output capacitors can be
calculated by the equation below:
(
PDISSCOUT = ICOUTRMS
)2 ⋅ R ESR
Soft start capacitor considerations:
Where a large amount of capacitance is present at the
output of the regulator, a fast rising output voltage can,
in extreme circumstances (since I=Cdv/dt), cause
current limit to operate and prevent startup. In order to
avoid this situation, the following equation can be used
to ensure tR (output rise time) is set correctly.
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Micrel, Inc.
C SS >
MIC24420/MIC24421
COUT ⋅VOUT ⋅ ISS
IS / C
Short Circuit Protection
It is recommended that a fold-back current characteristic
be implemented to protect both external and internal
MOSFETs during short circuit (S/C) events. This can be
achieved by the addition of one additional resistor RFBK
(R14 & R19 on the evaluation board) from VOUT to the
CS pin.
Where
IS/C is the short circuit, fold-back current limit.
CSS is the capacitor connected to EN/DLY pin
ISS is the EN/DLY pull up current.
Current Limit Resistor
The current limit circuit responds to the peak inductor
current flowing through the low-side FET. Calculating the
current setting resistor RCS should take into account the
peak inductor current and the blanking delay of
approximately 100ns.
Figure 9a. Short Circuit Protection
Current limit will occur at:
I OC =
Figure 9 shows the low-side MOSFET current waveform.
Peak current is measured after a small delay. The
equations used to calculate the current limit resistor
value are shown below:
IPP
2
I OC = I PK −
R CS =
RDS (ON )
⎛
⎞
V ⋅R
⋅ ⎜⎜ I CS ⋅ RCS + OUT CS − VCS _ OFF ⎟⎟
RFBK
⎝
⎠
Where VCS_OFF is the CS comparator offset voltage.
For simplicity, assuming VCS_OFF is 0V, we can set IS/C
(current limit when VOUT = 0V) to be half IOC (current limit
when VOUT = nominal):
I OC ⋅ RDS (ON )
RCS =
I CS ⋅ 2
VOUT
RFBK =
I CS
Figure 9. Overcurrent waveform
IPK = IOUT ⋅
1
To determine worst case values, one must take into
account VCS offset voltage, ICS range and the range of
values for RDS(ON) over the operating temperature range.
VOUT ⋅ t DLY
L
IOC ⋅ RDS ON
ICS
Some typical example values for a 30mΩ MOSFET:
IOC
IS/C RCS
RFBK
VOUT
3.3A
1.7
249
24.9k
5
4.3A
1.7
249
16k
3.3A
1.7
249
16.5k
3.3
4.3A
1.7
249
10.5k
3.3A
1.7
249
5.1k
1.2
4.3A
1.7
249
3.83k
Where:
IOC is the current limit set point
L = inductor value
tDLY = Current limit blanking time ~ 100ns
ICS is the overcurrent pin sense current (200µA nominal)
RDS(ON) is the on resistance of the low-side MOSFET
Due to the leading edge blanking, a 100ns slew rate for
the CS pin can be applied without interfering with current
limit operation. Limiting the CS pin’s slew rate will help to
prevent false triggering. A C·R product of at least 20ns
should be used.
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MIC24420/MIC24421
E.G. Where RCS = 250Ω, CCS = 82pF
is outlined below.
1. Measure the ringing frequency at the switch node
which is determined by parasitic LP and CP. Define this
frequency as f1.
2. Add a capacitor CS (normally at least 3 times as big as
the COSS of the FET) from the switch node to ground and
measure the new ringing frequency. Define this new
(lower) frequency as f2. LP and CP can now be solved
using the values of f1, f2 and CS.
3. Add a resistor RS in series with CS to generate critical
damping.
Snubber
A snubber is used to damp out high frequency ringing
caused by parasitic inductance and capacitance in the
buck converter circuit. Figure 10 shows a simplified
schematic of one of the buck converter phases. Stray
capacitance consists mostly of the output capacitance
(COSS) of the two MOSFET’s. The stray inductance is
mostly package and etch inductance. The arrows show
the resonant current path when the high-side MOSFET
turns on. This ringing causes stress on the
semiconductors in the circuit as well as increased EMI.
Step 1: First measure the ringing frequency on the
switch node voltage when the high-side MOSFET turns
on. This ringing is characterized by the equation:
1
f1 =
2π L P ⋅ C P
Where:
CP and LP are the parasitic capacitance and inductance
Step 2: Add a capacitor, CS, in parallel with the
synchronous MOSFET, Q2. The capacitor value should
be approximately 3 times the COSS of Q2. Measure the
frequency of the switch node ringing, f2.
f2 =
1
2π LP ⋅ (CS + CP )
Define f’ as:
Figure 10. Output Parasitics
f' =
One method of reducing the ringing is to use a resistor to
lower the Q of the resonant circuit. The circuit in Figure
11 shows an RC network connected between the switch
node and ground. Capacitor CS is used to block DC and
minimize the power dissipation in the resistor. This
capacitor value should be between 5 and 10 times the
parasitic capacitance of the MOSFET COSS. A capacitor
that is too small will have high impedance and prevent
the resistor from damping the ringing. A capacitor that is
too large causes unnecessary power dissipation in the
resistor, which lowers efficiency.
The snubber components should be placed as close as
possible to the low-side MOSFET and/or external
Schottky diode since it contributes to most of the stray
capacitance. Placing the snubber too far from the
MOSFET or using traces that are too long or too thin
adds inductance to the snubber and diminishes its
effectiveness.
f1
f2
Combining the equations for f1, f2 and f’ to derive CP, the
parasitic capacitance
CP =
CS
2 ⋅ (f ' ) 2 − 1
LP is solved by re-arranging the equation for f1.
LP =
1
(2π )
2
⋅ C P ⋅ (f1 ) 2
Step 3: Calculate the damping resistor.
Critical damping occurs at Q=1
Q=
1
RS
LP
=1
CS + CP
Solving for RS
Proper snubber design requires the parasitic inductance
and capacitance be known. A method of determining
these values and calculating the damping resistor value
June 2012
RS =
LP
CS + CP
Figure 11 shows the snubber in the circuit and the
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MIC24420/MIC24421
damped switch node waveform.
QG is the gate charge for both of the external MOSFETs.
This information should be obtained from the
manufacturer’s data sheet.
Since current from the gate drive is supplied by the input
voltage, power dissipated in the MIC24420/MIC24421
due to gate drive is:
PGATE_DRIVE = Q G ⋅ f S ⋅ VIN
Parameters that are important to MOSFET selection are:
The snubber capacitor, CS, is charged and discharged
each switching cycle. The energy stored in CS is
dissipated by the snubber resistor, RS, two times per
switching period. This power is calculated in the
equation below.
•
On resistance
•
Total gate charge
RMS Current and MOSFET Power Dissipation
Calculation
Switching loss in the low-side MOSFET can be
neglected since it is turned on and off at a VDS of 0V.
The power dissipated in the MOSFET is mostly
conduction loss during the on-time (PCONDUCTION).
2
Where:
fS is the switching frequency for each phase
VIN is the DC input voltage
2
PCONDUCTION = ISW_RMS ⋅ R DS(ON)
Where:
RDS(ON) is the on resistance of the MOSFET switch.
The RMS value of the MOSFET current is:
Low-side MOSFET Selection
An external N-channel logic level power MOSFET must
be used for the low-side switch. The MOSFET gate to
source drive voltage of the MIC24420/MIC24421 is
regulated by an internal 5V regulator. Logic level
MOSFETs, whose operation is specified at VGS = 4.5V
must be used. Use of MOSFETs with a lower specified
VGS (such as 3.3V or 2.5V) are not recommended since
the low threshold can cause them to turn on when the
high-side FET is turning on. When operating the
regulator below a 6V input, connect VDD to VIN to prevent
the VDD regulator from dropping out.
Total gate charge is the charge required to turn the
MOSFET on and off under specified operating conditions
(VDS and VGS). The gate charge is supplied by the
regulator’s gate drive circuit. Gate charge is a source of
power dissipation in the regulator due to the high
switching frequencies. At low output load this power
dissipation is noticeable as a reduction in efficiency. The
average current required to drive the MOSFETs is:
2
2
ISW_RMS = (1 − D) ⋅ (IOUT_MAX +
IPP
)
12
Where:
D is the duty-cycle of the converter
IPP is the inductor ripple current
D=
VOUT
η ⋅ VIN
Where:
η is the efficiency of the converter.
External Schottky Diode
A freewheeling diode in parallel with the low-side
MOSFET is needed to maintain continuous inductor
current flow while both MOSFETs are turned off (deadtime). Dead-time is necessary to prevent current from
flowing unimpeded through both MOSFETs. An external
Schottky diode is used to bypass the low-side
MOSFET’s parasitic body diode. An external diode
IDD = Q G ⋅ f S
Where:
June 2012
Voltage rating
The MOSFET is subjected to a VDS equal to the input
voltage. A safety factor of 20% should be added to the
VDS(max) of the MOSFET to account for voltage spikes
due to circuit parasitics. Generally, 30V MOSFETs are
recommended for all applications since lower VDS rated
MOSFETs tend to have a VGS rating that is lower than
the recommended 4.5V.
Figure 11. Snubber Circuit
Psnubber = f S ⋅ C S ⋅ VIN
•
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MIC24420/MIC24421
improves efficiency due to its lower forward voltage drop
as compared to the internal parasitic diode in the
MOSFET. It may also decrease high frequency noise
because the schottky diode junction does not suffer from
reverse recovery.
An external Schottky diode conducts at a lower forward
voltage preventing the body diode in the MOSFET from
turning on. The lower forward voltage drop dissipates
less power than the body diode. Depending on the circuit
components and operating conditions, an external
Schottky diode may give up to 1% improvement in
efficiency.
Compensation
The voltage regulation, filter and power stage sections
are shown in Figure 12. The error amplifier regulates the
output voltage and compensates the voltage regulation
loop. It is a simplified type III compensator utilizing two
compensating zeros and two poles. Figure 12 also
shows the transfer function for each section.
Compensation is necessary to insure the control loop
has adequate bandwidth and phase margin to properly
respond to input voltage and output current transients.
High gain at DC and low frequencies is needed for
accurate output voltage regulation. Attenuation near the
switching frequency prevents switching frequency noise
from interfering with the control loop.
The output filter contains a complex double pole formed
by the capacitor and inductor and a zero from the output
capacitor and its ESR. The transfer function of the filter
is:
1+
Gfilter(s) =
1+
s
ωz
s
s
+
ωo
Q ωo
2
Where:
ωz =
1
C O ⋅ R ESR
ωo =
Q =R⋅
1
CO ⋅ L O
CO
L
The Modulator gain is proportional to the input voltage
and inversely proportional to the internal ramp voltage
generated by the oscillator. The peak-to-peak ramp
voltage is 1V.
⎛ VIN
Gmod = ⎜⎜
⎝ VRAMP
⎞
⎟⎟
⎠
The output voltage divider attenuates VOUT and feeds it
back to the error amplifier. The divider gain is:
H=
V
R4
= REF
R1 + R4 VOUT
Figure 12. Voltage Loop and Transfer Functions
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MIC24420/MIC24421
The modulator, filter and voltage divider gains can be
multiplied together to show the open loop gain of these
parts.
Gea(s) = G DC
Gvd(s) = Gfilter(s) ⋅ H ⋅ Gmod
This transfer function is plotted in Figure 13. At low
frequency, the transfer function gain equals the
modulator gain times the voltage divider gain. As the
frequency increases toward the LC filter resonant
frequency, the gain starts to peak. The increase in the
gain’s amplitude equals Q. Just above the resonant
frequency, the gain drops at a -40db/decade rate. The
phase quickly drops from 0° to almost 180° before the
phase boost of the zero brings it back up to -90°. Higher
values of Q will cause the phase to drop quickly. In a
well damped, low Q system the phase will change more
slowly.
As the Gain/Phase plot approaches the zero frequency
(fZ), formed by CO and its ESR, the slope of the gain
curve changes from -40db/dec. to -20db/dec and the
phase increases. The zero causes a 90° phase boost.
Ceramic capacitors, with their smaller values of
capacitance and ESR, push the zero and its phase boost
out to higher frequencies, which allow the phase lag
from the LC filter to drop closer to -180°. The system will
be close to being unstable if the overall open loop gain
crosses 0dB while the phase is close to -180°.
The GDC is the DC gain of the error amplifier. It is
internally set to 2500 (68dB).
As illustrated in Figure 12, there are two compensating
zeros. ωz1 is internally set with R3 and C3. The zero
frequency is fixed at a nominal 16kHz in the
MIC24420/MIC24421. The second zero, ωz2, is set by
the external capacitor, C2.
For the MIC24420:
R3 = 100k
C3 = 100pf
fz1 =
fz2 =
90
40
60
30
Gain
GAIN (dB)
20
10
-30
Phase
0
-10
-20
-30
-40
0
-60
-90
VIN = 12V
-120
VOUT = 1.8V
-150
C OUT = 20µF
L = 4.7µH
-180
-50
10
100
PHASE (°)
30
1000
10000
1
= 16kHz
2 × π × R3 × C3
1
2 × π × 21 ⋅ 10 3 × C2
The two compensating pole frequencies are shown
below.
fp1 = 250Hz
1
fp2 =
2 × π × 12 ⋅ 10 3 × C2
fp2 and fz2 both depend on the value of C2 and are
proportionally spaced in frequency with the zero at a
lower frequency than the pole. This provides gain and
phase boost in the control loop.
Voltage Divider Feedforward Capacitor
The capacitor across the upper voltage divider resistor
boosts the gain and phase of the control loop by short
circuiting the high-side resistor at higher frequencies.
The capacitor and upper resistor form a zero at a lower
frequency. The capacitor and parallel combination of
upper and lower resistors form a pole at a higher
frequency. This phase boost circuit is most effective at
higher output voltages, where there is a larger
attenuation from the voltage divider resistors.
Gv d Transfer Function
50
s ⎞⎛
s ⎞
⎛
⎜1 +
⎟⎜1 +
⎟
ωz1 ⎠⎝
ωz2 ⎠
⎝
×
⎛
s ⎞⎛
s ⎞
⎟
⎟⎟⎜⎜1 +
⎜⎜1 +
ωp1 ⎠⎝
ωp2 ⎟⎠
⎝
-210
100000 1000000
FREQUENCY (Hz)
Figure 13: Gvd Transfer Function
If the output capacitance and/or ESR is high, the zero
moves lower in frequency and helps to boost the phase,
leading to a more stable system.
Error Amplifier Poles and Zeros
The error amplifier has internal poles and zeros that can
be shifted in frequency with an external capacitor. The
general form of the error amplifier compensation is
shown in the equation below:
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The general form of the feedforward circuit is shown
below.
s ⎞
⎛
⎜1 +
⎟
ωz3
R2
⎝
⎠
×
H(s) =
R1 + R2 ⎛
s ⎞
⎜⎜1 +
⎟
ωp3 ⎟⎠
⎝
Where:
1
fz3 =
2 × π × R1 × C1
1
fp3 =
⎛ R1 × R2 ⎞
2 × π × C1 × ⎜
⎟
⎝ R1 + R2 ⎠
The total open loop transfer function is:
T(s) = Gea(s) × Gmod × Gfilter(s) × H(s)
The following tables list the recommended values of
compensation and filter components for different output
voltages. The output capacitors are ceramic.
June 2012
MIC24420/MIC24421
MIC24420
VOUT
R1
R2
C7/8
C16/17
R22/23
C29/30
LMIN
1.0V
1k
2.32k
220pF
3.3nF
NF
NF
10µH
CoMIN
47µF
1.2V
1k
1.4k
220pF
3.3nF
NF
NF
10µH
47µF
1.4V
1k
1k
220pF
3.3nF
NF
NF
10µH
47µF
1.8V
1k
634
150pF
4.7nF
NF
NF
10µH
47µF
2.5V
1k
383
150pF
10nF
NF
NF
10µH
47µF
3.3V
1k
274
150pF
10nF
NF
NF
10µH
47µF
5.0V
1k
162
150pF
10nF
NF
NF
10µH
47µF
VOUT
R1
R2
C7/8
C16/17
R22/23
C29/30
LMIN
CoMIN
1.0V
1k
2.32k
1000pF
22nF
22k
100nF
22µH
100µF
1.2V
1k
1.4k
1000pF
22nF
22k
100nF
22µH
100µF
1.4V
1k
1k
1000pF
22nF
22k
100nF
22µH
100µF
1.8V
1k
634
1000pF
22nF
22k
100nF
22µH
100µF
2.5V
1k
383
1000pF
22nF
22k
100nF
22µH
100µF
3.3V
1k
274
1000pF
22nF
22k
100nF
22µH
100µF
5.0V
1k
162
1000pF
22nF
22k
100nF
22µH
100µF
MIC24421
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MIC24420/MIC24421
PCB Layout Guidelines
Warning!!! To minimize EMI and output noise, follow
these layout recommendations.
PCB Layout is critical to achieve reliable, stable and
efficient performance. A ground plane is required to
control EMI and minimize the inductance in power,
signal and return paths.
The following guidelines should be followed to insure
proper operation of the MIC24420/MIC24421 converter.
•
Do not replace the ceramic input capacitor with any
other type of capacitor. Any type of capacitor can be
placed in parallel with the input capacitor.
•
If a Tantalum input capacitor is placed in parallel
with the input capacitor, it must be recommended for
switching regulator applications and the operating
voltage must be derated by 50%.
•
In “Hot-Plug” applications, a Tantalum or Electrolytic
bypass capacitor must be used to limit the overvoltage spike seen on the input supply with power is
suddenly applied. The value must be sufficiently
large to prevent this voltage spike from exceeding
the
maximum
voltage
rating
of
the
MIC24420/MIC24421.
•
An additional Tantalum or Electrolytic bypass input
capacitor of 22µF or higher is required at the input
power connection.
IC
•
Place the IC and the external Low-side MOSFET
close to the point of load (POL).
•
Use fat traces to route the input and output power
lines.
•
The exposed pad (EP) on the bottom of the IC must
be connected to the ground.
•
Use several vias to connect the EP to the ground
plane on layer 2.
•
Signal and power grounds should be kept separate
and connected at only one location, the EP ground
of the package.
•
The following signals and their components should
be decoupled or referenced to the power ground
plane: VIND1, VIND2, PVDD, PGND1, PGND2,
LSD1, and LSD2.
•
•
Inductor
These analog signals should be referenced or
decoupled to the analog ground plane: VIN,
EN/DLY1, EN/DLY2, COMP1, COMP2, FB1, and
FB2.
•
Keep the inductor connection to the switch node
(SW) short.
•
Do not route any digital or analog signal lines
underneath or close to the inductor.
•
Keep the switch node (SW) away from the feedback
(FB) pin.
•
To minimize noise, place a ground plane underneath
the inductor.
Output Capacitor
Place the overcurrent sense resistor close to the
CS1 or CS2 pins. The trace coming from the switch
node to this resistor has high dv/dt and should be
routed away from other noise sensitive components
and traces. Avoid routing this trace under the
inductor to prevent noise from coupling into the
signal.
•
Use a wide trace to connect the output capacitor
ground terminal to the input capacitor ground
terminal.
•
Phase margin will change as the output capacitor
value and ESR changes. Contact the factory if the
output capacitor is different from what is shown in
the BOM.
•
The feedback trace should be separate from the
power trace and connected as close as possible to
the output capacitor. Sensing a long high current
load trace can degrade the DC load regulation.
•
If 0603 package ceramic output capacitors are used,
then make sure that it has enough capacitance at
the desired output voltage. Please refer to the
capacitor datasheet for more details.
Input Capacitor
•
Place the input capacitor next. Ceramic capacitors
must be placed between VIND1 and PGND1 and
between VIND2 and PGND2.
•
Place the input capacitors on the same side of the
board and as close to the IC and low-side MOSFET
as possible.
Diode
•
Keep both the VIN and PGND connections short.
•
•
Place several vias to the ground plane close to the
input capacitor ground terminal, but not between the
input capacitors and IC pins.
The external Schottky diode is placed next to the
low-side MOSFET.
•
•
Use either X7R or X5R dielectric input capacitors.
Do not use Y5V or Z5U type capacitors.
The connection from the Schottky diode’s Anode to
the input capacitors ground terminal must be as
short as possible.
•
The diode’s Cathode connection to the switch node
June 2012
23
M9999-062012-C
Micrel, Inc.
MIC24420/MIC24421
(SW) must be keep as short as possible.
the effect of dv/dt inducted turn-on.
RC Snubber
•
Place the RC snubber on the same side of the board
and as close as possible to the low-side MOSFET.
•
Do not put a resistor between the LSD output and
the gate.
•
Use a 4.5V Vgs rated MOSFET. Its higher gate
threshold voltage is more immune to glitches than a
2.5V or 3.3V rated MOSFET. MOSFETs that are
rated for operation at less than 4.5VGS should not be
used.
Low-side MOSFET
•
•
Low-side drive MOSFET traces (LSD pin to
MOSFET gate pin) must be short and routed over a
ground plane. The ground plane should be the
connection between the MOSFET source and
PGND.
High-side MOSFET
•
Chose a low-side MOSFET with a high CGS/CGD
ratio and a low internal gate resistance to minimize
June 2012
24
Add a 20 to 60 ohm resistor in series with the boost
pin. This will slow down the turn-on time of the highside MOSFET while leaving the turn-off time
unaffected.
M9999-062012-C
Micrel, Inc.
MIC24420/MIC24421
MIC24420 Evaluation Board Schematic
June 2012
25
M9999-062012-C
Micrel, Inc.
MIC24420/MIC24421
MIC24420 Bill of Materials
Item
Part Number
C1, C2, C13
GRM32ER61E226KE15
12103D226MAT2A
C4, C10, C16, C17
C5
Manufacturer
Description
Qty.
(1)
Murata
(2)
AVX
06033D103MAT2A
AVX
GRM21BR70J225KA01
Murata
Ceramic Capacitor, 22µF, 25V, X5R
Ceramic Capacitor, 10nF, 25V
3
4
1
Ceramic Capacitor, 2.2µF, 6.3V
08056D225MAT2A
AVX
C7
VJ0603Y151KXXMB
Vishay(3)
Ceramic Capacitor, 150pF, 50V, X7R
1
C8
VJ0603Y221KXXMB
Vishay
Ceramic Capacitor, 220pF, 50V, X7R
1
GRM31CR60J476ME19
Murata
12066D476MAT2A
AVX
Ceramic Capacitor, 47µF, 6.3V, X5R
2
06033D105MAT2A
AVX
Ceramic Capacitor, 1µF, 25V
1
C16, C17
VJ0603Y103KXXMB
Vishay
Ceramic Capacitor, 10nF, 50V, X7R
2
C18, C19
VJ0603Y471KXXMB
Vishay
Ceramic Capacitor, 470pF, 50V, X7R
2
GRM188R60J475KE19
Murata
C11, C14
C12
C20
06036D475MAT2A
AVX
VJ0603Y820KXXMB
Vishay
EEEFP1E151AP
Panasonic
VJ0603Y104KXXMB
D1, D2
D3, D4
C21, C22
C23
C24, C25, C26, C27, C28
1
Ceramic Capacitor, 4.7µF, 6.3V
Ceramic Capacitor, 82pF
2
150uF, 25V, AL.EL. (80mΩ ESR)
1
Vishay
Ceramic Capacitor, 100nF, 50V, X7R
4
Not Fitted
0
SD103BWS
Vishay
Schottky Diode, 100mA, 30V
2
B0530W
Diodes. Inc(4)
Schottky Diode, 30V, 0.5A
2
Inductor, 10 µH, 2.5A
2
C29, C30
Cooper
(5)
L1, L2
DR74-10R-R
R1, R6
CRCW06031001FRT1
Vishay Dale
Resistor, 1k (0603 size), 1%
2
R2
CRCW06032740FRT1
Vishay Dale
Resistor, 274 (0603 size), 1%
1
R3, R8
CRCW06031002FRT1
Vishay Dale
Resistor, 10k (0603 size), 1%
2
R4, R5
CRCW06032490FRT1
Vishay Dale
Resistor, 249 (0603 size), 1%
2
R7
CRCW06031401FRT1
Vishay Dale
Resistor, 1.4k (0603 size), 1%
1
R9, R15
CRCW06030000FRT1
Vishay Dale
Resistor, 0Ω (0603 size)
2
R12, R13
CRCW06034992FRT1
Vishay Dale
Resistor, 49.9k (0603 size), 1%
2
R10, R11
CRCW06036040FRT1
Vishay Dale
Resistor, 60.4 (0603 size), 1%
2
R16, R17
CRCW06032210FRT1
Vishay Dale
Resistor, 22.1 (0603 size), 1%
2
R14
CRCW06031472FRT1
Vishay Dale
Resistor, 14.7k (0603 size), 1%
1
R18
CRCW060310R0FRT1
Vishay Dale
Resistor, 10 (0603 size), 1%
1
R19
CRCW06035761FRT1
Vishay Dale
Resistor, 5.76k (0603 size), 1%
1
R20, R21
CRCW080512R1FRT1
Vishay Dale
Resistor, 12.1Ω (0805 size), 1%
2
R22, R23
-
-
Not Fitter
0
Q1, Q2
FDC855N
Fairchild(6)
MOSFET
2
Q3, Q4
BSS138
Fairchild
MOSFET
2
MIC24420YML
Micrel, Inc.(7)
2A Dual Output PWM Synchronous Buck
Regulator IC
1
U1
Notes:
1.
Murata: www.murata.com
2.
AVX: www.avx.com
June 2012
26
M9999-062012-C
Micrel, Inc.
3.
Vishay: www.vishay.com
4.
Diodes Inc.: www.diodes.com
5.
Cooper Magnetics: www.cooperet.com
6.
Fairchild Semiconductor: www.fairchildsemi.com
7.
Micrel, Inc.: www.micrel.com
June 2012
MIC24420/MIC24421
27
M9999-062012-C
Micrel, Inc.
MIC24420/MIC24421
MIC24421 Bill of Materials
Item
Part Number
C1, C2, C13
GRM32ER61E226KE15
12103D226MAT2A
C4, C10
C5
Description
Qty.
(1)
Murata
Ceramic Capacitor, 22µF, 25V, X5R
(2)
AVX
06033D103MAT2A
AVX
GRM21BR70J225KA01
Murata
Ceramic Capacitor, 10nF, 25V
3
4
1
Ceramic Capacitor, 2.2µF, 6.3V
08056D225MAT2A
AVX
VJ0603Y102KXXMB
Vishay(3)
Ceramic Capacitor, 1000pF, 50V, X7R
1
GRM31CR60J107ME39L
Murata
Ceramic Capacitor, 100µF, 6.3V, X5R
2
C7, C8
C11, C14
Manufacturer
C12
06033D105MAT2A
AVX
Ceramic Capacitor, 1µF, 25V
1
C16, C17
VJ0603Y223KXXMB
Vishay
Ceramic Capacitor, 22nF, 50V, X7R
2
C18, C19
VJ0603Y471KXXMB
Vishay
Ceramic Capacitor, 470pF, 50V, X7R
2
GRM188R60J475KE19
Murata
06036D475MAT2A
AVX
VJ0603Y101KXXMB
Vishay
EEEFP1E151AP
Panasonic
VJ0603Y104KXXMB
Vishay
SD103BWS
Vishay
C20
C21, C22
C23
C24, C25, C26, C27,
C28, C29, C30
D1, D2
Diodes. Inc
1
Ceramic Capacitor, 4.7µF, 6.3V
Ceramic Capacitor, 100pF
2
150uF, 25V, AL.EL. (80mΩ ESR)
1
Ceramic Capacitor, 100nF, 50V, X7R
(4)
7
Schottky Diode, 100mA, 30V
2
Schottky Diode, 30V, 0.5A
2
Inductor, 22 µH, 7A
2
D3, D4
B0530W
L1, L2
CDRH125-220
Murata
R1, R6
CRCW06031001FRT1
Vishay Dale
Resistor, 1k (0603 size), 1%
2
R2
CRCW06032740FRT1
Vishay Dale
Resistor, 274 (0603 size), 1%
1
R3, R8
CRCW06031002FRT1
Vishay Dale
Resistor, 10k (0603 size), 1%
2
R4, R5
CRCW06032490FRT1
Vishay Dale
Resistor, 249 (0603 size), 1%
2
R7
CRCW06031401FRT1
Vishay Dale
Resistor, 1.4k (0603 size), 1%
1
R9, R15
CRCW06030000FRT1
Vishay Dale
Resistor, 0Ω (0603 size)
2
R12, R13
CRCW06034992FRT1
Vishay Dale
Resistor, 49.9k (0603 size), 1%
2
R10, R11
CRCW06036040FRT1
Vishay Dale
Resistor, 60.4 (0603 size), 1%
2
R16, R17
CRCW06032210FRT1
Vishay Dale
Resistor, 22.1 (0603 size), 1%
2
R14
CRCW06031652FRT1
Vishay Dale
Resistor, 16.5k (0603 size), 1%
1
R18
CRCW060310R0FRT1
Vishay Dale
Resistor, 10 (0603 size), 1%
1
R19
CRCW06035101FRT1
Vishay Dale
Resistor, 5.1k (0603 size), 1%
1
R20, R21
CRCW080512R1FRT1
Vishay Dale
Resistor, 12.1Ω (0805 size), 1%
2
R22, R23
CRCW06032202FRT1
Vishay Dale
Resistor, 22kΩ (0603 size), 1%
2
MOSFET
2
MOSFET
2
2A Dual Output PWM Synchronous Buck
Regulator IC
1
Q1, Q2
FDC855N
Q3, Q4
BSS138
U1
MIC24421YML
(5)
Fairchild
Fairchild
(6)
Micrel, Inc.
Notes:
1.
Murata: www.murata.com
2.
AVX: www.avx.com
3.
Vishay: www.vishay.com
4.
Diodes Inc.: www.diodes.com
June 2012
28
M9999-062012-C
Micrel, Inc.
5.
Fairchild Semiconductor: www.fairchildsemi.com
6.
Micrel, Inc.: www.micrel.com
June 2012
MIC24420/MIC24421
29
M9999-062012-C
Micrel, Inc.
MIC24420/MIC24421
PCB Layout Recommendations
Top Layer
Mid Layer 1
June 2012
30
M9999-062012-C
Micrel, Inc.
MIC24420/MIC24421
PCB Layout Recommendations
Mid Layer 2
Bottom Layer
June 2012
31
M9999-062012-C
Micrel, Inc.
MIC24420/MIC24421
Package Information
24-Pin 4mm x 4mm MLF® (ML)
June 2012
32
M9999-062012-C
Micrel, Inc.
MIC24420/MIC24421
Recommended Land Pattern
24-Pin 4mm x 4mm MLF®
(ML
)
June 2012
33
M9999-062012-C
Micrel, Inc.
MIC24420/MIC24421
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com
Micrel makes no representations or warranties with respect to the accuracy or completeness of the information furnished in this data sheet. This
information is not intended as a warranty and Micrel does not assume responsibility for its use. Micrel reserves the right to change circuitry,
specifications and descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Micrel’s terms and conditions of sale for such products, Micrel assumes no liability
whatsoever, and Micrel disclaims any express or implied warranty relating to the sale and/or use of Micrel products including liability or warranties
relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product
can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant
into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A
Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to fully
indemnify Micrel for any damages resulting from such use or sale.
© 2009 Micrel, Incorporated.
June 2012
34
M9999-062012-C