MIC2155/2156 Two-Phase, Single-Output, PWM Synchronous Buck Control IC General Description Features The MIC2155 and MIC2156 are a family of two-phase, single-output synchronous buck control ICs featuring small size, high efficiency, and a high level of flexibility. The ICs implement a 500kHz (MIC2155) and 300kHz (MIC2156) voltage mode PWM control, with the outputs switching 180° out of phase. The result of the out-of-phase operation is 1MHz (or 600kHz) input ripple with ripple current cancellation, minimizing the required input filter capacitance. A 1% output voltage tolerance allows the maximum level of system performance. Internal drivers with adaptive gate drive allow the highest efficiency with the minimum external components. Two independent enable pins and a power good output are provided, allowing a high level of control and sequencing capability. The MIC215x family has a junction operating range from -40°C to +125°C. • Synchronous buck control ICs with outputs switching 180° out-of-phase • Remote sensing with internal differential amplifier • 4.5V to 14.5V input voltage range • Adjustable output voltages down to 0.7V • 1% output voltage accuracy • Starts up into a pre-biased output • 500kHz PWM operation (MIC2155) • 300kHz PWM operation (MIC2156) • Adaptive gate drive allows efficiencies over 95% • Adjustable current limit with no sense resistor • Senses low-side MOSFET current • Internal drivers allow 25A per phase • Power Good output allow simple sequencing • Dual enables with micro-power shutdown and UVLO • Programmable soft-start pin • Output over-voltage protection • Works with ceramic output capacitors • Multi-input supply capability • Single-output high-current capability with master/slave current sharing • External synchronization • Small footprint 32-pin 5mm × 5mm MLF® • Junction temperature range of -40°C to +125°C Data sheets and support documentation can be found on Micrel’s web site at www.micrel.com. Applications • • • • • Multi-output power supplies with sequencing DSP, FPGA, CPU and ASIC power supplies DSL modems Telecom and networking equipment Servers MLF and MicroLead Frame are registered trademarks of Amkor Technologies Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com November 2009 M9999-111209-B Micrel, Inc. MIC2155/2156 Contents Ordering Information ............................................................................................................................................................... 3 Typical Application .................................................................................................................................................................. 3 Pin Configuration..................................................................................................................................................................... 4 Pin Description ........................................................................................................................................................................ 4 Absolute Maximum Ratings .................................................................................................................................................... 6 Operating Ratings ................................................................................................................................................................... 6 Electrical Characteristics......................................................................................................................................................... 6 Typical Characteristics ............................................................................................................................................................ 9 Functional Diagram ............................................................................................................................................................... 11 Functional Description........................................................................................................................................................... 12 Startup .............................................................................................................................................................................. 12 Soft Start ........................................................................................................................................................................... 12 Enable............................................................................................................................................................................... 13 Supply Voltages and Internal References ........................................................................................................................ 13 UVLO ................................................................................................................................................................................ 14 Power Good ...................................................................................................................................................................... 14 Oscillator and Frequency Synchronization ....................................................................................................................... 15 MOSFET Gate Drive Circuitry .......................................................................................................................................... 15 dv/dt Induced Turn On of the Low-Side MOSFET............................................................................................................ 16 Remote Sense .................................................................................................................................................................. 16 Setting the Output Voltage................................................................................................................................................ 17 Current Limit and Overcurrent Protection ......................................................................................................................... 17 Current Limit Setting ......................................................................................................................................................... 18 The simple method ....................................................................................................................................................... 18 Accurate method .......................................................................................................................................................... 18 Example: ........................................................................................................................................................................... 18 Inductor Current Sensing.................................................................................................................................................. 19 Current Sharing................................................................................................................................................................. 19 Startup into a Pre-Biased Output...................................................................................................................................... 20 Separate Input Supplies ................................................................................................................................................... 20 Component Selection, Guidelines and Design Example .................................................................................................. 21 Output Filter Selection ...................................................................................................................................................... 21 Output Capacitor Selection............................................................................................................................................... 23 Inductor Current Sense Components ............................................................................................................................... 24 Input Capacitor Selection.................................................................................................................................................. 24 MOSFET Selection ........................................................................................................................................................... 24 RMS Current and MOSFET Power Dissipation Calculation............................................................................................. 25 External Schottky Diode ................................................................................................................................................... 26 Snubber Design ................................................................................................................................................................ 26 Compensation of the Output Voltage Loop ...................................................................................................................... 28 Error Amplifier Design Procedure ......................................................................................................................................... 30 Step 1: Decide on the crossover frequency...................................................................................................................... 30 Step 2: Determine the gain required at the crossover frequency ..................................................................................... 30 Step 3: Determine the gain boost needed at the crossover frequency (fc) ...................................................................... 30 Step 4: Determine the frequencies fz2 and fp1 ................................................................................................................ 30 Step 5: Determine the frequency for fz1........................................................................................................................... 30 Step 6: Determine the frequency for fp2........................................................................................................................... 31 Calculating Error Amplifier Component Values ................................................................................................................ 31 Compensation of the Current Sharing Loop ..................................................................................................................... 31 General Layout and Component Placement .................................................................................................................... 33 Design and Layout Checklist ............................................................................................................................................ 34 Package Information ............................................................................................................................................................. 35 November 2009 2 M9999-111209-B Micrel, Inc. MIC2155/2156 Ordering Information Part Number Frequency Voltage Junction Temp. (1) Range Package Lead Finish MIC2155YML 500kHz Adj. -40°C to +125°C 32-Pin 5mm × 5mm MLF Pb-Free MIC2156YML 300kHz Adj. -40°C to +125°C 32-Pin 5mm × 5mm MLF Pb-Free Typical Application VIN 500µF 10µF 30 21 29 5 28 13 1 FDMS7672 VOUT 1.8V 40A 1.5µH 0.22µF FDMS7660 ×2 0.1µF 2 25 3 24 4 23 31 27 10 18 11 26 32 20 FDMS7672 FDMS7660 ×2 250µF 17 15 9 16 8 6 7 19 12 40A Two-Phase Converter November 2009 3 M9999-111209-B Micrel, Inc. MIC2155/2156 BST2 EN1 VDD LSD2 PGND2 PGND1 LSD1 VIN1 Pin Configuration BST1 HSD1 SW1 CS1 EN2 SS HSD2 SW2 N/C VIN2 VOUT COMP2 COMP1 FB1 FB2 EA2+ PGOOD AGND AVDD N/C SYNC DIFFOUT RMVOUT RMGND EP ® 32-Pin MLF (ML) Pin Description Pin Number Pin Name Pin Function 1 BST1 Boost 1 (Input): Provides voltage for high-side MOSFET driver 1. The gate drive voltage is higher than the source voltage by VDD minus a diode drop. 2 HSD1 High-Side Drive 1 (Output): High-current output-driver for external high-side MOSFET. 3 SW1 Switch Node 1 (Output): Return for HSD1 CS1 Current Sense 1 (Input). Current-limit comparator non-inverting input. Current is sensed across the side 1 low-side FET during the off-time. Current limit is set by the resistor in series with the CS1 pin. 5 EN2 Enable 2 (Input): Channel 2 enable. Pull high to enable. Pull low to disable. 6 SS Soft Start (Input): Controls the turn-on time of the output voltage. Active at Power-up, Enable, and Current Limit recovery. 7 COMP1 8 FB1 9 DIFFOUT Output of remote sense differential amplifier. 10 RMVOUT Remote VOUT: Connect to VOUT at the remote sense point. Input to precision differential amplifier. 11 RMGND 12 AGND Analog Ground 13 AVDD Analog supply voltage (input). Connect to VDD through an RC filter network 14 N/C 15 SYNC 4 November 2009 Compensation 1 (Input): Output of the internal error amplifier for Channel 1. Feedback 1 (Input): Negative input to the error amplifier of Channel 1. Remote Ground: Connect to Ground at the remote sense point. Input to precision differential amplifier. No Connect Sync (Input): Synchronizes switching to an external source. Leave floating when not used. 4 M9999-111209-B Micrel, Inc. MIC2155/2156 Pin Description cont. Pin Number Pin Name Pin Function 16 PGOOD Power Good (Output): Asserts high when voltage on the FB pin rises above Power Good threshold. 17 EA2+ (input) Positive input to Channel 2 (current sharing) Error Amplifier. Connect to Channel 1 current sense. 18 FB2 Negative Input to Channel 2 (current sharing) Error Amplifier (Input). Connect to Channel 2 current sense. 19 COMP2 20 VOUT 21 VIN2 Supply Voltage for Channel 2 (Input). Used for Channel 2 UVLO circuit. 22 N/C No Connect 23 SW2 Switch node 2 (Output): Return for HSD2. 24 HSD2 High-Side Drive 2 (Output): High-current output-driver for the high-side MOSFET. 25 BST2 Boost 2 (Input): Provides voltage for high-side MOSFET driver in Channel 2. The gate drive voltage is higher than the source voltage by VDD minus a diode drop. 26 PGND2 27 LSD2 Low-Side Drive 2 (Output): High-current driver output for Channel 2 low-side external MOSFET. VDD 5V Internal Linear Regulator from VIN1 (Output): VDD is the ext. MOSFET gate drive supply voltage and an internal supply bus for the IC. When VIN1 is <5V, this regulator operates in drop-out mode. Connect external bypass capacitor. 29 EN1 Enable 1 (Input): Output enable. Turns off both sides. Pull high to enable. Pull low to disable. 30 VIN1 Supply voltage Channel 1 (Input): Used for UVLO and VDD circuits. 31 LSD1 Low-Side Drive 1 (Output): High-current driver output for Channel 1 low-side external MOSFET. 32 PGND1 EPAD EP 28 November 2009 Compensation 2 (Input): Pin for external compensation of Channel 2. Output Sense (input): Connect to output side of inductors. Used for current sharing. Power Ground 2. High current return for low-side driver 2. Power Ground 1. High current return for low-side driver 1. Exposed Pad (Power): Must make a full connection to the GND plane to maximize thermal performance of the package. 5 M9999-111209-B Micrel, Inc. MIC2155/2156 Absolute Maximum Ratings(1) Operating Ratings(2) Supply Voltage (VIN 1, 2) .................................. -0.3V to 15V Bootstrapped Voltage (VBST) ................................... VIN + 6V SS, FB1, RMVOUT, RMGND, AVDD, Sync, EA2+, FB2, VOUT .................................................................... -0.3V to 6V CS1, EN1, EN2 ................................................ -0.3V to 15V Junction Temperature Range...............-40°C ≤ TJ ≤ +125°C Ambient Storage Temperature...................-65°C to +150°C ESD .................................................... 100V Machine Model 1500V Human Body Model Lead Temperature (soldering 10sec)......................... 260°C Supply Voltage (VIN 1, 2)............................ +4.5V to +14.5V Output Voltage Range...................................... 0.7V to 3.6V Package Thermal Resistance 5mm × 5mm MLF® (θJA) ....................................50°C/W 5mm × 5mm MLF® (θJC).......................................5°C/W Electrical Characteristics(3) TJ = 25°C; VEN = VIN1 = VIN2 =12V; unless otherwise specified. Bold values indicate -40°C≤TJ≤+125°C Parameter Min Condition Typ Max Units 6 10 mA 210 300 µA VIN , VDD and VREF Supply Total Supply Current, IVIN1 + IVIN2 VFB = 0.8V (both O/Ps; non-switching) PWM Mode Supply Current Shutdown Current VEN1 = VEN2 = 0V CH1 VIN UVLO Start Voltage VDD = Open 3.6 4 4.4 V CH1 VIN UVLO Stop Voltage VDD = Open 3.4 3.97 4.2 V CH2 VIN UVLO Start Voltage VDD = Open 2.5 2.7 2.9 V CH2 VIN UVLO Stop Voltage VDD = Open 2.3 2.5 2.7 V VDD UVLO Start Voltage VIN1 = VDD for VIN < 6V 3.6 VDD UVLO Stop Voltage VIN1 = VDD for VIN < 6V 3.3 VIN UVLO Hysteresis VDD = open 40 VEN Shutdown Threshold (Each Channel) VEN Hysteresis (Each Channel) 0.6 1 mV 1.6 30 V mV IVDD = -75mA 4.9 5.25 5.6 IVDD = -50mA VIN = 6V 4.9 5 5.6 MIC2155 MIC2156 450 270 510 310 550 330 kHz MIC2155 MIC2156 860 500 1200 680 kHz Sync Level 0.5 3 V Maximum Duty Cycle (each Channel) 80 Internal Bias Voltage (VDD) V Oscillator / PWM Section PWM Frequency Sync Range Minimum Headroom between VDD and VOUT November 2009 Sync Input is 2x PWM Frequency Required for remote sense amplifier use 6 % 1.3 V M9999-111209-B Micrel, Inc. MIC2155/2156 Electrical Characteristics(3) cont. TJ = 25°C; VEN = VIN1 = VIN2 =12V; unless otherwise specified. Bold values indicate -40°C≤TJ≤+125°C Parameter Condition Minimum On-Time (each Channel) Note 4 Min Typ Max 30 Units ns Regulation CH1 Feedback Voltage Reference (+/- 1%) (+/- 2%) CH1 Feedback Bias Current VFB=0.7V Output Voltage Line Regulation 4.5 ≤ VIN ≤ 14.5 693 686 697 707 714 mV 30 nA 0.08 % 0.5 % 0.6 % 10 mV DC Gain 70 dB Output Sourcing/Sinking Current 1 mA 70 dB 1.25 mS Output Voltage Load Regulation Output Voltage Total Regulation 4.5V ≤ VIN ≤ 14.5V; 1A ≤ IOUT ≤ 10A (VOUT = 2.5V) Channel Current Balancing Asynchronous Mode VTH for Slave Output Error Amplifier (CH1) Error Amplifier (CH2) DC Gain Transconductance Differential Amplifier 1 Voltage Gain Offset Voltage Output Sourcing Current Range -20 +20 mV 0 500 µA 114 %Nom Output Over Voltage Protection VFB Threshold (Latches LSD High) 106 109 1 Delay Blanking time µs Soft Start 1.25 1 Internal Soft-Start Source Current November 2009 7 2 2.75 3 µA M9999-111209-B Micrel, Inc. MIC2155/2156 Electrical Characteristics(3) cont. TJ = 25°C; VEN = VIN1 = VIN2 =12V; unless otherwise specified. Bold values indicate -40°C≤TJ≤+125°C Parameter Condition Min Typ Max Units 180 195 220 µA -10 0 +10 mV 86 88.5 91 %Nom 0.225 0.3 V Current Sense CS Over Current Trip Point Program Current CS Comparator Sense Threshold (Senses drop across low-side FET) Power Good VFB Threshold PGOOD Voltage Low VFB = 0 V; IPGOOD = 1mA Gate Drivers Into 3000pF Source Sink 23 16 High-Side Drive Resistance VDD = VIN = 5V Source Sink 1.6 1.7 3.5 2.5 Ω Ω Low-Side Drive Resistance VDD = VIN = 5V Source Sink 2 1.4 3.5 2.5 Ω Ω Rise/Fall Time Driver Non-Overlap Time (adaptive) 60 ns ns Notes: 1. Absolute maximum ratings indicate limits beyond which damage to the component may occur. Electrical specifications do not apply when operating the device outside of its operating ratings. The maximum allowable power dissipation is a function of the maximum junction temperature, TJ(Max), the junction-to-ambient thermal resistance, θ JA, and the ambient temperature, TA. The maximum allowable power dissipation will result in excessive die temperature, and the regulator will go into thermal shutdown. 2. The device is not guaranteed to function outside its operating rating. 3. Specification for packaged product only. 4. Minimum on-time before automatic cycle skipping begins. See applications section. November 2009 8 M9999-111209-B Micrel, Inc. MIC2155/2156 Typical Characteristics VIN2 UVLO Threshold V IN 5.4 = 12V No Switching 5.2 VIN = 12V 5.0 -4.00 -6.00 -8.00 4.8 4.6 4.4 4.2 = 5V 3.5 10 20 30 40 50 60 70 LOAD (mA) 3.0 4 6 8 10 12 14 INPUT VOLTAGE (V) 9 16 140 120 0.6980 0.6975 0.6970 0.6965 0.6960 140 IN 3.5 = 12V 120 V 4.0 IN 100 4.0 V 0.6985 80 4.5 0.6990 -20 4.5 vs. Input Voltage No Switching Feedback Voltage vs. Temperature -40 5.0 VDD (V) 5.0 100 TEMPERATURE (°C) FEEDBACK VOLTAGE (V) IN 5.5 = 12V 60 -40 140 120 100 80 60 40 20 0 -20 VIN = 5V 4.0 80 -10.00 VDD V 140 vs. Temperature TEMPERATURE (°C) vs. Load 120 0.94 CH2 Falling 0.92 CH1 Falling 0.90 0.88 80 CH1 Rising CH2 Rising VDD -2.00 -40 1.04 1.02 1.00 0.98 0.96 TEMPERATURE (°C) 0.00 -14 VIN = 12V 40 16 -12.00 16 1.08 1.06 100 QUIESCENT CURRENT (mA) 140 120 8 10 12 14 INPUT VOLTAGE (V) 16 Enable Threshold vs. Temperature 0 6 8 10 12 14 INPUT VOLTAGE (V) 20 0.04 0.02 0 4 VDD VDD (V) 6 40 -2.00 November 2009 No Switching 60 -1.50 3.0 0 1 40 -1.00 No Switching 2 20 -0.50 IQ2 0.08 0.06 2.00 FREQUENCY (%) FREQUENCY (%) 0.12 0.10 4.00 0.50 0.00 IQ1 ENABLE1,2 = 0V Change in Switching Frequency vs. Temperature 1.00 5.5 3 -20 16 Change in Switching Frequency vs. Input Voltage 8 10 12 14 INPUT VOLTAGE (V) 4 0 0.04 0.03 0.18 0.16 0.14 Shutdown Current vs. Input Voltage VDD (V) 0.06 0.05 6 5 -40 0.20 0.09 0.08 0.07 -2.5 4 6 0 4 ENABLE THRESHOLD (V) Quiescent Current 2 vs. Input Voltage 0.02 0.01 No Switching 0 4 6 8 10 12 14 INPUT VOLTAGE (V) 7 TEMPERATURE (°C) SHUTDOWN CURRENT (mA) QUIESCENT CURRENT (mA) 0.10 8 -20 TEMPERATURE (°C) 80 UVLO Falling 2.45 2.40 140 120 80 100 60 40 0 20 -40 3.90 -20 3.92 100 UVLO Falling 3.94 2.50 60 3.96 2.55 40 3.98 2.60 0 4.00 2.65 -20 UVLO Rising -40 4.02 2.70 20 UVLO THRESHOLD (V) UVLO THRESHOLD (V) 4.04 9 UVLO Rising 60 2.75 4.06 20 4.08 Quiescent Current 1 vs. Input Voltage 0 VIN1 UVLO Threshold TEMPERATURE (°C) M9999-111209-B Micrel, Inc. MIC2155/2156 Typical Characteristics (cont.) R 1.8 RDSON (ohms) 1.7 DSON 140 120 80 100 60 40 0 -40 20 170 DSON High Side Drive Source/Sink SINK 140 120 100 80 60 SOURCE 20 0.5 0 1 -20 RDSON (ohms) VIN = 5V 2.2 V = 5V 2.1 IN 2.0 1.9 1.8 1.7 1.6 1.5 1.4 1.3 1.2 -40 VIN = 12V TEMPERATURE (°C) 180 R 1.5 0 190 TEMPERATURE (°C) 2.5 2 VIN = 5V 200 -20 CS PIN CURRENT (µA) 3 = 12V 210 160 16 140 SOFT START CURRENT (µA) 140 120 80 100 60 TEMPERATURE (°C) 8 10 12 14 INPUT VOLTAGE (V) Soft Start Current vs. Temperature 3.5 VIN = 5V 40 0 IN = 12V 20 V 6 120 16 -20 8 10 12 14 INPUT VOLTAGE (V) Differential Amplifier Gain vs. Temperature -20 1.022 1.020 1.018 1.016 1.014 1.012 1.010 1.008 1.006 1.004 1.002 1.000 6 -40 GAIN 0.6950 4 192 191 190 4 80 0.6955 194 193 100 0.6960 196 195 60 0.6965 V IN 40 0.6970 220 199 198 197 0 CS PIN CURRENT (µA) 0.6975 CS Pin Current vs. Temperature 40 200 -40 FEEDBACK VOLTAGE (V) 0.6980 CS Pin Current vs. Input Voltage 20 Feedback Voltage vs. Input Voltage TEMPERATURE (°C) LowSide Drive Source/Sink VIN = 5V SINK 1.6 1.5 1.4 SOURCE 1.3 1.2 140 120 100 80 60 40 20 0 -40 1 -20 1.1 TEMPERATURE (°C) November 2009 10 M9999-111209-B Micrel, Inc. MIC2155/2156 Functional Diagram MIC2155/6 Block Diagram November 2009 11 M9999-111209-B Micrel, Inc. MIC2155/2156 Functional Description The MIC2155 and MIC2156 are two-phase, synchronous buck controllers operating at a fixed frequency. The two controllers differ only in switching frequency with the MIC2155 switching at 500kHz per phase (1MHz at the input and output) and the MIC2156 switches at 300kHz per phase. Some of the advantages of multi-phase operation are: • Smaller input and output filtering components are required because of current cancelation and higher input and output frequency. • Faster transient response is possible with smaller output filter component values. • Load current through each phase is one half the total output current, which allows for even heat distribution and smaller components. • Control circuitry forces better current sharing in the MOSFETs than paralleling FETs in a single phase application. The controller utilizes a voltage-mode control scheme (VMC). Lossless current sharing is accomplished by sensing the DC voltage across each inductor winding. Lossless overcurrent protection is performed by sensing the voltage across the low-side MOSFET on-resistance during the off-time. Other features of the controller are: VOUT (1V/div) A typical output voltage and inductor current startup is shown in Figure 2. INDUCTOR CURRENT INDUCTOR CURRENT (2A/div) (2A/div) • • • • • • • • • Figure 1. Startup Sequence Overvoltage protection Soft start UVLO Enable Remote sensing Pre-biased output startup Multiple input supplies Power Good signal Frequency synchronization Channel 2 Time (4ms/div) Figure 2. Turn On Startup A typical startup sequence is shown in Error! Reference source not found. (also refer to the block diagram). The enable pins are asserted after VIN is applied. VDD is immediately turned on and an internal FET releases the soft start pin. The soft start pin controls the error amplifier voltage. As VSS ramps up, it reaches a threshold where the gate drive is enabled and the MOSFETs start to switch at a very low duty cycle. The rise of the soft start voltage controls the increase in VOUT by gradually allowing the COMP1 pin voltage to rise. A 10mV offset in the current controller keeps the Channel 2 low-side drive off when the output current is low to prevent current from circulating between the phases. PGOOD is asserted when VOUT reaches the PGOOD threshold. November 2009 Channel 1 Soft Start The soft-start capacitor controls how fast the output voltage rises by controlling the COMP pin risetime. Without soft start a fast or uncontrolled turn-on requires a higher current from the input source to charge up the output capacitance. The soft-start capacitor also controls the delay time between the enable pin assertion to when VOUT starts to rise. Figures 3 and 4 show the soft-start circuitry and waveform timing. 12 M9999-111209-B Micrel, Inc. MIC2155/2156 Enable There is an enable pin for each of the two channels. Asserting EN1 will enable Channel 1 gate drive and release the soft start circuit. De-asserting EN1 will disable the gate drive, discharge CSS and disable VDD. It will bring the controller into a low current off state. Enable 2 only controls switching of Channel 2. Disabling Channel 2 stops the switching of the power FETs on Channel 2 which reduces the VDD current draw. This can improve efficiency when operating at low output current, especially when large MOSFETs are used. VEN1/2 Slope = ISS/CSS VSS VOUT Supply Voltages and Internal References The MIC2155/6 is powered from a 4.5V to 14.5V supply. The two input supply pins (VIN1 and VIN2) are connected together in most applications. They are powered separately in configurations with two input supply voltages. VIN1 supplies an internal LDO, which generates the VDD supply voltage. VDD is used to power the gate drive circuitry and must be externally decoupled to the power ground pins (PGND1 and PGND2). A 10µF Ceramic capacitor is recommended for most applications. The AVDD pin is the supply pin for the Bandgap reference and internal analog circuits. A small RC filter (10Ω/0.1µF) connected to AVDD is recommended to help attenuate switching noise from the VDD supply. The dropout of the internal VDD regulator causes VDD to drop if VIN1 is below 6V. When operating below 6V, VDD may be jumpered to VIN1. This bypasses the internal LDO and prevents VDD from dropping out. An LDO or simple series pass regulator can be used to limit the VDD voltage for applications with an input voltage that spans above and below the 6V maximum VDD limit. Figures 5 and 6 illustrate two examples of regulating VDD with external circuitry. Figure 3. Soft Start Waveforms Figure 4. Soft Start Circuit The output voltage starts to rise when VSS is approximately 1 diode drop above ground, 0.6V. The startup delay and output voltage risetime can be approximated using the formula shown below: Delay td = CSS × 0.6V ISS Risetime C × VOUT tR = SS 14 × ISS C IN 1µF C VDD 10µF C BST The soft start pin is discharged under the following conditions: • • • • EN1 pin de-asserted UVLO on the VIN1 or VDD pins Overcurrent Overvoltage (latched off) November 2009 Figure 5. LDO Regulator 13 M9999-111209-B Micrel, Inc. MIC2155/2156 C VDD 10µF Using an external LDO to supply VDD (as in Figure 5) can lower power dissipation in the controller and reduce junction temperature by supplying VDD externally. Using an external regulator, the power dissipated in the controller is reduced to: C BST PDISS = (5V × (37nC × 4) × 500kHz = 0.37W Careful selection and temperature rise calculations of the external LDO should be done to prevent an excessively high LDO junction temperature. Figure 6. Emitter Follower Regulator UVLO Separate UVLO circuits monitor VIN1, VIN2 and VDD. Switching on Channel 1 is inhibited until the voltage on the VIN1 and VDD pins is greater than their respective UVLO thresholds. The gate drive on Channel 2 is inhibited until the VIN2 pin voltage exceeds its UVLO threshold. Individual UVLO thresholds are necessary to allow proper operation from separate input supplies. The VIN1 threshold prevents the IC from switching if the input voltage is too low to properly source the VDD voltage. The VIN2 UVLO threshold is lower than VIN1 to allow operation from a low voltage input. Channel 1 will switch and provide a regulated output voltage even if the VIN2 UVLO prevents Channel 2 from switching. The internal VDD regulator can supply up to 75mA of current to drive the external MOSFETs. Power dissipation inside the MIC2155/6 control IC is divided between power dissipated in the controller’s analog circuitry and power dissipated in the drive circuitry. Drive circuitry power is almost always much greater than analog circuitry power. Total regulator power dissipation is calculated using the following formula: PDISS = VIN1 × IIN1 = VIN1 × (fS × Qg + IQ ) Where: Qg = total gate charge of all MOSFETs fS = switching frequency of each stage (500kHz for the MIC2155 and 300kHz for the MIC2156) IQ = Controller quiescent current (non-switching supply current) Power Good The power good signal asserts high when the output voltage is greater than the power good threshold. The power good circuit compares a portion of the reference voltage to the voltage on the feedback pin. The output is an open drain FET as shown in Figure 7. To assert high it must be pulled up to AVDD through a resistor. In some instances, power dissipation inside the control IC may limit the controller’s maximum ambient temperature. For example, if the MIC2155 is powered from a 12V source and is driving 4 FETs. If each FET has a Qg=37nC, the total power dissipation in the MIC2155 is: AVDD PG Comparator PDISS = 12V × (37nC × 4) × 500kHz = 0.888 W PGOOD FB1 The maximum operating ambient temperature is: BandGap-10% TA(MAX ) = TJ(MAX ) − PDISS × θJC TA(MAX ) = 125°C − 0.888 W × 50 °C Figure 7. Power Good W The power good signal may be connected to the enable pin of other power supplies and used to sequence the other outputs. TA(MAX ) = 81°C November 2009 14 M9999-111209-B Micrel, Inc. MIC2155/2156 with an appropriate VGS threshold should be used in this situation. The voltage on the bootstrap capacitor drops each time it delivers charge to turn on the MOSFET. The voltage drop depends on the gate charge required by the MOSFET. Most MOSFET specifications specify gate charge vs. VGS voltage. Based on this information and a recommended ΔVHB of less than 0.1V, the minimum value of bootstrap capacitance is calculated as: Oscillator and Frequency Synchronization The internal oscillator free runs at a fixed frequency and requires no external components. The oscillator generates two clock signals that are 180° out of phase with each other. This forces each channel of the controller to switch 180° out of phase, which reduces input and output ripple current. The internal oscillator generates a clock signal and ramp signal. The clock signal terminates the switching cycle for each channel. The ramp voltage for Channel 1 is compared with the output of the error amplifier and regulates the output voltage. The ramp signal for Channel 2 is compared with the Channel 2 error amplifier output and forces the output current of Channel 2 to match Channel 1. CBST ≥ QGATE ΔVBST Where: QGATE = Total Gate Charge a VBST ΔVBST = Voltage drop at the BST pin RMP1 A minimum value of 0.1µF is required for each of the bootstrap capacitors, regardless of the MOSFETs being driven. Larger or paralleled MOSFETs may require larger capacitance values for proper operation. Placement is critical. The bypass capacitor (CBST) for the BST supply pins must be located close between the BST and SW1 pins. The etch connections should be short, wide and direct. The use of a ground plane to minimize connection impedance is recommended. Refer to the section on layout and component placement for more information. A delay between the switching of the two MOSFETs is necessary to prevent both MOSFETs from being on at the same time and shorting VIN to ground. An adaptive gate drive in the controller monitors the switch node (SW1) and low-side driver (LSD1) to minimize dead time while preventing both MOSFETs from being on at the same time. This enables the use of a broad range of MOSFETS without requiring excessive deadtime. CLK1 SYNC RMP2 CLK2 2 Phase Oscillator Figure 8. Oscillator and Sync Diagram The SYNC input (pin 15) allows the MIC2155/6 to synchronize to an external clock signal. When synchronized, each channel switches at half of the synchronization frequency. Limitations on the synchronization frequency and signal amplitude are listed in the electrical characteristics section of the spec. When not used, the sync pin should be left open (no connect). MOSFET Gate-Drive Circuitry The high-side drive circuit is designed to switch an Nchannel MOSFET. Figure 9 shows a diagram of the gate drive and bootstrap circuit. D2 and CBST comprise the bootstrap circuit, which is used to supply drive voltage to the high-side FET. Bootstrap capacitor CBST is charged through diode D2 while the low-side MOSFET is on and the voltage on the SW pin is approximately 0V. When the high-side MOSFET driver is turned on, energy from CBST is used to charge the MOSFET gate, turning on the FET. As the MOSFET turns on, the voltage on the SW pin increases to approximately VIN. Diode D2 is reversed biased and CBST is pulled high while continuing to keep the high-side MOSFET on. The high-side drive voltage, which is derived from VDD, is approximately 4.5V due the voltage drop across D2. When operating at 4.5VIN, without connecting VDD to VIN, the gate drive voltage to the high-side FET could be as low as 3.2V. MOSFETs November 2009 15 M9999-111209-B Micrel, Inc. MIC2155/2156 The following steps can be taken to lower the gate drive impedance, minimize the dv/dt induced current and lower the FETs susceptibility to the induced glitch: 1) Chose a MOSFET with: a) a high CGS/CGD ratio b) a low internal gate resistance 2) Do not put a resistor between the LSD output and the gate. 3) Insure both the gate drive and return etch are short, low inductance connections. 4) Use a 4.5V VGS-rated MOSFET because its higher gate threshold voltage is more immune to glitches than a 2.5V or 3.3V rated FET. 5) Connect VDD to VIN or a 5V supply if VIN is below 6V. The RDSON of the internal driver will be lower and a 4.5V rated MOSFET can be used. C BST Figure 9. Gate Drive dv/dt Induced Turn On of the Low-Side MOSFET As the high-side MOSFET turns on, the rising dv/dt on the switch-node forces current through CGD of the lowside FET causing a glitch on the FET’s gate. Figure 10 illustrates the basic mechanism causing this issue. If the glitch on the gate is greater than the FET’s turn-on threshold, it may cause an unwanted turn-on of the lowside FET while the high-side FET is on. A short circuit between input and ground would occur that lowers efficiency and increases power dissipation in both FETs. Additionally, turning on the low-side FET during the offtime could interfere with overcurrent sensing. Remote Sense Remote sensing provides accurate output voltage regulation by sensing at the load. Remote sensing makes up for losses in the power distribution path. It uses a unity gain differential amplifier to overcome voltage drops in both the output and return (ground) paths. The amplifier has common mode input range from -0.3V to 3.6V. For proper remote sense operation, VIN must be greater than 6V. If VIN is less than 6V, the VDD pin must be connected to VIN or externally supplied with 5V. The output of the remote sense amplifier can source up to 500µA. The voltage divider resistors (R1 and R4 in Figure 12) must be chosen to insure the output current of the amplifier does not exceed the maximum of 500µA. VDS R1MAX ≥ VOUT − VREF 500μA Where: VREF = 0.7V A gain/phase plot of the remote sense amplifier in Figure 11 shows a typical 2MHz bandwidth. Phase lag is 45° at 1MHz. Figure 10. dv/dt Induced Turn-On November 2009 16 M9999-111209-B MIC2155/2156 60 200 50 40 160 120 30 20 Phase 10 0 -10 Magnitude -20 -30 -40 1k 10k 100k 1M FREQUENCY (Hz) 80 40 0 -40 Setting the Output Voltage Regardless of whether the remote sensing or local output voltage sensing is used, the output voltage is set with voltage divider resistors R1 and R4 (Figure 12). The equation below is used to calculate VOUT. PHASE (°) MAG (dB) Micrel, Inc. ⎡ R1 ⎤ VOUT = VREF × ⎢1 + ⎥ ⎣ R4 ⎦ -80 -120 -160 -200 10M Where: VREF = 0.7V Figure 11. Remote Sense Amplifier Gain/Phase Plot A typical remote sense configuration is shown in Figure 12. The output of the remote sense amplifier feeds a voltage divider (R1, R4), which is connected to the Channel 1 error amplifier. The divider and compensation network for the remote sense are the same as for a local sense configuration. The 10Ω resistors provide an alternate feedback path if the remote sense connections are removed or opened. The remote sense connections should not be shorted or the output voltage will increase close to VIN. The OVP circuit in the controller will not protect against this type of fault since the feedback pin voltage will be 0V. Current Limit and Overcurrent Protection The MIC2155/6 uses the synchronous (low-side) MOSFETs RDSON to sense an over current condition. The low-side MOSFET is used because it displays lower parasitic oscillations after switching then the upper MOSFET. Additionally, it improves the accuracy and reduces false tripping at lower voltage outputs and narrow duty cycles since the off-time increases as duty cycle decreases. MIC2155/6 VIN HSD 200µA +SENSE LOAD CS1 Q1 –IL × RDSON RCS IL L1 –SENSE Current Limit LSD Q2 IL CO Figure 13. Overcurrent Circuit Inductor current flows from the lower MOSFET source to the drain during the off-time. The drain voltage becomes negative with respect to ground as the inductor current continues to flow from Source to Drain. This negative voltage is proportional to instantaneous inductor current times the MOSFET RDSON. The voltage across the lowside FET becomes even more negative as the output current increases. The overcurrent circuit operates by passing a known fixed current source (200µA) through a resistor RCS. This sets up an offset voltage (ICS × RCS) that is compared to the VDS of the low-side FET. When ISD (Source to Drain current) × IL is equal to this voltage, the MIC2155’s over current trigger is set, which disables the next high side gate drive pulse. After missing the high side pulse, the overcurrent (OC) trigger is reset. If on the next low-side drive cycle, the current is still too high i.e. VCS is ≤ 0V, another high side pulse is missed and so on. This effectively reduces the overall energy transferred to the output and VOUT starts to fall. Figure 12. Remote Sense November 2009 17 M9999-111209-B Micrel, Inc. MIC2155/2156 The MIC2155/6 current limit circuit restricts the maximum output current. If the load tries to draw additional current the output voltage drops until it is no longer within regulation limits. At this point (75% of nominal output voltage) a hiccup current mode is initiated to protect down stream loads from excessive current during hard short circuits. This helps reduce the overall power dissipation in the PWM converter components during a fault. Accurate Method For designs where ripple current is significant when compared to IOUT or for low duty cycle operation, calculating the current setting resistor RCS should take into account that we are sensing the peak inductor current and that there is a blanking delay of approximately 100ns. Figure 15. Overcurrent waveform The equations to accurately calculate the current limit resistor value are shown below: I I IPK = OUT + RIPPLE 2 2 VOUT × (1 − D) IRIPPLE = FS × L Figure 14. Overcurrent Sense Waveforms The MIC2155/6 only senses current across the low side MOSFET of Channel 1 since both channels operate in parallel. This means the total output current limit is approximately twice the calculated current limit. V × TDLY ISET = IPK − OUT L ISET × RDSON(MAX) RCS = ICS(MIN) Current Limit Setting The current limit circuit responds to the peak inductor current flowing through the low-side FET. The value of RCS can be estimated with the “simple” method or can be more accurately calculated by taking the inductor ripple current into account. D = Duty Cycle FS = Switching Frequency L = Power inductor value TDLY = Current limit blanking time ~ 100ns ICS(min) = 180µA The Simple Method Current limit can be quickly estimated with the following equation: Example: Consider a 12V to 3.3V @ 30A converter with 1.5µH power inductor and 90% efficiency at full load. Each channel will supply 15A at a 500kHz (MIC2155) switching frequency. The on-resistance of the low side MOSFET is 6mΩ. Using the simple method: RCS = IOUT/2 × RDSON(MAX)/180µA. Where: RDSON is the maximum on-resistance of the low side FET at the operating junction temperature RCS November 2009 18 30 A × 6mΩ = 2 = 500Ω 180μA M9999-111209-B Micrel, Inc. MIC2155/2156 Using the accurate method: D= The voltage across capacitor C1 is: VOUT 3 .3 = = 0 .3 VIN × Efficiency 12 × 0.9 sLo ⎤ ⎡ +1 ⎥ ⎢ RL ⎥ VS = IL × ⎢RL × sC1× R1 + 1⎥ ⎢ ⎥ ⎢ ⎦ ⎣ 3.3 × (1 − 0.3) = 3.1A 500kHz × 1.5μH 30 3.1 IPK = + = 16.55 A 2 2 3.3 × 100ns ISET = 16.55 − = 16.33 A 1.5μH 16.33 × 6mΩ RCS = = 544Ω 180μA IRIPPLE = If the R1 × C1 time constant is equal to the Lo/RL time constant, the voltage across capacitor C1 equals the RL × IL. Figure 17 is a plot of this equation and shows the results graphically. It assumes an inductance of 1.5µH, RL = 0.01Ω (-40dB), C1=0.1µF and R1=1.5k. The time constants are equal and diverge at the same rate. The overall impedance, H(s), equals RL for all frequencies. Using the simple method here would result in a current limit point lower than expected. This equation sets the minimum current limit point of the converter, but maximum will depend on the actual inductor value and on resistance of the MOSFET under current limit conditions. This could be in the region of 50% higher and should be considered to ensure that all the power components are within their thermal limits unless thermal protection is implemented separately. 50 GAIN (dB) 40 30 -50 10 H(s) 100 RC 1k 10k 100k FREQUENCY (Hz) 1M Figure 17. Current Sense Gain/Phase Plot Current Sharing The schematic in Figure 18 illustrates the current sharing scheme. The error amplifier in Channel 1, E/A 1, monitors the output voltage and adjusts the duty cycle of Channel 1 to regulate that voltage. The inputs of transconductance error amplifier, E/A 2, are connected to the current sense points of each channel. The error amplifier regulates Channel 2 current by monitoring the current sense point of Channel 1 and forcing the current sense point of Channel 2 to be equal. Any offset or difference in current between the two channels is caused by tolerances in the inductance, DCR, and tolerances of R1, C1, R2 and C2. Additionally, voltage offset in E/A 2 may cause variations in output current sharing. At lower currents, these variations may force the current of Channel 2 to be 0. A nominal 10mV offset inhibits the Channel 2 low-side MOSFET until the output current increases to the magnitude where the voltage across C1 is 10mV. This prevents the low-side MOSFET of Channel 2 from sinking current to ground during startup or during low current operation. Output Inductor and Winding Resistance Q2 Figure 16. Lossless Inductor Current Sense November 2009 0 -10 -20 -30 -40 Inductor Current Sensing Current sharing between the two phases is achieved by sensing the inductor current in each phase. Lossless inductor current sensing is used, which has the advantages of lower power loss and lower cost – over using a discrete resistor in series with the inductor. The inductor sense circuit is shown in Figure 16. It extracts the voltage drop across the inductor’s DC winding resistance. L/R 20 10 19 M9999-111209-B Micrel, Inc. MIC2155/2156 VIN E/A 1 Output1 Inductor and Winding Resistance Q1 PWM 1 IL RL1 L1 Driver VREF CO C1 R1 Q2 + VS – MIC2155/56 10mV VIN Q3 E/A 2 PWM 2 Driver Output2 Inductor and Winding Resistance IL RL2 R2 Q4 L2 C2 Figure 18. Current Sharing Diagram Startup into a Pre-Biased Output Soft start circuitry in a conventional synchronous buck regulator forces the regulator to start up by initially operating at a minimum duty cycle and gradually increasing the duty cycle until the output voltage reaches regulation. In a synchronous buck power supply, a narrow duty cycle means the low-side MOSFET is on for most of the switching period. If the output voltage is not 0V, the wide on time of the low-side MOSFET may discharge the output and cause high reverse current to flow in the inductor. The MIC2155/6 is designed to turn on into a pre-biased output without discharging the output. Circuitry in the controller monitors the input and output voltage and forces the soft start circuit to initially operate at the proper duty cycle. This allows the output to turn on in a controlled fashion without discharging the output. The minimum output voltage for proper operation of the prebias startup circuitry is 0.6V. If VOUT is less than 0.6V, a partial discharge of VOUT may occur. November 2009 Separate Input Supplies The MIC2155/6 can operate from two different input supplies with different voltages. Each of the two channels can have a different input voltage and still share current. This allows the supply to draw power from more than one supply. The controller will force the output current to be equal. Since the output voltage and currents of the two channels are the same, the input power drawn from each supply will approximately be the same. The input currents will be inversely proportional to the input voltages of each supply. For example, if the total output power is 50W and efficiency is 91%, the total input power from both supplies is: PIN = 20 POUT 50 = = 55 W η 0. 9 M9999-111209-B Micrel, Inc. MIC2155/2156 will also require more output capacitance to smooth out the larger ripple current. Smaller peak to peak ripple currents require a larger inductance value and therefore a larger and more expensive inductor. Higher switching frequencies allow the use of a small inductance but increase power dissipation in the inductor core and MOSFET switching loss. The MIC2155 switches at 500kHz/channel and is designed to use a smaller inductor at the expense of higher switching losses and slightly lower efficiency. While the 300kHz MIC2156 was optimized for higher efficiency and higher output current but its lower switching frequency requires a larger output inductance to maintain the same peak-topeak output ripple current. The peak output ripple current for a two-phase converter is shown in Figure 19. The graph shows that peak ripple current is a function of duty cycle. Since each channel is 180° out of phase with the other, at 50% duty cycle, the output ripple currents from each channel cancel and output ripple current is close to zero. Each supply contributes approximately half the power: PIN1 = PIN2 = 27.5 W For VIN1 = 12V and VIN2 = 3.3V IIN1 = 27.5 W = 2 .3 A 12V and IIN2 = 27.5 W = 8. 3 A 3 .3 V Component Selection, Guidelines and Design Example The following section outlines a procedure for designing a two-phase synchronous buck converter using the MIC2155. This example will use the following parameters: NORMALIZED OUTPUT RIPPLE CURRENT VIN = 12V VOUT = 1.8V IOUT = 30A Switching frequency (fS) = 500kHz/channel (MIC2155) Output Filter Selection The output filter is comprised of the output capacitors and the output inductors. The filter is designed to attenuate the output voltage ripple to the desired value. The output filter components also determine how well the supply responds to output current transients. If output transients are significant, the output capacitors should be chosen first to meet the transient specification. The output inductor is then selected to insure the filter attenuates the output ripple to meet the specification. A second, commonly used method of designing the filter is to select the inductor value to keep the ripple current between 20% and 30% of the output current for that channel. Then select the output capacitance to meet the output voltage ripple specification and output current transient specification. Values for inductance, peak and RMS currents are required to choose the output inductors. The input and output voltages and the inductance value determine the peak to peak inductor ripple current. Output capacitor selection requires calculation of transient current, RMS capacitor current and output voltage. There are several tradeoffs to be made when selecting the output inductor. Generally, higher inductance values are used with higher input voltages. Larger peak to peak ripple currents will increase the power dissipation in the inductor and MOSFETs. Larger output ripple currents November 2009 1.0 0.9 0.8 0.7 0.6 Single Phase 0.5 0.4 0.3 0.2 0.1 2 Phase 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 DUTY CYCLE Figure 19. 2 Phase Output Ripple Current vs. Duty Cycle For this example, with VIN = 12V, VOUT = 1.8V and efficiency = 88%, the duty cycle is: D= VOUT 1. 8 V = = 0.17 η × VIN 0.88 × 12 Figure 19 shows the peak-to-peak output ripple current normalized to: VOUT fS × L OUT The peak-to-peak output ripple current is less than for a single phase conversion. If VIN varies, the input voltage that generated the highest ripple current should be used for the calculation. 21 M9999-111209-B Micrel, Inc. MIC2155/2156 For this example, assume the output transient loading is small and the filter design is based on output ripple voltage requirement. The inductance value is calculated by the equation below: The peak inductor current in each channel is equal to the average output current plus one half of the peak to peak inductor ripple current: VOUT × (η × VIN(MAX ) − VOUT ) The RMS inductor current is used to calculate the I2 × R losses in the inductor: L= IPK = IOUT + 0.5 × IPP = 15 A + 0.5 × 3 A = 16.5 A η × VIN(MAX ) × fS × 0.2 × IOUT Where: 1 ⎛ IPP ⎜ IINDUCTOR(RMS) = IOUT × 1 + 12 ⎜⎝ IOUT fS is the switching frequency 0.2 is the ratio of AC ripple current to DC output current VIN(MAX) is the maximum input voltage IOUT is output current of the each channel or ½ of the total output current η is the converters efficiency If another inductor value is used, the ripple current for each channel is calculated from the formula below: IPP = VOUT × (η × VIN(MAX ) − VOUT ) η × VIN(MAX) × fS × L 1.8 V × (0.88 × 12V − 1.8 V ) = 3A 0.88 × 12V × 500kHz × 1μH The output capacitors see less ripple current than each channel because they are out of phase. The normalizing factor is: VOUT 1 .8 V = = 3 .6 fS × L OUT 500kHz × 1μH PINDUCTOR(COPPER) = (IINDUCTOR(RMS))2 x RWINDING = 15.12 x 1.9mΩ = 0.43W The output ripple current in the two-phase configuration is approximately: 0.65 × 1 ⎛ 3A ⎞ ⎟ = 15.1A ⎜ 12 ⎝ 15 ⎠ Maximizing efficiency requires the proper selection of core material and minimizing the winding resistance. The high frequency operation of the MIC2155 requires the use of ferrite materials for all but the most cost sensitive applications. Lower cost iron powder cores may be used but the increase in core loss will reduce the efficiency of the power supply. This is especially noticeable at low output power. The inductor winding resistance decreases efficiency at the higher output current levels. The winding resistance must be minimized although this usually comes at the expense of a larger inductor. The power dissipated in the inductor is equal to the sum of the core and copper losses. At higher output loads, the core losses are usually insignificant and can be ignored. At lower output currents the core losses can be a significant contributor. Core loss information is usually available from the magnetics vendor. For this example a Cooper HCF1305-1R0 inductor was chosen. Core loss for this application was taken from the data sheet and is 15mW. Winding resistance is 1.9mΩs Copper loss in the inductor is calculated by the equation below: 1.8 V × (0.88 × 12 V − 1.8 V ) = 1μH 0.88 × 12V × 500kHz × 0.2 × 15 A IPP = 2 2 IINDUCTOR(RMS) = 15 A × 1 + For this example: L= ⎞ ⎟⎟ ⎠ VOUT 1. 8 V = 0.65 × = 2. 3 A fS × L OUT 500kHz × 1μH For the input and output voltage in this application, going to a two-phase design decreased the total output ripple current from 3APP to 2.3APP. November 2009 22 M9999-111209-B Micrel, Inc. MIC2155/2156 The resistance of the copper wire, RWINDING, increases with temperature. If so desired, a more accurate calculation can be made if the maximum ambient temperature and temperature rise of the inductor is known. The value of the winding resistance at operating temperature is calculated with the formula below: For this example, using ΔVOPP = 10mV, the minimum COUT is: RWINDING(HOT) = RWINDING(20) x (1 + 0.0042 x (TempHOT – T20) A capacitance value this low is usually not used in high current converters because of transient output current requirements. For this example, 500µF total capacitance is used. It is split up into (4) 47µF ceramic capacitors and (2) 150µF Aluminum Polymer capacitors The total output ripple is a combination of the ESR and the output capacitance. The total ripple is calculated below: COUT ≥ Where: TempHOT is the temperature of the wire under operating load T20 is the ambient temperature RWINDING(20) is the resistance of the winding at room temperature, usually specified by the manufacturer. 2 .3 = 29μF 8 × 10mV × 2 × 500kHz 2 For this example, the approximate power dissipation is 0.43W. From the manufacturers data sheet this causes a 20°C rise in inductor temperature. Assuming ambient temperature stayed at 20°C, the maximum winding resistance would be increased from 1.9mΩs to: ΔVOUT To increase reliability, the recommended voltage rating of capacitor should be twice the output voltage for a tantalum and 20% greater for an aluminum electrolytic or ceramic. The output capacitor RMS current is calculated below: R WINDING(HOT ) = 1.9mΩ × (1 + 0.0042 × ( 40°C − 20°C) = 2.06mΩ Output Capacitor Selection In this example, the output capacitors are chosen to keep the output voltage ripple below a specified value. The output ripple voltage is determined by the capacitors ESR (equivalent series resistance) and capacitance. Voltage rating and RMS current capability are two other important factors in selecting the output capacitor. Ceramic output capacitors and most polymer capacitors have very low ESR and are recommended for use with the MIC2155/6. The output capacitance is usually the primary cause of output ripple in ceramic and very low ESR capacitors. The minimum value of COUT is calculated below: COUT ≥ ⎡ ⎤ IPP 2 = ⎢ ⎥ + [IPP × RESR ] ⎣ 8 × COUT × 2 × fS ⎦ I 2. 3 A ICOUT(RMS) = PP = = 0.66 A 12 12 The power dissipated in the output capacitors can be calculated by the equation below: ( ) PDISS(COUT ) = ICOUT(RMS) 2 × RESR IPP 8 × ΔVOPP × 2 × fS Where: ΔVOPP is the peak-to-peak output voltage ripple IPP is the peak-to-peak ripple current as see by the capacitors fS is the per channel switching frequency Notice the calculation is performed at 2x the switching frequency since the capacitors see ripple current from both phases. November 2009 23 M9999-111209-B Micrel, Inc. MIC2155/2156 The power dissipated in the input capacitor is: Inductor Current Sense Components The RC circuit values that sense current across the inductor can be calculated once the inductor is selected. The circuit is shown in Figure 20. ( ) MORMALIZED RMS INPUT CURRENT PDISS(CIN) = ICIN(RMS) 2 × RESR Output Inductor and Winding Resistance Q2 Figure 20. Inductor Current Sense 0.6 Single Phase 0.5 0.4 0.3 2 Phase 0.2 0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 DUTY CYCLE Figure 21. RMS Input Current vs. Duty Cycle The inductor has the following values: MOSFET Selection External N-channel logic level power MOSFETs must be used for the high and low side switches. The MOSFET gate to source drive voltage of the MIC2155 is regulated by an internal 5V VDD regulator. Logic level MOSFETs, whose operation is specified at VGS = 4.5V must be used. This resistance is used to calculate the losses during the MOSFET’s conduction time. If operating at 4.5VIN, without connecting VDD to VIN, the gate drive voltage to the high-side FET could be as low as 3.2V. MOSFETs with low VGS enhanced gates should be used in this situation. It is important to note the on-resistance of a MOSFET increases at high junction temperature. A 75°C rise in junction temperature will increase the channel resistance of the MOSFET by 40% to 75% of the resistance specified at 25°C. This change in resistance must be accounted for when calculating MOSFET power dissipation. Total gate charge is the charge required to turn the MOSFET on and off under specified operating conditions (VDS and VGS). The gate charge is supplied by the MIC2155 gate drive circuit. Gate charge can be a significant source of power dissipation in the controller due to the high switching frequencies and generally large MOSFETs that are driven. At low output load this power dissipation is noticeable as a reduction in efficiency. L = 1.0µH, R L= 1.9mΩ Proper sensing of the DC voltage across the inductor requires the RL/L time constant be equal to the R1×C1 time constant: L = C1× R1 RL A good range of values for C1 is 0.1µF to 1µF. For this example C1 is chosen as 0.22µF. R1 is: R1 = L 1μH = = 2.39k RL × C1 1.9mΩ × 0.22μF Input Capacitor Selection In addition to high-frequency ceramic capacitors, a larger bulk capacitance, either ceramic or Al. El. should be used to help attenuate ripple on the input and to supply current to the input during large output current transients. The input capacitors must be rated for the RMS input current of the power supply. RMS input capacitor current is determined at the maximum output current. The graph in Figure 21 shows the normalized RMS input ripple current vs. duty cycle. Data is normalized to the output current. For a two-phase converter operating at 17% duty cycle, the input RMS current is determined from the graph: ICIN _ RMS ≈ IOUT × 0.24 = 7.2A November 2009 24 M9999-111209-B Micrel, Inc. MIC2155/2156 Making the assumption the turn-on and turn-off transition times are equal, the total AC switching loss is: The average current required to drive the MOSFETs is: IDD = Qg × fs PAC = ( VIN +VD ) × ISW _ PEAK × Tt × fS Where: Where: Qg is the total gate charge for all high and low side MOSFETs. This information should be obtained from the manufacturer’s data sheet with a 5V VGS. Since the current from the gate drive comes from the input voltage, the power dissipated in the MIC2155 due to gate drive is: Tt is the switching transition time (typically 15ns to 30ns) fS it the switching frequency of each phase RMS Current and MOSFET Power Dissipation Calculation Under normal operation, the high side MOSFET’s RMS current is greatest when VIN is low (maximum duty cycle). The low side MOSFET’s RMS current is greatest when VIN is high (minimum duty cycle). However, the MOSFET sees maximum stress during short circuit conditions, where the output current is equal to the maximum overcurrent level. The calculations below are for normal operation. To calculate the stress under short circuit conditions, substitute the maximum overcurrent level for IOUT(max). The RMS value of the high side switch current is: PGATE _ DRIVE = Qg × fS × VIN A convenient figure of merit for switching MOSFETs is the on-resistance times the total gate charge (RDSON × Qg). Lower numbers translate into higher efficiency. Low gate charge, logic level MOSFETs are a good choice for use with the MIC2155. The internal LDO that supplies VDD is rated for 75mA. Exceeding this value could damage the regulator or cause excessive power dissipation in the IC. Refer to the “Supply Voltages and Internal Regulator” section of this specification for additional information. Parameters that are important to MOSFET switch selection are: I 2 ISW _ RMS(HIGH _ SIDE ) = D (IOUT(max)2 + PP ) 12 • Voltage rating • On resistance • Total Gate Charge The VDS voltage rating of the MOSFETs is essentially equal to the input voltage. A safety factor of 20% should be added to the VDS(max) of the MOSFETs to account for voltage spikes due to circuit parasitics. The power dissipated in the switching transistor is the sum of the conduction losses during the on-time (PCONDUCTION) and the switching losses that occur during the period of time when the MOSFETs turn on and off (PAC). I 2 ISW _ RMS(LOW _ SIDE ) = (1 − D) (IOUT(max)2 + PP ) 12 Where: D is the duty cycle of the converter IPP is the individual inductor ripple current V D = OUT η × VIN and η is the efficiency of the converter. Converter efficiency also depends on other component parameters that have not yet been selected. For design purposes, an efficiency estimate of 85% – 90% can be used. The efficiency can be more accurately calculated once the design is complete. If the assumed efficiency is grossly inaccurate, a second iteration through the design procedure should be made. For the high-side switch, the maximum DC power dissipation is: PSW = PCONDUCTION + PAC Where: PCONDUCTION = ISWITCH(rms )2 × RSWITCH PAC = PAC(off ) + PAC(on) RSWITCH is the on resistance of the MOSFET switch. ( ) PSWITCH1(DC) = RDSON1 × ISW1(rms ) 2 November 2009 25 M9999-111209-B Micrel, Inc. MIC2155/2156 This power dissipation is calculated below: For the low-side switch, the DC power dissipation is: ( ) PSWITCH 2(DC) = RDSON2 × ISW 2(rms ) 2 ID(ave ) = IOUT × 2 × t d × fS The switching loss for each of the high-side MOSFETs is: Where: td is the dead time when both MOSFETs are off. The reverse voltage requirement of the diode is: PAC = VIN × ISW (peak ) × Tt × fS VDIODE _ RRM = VIN The total power dissipation for each MOSFET is: The power dissipated by the diode is: PFET _ total = PSWITCH1(DC) + PAC External Schottky Diode A freewheeling diode in parallel with the low-side FET is needed to keep the inductor current flow continuous while both MOSFETs are turned off (dead time). Dead time is necessary to prevent current from flowing unimpeded through both MOSFETs. An external Schottky diode is not necessary for circuit operation since the low-side MOSFET contains a parasitic body diode. An external diode will improve efficiency due to its lower forward voltage drop as compared to the internal parasitic diode in the FET. It may also decrease high frequency noise because the schottky diode junction does not suffer from reverse recovery. If the MOSFET body diode is used, it must be rated to handle the peak and average current. The body diode may have a relatively slow reverse recovery time and a relatively high forward voltage drop. The power lost in the diode is proportional to the forward voltage drop of the diode. As the high-side MOSFET starts to turn on, the body diode becomes a short circuit for the reverse recovery period, dissipating additional power. The diode recovery and the circuit inductance will cause ringing during the high-side MOSFET turn on. If the internal FET diode is used, power dissipated during the dead time should be added to the PDISS of the low-side MOSFET. An external Schottky diode conducts at a lower forward voltage preventing the body diode in the MOSFET from turning on. The lower forward voltage drop dissipates less power than the body diode. The lack of a reverse recovery mechanism in a Schottky diode causes is less ringing and power loss. Depending on the circuit components and operating conditions, an external Schottky diode may give a ½% to 1% improvement in efficiency. PDIODE = ID _ AVE × VF Where: VF is the forward voltage at the peak diode current. Snubber Design A snubber is used to damp out high frequency ringing caused by parasitic inductance and capacitance in the buck converter circuit. A snubber is needed for each of the two phases in the converter. Figure 22 shows a simplified schematic of one of the buck converter phases. Stray capacitance consists mostly of the two MOSFET’s output capacitance (COSS). The stray inductance is mostly package and etch inductance. The arrows show the resonant current path when the high side MOSFET turns on. This ringing causes stress on the semiconductors in the circuit as well as increased EMI. COSS1 + LSTRAY1 LSTRAY2 L Q1 CIN VDC LSTRAY3 Sync_buck Controller Q2 COSS2 COUT LSTRAY4 – Figure 22. Output Parasitics November 2009 26 M9999-111209-B Micrel, Inc. MIC2155/2156 One method of reducing the ringing is to use a resistor and capacitor to lower the Q of the resonant circuit. The circuit in Figure 23 shows the resistor in between the switch node and ground. Capacitor Cs is used to block DC and minimize the power dissipation in the resistor. This capacitor value should be between 5 and 10 times the parasitic capacitance of the MOSFET COSS. A capacitor that is too small will have high impedance and prevent the resistor from damping the ringing. A capacitor that is too large causes unnecessary power dissipation in the resistor, which lowers efficiency. The snubber components should be placed as close as possible to the low-side MOSFET and/or external schottky diode since in contributes to most of the stray capacitance. Placing the snubber too far from the FET or using etch that is too long or thin will add inductance to the snubber and diminishes its effectiveness. A proper snubber design requires the parasitic inductance and capacitance be known. A method of determining these values and calculating the damping resistor value is outlined below. 1. Measure the ringing frequency at the switch node which is determined by parasitic LP and CP. Define this frequency as f1. 2. Add a capacitor CS (normally at least 3 times as big as the COSS of the FET) from the switch node to ground and measure the new ringing frequency. Define this new (lower) frequency as f2. LP and CP can now be solved using the values of f1, f2 and CS. Define f’ as: f f' = 1 f2 Combining the equations for f1, f2 and f’ to derive CP, the parasitic capacitance: CP = LP = Q= × CP × ( f1)2 1 RS LP =1 CS Solving for RS RS = LP CS Figure 23 shows the snubber in the circuit and the damped switch node waveform. 1 2π LP × CP LSTRAY1 Where: CP and LP are the parasitic capacitance and inductance LSTRAY2 RDS LSTRAY3 Step 2: Add a capacitor, CS, in parallel with the synchronous MOSFET, Q2. The capacitor value should be approximately 3 times the COSS of Q2. Measure the frequency of the switch node ringing, f2: November 2009 (2π) 1 2 Step 3: Calculate the damping resistor. Critical damping occurs at Q = 1: damping. Step 1: First measure the ringing frequency on the switch node voltage when the high-side MOSFET turns on. This ringing is characterized by the equation: f2 = 2 × ( f ' )2 − 1 LP is solved by re-arranging the equation for f1: 3. Add a resistor RS in series with C S to generate critical f1 = CS RS COSS2 CS LSTRAY4 1 2π Lp × (Cs + Cp) Figure 23. Snubber Circuit 27 M9999-111209-B Micrel, Inc. MIC2155/2156 Compensation is necessary to insure the control loop has adequate bandwidth and phase margin to properly respond to input voltage and output current transients. High gain at DC and low frequencies is needed for accurate output voltage regulation. Attenuation near the switching frequency prevents switching frequency noise from interfering with the control loop. For this analysis, the LC filter in the two phase design is combined into one. The inductances are in parallel and the output capacitance is the total sum of all COUT. The ESR is the parallel combination of all ESRs. The output load is represented by a resistor R. The output filter contains a complex double pole formed by the capacitor and inductor and a zero from the output capacitor and it’s ESR. The transfer function of the filter is: The snubber capacitor, CS, is charged and discharged each switching cycle. The energy stored in CS is dissipated by the snubber resistor, RS, two times per switching period. This power is calculated in the equation below: PSNUBBER = fS × CS × VIN2 Where: fS is the switching frequency for each phase VIN is the DC input voltage Compensation of the Output Voltage Loop The voltage regulation, filter and power stage section is shown in Figure 24. The error amplifier for Channel 1 is used to regulate the output voltage and compensate the voltage regulation loop. It is a voltage output op amp that is designed to use type III (PID) compensation. Type III compensation has two compensating zeros, two poles and a pole at the origin. The figure also shows the transfer function for each section. 1+ Gfilter(s) = 1+ s ωz s ⎛ s ⎞ +⎜ ⎟ 2 × Q × ω o ⎝ ωo ⎠ 2 Where: ωz = ωo = 1 CO × Re sr 1 CO × L O Q = R× CO L C1 E/A R2 C2 C3 R3 VIN Modulator Q1 R1 Filter L1 || L2 Driver CO R4 VREF = 0.7V Q2 RESR R Figure 24. Voltage Loop and Transfer Functions November 2009 28 M9999-111209-B Micrel, Inc. MIC2155/2156 The Modulator Gain is proportional to the input voltage and inversely proportional to the internal ramp voltage generated by the oscillator. The MIC2155/6 peak-peak ramp voltage is 1V: As the frequency approaches the zero frequency (Fz), formed by Co and it’s ESR, the slope of the gain curve changes from -40db/dec. to -20db/dec and the phase increases. The zero causes a 90° phase boost. Ceramic capacitors, with their smaller values of capacitance and ESR, push the zero and its phase boost out to higher frequencies, which allow the phase lag from the LC filter to drop closer to -180°. The system will be close to being unstable if the overall open loop gain crosses 0dB while the phase is close to -180°. If the output capacitance and/or ESR is high, the zero moves lower in frequency and helps to boost the phase, leading to a more stable system. The error amplifier is a type III which has two zeros, two poles and a pole at the origin. This type of error amplifier works well when Ceramic output capacitors make up the majority of COUT because it introduces an extra zero that helps improve phase margin: ⎛ VIN ⎞ ⎟⎟ GMOD = ⎜⎜ ⎝ VRAMP ⎠ The output voltage divider attenuates VOUT and feeds it back to the error amplifier. The divider gain is: H= R4 V = REF R1 + R4 VOUT The modulator, filter and voltage divider gains can be multiplied together to show the open loop gain of these parts: s ⎞⎛ s ⎞ ⎛ ⎜1 + ⎟⎜1 + ⎟ ω z 1 ω z2 ⎠ ⎝ ⎠ ⎝ Gea(s) = s ⎛ s ⎞⎛ s ⎞ ⎜1 + ⎟⎜1 + ⎟ ωpo ⎜⎝ ωp1 ⎟⎠⎜⎝ ωp2 ⎟⎠ G VD (s) = GFILTER (s) × H × GMOD This transfer function is plotted in Figure 25. At low frequency, the transfer function gain equals the modulator gain times the voltage divider gain. As the frequency increases toward the LC filter resonant frequency, the gain starts to peak. The increase in the gain’s amplitude equals Q. Just above the resonant frequency, the gain drops at a -40db/decade rate. The phase quickly drops from 0° to almost 180° before the phase boost of the zero brings it back up to -90°. Higher values of Q will cause the phase to drop quickly. In a well damped, low Q system the phase will change more slowly. Where: 1 R2 × C2 1 ωz 2 = (R1 + R3) ⋅ C3 1 ωpo = R1× C1 1 ωp1 = C1× C2 ⋅ R2 C1 + C2 1 ωp 2 = R3 × C3 ωz1 = 90 GAIN/PHASE 45 0 Gain Figure 26 shows the bode plot of the error amplifier transfer function. -45 Phase -90 -135 -180 10 100 1k 10k 100k FREQUENCY 1M Figure 25. GVD Transfer Function November 2009 29 M9999-111209-B Micrel, Inc. MIC2155/2156 Z2 1 Z0 = 2 ⋅ π ⋅ R1 ⋅ C 2 1 2 . π . ( R1 P1 R3 ) . C3 Step 3: Determine the gain boost needed at the crossover frequency (fc) Typically, 50° of phase margin can be used for most applications. This is a good tradeoff between an overdamped system (slower response to transients) and an underdamped system (overshoot or unstable response to transients). It also allows some margin for component tolerances and variations due to ambient temperature changes. The phase margin at the crossover frequency (fc) can be determined by plotting the GVD(s) phase on a bode plot or can be estimated with the following formula: 1 C2 . C1 . R2 2.π . C2 C1 R2 20. log R1 Z1 1 2 . π . R2 . C2 P2 1 2 . π . R3 . C3 ϕM ⎡ ⎤ fc ⎢ ⎥ ⎡ fc ⎤ −1 ⎢ Q × fo ⎥ = tan ⎢ + tan −1 ⎢ ⎥ 2⎥ ⎣ fz ⎦ ⎢1 − ⎛⎜ fc ⎞⎟ ⎥ ⎢⎣ ⎝ fo ⎠ ⎥⎦ The additional phase boost required from the error amplifier is: Figure 26. Type III Error Amplifier Gain/Phase Error Amplifier Design Procedure ϕBoost = 52° − ϕM Step 1: Decide on the crossover frequency To maximize transient response, the open loop bandwidth should be made reasonably high. Initially, the bandwidth can be selected to be 1/10 of the output switching frequency. This may be improved once the design is built and measurements are made. An initial bandwidth of 100kHz for the 2155 and 60kHz for the 2156 are good choices. Step 4: Determine the frequencies fz2 and fp1 The frequencies for the zero and pole (fz2 and fp1) are calculated for the desired amount of phase boost at the crossover frequency (fc): Step 2: Determine the gain required at the crossover frequency GBoost is how much gain boost is needed so the open loop transfer function crosses 0dB at the pre-determined crossover frequency. This can be measured by plotting the GVD(s) transfer function or can be estimated with the following formula: GBoost = 1 − sin[ϕBoost ] 1 + sin[ϕBoost ] fp1 = fc × 1 + sin[ϕBoost ] 1 − sin[ϕBoost ] Step 5: Determine the frequency for fz1 The low-frequency zero, fz1, is initially set to one-fifth of the LC resonant frequency. If it is set too low, it will force the low frequency gain to be low and impact transient response. If set too high, it will not add enough phase boost at the LC resonant frequency. This could cause conditional stability, which when the phase drops below 180° before the gain crosses 0dB. If the DC gain should drop in this situation, this may lead to an unstable system. 1 2 H × VIN ⎛ fo ⎞ ⎛ fc ⎞ ×⎜ ⎟ ×⎜ ⎟ VM ⎝ fc ⎠ ⎝ fz ⎠ Where: fo = LC filter resonant frequency fc= open loop bandwidth chosen in Step 1 fz = zero formed by COUT and its ESR H = voltage divider attenuation VM=amplitude of the internal sawtooth ramp (VM=1) VIN= Input voltage to the power supply November 2009 fz2 = fc × fz2 = 30 fo 5 M9999-111209-B Micrel, Inc. MIC2155/2156 Based on the amount of gain necessary at the crossover frequency the mid-band gain and R2 value is calculated using the following formula: Step 6: Determine the frequency for fp2 This is the high frequency pole, which is useful in additional attenuation of the switching frequency. It should initially be set at half of the switching frequency. If it is set too low, it will lower the phase margin at the crossover frequency, making it difficult to achieve the proper phase margin. If set too high, it will not provide attenuation of the switching frequency, which could lead to jitter of the switching waveform or instability under certain conditions. fp2 = 2 Vm fz2 ⎛ fo ⎞ ⎛ fc ⎞ ×⎜ ⎟ ×⎜ ⎟× H × Vin ⎝ fc ⎠ ⎝ fz ⎠ fp1 R2 = R1× GCO GCO = The other component values are calculated as follows: fs 2 Calculating Error Amplifier Component Values Once the pole and zero frequencies have been fixed, the error amplifier’s resistor and capacitor values are calculated. R1: This value is chosen first. All other component values are calculated from R1. A value of 10K is suggested. If R1 is chosen too high, R2 may be very large and the high impedances could be sensitive to noise. If the remote sense amplifier is used, R1 must be large enough so than not more than 500µA of current is drawn from the amplifier. R2: The value of R2 is determined from the mid-band gain of the error amplifier. This gain depends on the frequencies of the poles, zeros and LC filter resonant frequency. 1 2 × π × fz1× R2 C3 = 1 2 × π × fz2 × R1 C3 = C2 2 × π × ( fp1× C2 × R2 − 1) 1 2 × π × fp2 × C3 R3 = Compensation of the Current Sharing Loop The control circuitry for Channel 2 forces the channel’s output current to match the current in Channel 1. The Channel 2 error amplifier compares the inductor currents in the two channels and adjusts the duty cycle of Channel 2 to control its output current. A block diagram is shown in Figure 27. Filter VIN Modulator Channel 2 Transconductance E/A C2 = C2 R2 Q1 CZ1 Ramp L2 RL2 Driver RZ1 Q2 Channel 1 IL RL1 R1 L1 C1 CO Figure 27. Current Sharing Loop and Transfer Functions November 2009 31 M9999-111209-B Micrel, Inc. MIC2155/2156 Unlike the voltage output amplifier used for Channel 1 compensation, a transconductance amplifier is used for the Channel 2 compensation since only a pole/zero combination is required for compensation. The transconductance amplifier transfer function is: Gea(s) = gm × The loop is inherently stable because the phase shift is only 90 degrees. The error amplifier pole and zero is selected to achieve a desired crossover frequency. In this example, the desired crossover frequency is 50kHz. The transfer function of the filter, modulator and feedback is plotted in Figure 28. 1 + s × Rz1× Cz1 s × Cz1 50 GAIN/PHASE Where: Rz1 and Cz1 are the external components connected to the COMP2 pin gm is the transconductance of the internal amplifier. The pole and zero frequencies are: 0 Gain -50 Phase -100 10 gm fPOLE = 2 × π × Cz1 1 fZERO = 2 × π × Rz1× Cz1 100 1k 10k 100k FREQUENCY 1M Figure 28. Current Sharing Loop Gain/Phase The gain boost required at 50kHz is 28dB which is a gain of 25. The gain for frequencies above the zero is: The gain of the modulator is: gMOD = VIN = 12V VOUT = 1.8V L = 1.5µH GMID = Rz1× gm 1 VM For a typical gm = 1.25mS, solving for Rz1: Rz1 = Where: VM is the peak-to-peak amplitude of the internal sawtooth. The gain of the feedback circuit is output current divide by VEA GMID 25 = = 20kΩ gm 1.25mS Set the zero frequency to be 1/5 of the crossover frequency: H = RL 2 1 2 × π × Rz1× fz1 1 Cz1 = = 800pF 2 × π × 20k × 10k The filter transfer function is the output current over the applied voltage: Cz1 = V − VOUT GFILTER( s) = IN s × L2 The compensated open loop gain/phase plot is shown in Figure 29. The open loop transfer function is: GOL 2( s) = GEA ( s) × GMOD × H × GFILTER( s) = gm × (1 + s × Rz1× Cz1) × RL 2 × (VIN − VOUT ) (s × Cz1) × Vm × (s × L2) November 2009 32 M9999-111209-B Micrel, Inc. MIC2155/2156 200 fZERO = 10kHz fC = 50kHz Phase margin = 80° 134.17466 bb(f) Gain -100 -179.9424 -200 10 Cin 0 HSFET GAIN/PHASE 100 Phase 100 1k 10k 100k FREQUENCY 1M Figure 29. Compensated Current Sharing Loop Gain/Phase Figure 31. Layout General Layout and Component Placement There are three basic types of currents in a switching power supply – high di/dt, moderate di/dt and DC. Examples of each are shown in Figure 30. Moderate di/dt currents flow in the inductor and output capacitor. Although layout is not as critical, it is still important to minimize inductance by using short, wide traces and a ground plane. Figure 31 shows the etch connecting the inductor to the output is shaped to force current to flow past the output capacitor before reaching the output terminal (or output load). This minimizes the series inductance between the inductor and the capacitor, which improves the ability of the capacitor to filter ripple. Additionally, the inductor current has a large DC component and requires a wide trace to minimize voltage drop and power dissipation. DC currents in a high-current buck converter require wide etch paths to minimize voltage drop and power dissipation. The input and output current are mainly DC. At or near maximum output power, the inductor current is also predominately DC and requires ample etch to reduce copper loss, reduce temperature rise and improve efficiency. Minimizing voltage drops in the output and ground path helps improve output voltage regulation for configurations without remote voltage sensing. The gate drive connections to both the high-side and low-side MOSFETs must each have their own return current path. The high-side MOSFET’s source is connected to the switch node and returns back to the controller’s SW1 or SW2 pin. The high-side gate drive and return (switch node) traces should be routed on top of each other on adjacent layers to minimize inductance. These traces swing between VIN and ground and should be routed away from low-voltage and noise-sensitive analog etch or components. The low-side MOSFET return path is power ground. High di/dt currents flow in the low-side gate drive and return paths. These must be kept away from noise sensitive signal traces and signal ground planes. Figure 30. Current Diagram In a buck converter, high di/dt currents in the 0.5A/ns range are generated by MOSFETs switching on and off. These fast switching currents flow in the high and lowside MOSFETs, external freewheeling schottky diode and the input capacitor. Fast switching currents also flow in the gate drive and return etch between the controller and the power FETs. At that switching speed at 10nH piece of etch generates 5V across itself. Therefore, attention to proper layout techniques is essential. Traces that have high di/dt currents must be kept short and wide. Additionally a power ground plane should be used on an adjacent layer to help minimize etch inductance. Figure 31 shows a layout example that minimizes inductance. November 2009 33 M9999-111209-B Micrel, Inc. MIC2155/2156 • These analog signals should be referenced or decoupled to the analog ground plane: AVDD, SYNC, EN, SS, PGOOD, COMP1, COMP2, FB2, EA2, VOUT, FB1, AGND • Place the current sharing RC components (that connect across the inductor) and any related filtering components close to the FB2, EA2+ and VOUT pins (18, 17, 20). The traces connecting the inductors and these components should be routed close together to minimize pickup or EMI radiation. • Place the overcurrent sense resistor close to the CS1 pin (pin 4). The trace coming from the switch node to this resistor has high dv/dt and should be routed away from other noise sensitive components and traces. • The remote sense traces must be routed close together or on adjacent layers to minimize noise pickup. The traces should be routed away from the switch node, inductors, MOSFETs and other high dv/dt or di/dt sources. Ceramic capacitors are recommended for most decoupling and filtering applications because of their low impedance and small size. Depending on the application, most dielectrics (X5R, X7R, NPO) are acceptable, however, Z5U type ceramic capacitor dielectrics are not recommended due to their large change in capacitance over temperature and voltage. Design and Layout Checklist • Ceramic capacitor placed between the HS FET drain and the LSFET source. • MOSFET gate drive traces must be low inductance and routed away from noise sensitive analog signals, components and ground planes. • The signal and power ground planes must be separated to prevent high current and fast switching signals from interfering with the low level, noise sensitive analog signals. These planes should be connected at only 1 point, next to the MIC2155/6 controller. • The following signals and their components should be decoupled or referenced to the power ground plane: VIN1, VIN2, VDD, PGND1, PGND2 November 2009 34 M9999-111209-B Micrel, Inc. MIC2155/2156 Package Information 32-Pin MLF® (ML) MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. © 2009 Micrel, Incorporated. November 2009 35 M9999-111209-B