Freescale Semiconductor, Inc. Application Note Document Number: AN4991 Rev. 2.0, 3/2015 Power Management of Xilinx AP SoC Using Freescale PMIC Featuring the MMPF0100 1 Introduction This document provides a power management solution for Xilinx Zynq®-7000 System-on-Chips (SoCs), with the Xilinx ZedBoard highlighted as a design example. The ZedBoard is a development board with a broad range of expansion options and the Zynq®7000 as its on-board processor. The document presents the power rail requirements of the Xilinx Zynq®-7000 All Programmable SoCs, many of which are also applicable to Xilinx Field Programmable Gate Arrays (FPGAs). For more details about the specific devices contained in this note, visit www.freescale.com or contact the appropriate product application team. The PF0100 is Freescale's Power Management IC (PMIC) that integrates a total of 14 regulators. Its flexibility in the range of voltage and current options makes it an optimum choice in a wide range of applications. This application note addresses the ability of the PF0100 to provide an optimal solution to the power requirements of a Zynq®-7000 based system taking into account typical I/O, memory and peripherals that are interfaced with the ZedBoard. Freescale analog ICs are manufactured using the SMARTMOS process, a combinational BiCMOS manufacturing flow that integrates precision analog, power functions and dense CMOS logic together on a single cost-effective die. © Freescale Semiconductor, Inc., 2015. All rights reserved. Contents 1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 ZedBoard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 Zynq®-7000 SoC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 MMPF0100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5 Power Solution for the ZedBoard . . . . . . . . . . . . . . . . . . . . 11 6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 ZedBoard 2 ZedBoard 2.1 ZedBoard Overview The Xilinx ZedBoard is an evaluation and development board based on the Xilinx Zynq®-7000 All Programmable SoC (AP SoC). The ZedBoard provides appropriate hardware capabilities for interfacing with a number of peripherals and compatible expansion headers for Xilinx Analog to Digital Convertor (XADC), FPGA Mezzanine Card (FMC) and Diligent Pmod™. 2.2 ZedBoard Features The ZedBoard features are: Table 1. ZedBoard Features Feature Description Processor Zynq®-7000 AP SoC XC7Z020-CLG484-1 Memory 512 MB DDR3 256 Mb Quad-SPI Flash 4.0 GB SD card Communication Onboard USB-JTAG Programming 10/100/1000 Ethernet USB OTG 2.0 and USB-UART Expansion Connectors Expansion connectors FMC-LPC connector (68 single-ended or 34 differential I/Os) Five Pmod™ compatible headers (2x6) Agile Mixed Signaling (AMS) header Clocking 33.33 MHz clock source for PS 100 MHz oscillator for PL Display HDMI output supporting 1080p60 with 16-bit, YCbCr, 4:2:2 mode color VGA output (12-bit resolution color) 128 x 32 OLED display Configuration and Debug Onboard USB-JTAG interface Xilinx Platform Cable JTAG connector General Purpose I/O Eight user LEDs Seven push buttons Eight DIP switches AN4991 Application Note Rev. 2.0 3/2015 2 Freescale Semiconductor, Inc. . Zynq®-7000 SoC 3 Zynq®-7000 SoC 3.1 Zynq®-7000 SoC Overview The Xilinx Zynq®-7000 is a family of All Programmable SoCs, aimed at a range of applications from radio and LTE to defense-grade applications. The versatile nature and adaptability of the SoC makes it suitable for multiple applications. The Zynq®-7000 SoC in discussion here, XC7Z020-CLG484-1, has an ARM® Cortex A9 processor with a maximum frequency capability of 667 MHz. 3.2 Zynq®-7000 SoC Features The Zynq®-7000 SoC features include: Table 2. Zynq-XC7Z020-CLG484-1 Features Feature Description Processor Core Dual ARM® Cortex™-A9 MPCore™ with CoreSight™ Processor Extensions NEON™ and Single/Double Precision Floating Point for each processor Maximum Frequency 667 MHz L1 Cache 32 KB Instruction, 32 KB Data per processor L2 Cache 512 KB On-Chip Memory 256 KB External Memory Support DDR3, DDR3L, DDR2, LPDDR2 External Static Memory Support 2x Quad-SPI, NAND, NOR DMA Channels Eight (4 dedicated to Programmable Logic) Peripherals 2x UART, 2x CAN 2.0B, 2x I2C, 2x SPI, 4x 32b GPIO Peripherals w/ Built-in DMA 2x USB 2.0 (OTG), 2x Tri-mode Gigabit Ethernet, 2x SD/SDIO Security RSA Authentication of First Stage Boot Loader, AES and SHA 256b Decryption and Authentication for Secure Boot and for Secure Programmable Logic Configuration Processing System to Programmable Logic Interface 2x AXI 32b Master, 2x AXI 32b Slave, 4x AXI 64b/32b Memory, AXI 64b ACP, 16 Interrupts Ports (Primary Interfaces & Interrupts Only) Programmable Logic Cells (Approximate ASIC Gates) 85 k Logic Cells (~1.3 M) Look Up Tables (LUTs) 53,200 Flip-Flops 106,400 Extensible Block RAM (# 36 Kb Blocks) 560 KB (140) Programmable DSP Slices (18 x 25 MACCs) 220 Peak DSP Performance (Symmetric FIR) 276 GMACs Analog Mixed Signal (AMS)/XADC 2 x 12 bit, MSPS ADCs with up to 17 Differential Inputs Processing System User I/Os (excludes DDR dedicated I/Os) 54 Multi-standards and Multi-voltage Select IOTM Interfaces (1.2 V, 1.35 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V) 200 AN4991 Application Note Rev. 2.0 3/2015 Freescale Semiconductor, Inc. 3 Zynq®-7000 SoC 3.3 Power Profile Requirements Zynq® Z-7020 has three different sets of voltage requirements, one each for the following: Processing System (PS), Programming Logic (PL) and the XADC. Each set in turn has a number of different voltage level requirements. The voltage profile recommendations from Xilinx are as listed in Table 3 Table 3. Recommended Voltage Levels Symbol Description Min. Typ. Max. Units Notes PROCESSING SYSTEM (PS) VCCPINT PS Internal Supply Voltage 0.95 1.00 1.05 V VCCPAUX PS Auxiliary Supply Voltage 1.71 1.80 1.89 V PS PLL Supply Voltage 1.71 1.80 1.89 V VCCO_DDR PS DDR I/O Supply Voltage 1.14 – 1.89 V VCCO_MIO PS MIO I/O Supply Voltage for MIO Banks 1.71 – 3.465 V -0.20 – VCCO_DDR + 0.20 VCCO_MIO + 0.20 V VCCPLL VPIN PS DDR and MIO I/O Input Voltage PROGRAMMING LOGIC (PL) VCCINT PL Internal Supply Voltage 0.95 1.00 1.05 V VCCAUX PL Auxiliary Supply Voltage 1.71 1.80 1.89 V PL Block RAM Supply Voltage 0.95 1.00 1.05 V PL Supply Voltage for 3.3 V High Range I/O Banks 1.14 – 3.465 V I/O Input Voltage -0.20 – VCCO + 0.20 V I/O Input Voltage (when VCCO = 3.3 V) for VREF and Differential I/O Standards Except TMDS_33 -0.20 – 2.625 V Battery Voltage 1.0 – 1.89 V XADC supply relative to GNDADC 1.71 1.80 1.89 V Externally supplied reference voltage 1.20 1.25 1.30 V VCCBRAM VCCO VIN VCCBATT (1) XADC VCCADC VREFP Notes: 1.VCCBATT applies only when using bitstream encryption and is otherwise tied to VCCAUX or ground. Note: 1.These voltage ranges are the recommended supply ranges and are what the power system design in consideration is expected to deliver. Further, to ensure safe operation, the power system should be able to support these voltages at the recommended accuracies summarized in Table 4. Table 4. Required Accuracy Levels On The Different Rails Voltage Accuracy VCCPINT ±5.0% VCCPAUX ±5.0% VCCPLL ±5.0% VCCO_DDR ±5.0% VCCO_MIO ±5.0% AN4991 Application Note Rev. 2.0 3/2015 4 Freescale Semiconductor, Inc. . Zynq®-7000 SoC Table 4. Required Accuracy Levels On The Different Rails (continued) VPIN ― VCCINT ±5.0% VCCAUX ±5.0% VCCBRAM ±5.0% VCCO ±5.0% VIN ― VCCBATT ― VCCADC ±5.0% VREFP ±0.2%, 50 ppm/℃ The current drawn is an important consideration in power supply designs. A robust power system takes into account worst-case considerations in order to arrive at an optimal value for the maximum current drawn. The currents drawn by the particular device in consideration, XC7Z020-CLG484-1, are documented in Table 5: Table 5. Quiescent Currents Symbol Description Current ICCPINTQ PS quiescent VCCPINT supply current 122 mA ICCPAUXQ PS quiescent VCCPAUX supply current 13 mA ICCDDRQ PS quiescent VCCO_DDR supply current 4.0 mA ICCINTQ PL quiescent VCCINT supply current 78 mA ICCAUXQ PL quiescent VCCAUX supply current 38 mA ICCOQ ICCBRAMQ PL quiescent VCCO supply current PL quiescent VCCBRAM supply current 3.0 mA(2) 6.0 mA Total quiescent supply current is 264 mA. Notes 2. In addition to the above mentioned quiescents, Table 6 shows the minimum current required by the Zynq® device for proper power-on and configuration. Table 6. Power-on Currents(3) Symbol Description Current ICCPINTMIN Minimum power-on VCCPINT supply current 192 mA ICCPAUXMIN Minimum power-on VCCPAUX supply current 53 mA ICCDDRMIN Minimum power-on VCCO_DDR supply current 104 mA ICCINTMIN Minimum power-on VCCINT supply current 148 mA ICCAUXMIN Minimum power-on VCCAUX supply current 98 mA ICCOMIN Minimum power-on VCCO supply current 453 mA ICCBRAMMIN Minimum power-on VCCBRAM supply current 46 mA Total power-on current is 1094 mA. Notes 3. The currents are calculated assuming one DDR bank and five HR I/O banks. The values of ICCDDRMIN and ICCOMIN increase or decrease by 100 mA and 90 mA per bank respectively for a corresponding increase or decrease in the number of banks. AN4991 Application Note Rev. 2.0 3/2015 Freescale Semiconductor, Inc. 5 Zynq®-7000 SoC The Xilinx Power Estimator (XPE) tool acts as a very important step in the pre-implementation phase of the design. Once the device startup currents are met, the current demand on each rail must be satisfied. The XPE provides an estimate of these currents, based on user inputs, and the worst case estimate helps decide the power system configuration. Table 7 provides an approximate estimate of the current drains on each of the supply rails, obtained from the XPE. This estimate is based on the ZedBoard's utilization of the Zynq®-7000 device. Table 7. Current Drain On Supplies 3.4 Symbol Description Current ICCPINT Current drawn on VCCPINT supply 0.8 A ICCPAUX Current drawn on VCCPAUX supply 0.04 A ICCDDR Current drawn on VCCO_DDR supply 0.4 A ICCINT Current drawn on VCCINT supply 1.9 A ICCAUX Current drawn on VCCAUX supply 0.5 A ICCPLL Current drawn on VCCPLL supply 0.11 A ICCBRAM Current drawn on VCCBRAM supply 0.1 A Power-on Sequence The processor-centric approach of the Zynq® SoC requires the processor to be powered up first. This results in the VCCINT rail occupying top priority in the power-up sequence. The PS and PL rails can be powered up independent of each other as they are isolated from each other in order to prevent damage. The device specification recommends that the power-off sequence be the reverse of the power-on sequence. Figure 1 shows a recommendation for the power-on sequence. Supply V PS VCCPAUX VCCPINT PL VCCPLL VCCINT VCCBRAM VCCO_MIO0 VCCO_MIO1 VCCO_DDR VCCAUX VCCO Figure 1. Power-on Sequence AN4991 Application Note Rev. 2.0 3/2015 6 Freescale Semiconductor, Inc. . Zynq®-7000 SoC Table 8 and Figure 2 illustrate the constraints on the ramp times. tVCCO2VCCAUX is the time for which the difference between the I/O’s supply in the PS or PL (VCCO_MIO or VCCO) and the corresponding auxiliary supply (VCCPAUX or VCCAUX) can exceed 2.625 V. tVCCO2VCCAUX has to be below 800 ms when the junction temperature is 85 °C and below 300 ms for a junction temperature of 125 °C. This constraint has to be followed to maintain safe operation of the device. Table 8. Power Supply Ramp Times Symbol Description Min Max Units tVCCPINT Ramp time from GND to 90% of VCCPINT 0.2 50 ms tVCCPAUX Ramp time from GND to 90% of VCCPAUX 0.2 50 ms tVCCO_DDR Ramp time from GND to 90% of VCCO_DDR 0.2 50 ms tVCCO_MIO Ramp time from GND to 90% of VCCO_MIO 0.2 50 ms tVCCINT Ramp time from GND to 90% of VCCINT 0.2 50 ms tVCCO Ramp time from GND to 90% of VCCO 0.2 50 ms tVCCAUX Ramp time from GND to 90% of VCCAUX 0.2 50 ms PS PL Power S Power Supply tVCCPINT tVCCINT VCCPINT VCCINT tVCCPAUX tVCCAUX VCCPAUX VCCAUX tVCCO_DDR tVCCO VCCO_DDR VCCO tVCCO_MIO VCCO_MIO Figure 2. Ramp Times It is essential for the designer to keep in mind the voltage and current levels and accuracy, the power supply sequence, the ramp, and delay times, to ensure safe operation of the system. AN4991 Application Note Rev. 2.0 3/2015 Freescale Semiconductor, Inc. 7 MMPF0100 4 MMPF0100 The PF0100 SMARTMOS Power Management Integrated Circuit (PMIC) provides a highly programmable/configurable architecture, with fully integrated power devices and minimal external components. With up to six buck converters, six linear regulators, Real Time Clock (RTC) supply, and coin-cell charger, the PF0100 can provide power for a complete system, including applications processors, memory, and system peripherals, in a wide range of applications. Features: • Four to six buck converters, depending on configuration — Single/parallel options — DDR termination tracking mode option • Boost regulator to 5.0 V output • Six general purpose linear regulators • Programmable output voltage, sequence, and timing • OTP (One Time Programmable) memory for device configuration • Coin cell charger and RTC supply • DDR termination reference voltage • Power control logic with processor interface and event detection • I2C control • Individually programmable ON, OFF, and Standby modes MMPF0100 Functional Internal Block Diagram Power Generation OTP Startup Configuration OTP Prototyping (Try before buy) Sequence and timing Voltage Switching Regulators Power stage SW1A/B/C (0.3 V to 1.875 V) Configurable 4.5 A or 2.5 A + 2.0 A Bias & References Internal Core Voltage Reference SW2 (0.4 V to 3.3 V, 2 A) DDR Voltage Reference Logic and Control Parallel MCU Interface Regulator Control Linear Regulators VGEN1 (0.8 V to 1.55 V, 100 mA) VGEN2 (0.8 V to 1.55 V, 250 mA) VGEN3 (1.8 V to 3.3 V, 100 mA) SW3A/B (2.5 A) (0.4 V to 3.3 V) Configurable 2.5A or 1.25 A +1.25 A VGEN4 (1.8 V to 3.3 V, 350 mA) SW4 (0.4 V to 3.3 V, 1 A) VGEN6 (1.8 V to 3.3 V, 200 mA) Boost Regulator (5 V to 5.15 V, 600 mA) USB OTG Supply VSNVS (1.0 V to 3.0 V, 400 uA) RTC supply with coin cell charger VGEN5 (1.8 V to 3.3 V, 100 mA) 2 I C Communication & Registers Fault Detection and Protection Thermal Current Limit Short-Circuit Figure 3. Functional Internal Block Diagram of the MMPF0100 The number of available voltage options from the MMPF0100 PMIC at different currents enables it to provide to the different power needs of the ZedBoard. The buck regulators can be configured in four different modes, depending on the requirement. Table 9 shows a configuration where the maximum number of rails are available, at reduced currents, whereas Table 10 shows a configuration where only four rails are available but can support higher current demands. AN4991 Application Note Rev. 2.0 3/2015 8 Freescale Semiconductor, Inc. . MMPF0100 Table 9. Six Independent Buck Regulators Regulator Name Output Voltage Range DC Current Load Capability SW1AB 0.3 V to 1.875 V 2.5 A SW1C 0.3 V to 1.875 V 2.0 A SW2 0.4 V to 3.3 V 2.0 A SW3A 0.4 V to 3.3 V 1.25 A SW3B 0.4 V to 3.3 V 1.25 A SW4 0.4 V to 3.3 V 1.0 A Table 10. Four Independent Buck Regulators Regulator Name Output Voltage Range DC Current Load Capability SW1ABC 0.3 V to 1.875 V 4.5 A SW2 0.4 V to 3.3 V 2.0 A SW3AB 0.4 V to 3.3 V 2.5 A SW4 0.4 V to 3.3 V 1.0 A SW1AB and SW1C may be combined independent of SW3A and SW3B and vice versa. This leads to two different configurations, with five regulators each, shown in Table 11 and Table 12. The PF0100 used in this application is programmed according to the configuration shown in Table 11. Table 11. Five Independent Buck Regulators - Option 1 Regulator Name Output Voltage Range DC Current Load Capability SW1ABC 0.3 V to 1.875 V 4.5 A SW2 0.4 V to 3.3 V 2.0 A SW3A 0.4 V to 3.3 V 1.25 A SW3B 0.4 V to 3.3 V 1.25 A SW4 0.4 V to 3.3 V 1.0 A Table 12. Five Independent Buck Regulators - Option 2 Regulator Name Output Voltage Range DC Current Load Capability SW1AB 0.3 V to 1.875 V 2.5 A SW1C 0.3 V to 1.875 V 2.0 A SW2 0.4 V to 3.3 V 2.0 A SW3AB 0.4 V to 3.3 V 2.5 A SW4 0.4 V to 3.3 V 1.0 A AN4991 Application Note Rev. 2.0 3/2015 Freescale Semiconductor, Inc. 9 MMPF0100 Of particular note are the One Time Programmable (OTP) mode and the Try Before Buy (TBB) mode. The OTP mode allows you to pre-program the default values for the PF0100 registers at start up. The TBB mode gives you the option of trying out various settings before the registers are actually written to with their values. The TBB mode is especially useful when the power system is being designed or there are modifications needed to an existing solution. You can also shift between Pulse Width Modulation (PWM), Pulse Frequency Modulation (PFM) and Auto Pulse Skip Mode (APS) for the buck regulators. The Power Stage Control registers can be used to reduce the required inductor current limit when the regulators are not operating at their rated output currents, enabling use of smaller inductors. This provides a significant advantage to the PF0100 as there may be a number of applications where not all regulators are exercised to their current limits. Furthermore, the Dynamic Voltage Scaling (DVS) feature eliminates the need for a resistor divider network in the feedback loop of the buck regulators, thereby reducing the number of external components required. AN4991 Application Note Rev. 2.0 3/2015 10 Freescale Semiconductor, Inc. . Power Solution for the ZedBoard 5 Power Solution for the ZedBoard Before a power solution can be installed, it is important to have an estimate of the various voltage rails and the current drawn on each of them. Although the Zynq®-7000 SoC section provides a summary of the voltage domains necessary for proper operation of the Zynq® device, recommended settings allow—and in some cases, require—some of the voltages to be combined and powered by the same rail, whenever they are of the same voltage levels. Furthermore, there may be a need for multiple VCCO, VCCO_MIO, and VCCO_DDR rails, depending on the voltage requirements of the peripherals. This highlights the need for doing a detailed analysis of the voltage level requirements for the case being implemented. Freescale recommends using the Xilinx Power Estimator (XPE) tool to arrive at an estimate for the particular case under consideration. Although this yields only an approximate estimate, it is usually accurate enough for the pre-synthesis phase and it provides the designer with a general idea of the current requirements. The Power Analyzer tool provides a more accurate estimate once the design is implemented. Furthermore, you can import data from the Power Analyzer tool to the XPE to compare with the pre-implementation analysis and to take corrective measures if necessary. Designers should be aggressive in doing worst-case estimates while keeping in mind that over-designing may impact cost. The different use cases may vary significantly from the worst-case estimate. Settings Summary Device Total On-Chip Power Family Zynq-7000 Device XC7Z020 Package CLG484 Thermal Margin Speed Grade -1 Effective JA Temp Grade Commercial Process Maximum Voltage ID Used Junction Temperature Production, v1.0, 2012-07-11 Characterization Environment Junction Temperature User Override Ambient Temp Effective JA 34.3 °C Core Dynamic 25.0 °C User Override Airflow 4.8 °C/W 250 LFM Heat Sink Medium Profile SA # of Board Layers I/O Medium (10"x10") 8 to 11 JB PS Dynamic Static PL Implementation Usage/Optimization Default PL Static 0.000W Power Supply Power (W) Source (%) Voltage Total (A) Static Active V CCINT 1.000 0.104 0.047 0.045 2 V CCBRAM 1.000 0.040 0.002 0.000 LOGIC 0.004 0 V CCAUX 1.800 0.141 0.023 0.118 BRAM 0.005 0 V CCAUX_IO 2.000 0.000 0.000 0.000 DSP 0.000 0 V CCO 3.3V 3.300 0.091 0.001 0.019 PLL 0.000 0 V CCO 2.5V 2.500 0.091 0.001 0.000 MMCM 0.208 11 V CCO 1.8V 1.854 0.000 0.000 0.000 Other 0.000 0 V CCO 1.5V 1.500 0.000 0.000 0.000 0.000 0 V CCO 1.35V 1.350 0.000 0.000 0.000 0.068 4 V CCO 1.2V 1.200 0.000 0.000 0.000 0.000 0 - 1.800 0.000 0.000 0.000 0.000 0 - 1.000 0.000 0.000 0.000 1.314 68 - 1.200 0.000 0.000 0.000 0.161 8 VCCPINT 1.000 0.494 0.097 0.397 0.142 7 0.034 IO Transceiver 25.0 °C 0.303W Pow er supplied to of f -chip devices 0.034 7.4 °C/W Board Temperature 1.566W 16% Device Static….. CLOCK 4.6 °C/W Board Selection 0.068W 81% PS+FPGA Dyn.. 10.0W 4.8 °C/W (Jump to sheet) 0.000W 4% I/O……………… 34.3 °C 50.7°C On-Chip Power Resource No 0% Transceiver…… 1.938 W PS 0.303 1 Messages VCCPAUX 1.800 0.055 0.021 VCCPLL 1.800 0.119 0.006 0.113 VCCO_DDR 1.500 0.514 0.006 0.509 VCCO_MIO0 1.800 0.004 0.002 0.002 VCCO_MIO1 1.800 0.005 0.002 0.003 VCCADC 1.854 0.025 0.025 0.000 Figure 4. Power Estimation Data for Use Case 1 Figure 4 shows the power supply summary obtained from XPE for a particular use case implemented in the ZedBoard. It also involves the use of HDMI, I2S audio, I2C and GPIO pins, and runs PetaLinux OS from the SD card. AN4991 Application Note Rev. 2.0 3/2015 Freescale Semiconductor, Inc. 11 Power Solution for the ZedBoard Settings Summary Device Total On-Chip Power Family Zynq-7000 Device XC7Z020 Package CLG484 Thermal Margin Speed Grade -1 Effective JA Temp Grade Commercial Process Maximum Voltage ID Used Junction Temperature Production, v1.0, 2012-07-11 Characterization User Override Ambient Temp Effective JA 81.8 °C Core Dynamic 72.1 °C User Override Airflow 4.8 °C/W 250 LFM Heat Sink Medium Profile SA # of Board Layers I/O Medium (10"x10") 8 to 11 JB PS Dynamic Static PL Implementation Usage/Optimization PL Static Default 0.775W 18% PS+FPGA Dyn.. 0.370W 43% Device Static….. 0.878W Pow er supplied to of f -chip devices 0.000W Power Supply Power (W) Source (%) Voltage Total (A) 1.000 0.384 0.256 V CCBRAM 1.000 0.040 0.011 LOGIC 0.000 0 V CCAUX 1.800 0.377 0.063 BRAM 0.000 0 V CCAUX_IO 2.000 0.000 0.000 DSP 0.000 0 V CCO 3.3V 3.300 0.000 0.000 PLL 0.100 5 V CCO 2.5V 2.500 0.000 0.000 MMCM 0.000 0 V CCO 1.8V 1.800 0.091 0.001 Other 0.268 13 V CCO 1.5V 1.575 0.288 0.001 0.000 0 V CCO 1.35V 1.350 0.000 0.000 0.775 38 V CCO 1.2V 1.200 0.000 0.000 0.000 0 - 1.800 0.000 0.000 0.000 0 - 1.000 0.000 0.000 0.000 0 - 1.200 0.000 0.000 0.450 22 1.000 0.402 0.402 0.429 21 IO PS 0.878 1 VCCPINT VCCPAUX 1.800 0.021 0.021 VCCPLL 1.800 0.006 0.006 1.500 VCCO_DDR Messages XILINX Power Advantage (check for updates) File Support Request (WebCase) Introduction to XPE (video) © Copyright 1994-2014 Xilinx, Inc. All Rights Reserved Legend User Entry Calculated Value Static V CCINT 0 Transceiver 25.0 °C 0.000W 0.001 7.4 °C/W Board Temperature 0% Transceiver…… 38% I/O……………… CLOCK 4.6 °C/W Board Selection 0.7W 4.8 °C/W (Jump to sheet) Environment Junction Temperature 81.8 °C 3.2°C On-Chip Power Resource No 2.023 W 0.000 0.000 VCCO_MIO0 1.800 0.000 0.000 VCCO_MIO1 1.800 0.000 0.000 VCCADC 1.800 0.025 0.025 Xilinx Power Estimator User Guide Whitepaper - 7 Steps for Worst Case Power Estimation Summary Value User Override Warning Error Figure 5. Power Estimation Data for Use Case 2 Figure 5 shows the power supply summary obtained from XPE for an use case that portrays the use of HDMI and DDR3 memory. AN4991 Application Note Rev. 2.0 3/2015 12 Freescale Semiconductor, Inc. . Power Solution for the ZedBoard Settings Summary Device Total On-Chip Power 5.814 W Junction Temperature 52.8 °C Family Zynq-7000 Device XC7Z020 Package CLG484 Thermal Margin Speed Grade -1 Effective JA Temp Grade Commercial Process Maximum Voltage ID Used No (Jump to sheet) Environment Junction Temperature User Override Ambient Temp Effective JA 52.8 °C Core Dynamic 25.0 °C User Override Airflow 4.8 °C/W 250 LFM Heat Sink Medium Profile SA # of Board Layers I/O Medium (10"x10") 8 to 11 JB PS Dynamic Static PL Implementation Usage/Optimization Default PL Static © Copyright 1994-2014 Xilinx, Inc. All Rights Reserved Legend User Entry Power 0.538W Pow er supplied to off-chip devices 0.000W (W) Source (%) Voltage Total (A) Static VCCINT 1.050 1.903 0.120 VCCBRAM 1.050 0.093 0.025 LOGIC VCCAUX 1.890 0.483 0.032 0.393 7 BRAM 1.117 19 VCCAUX_IO 2.060 0.000 0.000 DSP 0.136 2 VCCO 3.3V 3.450 0.168 0.001 PLL 0.106 2 VCCO 2.5V 2.625 0.091 0.001 MMCM 0.219 4 VCCO 1.8V 1.890 0.091 0.001 Other 0.332 6 VCCO 1.5V 1.575 0.306 0.001 IO PS 0.538 0.000 0 VCCO 1.35V 1.350 0.000 0.000 1.438 25 VCCO 1.2V 1.260 0.000 0.000 0.000 0 - 1.850 0.000 0.000 0.000 0 - 1.030 0.000 0.000 1.419 24 - 1.230 0.000 0.000 0.269 5 VCCPINT 1.050 0.810 0.190 0.269 5 0.021 1 File Support Request (WebCase) Introduction to XPE (video) Calculated Value 3.837W 9% Device Static….. Power Supply Messages XILINX Power Advantage (check for updates) 1.438W 66% PS+FPGA Dyn.. 2 Transceiver 25.0 °C 25% I/O……………… 0.115 2.1 °C/W Board Temperature 0.000W CLOCK 4.6 °C/W Board Selection 6.2W 4.8 °C/W On-Chip Power Resource Production, v1.0, 2012-07-11 Characterization 32.2°C 0% Transceiver…… VCCPAUX 1.890 0.040 VCCPLL 1.890 0.112 0.006 VCCO_DDR 1.500 0.366 0.006 VCCO_MIO0 3.450 0.013 0.002 VCCO_MIO1 1.890 0.008 0.002 VCCADC 1.890 0.027 0.025 Xilinx Power Estimator User Guide Whitepaper - 7 Steps for Worst Case Power Estimation Summary Value User Override Warning Error Figure 6. Worst-case Estimate from XPE Figure 6 shows the worst-case power estimates for the ZedBoard. The calculations are made using exaggerated activity rates and loads in order to account for unexpected user anomalies. Notice that the current capabilities of the PF0100 offer a satisfactory level of tolerance above this calculated limit. Furthermore, some of the LDOs on the PF0100 are left unused and are available for other system uses. While these cases show the PF0100's compatibility with the Zynq® XC7Z020 on the ZedBoard, you can also use them to power other platforms based on the Z-7020 or other Zynq® SoCs. AN4991 Application Note Rev. 2.0 3/2015 Freescale Semiconductor, Inc. 13 Power Solution for the ZedBoard Settings Summary Device Family Zynq-7000 Device XC7Z010 Total On-Chip Power 4.344 W Junction Temperature 75.1 °C Package CLG400 Thermal Margin Speed Grade -1 Effective JA Temp Grade Commercial Process Maximum Voltage ID Used No (Jump to sheet) Environment Junction Temperature User Override Ambient Temp Effective JA 75.1 °C Core Dynamic 25.0 °C User Override 11.5 °C/W Airflow 250 LFM Heat Sink None SA # of Board Layers I/O Medium (10"x10") 8 to 11 JB PL Implementation Usage/Optimization Default 0.672W 0.000W Power Supply Power (W) Source (%) 1.050 0.930 0.109 1 VCCBRAM 1.050 0.047 0.017 3 VCCAUX 1.890 0.470 0.022 0.479 11 VCCAUX_IO 2.000 0.000 0.000 DSP 0.049 1 VCCO 3.3V 3.450 0.091 0.001 PLL 0.106 2 VCCO 2.5V 2.625 0.091 0.001 MMCM 0.219 5 VCCO 1.8V 1.890 0.091 0.001 Other 0.332 8 VCCO 1.5V 1.575 0.306 0.001 0.000 0 VCCO 1.35V 1.350 0.000 0.000 0.883 20 VCCO 1.2V 1.200 0.000 0.000 0.000 0 - 1.800 0.000 0.000 0.000 0 - 1.000 0.000 0.000 0.672 1.419 33 1.200 0.000 0.000 0.444 10 VCCPINT 1.050 0.977 0.357 0.228 5 VCCPAUX 1.890 0.040 0.021 - 1 Messages XILINX Power Advantage (check for updates) © Copyright 1994-2014 Xilinx, Inc. All Rights Reserved Legend User Entry File Support Request (WebCase) Introduction to XPE (video) Calculated Value Voltage Total (A) Static VCCINT 0.130 PS PL Static 15% Device Static….. Pow er supplied to off-chip devices BRAM IO PS Dynamic Static 2.789W LOGIC Transceiver 25.0 °C 0.883W 64% PS+FPGA Dyn.. 0.056 7.4 °C/W Board Temperature 20% I/O……………… CLOCK 0.0 °C/W Board Selection 0.000W 0.8W 11.5 °C/W On-Chip Power Resource Production, v1.0, 2012-07-11 Characterization 9.9°C 0% Transceiver…… VCCPLL 1.890 0.112 0.006 VCCO_DDR 1.500 0.366 0.006 VCCO_MIO0 3.450 0.013 0.002 VCCO_MIO1 1.890 0.008 0.002 VCCADC 1.800 0.027 0.025 Xilinx Power Estimator User Guide Whitepaper - 7 Steps for Worst Case Power Estimation Summary Value User Override Warning Error Figure 7. XPE Estimate for Z-7010 The power demand of the Z-7010, presented by the estimate in Figure 7, is met by the PF0100. 5.1 Power Tree Design The supply to the ZedBoard is from a 12 V barrel-jack connector. This is stepped down to 3.6 V in order to meet the input side supply requirement of the PF0100. Following Xilinx recommendations: • VCCINT and VCCBRAM should be connected to the same supply • VCCPAUX, VCCPLL and the VCCO, VCCO_MIO, VCCO_DDR rails which have the same voltages may be powered from the same rails • VCCAUX and VCCO may be powered from the same rails if they have the same recommended voltages AN4991 Application Note Rev. 2.0 3/2015 14 Freescale Semiconductor, Inc. . Power Solution for the ZedBoard Taking into account the recommendations and the ZedBoard needs, the required rails are: • One 1 V rail for VCCPINT, VCCINT and VCCBRAM • One 1.8 V rail for VCCAUX, VCCPAUX, VCCPLL, VCCBATT and VCCO_MIO1 (supplies to USB-UART, USB-OTG, SD Card, Push buttons and Ethernet) • One 3.3 V rail for VCCO (supplies to JTAG, LEDs, OLED display, HDMI, VGA, Pmod and Audio codec) and VCCO_MIO0 (supplies to Pmod and QSPI) • One adjustable 3.3/2.5/1.8 V rail for VCCO (supplies to FMC, XADC, push buttons and switches) • One 5 V rail for USB OTG, HDMI and audio codec • One 1.5 V rail for VCCO_DDR • One 0.75 V rail for VTT_DDR (DDR3 termination voltage) • One 1.8 V rail for VCCADC • One 1.25 V rail for VREFP (low current, high accuracy) The ZedBoard power requirements and the corresponding supplies are summarized in Table 13. Table 13. Power Requirements for ZedBoard Rail Voltage level Current drawn Supply VCCINT 1.0 V 4.5 A SW1ABC (PF0100) VCCAUX 1.8 V 1.0 A SW3B (PF0100) VCCO1 3.3 V 3.0 A MC34713 VCCO2 3.3/2.5/1.8 V 2.0 A SW2 (PF0100) VCC5V0 5.0 V 0.6 A SWBST (PF0100) VCCO_DDR 1.5 V 1.0 A SW3A (PF0100) VTT_DDR 0.75 V 1.0 A SW4 (PF0100) VCCADC 1.8 V 0.1 A VGEN4 (PF0100) VREFP 1.25 V 0.005 A Reference generator The buck regulators in the PF0100 may be configured as five independent regulators to power VCCINT, VCCAUX, VCCO2, VCCO_DDR and VTT_DDR rails. The PF0100 VTT tracking mode is software enabled. This allows the VTT_DDR rail to automatically track half of VCCO_DDR if they are connected to SW4 and SW3A respectively. VGEN4 may be used to power VCCADC. The boost regulator in the PF0100 is utilized to supply the VCC5V0 rail. The VCCO1 rail requires a buck converter to convert the available 3.6 V to 3.3 V, while being capable of supplying 3 A. Because most peripherals are supplied through this rail, the current being drawn may vary. Therefore, to ensure safe operation, both this rail and the VCCINT rail are provided with sufficient margins. The Freescale Switched-mode Power Supply (SMPS) MC34713 provides a good option for achieving this. The MC34713 is a highly integrated, space efficient, low cost, single synchronous buck switching regulator with integrated N-channel power MOSFETs. It is a high performance point-of-load (PoL) power supply with the ability to track an external reference voltage in different configurations. Its high-efficient 5.0 A continuous output current capability combined with its voltage tracking/sequencing ability and tight output regulation, makes it ideal as a single power supply. The Shutdown pin on the MC34713 is controlled to ensure that the supply from this rail is compatible with the sequence constraints. The power-off sequence is enforced by software. PF0100 can be communicated to via I2C. Appropriate register settings are sent over I2C so that the rails are turned off in the recommended sequence. AN4991 Application Note Rev. 2.0 3/2015 Freescale Semiconductor, Inc. 15 Power Solution for the ZedBoard 12 V input to ZedBoard SW3B (PF0100) SW1ABC (PF0100) 1 V at 4.5 A 1.8 V at 1 A VCCAUX 5 V at 0.6 A VCCINT Buck Converter 3.6 V Internal and auxiliary supplies Buck Converter MC34713 3.3 V at 3 A VCCO1 VCC5V0 Boost (PF0100) SW2 (PF0100) SW3A (PF0100) 3.3/2.5/1.8 V at 2 A VCCO2 SW4 (PF0100) 0.75 V at 1 A 1.5 V at 1 A VCCO_DDR VTT_DDR Peripherals DDR Reference Generator VGEN4 (PF0100) 1.8 V at 0.1 A VCCADC 1.25 V at 5 mA VREFP XADC Figure 8. Power Tree The ZedBoard's power tree is represented in Figure 8. AN4991 Application Note Rev. 2.0 3/2015 16 Freescale Semiconductor, Inc. . Power Solution for the ZedBoard 5.2 PF0100 interface with Zynq® VCCINT, 1 V at 4.5 A SW1ABC VCCINT, VCCPINT, VCCBRAM VCCADC, 1.8 V at 0.1 A VCCADC VGEN4 5 V at 0.6 A Boost PF0100 Zynq VCC5V0, 5 V supply to peripherals SW2 VCCO2, 3.3/2.5/1.8 V at 2 A SW3B VCCAUX, 1.8 V at 1 A PL Bank 34, Bank 35 PS Bank 1 PL PS Bank 0 Bank 13 Bank 33 Bank 0 SW3A SW4 VREFDDR VCCO1, 3.3 V at 3 A DDR Memory Reference 0.75 V at 10 mA VTT_DDR, 0.75 V at 1 A DDR MC34713 VCCO_DDR, 1.5 V at 1 A Figure 9. Zynq® Power Bank Assignments Figure 9 demonstrates the power bank assignments and the interface connections from the PF0100 to the XC7Z010-CLG484-1 IC on the ZedBoard. AN4991 Application Note Rev. 2.0 3/2015 Freescale Semiconductor, Inc. 17 Power Solution for the ZedBoard Figure 10. Power Rails Generated using the PF0100 Figure 10 shows the PF0100 used to supply the seven power rails required by the on-board Zynq® processor. To control ramp times, modify the DVS settings in the PF0100. A DVS setting of 3.125 mv/usec and a sequencer setting of 1.00 ms ensures that the start-up requirements are met. Using the PF0100's Power-OK output to control the MC34713's Shut-down mode input pin ensures that the VCCO1 signal powers up last in the sequence. Because VCCO1 is a peripheral rail, this complies with the power-on recommendations for the Zynq®-7020. Furthermore, the PF0100 settings, including output voltages, start-up sequences, frequency, and switching mode (PWM, APS, PFM), are completely configurable on-the-fly using I2C. Table 14 illustrates the ramp time and sequence configurations from the demonstration board. AN4991 Application Note Rev. 2.0 3/2015 18 Freescale Semiconductor, Inc. . Power Solution for the ZedBoard Table 14. Ramp Timing and Sequence Settings of Individual Rails on the Hardware Board Voltage Rail Sequence Position Rise Time - GND to 90% (in ms) VCC3V6 0 0.834 1 0.103 (4)(5) VCC5V0 VCCINT 2 0.258 VCCADC 3 0.225 VCCAUX 4 0.685 VCCODDR 4 0.539 VTT_DDR 4 0.616 VCC02 4 1.434 VCC01 5 2.710 4. Because the 5 V rail supplies peripherals like USB-OTG and does not directly impact the operation of Zynq®, it is powered on before other rails 5. The ramp time for the 5 V rail is measured from 3.6V to 90% and not from GND to 90% AN4991 Application Note Rev. 2.0 3/2015 Freescale Semiconductor, Inc. 19 Power Solution for the ZedBoard 5.3 Schematics Figure 11. MMPF0100 AN4991 Application Note Rev. 2.0 3/2015 20 Freescale Semiconductor, Inc. . Power Solution for the ZedBoard Figure 12. MC34713 NOTE For full schematics and layout, please contact your Freescale representative. AN4991 Application Note Rev. 2.0 3/2015 Freescale Semiconductor, Inc. 21 Power Solution for the ZedBoard Figure 13. Zynq®-7020 board powered by PF0100 AN4991 Application Note Rev. 2.0 3/2015 22 Freescale Semiconductor, Inc. . Conclusion 6 Conclusion This Application Note offers an example of an optimal power management solution using the Xilinx ZedBoard development board in conjunction with the Freescale’s PF0100 Power Management IC (PMIC).The PF0100 PMIC is an ideal candidate for the power management of Xilinx Zynq® AP SoCs, particularly when used with the ZedBoard. The solution discussed in this document may be tweaked to provide a power solution for other systems based on Zynq® devices. Some distinct advantages of using the PF0100 are: • The PF0100 PMIC-based power solution discussed above results in a design that uses a low number of discrete components. This offers the possibility of an overall reduction in silicon real-estate and a corresponding reduction in cost. • The start-up sequence and output voltages can be enforced using software rather than passive components or other external circuitry. This ensures more accurate control • Enforcing the Power Stage Control and DVS ensures a reduction in the inductor current limits and sizes, and improves efficiency and stability • The PF0100 has a built-in VTT tracking mode which eliminates the need for an external DDR voltage termination component • The VREFDDR option in the PF0100 may be utilized for DDR3 reference voltage • The unused LDOs in the PF0100 are available for other user demands AN4991 Application Note Rev. 2.0 3/2015 Freescale Semiconductor, Inc. 23 References 7 References Following are URLs where you can obtain information on related Freescale products and application solutions: Support Pages Description URL MMPF0100 Data Sheet http://www.freescale.com/files/analog/doc/data_sheet/MMPF0100.pdf MC34713 Data Sheet www.freescale.com/files/analog/doc/data_sheet/MC34713.pdf MMPF0100 Product Summary Page http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code= MMPF0100 Analog Home Page http://www.freescale.com/analog Xilinx Home Page http://www.xilinx.com 7.1 Support Visit www.freescale.com/support for a list of phone numbers within your region. 7.2 Warranty Visit www.freescale.com/warranty for a list of phone numbers within your region. AN4991 Application Note Rev. 2.0 3/2015 24 Freescale Semiconductor, Inc. . Revision History 8 Revision History Revision Date Description 1.0 9/2014 • Initial release 2.0 3/2015 • Updated with results from hardware board AN4991 Application Note Rev. 2.0 3/2015 Freescale Semiconductor, Inc. 25 How to Reach Us: Home Page: freescale.com Web Support: freescale.com/support Information in this document is provided solely to enable system and software implementers to use Freescale products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. Freescale reserves the right to make changes without further notice to any products herein. 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U.S. Pat. & Tm. Off. SMARTMOS is a trademark of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2015 Freescale Semiconductor, Inc. Document Number: AN4991 Rev. 2.0 3/2015