NCV890203 D

NCV890203
2.0 A, 2 MHz Automotive
Buck Switching Regulator
with RSTB
The NCV890203 is a fixed−frequency, monolithic, Buck switching
regulator intended for Automotive, battery−connected applications
that must operate with up to a 36 V input supply. The regulator is
suitable for systems with low noise and small form factor
requirements often encountered in automotive driver information
systems. The NCV890203 is capable of converting the typical 4.5 V to
18 V automotive input voltage range to outputs as low as 3.3 V at
a constant switching frequency above the sensitive AM band,
eliminating the need for costly filters and EMI countermeasures.
A Reset pin signals when the output is in regulation, and a pin is
provided to adjust the delay before the RSTB signal goes high.
The NCV890203 also provides several protection features expected in
Automotive power supply systems such as current limit, short circuit
protection, and thermal shutdown. In addition, the high switching
frequency produces low output voltage ripple even when using small
inductor values and an all−ceramic output filter capacitor − forming
a space−efficient switching regulator solution.
Features
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Internal N−Channel Power Switch
Low VIN Operation Down to 4.5 V
High VIN Operation to 36 V
Withstands Load Dump to 40 V
2 MHz Free−running Switching Frequency
Logic level Enable Input Can be Directly Tied to
Battery
Reset with Adjustable Delay
2.2 A (min) Cycle−by−Cycle Peak Current Limit
Short Circuit Protection enhanced by Frequency
Foldback
±1.75% Output Voltage Tolerance
Output Voltage Adjustable Down to 0.8 V
© Semiconductor Components Industries, LLC, 2014
November, 2014 − Rev. 0
•
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MARKING DIAGRAM
DFN10
CASE 485C
A
L
Y
W
G
V8902
03
ALYWG
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Device
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 17 of this data sheet.
1.4 Millisecond Internal Soft−Start
Thermal Shutdown (TSD)
Low Shutdown Current
Wettable Flanks DFN (pin edge plating)
NCV Prefix for Automotive and Other Applications
Requiring Unique Site and Control Change
Requirements; AEC−Q100 Qualified and PPAP Capable
These Devices are Pb−Free and are RoHS Compliant
Applications
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1
Audio
Infotainment
Safety − Vision Systems
Instrumentation
Publication Order Number:
NCV890203/D
NCV890203
CDRV
DBST
NCV890203
L1
VIN
1 VIN
SW 10
CBST
CIN
2 DRV
DFW
BST 9
RFB1
DELAY
RSTB
3 RSTB
VOUT
COUT
DELAY 8
CDELAY
FB 7
4 GND
EN
5 EN
COMP 6
RFB2
RCOMP
CCOMP
Figure 1. Typical Application
CDRV
DBST
VIN
VIN
SW
L1
CIN
3V
Reg
CBST
Oscillator
DRV
BST
PWM
LOGIC
ON OFF
VOUT
RSTB
RSTB
DELAY
CDELAY
2A
+
−
FB
+
−
GND
+
+S
Reset
Delay
TSD
+
Soft−Start
RESET
COMP
VOLTAGES
MONITORS
EN
+
−
Enable
DFW
RCOMP
+
CCOMP
Figure 2. NCV890203 Block Diagram
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2
VOUT
COUT
NCV890203
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
−0.3 to 40
V
40
V
−0.7 to 40
V
−3.0
V
Min/Max Voltage BST to SW
−0.3 to 3.6
V
Min/Max Voltage on EN
−0.3 to 40
V
Min/Max Voltage COMP
−0.3 to 2
V
Min/Max Voltage FB
−0.3 to 18
V
Min/Max Voltage DRV, DELAY
−0.3 to 3.6
V
−0.3 to 6
V
50
°C/W
−55 to +150
°C
Min/Max Voltage VIN, BST
Max Voltage VIN to SW
Min/Max Voltage SW
Min Voltage SW − 20ns
Min/Max Voltage RSTB
Thermal Resistance, 3x3 DFN Junction−to−Ambient*
RqJA
Storage Temperature Range
Operating Junction Temperature Range
TJ
ESD withstand Voltage
Human Body Model
VESD
Moisture Sensitivity
MSL
−40 to +150
°C
kV
2.0
Peak Reflow Soldering Temperature
Level 1
260
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
*Mounted on 1 sq. in. of a 4−layer PCB with 1 oz. copper thickness.
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3
NCV890203
VIN
1
10
SW
DRV
2
9
BST
RSTB
3
8
DELAY
GND
4
7
FB
EN
5
6
COMP
(Top View)
Figure 3. Pin Connections
PIN FUNCTION DESCRIPTIONS
Pin No.
Symbol
Description
1
VIN
Input voltage from battery. Place an input filter capacitor in close proximity to this pin.
2
DRV
Output voltage to provide a regulated voltage to the Power Switch gate driver.
3
RSTB
RSTB open drain output. Goes high impedence when the output is above 94% of its regulation level,
after the delay set by the DELAY pin times out. Goes low when the output is below 92 % of its
regulation level (sensed on the FB signal)
4
GND
Battery return, and output voltage ground reference.
5
EN
This TTL compatible Enable input allows the direct connection of Battery as the enable signal.
Grounding this input stops switching and reduces quiescent current draw to a minimum.
6
COMP
Error Amplifier output, for tailoring transient response with external compensation components.
7
FB
8
DELAY
9
BST
Bootstrap input provides drive voltage higher than VIN to the N−channel Power Switch for optimum
switch RDS(on) and highest efficiency.
10
SW
Switching node of the Regulator. Connect the output inductor and cathode of the freewheeling diode
to this pin.
Exposed
Pad
Feedback input pin to program output voltage, and detect pre−charged or shorted output conditions.
Delay adjust input. Connecting an external capacitor adjusts the delay for the RSTB function.
Connect to Pin 4 (electrical ground) and to a low thermal resistance path to the ambient temperature
environment.
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NCV890203
ELECTRICAL CHARACTERISTICS
(VIN = 4.5 V to 28 V, VEN = 5 V, VBST = VSW + 3.0 V, CDRV = 0.1 mF, Min/Max values are valid for the temperature range
−40°C ≤ TJ ≤ 150°C unless noted otherwise, and are guaranteed by test, design or statistical correlation.)
Symbol
Conditions
Max
Unit
Quiescent Current, shutdown
IqSD
VIN = 13.2 V, VEN = 0 V, TJ = 25°C
5
mA
Quiescent Current, enabled
IqEN
VIN = 13.2 V
3
mA
VUVLSTT
VIN rising
4.1
4.5
V
UVLO Stop Threshold
VUVLSTP
VIN falling
3.2
3.6
V
UVLO Hysteresis
VUVLOHY
0.5
1.3
V
0.8
V
Parameter
Min
Typ
QUIESCENT CURRENT
UNDERVOLTAGE LOCKOUT − VIN (UVLO)
UVLO Start Threshold
ENABLE (EN)
Logic Low (Voltage input needed to guarantee
logic low)
VENLO
Logic High (Voltage input needed to
guarantee logic high)
VENHI
2
IEN
8
tSS
0.8
COMP shorted to FB
0.786
IFBBIAS
VFB = 0.8 V
0.25
gm
gm(HV)
VCOMP = 1.3 V
4.5 V < VIN < 18 V
20 V < VIN < 28 V
Input Current
V
30
mA
1.4
2.0
ms
0.8
0.814
V
SOFT−START (SS)
Soft−Start Completion Time
VOLTAGE REFERENCE
VFBR
FB Pin Voltage during regulation
ERROR AMPLIFIER
FB Bias Current
Transconductance
Output Resistance
0.6
0.3
COMP Sink Current Limit
ISINK
Minimum COMP voltage
1
0.5
1.5
0.75
1.4
ISOURCE
mA
mmho
ROUT
COMP Source Current Limit
1
MW
mA
VFB = 0.63 V, VCOMP = 1.3 V
4.5 V < VIN < 18 V
20 V < VIN < 28 V
75
40
VFB = 0.97 V, VCOMP = 1.3 V
4.5 V < VIN < 18 V
20 V < VIN < 28 V
75
40
mA
VCMPMIN
VFB = 0.97 V
0.05
FSW
FSW(HV)
4.5 < VIN < 18 V
20 V < VIN < 28 V
1.8
0.9
VFLDUP
VFLDDN
VFB = 0.63 V
18.4
18
0.55
V
2.2
1.1
MHz
20
19.8
V
0.4
V
3.20
1.60
A/ms
OSCILLATOR
Frequency
2.0
1.0
VIN FREQUENCY FOLDBACK MONITOR
Frequency Foldback Threshold
Frequency Foldback Hysteresis
VIN rising
VIN falling
VFLDHY
0.2
0.3
SLOPE COMPENSATION
Ramp Slope (Note 1)
(With respect to switch current)
Sramp
Sramp(HV)
4.5 < VIN < 18 V
20 V < VIN < 28 V
1.70
0.80
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
1. Not tested in production. Limits are guaranteed by design.
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5
NCV890203
ELECTRICAL CHARACTERISTICS (continued)
(VIN = 4.5 V to 28 V, VEN = 5 V, VBST = VSW + 3.0 V, CDRV = 0.1 mF, Min/Max values are valid for the temperature range
−40°C ≤ TJ ≤ 150°C unless noted otherwise, and are guaranteed by test, design or statistical correlation.)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Threshold (in percentage of targeted regulation VOUT).
KRESD
KRESU
VOUT going down
VOUT going up
90
92
92
94.5
94
97
%
Filtering delay (high-to-low transitions)
tRESD
VOUT going down
1.5
2.0
3.0
ms
Sink current
IRES
VRESET = 0.4 V
1
Upper charging level
VDELU
VFB > KRESU x VFBR
1.6
1.9
2.15
V
Lower detection threshold
VDELTH
VDELAY decreasing
0.7
0.9
1.1
V
Discharging current
IDELAY
VDELAY = 1.5 V
4.1
4.4
6.0
mA
Reset delay (low-to-high transition)
tRESU
VOUT going up, CDELAY = 100 pF
22
29
35
ms
RESET
mA
DELAY
POWER SWITCH
ON Resistance
RDSON
VBST = VSW + 3.0 V
650
mW
Leakage current VIN to SW
ILKSW
VEN = 0 V, VSW = 0, VIN = 18 V
10
mA
Minimum ON Time
tONMIN
Measured at SW pin
70
ns
Minimum OFF Time
tOFFMIN
Measured at SW pin
At FSW = 2 MHz (normal)
At FSW = 500 kHz (max duty cycle)
45
ns
30
30
50
70
3.1
3.25
3.7
A
400
200
24
500
250
32
600
300
40
kHz
VDRV
3.1
3.3
3.5
V
DRV POR Start Threshold
VDRVSTT
2.7
2.9
3.05
V
DRV POR Stop Threshold
VDRVSTP
2.5
2.8
3.0
V
45
mA
50
mV
PEAK CURRENT LIMIT
Current Limit Threshold
ILIM
SHORT CIRCUIT FREQUENCY FOLDBACK
Lowest Foldback Frequency
Lowest Foldback Frequency − High Vin
Hiccup Mode
FSWAF
FSWAFHV
FSWHIC
VFB = 0 V, 4.5 V < VIN < 18 V
VFB = 0 V, 20 V < VIN < 28 V
VSW = 0 V
GATE VOLTAGE SUPPLY (DRV pin)
Output Voltage
DRV Current Limit
IDRVLIM
VDRV = 0 V
16
OUTPUT PRECHARGE DETECTOR
VSSEN
20
Activation Temperature (Note 1)
TSD
150
190
°C
Hysteresis (Note 1)
THYS
5
20
°C
Threshold Voltage
35
THERMAL SHUTDOWN
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
1. Not tested in production. Limits are guaranteed by design.
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NCV890203
IqEN. ENABLED QUIESCENT CURRENT
(mA)
8
VIN = 13.2 V
7
6
5
4
3
2
1
0
−50
−25
0
25
50
75
100
125
150
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
−50
25
50
75
100
125
Figure 5. Enabled Quiescent Current vs.
Junction Temperature
4.5
4.4
4.3
4.2
4.1
4.0
−25
0
25
50
75
100
125
TJ. JUNCTION TEMPERATURE (°C)
3.7
3.6
3.5
3.4
3.3
3.2
3.1
3.0
−50
150
150
3.8
0
50
100
TJ. JUNCTION TEMPERATURE (°C)
Figure 6. UVLO Start Threshold vs. Junction
Temperature
150
Figure 7. UVLO Stop Threshold vs. Junction
Temperature
2.4
0.85
VFBR. FB REGULATION VOLTAGE (V)
tSS. SOFT−START DURATION (ms)
0
Figure 4. Shutdown Quiescent Current vs.
Junction Temperature
4.6
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
−50
−25
TJ. JUNCTION TEMPERATURE (°C)
4.7
3.9
−50
2.6
TJ. JUNCTION TEMPERATURE (°C)
VUVLO. UVLO STOP THRESHOLD (V)
VUVLSTT. UVLO START THRESHOLD (V)
IqSD. SHUTDOWN QUIESCENT CURRENT
(mA)
TYPICAL CHARACTERISTICS CURVES
−25
0
25
50
75
100
125
150
0.84
0.83
0.82
0.81
0.80
0.79
0.78
0.77
0.76
0.75
−50
−25
0
25
50
75
100
125
TJ. JUNCTION TEMPERATURE (°C)
TJ. JUNCTION TEMPERATURE (°C)
Figure 8. Soft−Start Duration vs. Junction
Temperature
Figure 9. FB Regulation Voltage vs. Junction
Temperature
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150
NCV890203
TYPICAL CHARACTERISTICS CURVES
100
ISOURCE. ERROR AMPLIFIER
SOURCING CURRENT (mA)
gm. ERROR AMPLIFIER
TRANSCONDUCTANCE (mS)
1.4
1.2
1.0
VIN = 4.5 V
0.8
0.6
VIN = 28 V
0.4
0.2
−50
−25
0
25
50
75
100
125
70
60
50
VIN = 28 V
40
30
−25
0
25
50
75
100
125
TJ. JUNCTION TEMPERATURE (°C)
TJ. JUNCTION TEMPERATURE (°C)
Figure 10. Error Amplifier Transconductance
vs. Junction Temperature
Figure 11. Error Amplifier Max Sourcing
Current vs. Junction Temperature
FSW. OSCILLATOR FREQENCY (MHz)
ISINK. ERROR AMPLIFIER SINKING
CURRENT (mA)
VIN = 4.5 V
80
20
−50
150
100
90
VIN = 4.5 V
80
70
60
50
VIN = 28 V
40
30
20
−50
−25
0
25
50
75
100
125
150
VIN = 13.2 V
2.0
1.8
1.6
1.4
1.2
VIN = 28 V
1.0
0.8
−50
−25
0
25
50
75
100
125
TJ. JUNCTION TEMPERATURE (°C)
Figure 12. Error Amplifier Max Sinking Current
vs. Junction Temperature
Figure 13. Oscillator Frequency vs. Junction
Temperature
150
900
19.2
RDS(on). POWER SWITCH ON
RESISTANCE (mW)
19.4
VFLDUP
19.0
VFLDDN
18.8
18.6
18.4
18.2
−50
150
2.2
TJ. JUNCTION TEMPERATURE (°C)
19.6
VFLDUP. VFLDDN, FREQ. FOLDBACK
THRESHOLD (V)
90
−25
0
25
50
75
100
125
TJ. JUNCTION TEMPERATURE (°C)
150
800
700
600
500
400
300
200
100
0
−50
Figure 14. Rising Frequency Foldback
Threshold vs. Junction Temperature
−25
0
25
50
75
100
125
TJ. JUNCTION TEMPERATURE (°C)
15 0
Figure 15. Power Switch RDS(on) vs. Junction
Temperature
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NCV890203
80
75
75
70
tOFFMIN. MINIMUM TIME (ns)
tONMIN. MINIMUM TIME (ns)
TYPICAL CHARACTERISTICS CURVES
70
65
60
55
50
45
40
−50
−25
0
25
50
75
100
125
65
60
55
50
45
40
35
−50
150
50
75
100
125
Figure 17. Minimum Off Time vs. Junction
Temperature
150
FSWAF. FOLDBACK MODE
SWITCHING FREQUENCY (kHz)
600
2.70
2.60
2.50
2.40
2.30
2.20
2.10
−25
0
25
50
75
100
125
150
VIN = 4.5 V
550
500
450
400
350
300
VIN = 28 V
250
200
−50
−25
0
25
50
75
100
125
150
TJ. JUNCTION TEMPERATURE (°C)
TJ. JUNCTION TEMPERATURE (°C)
Figure 18. Current Limit Threshold vs.
Junction Temperature
Figure 19. Short−Circuit Foldback Frequency
vs. Junction Temperature
40
3.50
38
3.45
VDRV. DRV VOLTAGE (V)
ILIM, PEAK CURRENT LIMIT (A)
FSWHC. HICCUP MODE FREUQNCY
(kHz)
25
Figure 16. Minimum On Time vs. Junction
Temperature
2.80
36
34
32
30
28
3.40
3.35
IDRV = 0 mA
3.30
IDRV = 16 mA
3.25
3.20
3.15
26
24
−50
0
TJ. JUNCTION TEMPERATURE (°C)
2.90
2.00
−50
−25
TJ. JUNCTION TEMPERATURE (°C)
−25
0
25
50
75
100
125
150
3.10
−50
TJ. JUNCTION TEMPERATURE (°C)
−25
0
25
50
75
100
125
TJ. JUNCTION TEMPERATURE (°C)
Figure 20. Hiccup Mode Frequency vs.
Junction Temperature
Figure 21. DRV Voltage vs. Junction
Temperature
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150
NCV890203
TYPICAL CHARACTERISTICS CURVES
IDRVLIM. DRV CURRENT LIMIT (mA)
30
3.0
2.9
VDRVSTT
2.8
VDRVSTP
2.7
2.6
2.5
−50
−25
0
25
50
75
100
125
TJ. JUNCTION TEMPERATURE (°C)
150
29
28
27
26
25
24
23
22
21
−50
Figure 22. DRV Reset Threshold vs. Junction
Temperature
−25
0
25
50
75
100
125
TJ. JUNCTION TEMPERATURE (°C)
Figure 23. DRV Current Limit vs. Junction
Temperature
55
VSSEN. OUTPUT PRECHARGE
DETECTOR THRESHOLD (mV)
VDRVSTT. VDRVSTP, DRV RESET
THRESHOLDS (V)
3.1
50
45
40
35
30
25
20
−50
−25
0
25
50
75
100
125
TJ. JUNCTION TEMPERATURE (°C)
Figure 24. Output Precharge Detector
Threshold vs. Junction Temperature
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150
150
NCV890203
GENERAL INFORMATION
INPUT VOLTAGE
SLOPE COMPENSATION
An Undervoltage Lockout (UVLO) circuit monitors the
input, and inhibits switching and resets the Soft−start circuit
if there is insufficient voltage for proper regulation.
The NCV890203 can regulate a 3.3 V output with input
voltages above 4.5 V and a 5.0 V output with an input above
6.5 V.
The NCV890203 withstands input voltages up to 40 V.
To limit the power lost in generating the drive voltage for
the Power Switch, the switching frequency is reduced by
a factor of 2 when the input voltage exceeds the VIN
Frequency Foldback threshold VFLDUP (see Figure 25).
Frequency reduction is automatically terminated when the
input voltage drops back below the VIN Frequency Foldback
threshold VFLDDN.
A fixed slope compensation signal is generated internally
and added to the sensed current to avoid increased output
voltage ripple due to bifurcation of inductor ripple current
at duty cycles above 50%. The fixed amplitude of the slope
compensation signal requires the inductor to be greater than
a minimum value, depending on output voltage, in order to
avoid sub−harmonic oscillations. For 3.3 V and 5 V output
voltages, the recommended inductor value is 4.7 mH.
SHORT CIRCUIT FREQUENCY FOLDBACK
During severe output overloads or short circuits,
the NCV890203 automatically reduces its switching
frequency. This creates duty cycles small enough to limit the
peak current in the power components, while maintaining
the ability to automatically reestablish the output voltage if
the overload is removed. If the current is still too high after
the switching frequency folds back to 500 kHz, the regulator
enters an auto−recovery burst mode that further reduces the
dissipated power.
Fsw
(MHz)
2
CURRENT LIMITING
Due to the ripple on the inductor current, the average
output current of a buck converter is lower than the peak
current setpoint of the regulator. Figure 26 shows − for
a 4.7 mH inductor − how the variation of inductor peak
current with input voltage affects the maximum DC current
the NCV890203 can deliver to a load.
1
4
18 20
2.3
36
MINIMUM CURRENT LIMIT (A)
VIN (V)
Figure 25. NCV890203 Switching Frequency
Reduction at High Input Voltage
ENABLE
The NCV890203 is designed to accept either a logic level
signal or battery voltage as an Enable signal. EN low induces
a ’sleep mode’ which shuts off the regulator and minimizes
its supply current to a couple of mA typically (IqSD) by
disabling all functions. Upon enabling, voltage is
established at the DRV pin, followed by a soft−start of the
switching regulator output.
2.2
(3.3 VOUT)
2.1
(5 VOUT)
2.0
1.9
1.8
1.7
1.6
0
5
10
15
20
25
30
35
40
INPUT VOLTAGE (V)
SOFT−START
Figure 26. NCV890203 Load Current Capability
with 4.7 mH Inductor
Upon being enabled or released from a fault condition,
and after the DRV voltage is established, a soft−start circuit
ramps the switching regulator error amplifier reference
voltage to the final value. During soft−start, the average
switching frequency is lower than its normal mode value
(typically 2 MHz) until the output voltage approaches
regulation.
OUTPUT VOLTAGE SELECTION
The voltage output for the switcher is adjustable and can
be set with a resistor divider. The FB reference for the
switcher is 0.8 V.
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NCV890203
VOUT
The RSTB pin is also pulled low in case of UVLO (VIN
below the UVLO threshold), TSD (temperature shutdown)
or Disable (VEN below the enable threshold) events.
RUPPER
VOUT
FB = 0.8 V
RLOWER
time
DELAY
V DELU
Use the following equation:
R UPPER + R LOWER
V DELTH
V OUT*V FB
V FB
time
Some common setups are listed below:
RSTB
Desired
Output (V)
VREF (V)
RUPPER
(W, 1%)
RLOWER
(W, 1%)
1.2
0.8
100
200
1.5
0.8
100
115
1.8
0.8
100
80.6
2.5
0.8
100
47.5
3.3
0.8
100
32.4
5.0
0.8
100
19.1
t RESU
time
Figure 27. Typical Operation of the Reset
with Delay Function
BOOTSTRAP
At the DRV pin an internal regulator provides
a ground−referenced voltage to an external capacitor
(CDRV), to allow fast recharge of the external bootstrap
capacitor (CBST) used to supply power to the power switch
gate driver. If the voltage at the DRV pin goes below the
DRV UVLO Threshold VDRVSTP, switching is inhibited and
the Soft−start circuit is reset, until the DRV pin voltage goes
back up above VDRVSTT.
In order for the bootstrap capacitor to stay charged, the
Switch node needs to be pulled down to ground regularly. In
very light load condition, the NCV890203 skips switching
cycles to ensure the output voltage stays regulated. When the
skip cycle repetition frequency gets too low, the bootstrap
voltage collapses and the regulator stops switching.
Practically, this means that the NCV890203 needs
a minimum load to operate correctly. Figure 28 shows the
minimum current requirements for different input and
output voltages.
RESET WITH ADJUSTABLE DELAY
The RSTB pin is pulled low as long as the voltage on the
FB pin is lower than 92% (typical) of the reference voltage
(which corresponds to the output voltage being lower than
92% of its regulation level). It is high impedence when the
voltage goes above 94% (typical) of the regulation level,
after a delay adjusted by the capacitor on the DELAY pin.
The capacitor is held at ground until the output enters
regulation: CDELAY is then quickly charged to the internal
rail voltage (VRESU), then discharged by the Idelay current
until its voltage reaches the lower threshold VDELTH. Only
at this moment the RSTB pin voltage goes high, indicating
the end of the Reset condition.
A small filtering delay (of duration tPG) ensures that the
RSTB signal doesn’t toggle from high to low in case of high
frequency noise when the output is in regulation.
A pull-up resistor is needed on the RSTB pin, as it features
an open collector output, capable of sinking 1 mA minimum
at 400 mV.
www.onsemi.com
12
NCV890203
16
MINIMUM OUTPUT CURRENT (mA)
MINIMUM OUTPUT CURRENT (mA)
50
40
L = 2.2 mH
30
20
L = 4.7 mH
10
0
5.2
6.2
7.2
8.2
L = 4.7 mH
10
8
6
4
L = 2.2 mH
2
9.2
4.2
4.7
5.2
5.7
6.2
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
Minimum Load 5 V Out
Minimum Load 3.3 V Out
20
6.7
7.2
50
MINIMUM OUTPUT CURRENT (mA)
MINIMUM OUTPUT CURRENT (mA)
12
0
4.2
18
16
14
12
L = 2.2 mH
10
8
6
14
L = 4.7 mH
4
2
0
4.2
4.7
5.2
5.7
6.2
6.7
45
L = 2.2 mH
40
35
30
25
L = 4.7 mH
20
15
10
5
0
7.2
4.2
6.2
8.2
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
Minimum Load 3.7 V Out
Minimum Load 5.5 V Out
10.2
Figure 28. Minimum Load Current with Different Input and Output Voltages
OUTPUT PRECHARGE DETECTION
Prior to Soft−start, the FB pin is monitored to ensure the
SW voltage is low enough to have charged the external
bootstrap capacitor (CBST). If the FB pin is higher than
VSSEN, restart is delayed until the output has discharged.
Figure 29 shows the IC starts to switch after the voltage on
FB pin reaches VSSEN, even the EN pin is high. After the
IC is switching, the FB pin follows the soft starts reference
to reach the final set point.
EN
Time
FB
VSSEN
THERMAL SHUTDOWN
A thermal shutdown circuit inhibits switching, resets the
Soft−start circuit, and removes DRV voltage if internal
temperature exceeds a safe level. Switching is automatically
restored when temperature returns to a safe level.
Time
SW
Figure 29. Output Voltage Detection
www.onsemi.com
13
Time
NCV890203
MINIMUM DROPOUT VOLTAGE
However, the ESR of the output capacitor also contributes
to the output voltage ripple, so to comply with the
requirement, the ESR cannot exceed RESRmax:
When operating at low input voltages, two parameters
play a major role in imposing a minimum voltage drop
across the regulator: the minimum off time (that sets the
maximum duty cycle), and the on state resistance.
When operating in continuous conduction mode (CCM),
the output voltage is equal to the input voltage multiplied by
the duty ratio. Because the NCV890203 needs a sufficient
bootstrap voltage to operate, its duty cycle cannot be 100%:
it needs a minimum off time (tOFFmin) to periodically re−fuel
the bootstrap capacitor CBST. This imposes a maximum duty
ratio
R ESR max +
I OUTac +
V OUT + D MAX @ V IN(min) * V SWdrop
ǒ
EXPOSED PAD
P Dloss + I OUT @ 1 *
The exposed pad (EPAD) on the back of the package must
be electrically connected to the electrical ground (GND pin)
for proper, noise−free operation.
The NCV890203 being a fixed−frequency regulator with
the switching element integrated, is optimized for one value
of inductor. This value is set to 4.7 mH, and the slope
compensation is adjusted for this inductor. The only
components left to be designed are the input and output
capacitor and the freewheeling diode. Please refer to the
design spreadsheet www.onsemi.com NCV890203 page
that helps with the calculation.
Output capacitor:
The minimum output capacitor value can be calculated
based on the specification for output voltage ripple:
I DRMS +
DI L +
IN
Ǔ
DI L
(eq. 4)
2 Ǹ3
V IN
@ V F ) I DRMS @ R D (eq. 5)
Ǹ
ǒ
(1 * D) I OUT 2 )
DI L
12
Ǔ
2
(eq. 6)
Input capacitor:
The input capacitor must sustain the RMS input ripple
current IINac:
(eq. 1)
DI L
2
ǸD3
(eq. 7)
It can be designed in combination with an inductor to build
an input filter to filter out the ripple current in the source, in
order to reduce EMI conducted emissions.
For example, using a 4.7 mH input capacitor, it is easy to
calculate that an inductor of 200 nH will ensure that the
input filter has a cut−off frequency below 200 kHz (low
enough to attenuate the 2 MHz ripple).
OUT
V
Ǔ
V OUT
I INac +
ǒ
IN
− RD the dynamic resistance of the diode (extracted from
the V/I curve of the diode in its datasheet).
Then, knowing the thermal resistance of the package and
the amount of heatsinking on the PCB, the temperature rise
corresponding to this power dissipation can be estimated.
With
V OUT @ 1 *
V
with:
− IOUT the average (dc) output current
− VF the forward voltage of the diode
− IDRMS the RMS current in the diode:
DESIGN METHODOLOGY
V
(eq. 3)
Freewheeling diode:
The diode must be chosen according to its maximum
current and voltage ratings, and to thermal considerations.
As far as max ratings are concerned, the maximum reverse
voltage the diode sees is the maximum input voltage (with
some margin in case of ringing on the Switch node), and the
maximum forward current the peak current limit of the
NCV890203, ILIM.
The power dissipated in the diode is PDloss:
Which leads to the maximum output voltage in low Vin
condition:
− DIL the inductor ripple current:
Ǔ
OUT
Typically, with the recommended 4.7 mH inductor, two
ceramic capacitors of 10 mF each in parallel give very good
results.
V SWdrop + I OUT @ R DSon
8 @ DV OUT @ F SW
V
Finally, the output capacitor must be able to sustain the ac
current (or RMS ripple current):
with the switching frequency being folded back down to
FSW(min) = 500 kHz to keep regulating at the lowest input
voltage possible.
The drop due to the on−state resistance is simply the
voltage drop across the Switch resistance RDSON at the
given output current:
C OUT min +
ǒ
V OUT 1 *
D MAX + 1 * t OFFmin @ F SW(min),
DI L
DV OUT @ L @ F SW
(eq. 2)
L @ F SW
− DVOUT the desired voltage ripple.
www.onsemi.com
14
NCV890203
Error Amplifier and Loop Transfer Function
simple, type II compensation to optimize the dynamic
response according to system requirements.
Figure 30 shows the error amplifier with the
compensation components and the voltage feedback divider.
The error amplifier is a transconductance type amplifier.
The output voltage of the error amplifier controls the peak
inductor current at which the power switch shuts off. The
Current Mode control method employed allows the use of a
VOUT
RFB1
VCOMP
VFB
V
RCOMP
Cp
RFB2
RO
gm * V
CCOMP
Vref
Figure 30. Feedback Compensator Network Model
The transfer function from VOUT to VCOMP is the
product of the feedback voltage divider and the error
amplifier.
RFB2
Gdivider(s) +
RFB1 ) RFB2
s
1 ) wz
Gerr amp(s) + gm @ Ro @
1) s
1) s
wpl
wph
ǒ
wz +
Ǔǒ
1
RCOMP @ CCOMP
Ǔ
wpl +
1
Ro @ CCOMP
wph +
(eq. 8)
(eq. 11)
1
RCOMP @ Cp
(eq. 12)
The output resistor Ro of the error amplifier is 1.4 MW and
gm is 1 mA/V. The capacitor Cp is for rejecting noise at high
frequency and is integrated inside the IC with a value of
18 pF.
The power stage transfer function (from Vcomp to output)
is shown below:
(eq. 9)
(eq. 10)
s
1 ) wz
1
Gps(s) + Rload @
@
@ Fh(s) (eq. 13)
Ri
s
1 ) Rload@Tsw @ [Mc @ (1 * D) * 0.5]
1 ) wp
L
ǒ
where
Mc + 1 ) Se
Sn
(eq. 16)
Sn + Vin * Vout @ Ri
L
(eq. 17)
1
2
s
) s
wn@Qp wn 2
wn + p @ Fsw
Qp +
1)
1
p @ [Mc @ (1 * D) * 0.5]
wz +
1
Resr @ Cout
wp +
Mc @ (1 * D) * 0.5
1
(eq. 15)
)
L @ Cout @ Fsw
Rload @ Cout
(eq. 14)
The total loop transfer function is the product of power
stage and feedback compensation network.
Gloop(s) + Gdivider(s) @ Gerr amp(s) @ Gps(s) (eq. 20)
The bode plots of the open loop transfer function will
show the gain and phase margin of the system. The
compensation network is designed to make sure the system
has enough phase margin and bandwidth.
Ri represents the equivalent sensing resistor which has a
value of 0.21 W, Se is the compensation slope which is
500 kV/S, Sn is the slope of the sensing resistor current
during on time. Fh(s) represents the sampling effect from the
current loop which has two poles at one half of the switching
frequency:
Fh(s) +
Ǔ
Design of the Compensation Network
The function of the compensation network is to provide
enough phase margin at crossover frequency to stabilize the
system as well as to provide high gain at low frequency to
eliminate the steady state error of the output voltage. Please
refer to the design spreadsheet www.onsemi.com
NCV890203 page that helps with the calculation.
The design steps will be introduced through an example.
Example:
Vin = 15.5 V, Vout = 3.3 V, Rload = 1.65 W, Iout = 2 A, L =
4.7 mH, Cout = 20 mF (Resr = 7 mW)
(eq. 18)
(eq. 19)
www.onsemi.com
15
NCV890203
(dB)
The reference voltage of the feedback signal is 0.8 V and
to meet the minimum load requirements, select RFB1 =
100 W, RFB2 = 31.6 W.
20 x log
⎣
Gps ⎣f ( m )
⎦
From the specification, the power stage transfer function can
be plotted as below:
90
180
45
90
0
0
− 45
arg (Gps (f m )) x
180
p
− 90
− 90
100
3
4
1⋅ 10
− 180
6
1⋅ 10
5
1⋅ 10
1⋅ 10
fm
(Hz)
Figure 31. Power Stage Bode Plots
The crossover frequency is chosen to be Fc = 70 kHz, the
power stage gain at this frequency is −5.3 dB (0.54) from
calculation. Then the gain of the feedback compensation
network must be 5.3 dB. Next is to decide the locations of
one zero and one pole of the compensator. The zero is to
provide phase boost at the crossover frequency and the pole
is to reject the noise of high frequency. In this example, a
zero is placed at 1/10 of the crossover frequency and a pole
is placed at 1/5 of the switching frequency (Fsw = 2 MHz):
Fz = 7000 Hz, Fp = 400000 Hz,
RCOMP, CCOMP and Cp can be calculated from the
following equations:
RCOMP +
Fp @ gm
@ Vout @
(Fp * Fz) @ |Gps(Fc)| Vref
CCOMP +
Cp +
Ǹ
ǒ Ǔ
Ǹ
ǒ Ǔ
1 ) Fz
Fc
(eq. 23)
Note: there is an 18 pF capacitor at the output of the OTA
integrated in the IC, and if a larger capacitor needs to be
used, subtract this value from the calculated Cp. Figure 32
shows Cp is split into two capacitors. Cint is the 18 pF in the
IC. Cext is the extra capacitor added outside the IC.
From the calculation:
VOUT
RFB1
VCOMP
VFB
V
31.6 W
RFB2
2
(eq. 22)
RCOMP = 7.7 KW, CCOMP = 3 nF, Cp = 41 pF
So the feedback compensation network is as below:
100 W
2
1 ) Fc
Fp
1
2p @ Fz @ RCOMP
1
2p @ Fp @ RCOMP
(eq. 21)
18 pF
RO
gm*V
Cint
Vref
0.8 V
RCOMP
7.7 KW
CCOMP
3 nF
Figure 32. Example of the Feedback Compensation Network
www.onsemi.com
16
23 pF
Cext
NCV890203
(dB)
Figure 33 shows the bode plot of the OTA compensator
20 x log
⎣
Gerr_amp ⎣f ( m )⎦
⎦
90
180
45
90
0
0
− 45
arg (Gerr_amp (f m )) x
180
p
− 90
− 90
100
1 ⋅ 10
3
1 ⋅ 10
4
1 ⋅ 10
− 180
6
1 ⋅ 10
5
fm
(Hz)
Figure 33. Bode Plot of the OTA Compensator
(dB)
The total loop bode plot is as below:
20 x log
90
180
45
90
⎣ Gloop ⎣f ( m ) ⎦ 0
0
− 45
− 90
100
arg (Gloop (f m )) x
180
p
− 90
3
4
1⋅ 10
5
1⋅ 10
1⋅ 10
− 180
6
1⋅ 10
fm
(Hz)
Figure 34. Bode Plot of the Total Loop
The crossover frequency is at 70 KHz and phase margin is 75 degrees.
PCB LAYOUT RECOMMENDATION
Freewheeling diode ³ inductor ³ Output capacitor
³ return through ground
− Minimize the length of high impedance signals, and
route them far away from the power loops:
♦ Feedback trace
♦ Comp trace
♦
As with any switching power supplies, there are some
guidelines to follow to optimize the layout of the printed
circuit board for the NCV890203. However, because of the
high switching frequency extra care has to be taken.
− Minimize the area of the power current loops:
♦ Input capacitor ³ NCV890203 switch ³ Inductor
³ output capacitor ³ return through Ground
ORDERING INFORMATION
Device
NCV890203MWTXG
Package
Shipping†
DFN10 with wettable flanks
(Pb−Free)
3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
www.onsemi.com
17
NCV890203
PACKAGE DIMENSIONS
DFN10, 3x3, 0.5P
CASE 485C
ISSUE C
D
EDGE OF PACKAGE
A
B
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
5. TERMINAL b MAY HAVE MOLD COMPOUND
MATERIAL ALONG SIDE EDGE. MOLD
FLASHING MAY NOT EXCEED 30 MICRONS
ONTO BOTTOM SURFACE OF TERMINAL b.
6. DETAILS A AND B SHOW OPTIONAL VIEWS
FOR END OF TERMINAL LEAD AT EDGE OF
PACKAGE.
7. FOR DEVICE OPN CONTAINING W OPTION,
DETAIL B ALTERNATE CONSTRUCTION IS
NOT APPLICABLE.
L1
PIN 1
REFERENCE
ÇÇÇÇ
ÇÇÇÇ
ÇÇÇÇ
E
DETAIL A
Bottom View
(Optional)
0.15 C
2X
EXPOSED Cu
TOP VIEW
MOLD CMPD
0.15 C
2X
(A3)
DETAIL B
0.10 C
A1
A
10X
A1
D2
10X
C
DETAIL A
SOLDERING FOOTPRINT*
e
L
1
A3
DETAIL B
Side View
(Optional)
SEATING
PLANE
0.08 C
SIDE VIEW
ÉÉÉ
ÉÉÉ
5
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
L1
MILLIMETERS
MIN
MAX
0.80
1.00
0.00
0.05
0.20 REF
0.18
0.30
3.00 BSC
2.40
2.60
3.00 BSC
1.70
1.90
0.50 BSC
0.19 TYP
0.35
0.45
0.00
0.03
2.6016
E2
10X
K
10
10X
0.10 C A B
0.05 C
1.8508
2.1746
6
3.3048
b
BOTTOM VIEW
NOTE 3
10X
0.5651
10X
0.5000 PITCH
0.3008
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended,
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or
unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable
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NCV890203/D