ADP1043A Evaluation Board Forward Active Clamp PRD 1168 Reference Design FEATURES Forward Active Clamp with Synchronous rectifier Voltage Feedback Loop Dimensions: 58.4mm×61mm×12mm (Half Brick) Input Voltage Range: -34V to -60V DC Output Voltage/Current: 18V/6A DC 95% Max. Efficiency I2C serial interface Software GUI PRD 1168 OVERVIEW The PRD 1168 is designed for evaluating ADP1043A application using forward active clamp topology. The ADP1043A is a secondary side power supply controller IC designed to provide all the functions that are typically needed in an AC-DC or isolated DC-DC application. The board output 18V/6A DC from a -34to -60VDC input. The maximum efficiency can reach 95%. It has versatile protection, such as OCP, SCP, OTP etc. And the protection mode also can be programmed through GUI. Using this board and its accompanying software, the ADP1043A can be interfaced to any PC running Windows 2000, Windows NT, Windows XP or Windows Vista via the computer's USB port. EVALUATION EQUIPMENT To evaluate this demo board, a PC, oscilloscope, electronic load and a DC power source are required. SR2 Figure 1 Forward Active Clamp Topology. Rev. Prelim.A, Oct. 2009 10/30/2009 4:36:00 PM Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2009 Analog Devices, Inc. All rights reserved. Reference Design PRD 1168 TABLE OF CONTENTS Features ......................................................................................................................................................................................................... 1 PRD 1168 Overview ..................................................................................................................................................................................... 1 Evaluation Equipment ................................................................................................................................................................................... 1 Evaluation Board Hardware .......................................................................................................................................................................... 4 Specifications ............................................................................................................................................................................................ 4 Topology and operation waveforms .......................................................................................................................................................... 4 Connectors................................................................................................................................................................................................. 5 Interface Connector ................................................................................................................................................................................... 5 Test Results ................................................................................................................................................................................................... 7 Getting Started............................................................................................................................................................................................... 9 Equipment ................................................................................................................................................................................................. 9 Setup.......................................................................................................................................................................................................... 9 Board Evaluation ......................................................................................................................................................................................... 11 Line and Load Voltage Regulation .......................................................................................................................................................... 11 Output Voltage Setting ............................................................................................................................................................................ 11 Soft Start.................................................................................................................................................................................................. 11 Digital Filter – Transient Analysis ........................................................................................................................................................... 12 PWM – Switching Frequency ................................................................................................................................................................. 13 Light Load Optimization ......................................................................................................................................................................... 13 Primary Side Current Sense and Secondary Side Current Sense ............................................................................................................. 13 Flags and Fault configurations ................................................................................................................................................................ 14 Flag and Fault Response Configuration: ............................................................................................................................................. 14 Appendix ..................................................................................................................................................................................................... 16 Schematic ................................................................................................................................................................................................ 16 Bill of Materials ...................................................................................................................................................................................... 18 PCB Layout ............................................................................................................................................................................................. 20 Board Setting ........................................................................................................................................................................................... 22 Register Setting ....................................................................................................................................................................................... 23 NOTES ........................................................................................................................................................................................................ 27 Rev Prelim A Oct.2009 | Page 2 of 27 Reference Design PRD 1168 TABLE OF FIGURES Figure 1 Forward Active Clamp Topology. ................................................................................................................................................... 1 Figure 2 Driver Signal ................................................................................................................................................................................. 4 Figure 3 Pin Connection Diagram (Bottom view) ....................................................................................................................................... 5 Figure 4 Eval Board Picture(Bottom View) ................................................................................................................................................. 6 Figure 5 Test Configuration for the Evaluation Board ................................................................................................................................. 6 Figure 6 Efficiency....................................................................................................................................................................................... 7 Figure 7 Output Voltage Response................................................................................................................................................................ 7 Figure 8 Output Voltage Ripple at No Load Current. ................................................................................................................................... 7 Figure 9 Output Voltage Ripple at Nominal Load Current. .......................................................................................................................... 7 Figure 10 Turn-on Transient at No Load Current. ........................................................................................................................................ 8 Figure 11 Turn-on Transient at Nominal Load Current................................................................................................................................. 8 Figure 12 Output Over Current. .................................................................................................................................................................... 8 Figure 13 Output Short Circuit. .................................................................................................................................................................... 8 Figure 14 Connection with Computer .......................................................................................................................................................... 9 Figure 15 Getting Started ............................................................................................................................................................................. 9 Figure 16 Load Board Setting .................................................................................................................................................................... 10 Figure 17 Graphical User Interface.............................................................................................................................................................11 Figure 18 General Settings Window .......................................................................................................................................................... 12 Figure 19 Digital Filter Window ................................................................................................................................................................ 12 Figure 20 Timing Window ......................................................................................................................................................................... 13 Figure 21 Light Load Current Threshold ................................................................................................................................................... 13 Figure 22 Flags .......................................................................................................................................................................................... 14 Figure 23 Fault Configurations .................................................................................................................................................................. 15 Figure 24 Main Circuit .............................................................................................................................................................................. 16 Figure 25 ADP1043A Control Circuit ....................................................................................................................................................... 17 Figure 26 Aux. Power Circuit .................................................................................................................................................................... 17 Figure 27 Top View of Board..................................................................................................................................................................... 20 Figure 28 Bottom View of Board ............................................................................................................................................................... 21 Rev Prelim A Oct.2009 | Page 3 of 27 Reference Design PRD 1168 EVALUATION BOARD HARDWARE SPECIFICATIONS • Nominal input voltage: -48 DC • Input voltage range: -34~-60V DC • Nominal output voltage: 18V DC • Nominal output current: 6A DC • Switching frequency: 180kHz • Efficiency: 95% at full load TOPOLOGY AND OPERATION WAVEFORMS A typical DC/DC switching power supply is the basis for the eval board. It is a forward active clamp with synchronous rectifier topology, shown as Figure 1. The forward active clamp converter is an isolated converter, which operates with variable duty cycle which can be over 50%, so that a wide range input converter can provide high efficiency under the conditions of regulated output. The primary side consists of the input terminals, main switch, aux switch (PMOS) and main transformer. The gate driver signal for the switches comes from the ADP1043A, through the iCoupler and the drivers. There is also a current transformer (CT), to transmit the primary side current information to the ADP1043A on the secondary side. Figure 2 Driver Signal Q1 D t Q2 t SR1 t SR2 1-D t Ts The secondary side power stage consists of the synchronous rectifiers, inductor, output capacitor and sensing resistor. This provides 18V @ 6A at the output. The ADP1043A is located on the secondary side. The ADP1043A provides the feedback signal that is used to regulate the voltage, limit the current, allow current sharing and shutdown to be implemented. Low side current sensing is used. There is a 8pins connector on the board. 4pins of the connector is for I2C. This allows the PC software to communicate with the eval board through the USB port of the PC. The user can readily change register settings on the ADP1043A this way, and also monitor the status registers. The eval board is designed with a 2mOhm RSENSE resistor. The power supply is designed to support a maximum continuous output of 6 A. A variable load is required to perform a thorough evaluation. The output voltage is available between P4 and P5. This is also where the load should be connected. The power supply will be in Continuous Conduction Mode. If the synchronous rectifiers are enabled, the power supply will remain in CCM mode over the full load range. Rev Prelim A Oct.2009 | Page 4 of 27 Reference Design PRD 1168 Figure 3 Pin Connection Diagram (Bottom View) CONNECTORS The connections to the eval board are shown in Table 1. Table 1. Power module pin assignment Pin Designation Eval Board Function P1 Vin- Negative Input P2 On/Off Remote Control P3 Vin+ Positive Input P4 Vo- Negative Output P5 Vo+ Positive Output P6 Interface Interface INTERFACE CONNECTOR The signal pins are P6.1~P6.8 as shown in Table 2. Among them P6.7, P6.5, P6.3 and P6.1 are connected to USB dongle. Table 2. Signal pins Pin Designation Pin Designation P6.1 GND P6.5 SCL P6.2 PGOOD P6.6 Vsen- P6.3 SDA P6.7 5V P6.4 Vsen+ P6.8 Address Rev Prelim A Oct.2009 | Page 5 of 27 Reference Design PRD 1168 Figure 3 shows the photo of eval board. Figure 4 provides a typical circuit diagram which details the filtering for normal operation and output ripple test Figure 4 Eval Board Picture(Bottom View) Figure 5 Test Configuration for the Evaluation Board Rev Prelim A Oct.2009 | Page 6 of 27 Reference Design PRD 1168 TEST RESULTS Figure 6 Efficiency at nominal output voltage vs. load current for minimum, nominal, and maximum input voltage at 25°C. Figure 7 Output voltage response to step-change in load current (25%75%-25% of Iout(max): dI/dt = 1A/μs). Ch 2: Vout (500mV/div), Ch 4: Iout (2A/div). Figure 8 Output voltage ripple at nominal input voltage and no load current . Ch 2: Vout (50mV/div), Bandwidth: 20 MHz. Figure 9 Output voltage ripple at nominal input voltage and nominal load current. Ch 2: Vout (50mV/div), Bandwidth: 20 MHz. Rev Prelim A Oct.2009 | Page 7 of 27 Reference Design PRD 1168 Figure 10 Turn-on transient at nominal input voltage and no load current. Ch 2: Vout (5V/div), Ch 4: Load Current (5A/div). Figure 11 Turn-on transient at nominal input voltage and nominal load current. Ch 2: Vout (5V/div), Ch 4: Load Current (5A/div). Figure 12 Output over current protection function. Increase load current at nominal input voltage to over current limit. Ch 2: Vout (5V/div), Ch 4: Load Current (5A/div). Figure 13 Output short circuit protection function. Turn on at nominal input voltage and rated load current then short circuit. Ch 2: Vout (5V/div), Ch 4: Load Current (5A/div). Rev Prelim A Oct.2009 | Page 8 of 27 Reference Design PRD 1168 GETTING STARTED EQUIPMENT • • • • • • DC Power Supply 0-60V (Sorensen DLM150-20E) Electronic Load capable of 18V/6A (Chroma 63112) Oscilloscope (Tektronix TDS5054B) PC with ADP1043A GUI installed Precision Digital Multi-meters (Agilent 34401A) Current Probe for measuring up to 6A DC (Tektronix TCP202) SETUP NOTE: DO NOT CONNECT THE USB CABLE TO THE EVAL BOARD UNTIL AFTER THE SOFTWARE HAS BEEN INSTALLED. Figure 14 Connection with Computer 1. Install the ADP1043A software. Refer to the Quick Start Guide that comes on the CD (If already installed, skip to the next step). 2. Connect the evaluation board to the USB port on the computer, using the “USB to I2C interface” dongle. If the dongle driver was not previously installed, run the software from the Start Menu under “Programs/ADI/ADP1043A”. 3. The software should report that the ADP1043A has been located on the board. Click Finish to proceed to the Main Software Interface Window. Figure 15 Getting Started 4. Click on the icon and “Load Board Setting”: select the “PRD1168.43b file”. This file contains all the board information including values of shunt and voltage dividers Rev Prelim A Oct.2009 | Page 9 of 27 Reference Design PRD 1168 Figure 16 Load Board Setting 5. The ADP1043A is pre-programmed and calibrated, so there is no programming necessary. 6. Connect an electronic load at the output. 7. For the input voltage source, a DC power supply can be used. The input voltage range is -34V to -60 VDC (-48VDC is recommended). This input voltage is the signal which will be regulated to provide a 18V/6A supply at the output. Set the voltage to -48VDC. 8. The eval board should now up and running, and ready to evaluate. The output should be 18 VDC. Rev Prelim A Oct.2009 | Page 10 of 27 Reference Design PRD 1168 BOARD EVALUATION The ADP1043A is optimized for improving the power supply design and evaluation process. The goal of this eval kit is to allow the user to get an insight into the flexibility offered by the extensive programming options offered by the ADP1043A. The ADP1043A performs many monitoring and housekeeping functions in the power supply. The eval board allows the user to simulate various events that could affect the ADP1043A in a working system. The user can monitor how the ADP1043A handles this event in many ways. One way is to use an oscilloscope and/or multi-meter, and probe the eval board, to see various conditions in the system. The user can also use the software to monitor the conditions of the ADP1043A, and how it has reacted to the event. The following section gives some experiments that the user might typically evaluate. LINE AND LOAD VOLTAGE REGULATION Vary the input voltage from -34VDC to -60VDC. The output voltage remains18V. Vary the load current from 0 to 6A. The output voltage remains 18V. The line and load regulation are less than ±1%. Figure 17 Graphical User Interface OUTPUT VOLTAGE SETTING The output voltage setting is programmable. Using the Voltage Setting window in the software, adjust the output voltage (using the o/p trim menu). Monitor the actual output voltage of the power supply using the software or a multi-meter, or looking at the output voltage reading on the electronic load. It should match the programmed value. This will be used to calibrate the power supply in the production environment. By doing this evaluation, the user can see how the ADP1043A can be trimmed digitally to adjust the output voltage. SOFT START Once the input voltage is applied it is possible to test the Soft Start of the ADP1043A. The settings are located in the General Settings Window. Please refer to the Software Reference Guide for a detailed explanation of all the controls (EVAL-ADP1043A-GUI-RG). Rev Prelim A Oct.2009 | Page 11 of 27 Reference Design PRD 1168 Figure 18 General Settings Window Soft Start is enabled and set to 20ms. You can experiment with different times. DIGITAL FILTER – TRANSIENT ANALYSIS The digital filter can be changed using the software. The effect on transient analysis can be evaluated this way. Connect a switching electronic load to the output of the eval board. The load should be set to switch between 25%-75%, changing every 10msecs. Set up an oscilloscope to capture the transient waveform of the power supply output. Use a differential probe on the scope, connecting it to the eval board output. Turn on the load, and note the waveform response. Now, vary the digital filter using the software. Click on “Filter Settings” the window shows the filter settings for Normal mode. Click on the curve to move position of poles, zeroes and gains. Figure 19 Digital Filter Window The transient response will change. This evaluation shows the user how the digital filter can easily be programmed to optimize the transient response of the power supply. Rev Prelim A Oct.2009 | Page 12 of 27 Reference Design PRD 1168 PWM – SWITCHING FREQUENCY The converter switching frequency is programmable. In the “PWM & SR Settings” change the switching frequency. The minimum and maximum modulation limits can also be modified. Figure 20 Timing Window NOTE: It is recommended to evaluate this feature with the power supply turned off. This prevents the chance of damaging the power supply by introducing shoot-through. LIGHT LOAD OPTIMIZATION The ADP1043A can be programmed to optimize performance when a output current drops below a certain level. The threshold for light load mode can be programmed in the digital filter window. Once the current will drop below this level the sync rectifiers (SR1 and SR2) will be disabled. The “Light Load Mode Settings” will be used. The response time for the ADP1043A to switch from one mode to another is between 10 and 20ms. The light load mode can be disabled by selecting a Light Load Current Threshold of 0%. Figure 21 Light Load Current Threshold PRIMARY SIDE CURRENT SENSE AND SECONDARY SIDE CURRENT SENSE Current sensing is available for both the primary side current and the secondary side current. Primary side current sensing is performed using the current transformer, T1. Secondary side current sensing uses a low-side sense resistor. Open the Monitor window in the software. Click on the Flags and Readings tab. Adjust the load current from 0A to 6A. The input current and output current values will change in the software, matching the changes being made at the load. Rev Prelim A Oct.2009 | Page 13 of 27 Reference Design PRD 1168 FLAGS AND FAULT CONFIGURATIONS Open the Monitor window in the software. Click on the Flags and Readings tab. The window will show all of the fault flags. If a flag is set, then there is a red box next to the flag. If the flag is ok, then there is a green box next to the flag. Set the load current to 0.3A. The CS2 OCP flag should be green. Figure 22 Flags Now change the load to 8A. The CS2 OCP flag should now have turned red, because the CS2 OCP threshold has been reached. The board wills ender in hiccup mode and try and restart. Set the load back to 2A, and the flag turns green again. This shows how the user can easily monitor the health of the power supply by monitoring the status of the various flags. Flag and Fault Response Configuration: The ADP1043A is programmed to respond to the various fault conditions in the Fault Configuration Tab. Rev Prelim A Oct.2009 | Page 14 of 27 Reference Design PRD 1168 Figure 23 Fault Configurations You can change the resolve issue to “Remain Disabled”. If the over current is applied again the ADP1043A will shut down and remain off until PSON is cycled. This evaluation shows how it is quite easy to configure the response to a fault condition. Change the load back to 2A, then toggle the PS_ON switch to restart the power supply. Rev Prelim A Oct.2009 | Page 15 of 27 Reference Design PRD 1168 APPENDIX SCHEMATIC 3 CS+ Vin+ Vout+ 3 JP1 4 1 C7 68nF C15 2.2uF 2.2uF 2.2uF 32uH R92 C47 C46 10nF 5.1k 10nF 2 MURA110 R91 5.1k R90 5.1k C9 C10 C11 C12 C13 10uF 4.7uF 10uF 10uF 4.7uF R11 10K PGND Vout- 1 Q2 Si3437 Q3 IPD053N08N3 R89 Q7 Vin+ R10 R7 10K 8 7 6 5 12V_SEC C22 1uF ADP3634 EN INA GND INB ADP3634 EN INA GND INB PAD OTW OUTA VS OUTB 1 2 3 4 5V_PRI U3 8 7 C19 6 5 0.1uF 5V_PRI 10K R99 5.1K Q9 D13 ZR431F01 R62 ON/OFF 1 MMBT2907AW1 R72 1K C20 0.1uF R101 0 220 D12 BAV70WT1 C38 10nF C40 1uF R100 5.1K OUTA OUTB OUTB SR1 1 2 3 4 VDD2VDD1 VOA VIA VOB VIB GND2GND1 VDD1VDD2 VIA VOA VIB VOB GND1GND2 SR2 12V_SEC 5V_PRI OUTA OUTB 5V_PRI 12V_PRI C21 0.1uF Vout+ Vout- 0 Vout+ VoutPGND 12V_PRI PSON PSON TR4 TR4 3V3_SEC 3V3_SEC 3V3_SEC U4 1 2 3 4 8 7 6 5 R102 12V_SEC 0.1uF 220 C48 10nF 1 2 3 EN_LDO4 R104 5.1K R106 10K ADUM3210 0 U14 3V3_SEC PSON C36 0 1 JP4 AGND OUTA 12V_SEC 3V3_SEC 5V_PRI R68 R65 8.2K SR1 SR1 PGND R66 330K SR2 SR2 1 2 3 4 ADUM3210 R69 100K CS+ AGND U8 9 C18 1uF OTW OUTA VS OUTB Vin- CS+ U9 R15 2 JP3 8 7 6 5 Vin+ 10K Vin- 12V_PRI 1 JP5 D7 D5 R5 4.7 2m Vout- PAD Vin- 1 1 M7 9 Vin- C33 0.1uF 1N5819HW 2 1 1N5819HW 1 2 MMBT4403 IPD200N15N3 R6 10K 1 JP11 R16 2 R93 5.1k D2 C6 1 Q4 PA1005.100NL BEQ-25 C5 L5 2 2 D3 MURA110 IPD053N08N3 T1 8 7 Vin+ Vout+ TR4 T4 1 1 1 1 1 AGND Figure 24 Main Circuit C54 1uF C55 1uF GND IN OUT EN GND4 GND3 GND2 GND1 8 7 6 5 ADP1720ARMZ-3.3 C69 0.1uF C39 10nF 0 Rev Prelim A Oct.2009 | Page 16 of 27 Reference Design PRD 1168 Figure 25 ADP1043A Control Circuit Vout+ PGND Vout- TR4 D6 BAV70WT1 R25 R23 10 Vout+ C32 100pF 680 Vsen+ R26 34KF CS+ R30 R34 25 25 R29 34KF C25 R31 R28 10K 10K VS1 R27 4.7K AGND C58 R33 1nF 34KF NC VS3+ R74 R32 2KF 100pF Vout+ Vout+ Vout- R35 2KF Vout- CS+ 0 CS2+ CS2- SR1 SR2 R36 SR1 C59 SR2 16 1 GATE VS2 3 VS1 8 PGND CS2- CS2+ 5 4 10 SR2 SR1 9 6 ACSNS VsenVS3+ VS3- 7 CS1 VCORE VS3- 31 OUTA 12 OUTB 13 14 15 VDD TR4 OUTA 26 C27 0.1uF OUTB DGND ADP1043A OUTC AGND OUTD TPAD C24 0.1uF 25 33 R43 R64 10K 24 0 3V3_SEC SDA 2.2K JP10 R44 2.2K 18 17 30 12V_SEC Share 23 R67 Vout- 100 SDA R41 10K C28 33pF R45 2.2K 5V C29 33pF 0 R70 100 R42 0 PGOOD SCL RES ADD RTD R40 2.2K 28 3V3_SEC ADD 29 PGOOD2 PGOOD1 22 FLAGIN 21 PSON 20 19 PSON SHAREi 12V_SEC C26 0.1uF 3V3_SEC 2 OUTAUX SHAREo OUTB 3V3_SEC OUTA PGND OUTA OUTB 27 PSON TR4 PGND R38 10 3V3_SEC 11 SR2 PSON Vout- 32 AGND SR1 2KF 1nF U6 CS+ AGND VS3+ R71 10K 1 3 5 7 2 4 6 8 PGOOD Vsen+ VsenADD Connector 0 D4 SCL 49.9K 0.1% 1N4148 C30 33pF 0 0 R17 2 12V_SEC C31 33pF 0 RT1 100KOhm PGND1 2 JP9 SHORTPIN 0 0 0 Figure 26 Aux. Power Circuit T3 Vin+ D15 BAV70WT1 12V_SEC 2 5 R76 20K R78 499K R77 C41 20K 470pF/250V D16 MMBD1504A 12V_PRI 1 3 8 7 6 C43 5V_PRI 10uF/16V 3V3_SEC 4 12V_SEC R85 499K BSER9-77 8 7 6 5 VD GND VCC CT UV VFB OV COM U12 R84 55K 1 2 3 4 C45 390pF R80 680 C49 R81 680 Vout- 5V_PRI C50 1nF C35 0.1uF R83 10K R82 5.1K Vin+ Vin- R79 20K 10uF/16V 3 NCP1031A C56 1uF D18 2 0.1uF PGND 0 1 C34 AGND D17 BAV70WT1 D8 GND19 1N4148 12V_PRI C52 Vout1000pF/2000V C53 MMBZ5231BLT/5.1V 220pF R86 36K AUX. Power Rev Prelim A Oct.2009 | Page 17 of 27 12V_PRI 5V_PRI 3V3_SEC 12V_SEC AGND PGND Vin+ VinVout- Reference Design PRD 1168 BILL OF MATERIALS Item Reference Description Part Number Manufacture Qty 1 2 3 4 CAP 2.2uF/100V X7R 1210 CAP 68nF/250V X7R 1206 CAP 10uF/25V X7R 1210 CAP 4.7uF/25V X7R 1206 C3225X7R2A225K C3216X7R2E683K C3225X7R1E106K C3216X7R1E475K TDK TDK TDK TDK 3 1 3 2 CAP 1uF/16V X7R 0603 C1608X7R1C105K TDK 6 CAP 0.1uF/16V X7R 0402 C1005X7R1C104K TDK 10 CAP 100pF/50V C0G 0402 CAP 33pF/50V C0G 0402 CAP 100pF/50V X7R 0402 CAP 0.1uF/50V X7R 0603 CAP 10nF/25V X7R 0402 CAP 470pF/250V COG 0603 CAP 10uF/16V X7R 1206 CAP 390pF/50V C0G 0402 CAP 10nF/250V X7R 0805 CAP 1nF/50V X7R 0402 CAP 1000pF/2000V X7R 1808 CAP 220pF/50V X7R 0402 Diode 1A 100V Diode 150mA 75V Diode 1A 40V Diode 200mA 70V Adjustable from Vref=2.5V 1% Diode 200mA 200V Zener 5.1V C1005C0G1H101J C1005C0G1H330J C1005X7R1H101J C1608X7R1H104K C1005X7R1E103K C1608C0G2E471J C3216X7R1C106K C1005C0G1H391J C2012X7R2E103K C1005X7R1H102K C4520X7R3D102K C1005X7R1H221K MURA110 1N4148 1N5819HW BAV70WT1 ZR431F01 MMBD1504A MMBZ5231BLT TDK TDK TDK TDK TDK TDK TDK TDK TDK TDK TDK TDK On Semi Fairchild Fairchild Fairchild Zetex Fairchild On Semi 1 4 1 1 3 1 2 1 2 3 1 1 2 2 2 4 1 1 1 Any 1 Jinchuan Vishay Infineon Infineon Infineon On Semi On Semi Vishay Generic 1 1 1 1 1 1 1 1 1 Generic 7 Generic 2 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 C5,C6,C15 C7 C9,C11,C12 C10,C13 C18,C22,C40,C54 C55,C56 C19,C20,C21,C24,C26, C27,C34,C35,C36,C69 C25 C28,C29,C30,C31 C32 C33 C38,C39,C48 C41 C43,C49 C45 C46,C47 C50,C58,C59 C52 C53 D2,D3 D4,D8 D5,D7 D6,D12,D15,D17 D13 D16 D18 JP1,JP3,JP4,JP5 JP9,JP10,JP11 L5 M7 Q2 Q3 Q4 Q7 Q9 RT1 R5 R6,R7,R10,R11 R68,R83,R106 R15,R16 Terminal LDC‐25‐7 Aux Switch(PMOS) MOSFET MOSFET MOSFET PNP ‐600mA ‐40V PNP ‐800mA ‐40V THERMISTOR 100KOHM 1% 0603 RES 4.7OHM 5% 1/10W 0603 RES 10KOHM 5% 1/16W 0402 INDUCTOR Si3437 IPD200N15N3 IPD053N08N3 IPD068N10N3 MMBT4403 MMBT2907AWT1 RES 2OHM 5% 1/10W 0603 Rev Prelim A Oct.2009 | Page 18 of 27 Reference Design PRD 1168 38 39 40 41 42 R17 R23,R38 R25 R26,R29,R33 R27 RES 2OHM 5% 1/16W 0402 RES 10OHM 5% 1/16W 0402 RES 680OHM 5% 1/16W 0402 RES 34KOHM 1% 1/16W 0402 RES4.7KOHM 5% 1/10W 0603 Generic Generic Generic Generic Generic 1 2 1 3 1 43 R28,R31,R41,R64,R71 RES 10KOHM 1% 1/16W 0402 Generic 5 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 R30,R34 R32,R35,R36 R40,R43,R44,R45 R42 R62,R102 R65 R66 R67,R70 R69 R72 R74 R76,R77 R78,R85 R79 R80,R81 R82,R99,R100,R104 R84 R86 R89 R90,R91,R92,R93 R101 T1 T3 T4 U3,U4 U6 U8,U9 U12 RES 25OHM 5% 1/10W 0603 RES 2KOHM 1% 1/16W 0402 RES 2.2KOHM 1% 1/16W 0402 RES 49.9KOHM 0.1% 1/16W 0402 RES 220OHM 5% 1/16W 0402 RES 8.2KOHM 1% 1/16W 0402 RES 330KOHM 1% 1/16W 0402 RES 100OHM 5% 1/16W 0402 RES 100KOHM 5% 1/10W 0603 RES 1KOHM 5% 1/16W 0402 RES 0OHM 5% 1/16W 0402 RES 20KOHM 5% 1/10W 0603 RES 499KFOHM 5% 1/10W 0603 RES 20KOHM 5% 1/16W 0402 RES 680OHM 5% 1/8W 0805 RES 5.1KOHM 5% 1/16W 0402 RES 55KOHM 5% 1/16W 0402 RES 36KOHM 5% 1/16W 0402 RES 2m OHM 1% 1/4W 1206 RES 5.1KOHM 1/4W 1206 RES 0OHM 5% 1/16W 0402 PA1005.100NL 20A 1:100 AUX TRANSFORMER MAIN TRANSFORMER iCoupler Secondary PWM Controller Dual channel driver IC NCP1031A Generic Generic Generic Generic Generic Generic Generic Generic Generic Generic Generic Generic Generic Generic Generic Generic Generic Generic Vishay Generic Generic Pulse Jinchuan Jinchuan ADI ADI ADI On Semi 2 3 4 1 2 1 1 2 1 1 1 2 2 1 2 4 1 1 1 4 1 1 1 1 2 1 2 1 72 U14 LDO ADI 1 BSER9‐77 BEQ‐25 ADuM3210 ADP1043A ADP3634 NCP1031A ADP1720ARMZ‐ 3.3‐R7 Rev Prelim A Oct.2009 | Page 19 of 27 Reference Design PRD 1168 PCB Layout Figure 27 Top view of Board Rev Prelim A Oct.2009 | Page 20 of 27 Reference Design PRD 1168 Figure 28 Bottom View of Board Rev Prelim A Oct.2009 | Page 21 of 27 Reference Design PRD 1168 BOARD SETTING Input Voltage = 48 V N1 = 5 N2 = 4 R (CS2) = 2.07 mOhm I (load) = 6 A R1 = 34 KOhm R2 = 2 KOhm C3 = 0.001 uF C4 = 0.001 uF N1 (CS1) = 1 N2 (CS1) = 100 R (CS1) = 10 Ohm ESR (L1) = 5 mOhm L1 = 14 uH C1 = 13.2 uF ESR (C1) = 1 mOhm ESR (L2) = 0 mOhm L2 = 0 uH C2 = 240 uF ESR (C2) = 35 mOhm R (Normal-Mode) (Load) = 3 Ohm R (Light-Load-Mode) (Load) = 36 Ohm Cap Across R1 & R2 = 0 "(1 = Yes: 0 = No)" Topology = 4 (0 = Full Bridge: 1 = Half Bridge: 2 = Two Switch Forward: 3 = Interleaved Two Switch Forward: 4 = Active Clamp Forward: 5 = Resonant Mode: 6 = Custom) Switches / Diodes = 1 (0 = Switches: 1 = Diodes) High Side / Low Side Sense (CS2) = 0 (1 = High-Side: 0 = Low-Side Sense) Second LC Stage = 1 (1 = Yes: 0 = No) CS1 Input Type = 0 (1 = AC: 0 = DC) R3 = 0 KOhm R4 = 0 KOhm PWM Main = 1 (0 = OUTA: 1 = OUTB: 2 = OUTC: 3 = OUTD: 4 = SR1: 5 = SR2: 6 = OUTAUX) Rev Prelim A Oct.2009 | Page 22 of 27 Reference Design PRD 1168 REGISTER SETTING Reg(0h) = F8h - Fault Register 1 Reg(1h) = 0h - Fault Register 2 Reg(2h) = 4h - Fault Register 3 Reg(3h) = 44h - Fault Register 4 Reg(4h) = F8h - Latched Fault Register 1 Reg(5h) = 0h - Latched Fault Register 2 Reg(6h) = 4h - Latched Fault Register 3 Reg(7h) = 45h - Latched Fault Register 4 Reg(8h) = 33h - Fault Configuration Register 1 Reg(9h) = 3Fh - Fault Configuration Register 2 Reg(Ah) = F0h - Fault Configuration Register 3 Reg(Bh) = 0h - Fault Configuration Register 4 Reg(Ch) = 0h - Fault Configuration Register 5 Reg(Dh) = 0h - Fault Configuration Register 6 Reg(Eh) = 81h - Flag Configuration Reg(Fh) = 66h - Soft-Start Flag Blank Reg(10h) = 0h - First Flag ID Reg(11h) = FFh - Reserved Reg(12h) = 0h - VS1 Value Reg(13h) = 0h - CS1 Value Reg(14h) = 0h - CS1 x VS1 Value Reg(15h) = 0h - VS1 Voltage Value Reg(16h) = 0h - VS2 Voltage Value Reg(17h) = 148h - VS3 Voltage Value Reg(18h) = 0h - CS2 Value Reg(19h) = 0h - CS2 x VS3 Value Reg(1Ah) = 4DE0h - RTD Temperature Value Reg(1Bh) = FFh - Reserved Reg(1Ch) = FFh - Reserved Reg(1Dh) = 0h - Share Bus Value Reg(1Eh) = C0h - Modulation Value Reg(1Fh) = FFh - Line Impedance Value Reg(20h) = FFh - Reserved Reg(21h) = 87h - CS1 Gain Trim Reg(22h) = 2Ah - CS1 OCP Limit Reg(23h) = 3Bh - CS2 Gain Trim Reg(24h) = 10h - CS2 Offset Trim Rev Prelim A Oct.2009 | Page 23 of 27 Reference Design PRD 1168 Reg(25h) = 0h - CS2 Digital Trim Reg(26h) = 3Ah - CS2 OCP Limit Reg(27h) = 0h - CS1 and CS2 OCP Setting Reg(28h) = 0h - VS Balance Gain Setting Reg(29h) = 0h - Share Bus Bandwidth Reg(2Ah) = 30h - Share Bus Setting Reg(2Bh) = 1Bh - Temperature Trim Reg(2Ch) = 62h - PSON/Soft Start Setting Reg(2Dh) = 0h - Pin Polarity Setting Reg(2Eh) = 12h - Modulation Limit Reg(2Fh) = 0h - OTP Threshold Reg(30h) = C0h - OrFET Reg(31h) = A4h - VS3 Voltage Setting Reg(32h) = 0h - VS1 Overvoltage Limit Reg(33h) = Ah - VS3 Overvoltage Limit Reg(34h) = 0h - VS1 Undervoltage Limit Reg(35h) = 0h - Line Impedance Limit Reg(36h) = 7h - Load Line Impedance Reg(37h) = FFh - Reserved Reg(38h) = CAh - VS1 Trim Reg(39h) = 9h - VS2 Trim Reg(3Ah) = CFh - VS3 Trim Reg(3Bh) = 0h - Light Load Disable Setting Reg(3Ch) = 5h - Silicon Revision ID Reg(3Dh) = 41h - Manufacturer ID Reg(3Eh) = 43h - Device ID Reg(3Fh) = 10h - OUTAUX Switching Frequency Setting Reg(40h) = 1Fh - PWM Switching Frequency Setting Reg(41h) = 0h - PWM 1 Positive Edge Timing Reg(42h) = 20h - PWM 1 Positive Edge Setting Reg(43h) = 24h - PWM 1 Negative Edge Timing Reg(44h) = 48h - PWM 1 Negative Edge Setting Reg(45h) = 2h - PWM 2 Positive Edge Timing Reg(46h) = 0h - PWM 2 Positive Edge Setting Reg(47h) = 22h - PWM 2 Negative Edge Timing Reg(48h) = 48h - PWM 2 Negative Edge Setting Reg(49h) = 12h - PWM 3 Positive Edge Timing Reg(4Ah) = 28h - PWM 3 Positive Edge Setting Reg(4Bh) = 42h - PWM 3 Negative Edge Timing Rev Prelim A Oct.2009 | Page 24 of 27 Reference Design PRD 1168 Reg(4Ch) = E0h - PWM 3 Negative Edge Setting Reg(4Dh) = 0h - PWM 4 Positive Edge Timing Reg(4Eh) = 0h - PWM 4 Positive Edge Setting Reg(4Fh) = 11h - PWM 4 Negative Edge Timing Reg(50h) = 0h - PWM 4 Negative Edge Setting Reg(51h) = 2h - SR 1 Positive Edge Timing Reg(52h) = 70h - SR 1 Positive Edge Setting Reg(53h) = 22h - SR 1 Negative Edge Timing Reg(54h) = 88h - SR 1 Negative Edge Setting Reg(55h) = 23h - SR 2 Positive Edge Timing Reg(56h) = A8h - SR 2 Positive Edge Setting Reg(57h) = 1h - SR 2 Negative Edge Timing Reg(58h) = 20h - SR 2 Negative Edge Setting Reg(59h) = 0h - PWM AUX Positive Edge Timing Reg(5Ah) = 0h - PWM AUX Positive Edge Setting Reg(5Bh) = 3Ah - PWM AUX Negative Edge Timing Reg(5Ch) = F0h - PWM AUX Negative Edge Setting Reg(5Dh) = 98h - PWM and SR Pin Disable Setting Reg(5Eh) = 0h - Password Lock Reg(5Fh) = 0h - Soft-Start Digital Filter LF Gain Setting Reg(60h) = 7h - Normal Mode Digital Filter LF Gain Setting Reg(61h) = F8h - Normal Mode Digital Filter Zero Setting Reg(62h) = F7h - Normal Mode Digital Filter Pole Setting Reg(63h) = 11h - Normal Mode Digital Filter HF Gain Setting Reg(64h) = Eh - Light Load Digital Filter LF Gain Setting Reg(65h) = D6h - Light Load Digital Filter Zero Setting Reg(66h) = D5h - Light Load Digital Filter Pole Setting Reg(67h) = 12h - Light Load Digital Filter HF Gain Setting Reg(68h) = 0h - Dead Time Threshold Reg(69h) = 0h - Dead Time 1 Reg(6Ah) = 0h - Dead Time 2 Reg(6Bh) = 0h - Dead Time 3 Reg(6Ch) = 0h - Dead Time 4 Reg(6Dh) = 0h - Dead Time 5 Reg(6Eh) = 0h - Dead Time 6 Reg(6Fh) = 0h - Dead Time 7 Reg(70h) = 14h Reg(71h) = Bh Reg(72h) = 53h Rev Prelim A Oct.2009 | Page 25 of 27 Reference Design PRD 1168 Reg(73h) = 9h Reg(74h) = 0h Reg(75h) = FFh Reg(76h) = FFh Reg(77h) = 0h Reg(78h) = 0h Reg(79h) = 1Bh Reg(7Ah) = 2h Reg(7Bh) = FFh - Factory Default Settings Reg(7Ch) = 1h - EEPROM X Address Reg(7Dh) = 35h - EEPROM Y Address Reg(7Eh) = 35h - EEPROM Register Reg(7Fh) = FFh Reg(80h) = 35h Reg(81h) = 35h Reg(82h) = 35h - Rev Prelim A Oct.2009 | Page 26 of 27 Reference Design PRD 1168 NOTES ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Error! Unknow Rev Prelim A Oct.2009 | Page 27 of 27