PD-97514 IR3859MPbF SupIRBuck HIGHLY EFFICIENT TM INTEGRATED 9A, SYNCHRONOUS BUCK REGULATOR Features • • • • • • • • • • • • • • • • • • • • • • Applications • • • Description Greater than 95% Maximum Efficiency Wide Input Voltage Range 1.5V to 21V Wide Output Voltage Range 0.7V to 0.9*Vin Continuous 9A Load Capability Integrated Bootstrap-diode High Bandwidth E/A for excellent transient performance Programmable Switching Frequency up to 1.5MHz Programmable Over Current Protection Over Voltage Protection Dedicated input for output voltage monitoring Programmable PGood output Hiccup Current Limit Precision Reference Voltage (0.7V, +/-1%) Programmable Soft-Start Enable Input with Voltage Monitoring Capability Enhanced Pre-Bias Start-up Seq input for Tracking applications External Synchronization -40oC to 125oC operating junction temperature Thermal Protection 4mm x 5mm Power QFN Package Halogen Free, Lead Free and RoHS compliant Server Applications Storage Applications Embedded Telecom Systems The IR3859 SupIRBuckTM is an easy-to-use, fully integrated and highly efficient DC/DC synchronous Buck regulator. The MOSFETs copackaged with the on-chip PWM controller make IR3859 a space-efficient solution, providing accurate power delivery for low output voltage applications. IR3859 is a versatile regulator which offers programmability of start up time, switching frequency and current limit while operating in wide input and output voltage range. The switching frequency is programmable from 250kHz to 1.5MHz for an optimum solution. It also features important protection functions, such as Pre-Bias startup, hiccup current limit and thermal shutdown to give required system level security in the event of fault conditions. • • • • Distributed Point of Load Power Architectures Netcom Applications Computing Peripheral Voltage Regulators General DC-DC Converters Fig. 1. Typical application diagram Rev 5.0 1 PD-97514 IR3859MPbF ABSOLUTE MAXIMUM RATINGS (Voltages referenced to GND unless otherwise specified) • Vin ……………………………………………………. -0.3V to 25V • Vcc ……………….….…………….……..……….…… -0.3V to 8V (Note2) • Boot ……………………………………..……….…. -0.3V to 33V • SW …………………………………………..……… -0.3V to 25V(DC), -4V to 25V(AC, 100ns) • Boot to SW • OCSet • Input / output Pins • PGND to GND ……………...………………………….. -0.3V to +0.3V • Storage Temperature Range ................................... -55°C To 150°C • Junction Temperature Range ................................... -40°C To 150°C (Note2) • ESD Classification …………………………… ……… JEDEC Class 1C • Moisture sensitivity level………………...………………JEDEC Level 3@260 °C (Note5) ……..…………………………….…..….. -0.3V to Vcc+0.3V (Note1) ………………………………………….……. -0.3V to 30V (Max 30mA) ……………………………….. ... -0.3V to Vcc+0.3V (Note1) Note1: Must not exceed 8V Note2: Vcc must not exceed 7.5V for Junction Temperature between -10oC and -40oC Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications are not implied. PACKAGE INFORMATION 4mm x 5mm POWER QFN θ JA( Sync _ FET ) = 45 o C / W * 13 12 VIN SW 11 θ JA( Ctrl _ FET ) = 45 o C / W * PGnd θ J -PCB = 2 o C / W Exposed pads on underside are connected to copper pads of a 4-layer (2 oz.) PCB * Boot 14 Enable 15 Seq 16 1 ORDERING INFORMATION Rev 5.0 10 17 Gnd 2 3 4 5 Fb Vsns COMP Gnd Rt 6 Vcc 9 Sync 8 PGood 7 SS OCSet PACKAGE DESIGNATOR PACKAGE DESCRIPTION PIN COUNT PARTS PER REEL M IR3859MTRPbF 17 4000 M IR3859MTR1PbF 17 750 2 PD-97514 IR3859MPbF Block Diagram Fig. 2. Simplified block diagram of the IR3859 Rev 5.0 3 PD-97514 IR3859MPbF Pin Description Pin Name Description 1 Fb 2 Vsns 3 Comp 4;17 Gnd 5 Rt 6 SS/SD 7 OCSet 8 PGood Power Good status pin. Output is open drain. Connect a pull up resistor from this pin to Vcc. 9 Sync Sync pin, connect external system clock to synchronize multiple POLs with the same frequency 10 V CC 11 PGnd This pin powers the internal IC and the drivers. A minimum of 1uF high frequency capacitor must be connected from this pin to the power ground (PGnd). Power Ground. This pin serves as a separated ground for the MOSFET drivers and should be connected to the system’s power ground plane. 12 SW Switch node. This pin is connected to the output inductor. 13 VIN Input voltage connection pin. 14 Boot 15 Enable 16 Seq Rev 5.0 Inverting input to the error amplifier. This pin is connected directly to the output of the regulator via resistor divider to set the output voltage and provide feedback to the error amplifier. Sense pin for PGood Output of error amplifier. An external resistor and capacitor network is typically connected from this pin to Fb pin to provide loop compensation. Signal ground for internal reference and control circuitry. Set the switching frequency. Connect an external resistor from this pin to Gnd to set the switching frequency. See Table 1 for Fs vs. Rt. Soft start / shutdown. This pin provides user programmable soft-start function. Connect an external capacitor from this pin to Gnd to set the start up time of the output voltage. The converter can be shutdown by pulling this pin below 0.3V. Current limit set point. A resistor from this pin to SW pin will set the current limit threshold. Supply voltage for high side driver. A 0.1uF capacitor must be connected from this pin to SW. Enable pin to turn on and off the device. Use two external resistors to set the turn on threshold (see Enable section). Connect this pin to Vcc if it is not used. Sequence pin. Use two external resistors to set Simultaneous Power up sequencing. If this pin is not used connect to Vcc. 4 PD-97514 IR3859MPbF Recommended Operating Conditions Symbol Vin Vcc Boot to SW Vo Io Fs Tj Definition Input Voltage Supply Voltage Supply Voltage Output Voltage Output Current Switching Frequency Junction Temperature Min Max 1.5 4.5 4.5 0.7 0 225 -40 21* 5.5 5.5 0.9*Vin 9 1650 125 Units V A kHz o C * Note: SW node should not exceed 25V Electrical Specifications Unless otherwise specified, these specification apply over 4.5V< Vcc<5.5V, Vin=12V, 0oC<Tj< 125oC. Typical values are specified at Ta = 25oC. PARAMETER POWER STAGE Power Losses SYMBOL TEST CONDITION Ploss Vcc=5V, Vin=12V, Vo=1.8V, Io=9A, Fs=600kHz, L=0.68uH, Note4 Top Switch Rds(on)_Top Bottom Switch Deadband Time Rds(on)_Bot Tdb Bootstrap Diode Forward Voltage SW leakage Current o VCC Supply Current (Dyn) UNIT W 29 11 16 5 10 30 ns 180 260 470 mV Vcc=5V, ID=9A, Tj=25 C mΩ SW=0V, Enable=0V 6 SW=0V, Enable=high, SS=3V, Vseq=0V, Note4 SUPPLY CURRENT VCC Supply Current (Standby) MAX 21 o Note4 TYP 2.1 VBoot -Vsw =5V, ID=9A, Tj=25 C I(Boot)= 30mA Isw MIN ICC(Standby) SS=0V, Vcc=5V, Enable low , No Switching ICC(Dyn) SS=3V, Vcc=5V, Enable high, Fs=500kHz 500 5.5 9.97 14 uA uA mA REFERENCE VOLTAGE Feedback Voltage VFB 0.7 o Accuracy o 0 C<Tj<125 C o o -40 C<Tj<125 C, Note3 V -1.0 +1.0 -2.0 -2.0 % SOFT START / SD Soft Start Current Soft Start Clamp Voltage Shutdown Output Threshold Rev 5.0 ISS Vss(clamp) SD Source 14 20 26 2.7 3.0 3.3 0.3 uA V 5 PD-97514 IR3859MPbF Electrical Specifications (continued) Unless otherwise specified, these specifications apply over 4.5V< Vcc<5.5V, Vin=12V, 0oC<Tj< 125oC. Typical values are specified at Ta = 25oC. PARAMETER ERROR AMPLIFIER Input Offset Voltage SYMBOL MAX UNIT -10 +10 mV Input Bias Current IFb(E/A) -1 +1 Input Bias Current IVseq(E/A) -1 +1 Sink Current Isink(E/A) 0.40 0.85 1.2 Isource(E/A) 8 10 13 mA Source Current Slew Rate Gain-Bandwidth Product DC Gain Vos TYP μA Note4 7 12 20 V/μs GBWP Note4 20 30 40 MHz Gain Note4 100 110 120 dB Vcc=4.5V 3.4 3.5 3.75 V 120 220 mV 1 V V Vmax(E/A) Minimum Voltage Vmin(E/A) Note4 Seq Common Mode Voltage Frequency Range Vfb-Vseq, Vseq=0.8V MIN SR Maximum Voltage OSCILLATOR Rt Voltage TEST CONDITION Vrt FS 0 0.665 0.7 0.735 Rt=59K 225 250 275 Rt=28.7K 450 500 550 Rt=9.31K, Note4 1350 1500 1650 kHz Vramp Note4 1.8 Vp-p Ramp Offset Ramp(os) Note4 0.6 V Min Pulse Width Dmin(ctrl) Note4 50 ns Ramp Amplitude Max Duty Cycle Dmax Fixed Off Time Toff Fs=250kHz 92 Note4 130 Sync Frequency Range Fsync 225 Sync Pulse Duration Tsync 100 Sync Level Threshold High 2 Low Rev 5.0 % 200 ns 1650 kHz 200 ns V 0.6 6 PD-97514 IR3859MPbF Electrical Specifications (continued) Unless otherwise specified, these specification apply over 4.5V< Vcc<5.5V, Vin=12V, 0oC<Tj< 125oC. Typical values are specified at Ta = 25oC. P ARAMETER S YMBOL TEST CONDITION MIN TYP MAX Fs =250kHz 20.8 23.6 26.4 Fs =500kHz 43 48.8 54.6 Fs =1500k Hz 136 154 172 Note4 -10 0 +10 UNIT FAULT PROTECTION OCSET Current OC com p Offset Voltage SS off tim e OVP Trip Threshold OVP Fault Prop. Delay I OCSET VOFFS ET SS_Hicc up OVP(trip) OVP(delay) 4096 Vsns Rising 110 115 Note4 Therm al Shutdown Note4 140 Therm al Hysteresis Note4 20 120 %Vref 150 ns °C V CC _UVLO_S tart Vcc Rising Trip Level 3.95 4.15 4.35 VCC-Stop-Threshold V CC _UVLO_S top Vcc Falling Trip Level 3.65 3.85 4.05 INPUT/OUTPUT SIGNAL Enable-Start-Threshold E nable_UVLO_Start Supply ramping up 1.14 1.2 1.36 Enable-Stop-Threshold E nable_UVLO_Stop Supply ramping down 0.9 1.0 1.06 Enable leakage current Ien Enable= 3.3V VPG Vsns Rising 85 15 90 PGood Com parator Delay PG(Delay) Vsns Rising PGood Delay Com parator Threshold SS(Delay) Relative to charge voltage, SS rising PGood Delay Com parator Hysteresis Delay(SShys) PGood Leak age Current PGood Voltage Low Note4 I(PGDlk) PG(voltage) IP good= -5mA 80 mV Cyc les VCC-Start-Threshold Power Good Threshold uA 256/Fs V V uA %Vref s 2 2.1 2.3 V 260 300 340 mV 0 10 uA 0.5 V Note3: Cold temperature performance is guaranteed via correlation using statistical quality control. Not tested in production. Note4: Guaranteed by Design but not tested in production. Note5: Upgrade to industrial/MSL2 level applies from date codes 1227 (marking explained on application note AN1132 page 2). Products with prior date code of 1227 are qualified with MSL3 for Consumer market. Rev 5.0 7 PD-97514 IR3859MPbF Typical Efficiency and Power Loss Curves Vin=12V, Vcc=5V, Io=0.9A- 9A, Fs=600kHz, Room Temperature, No Air Flow The table below shows the inductors used for each of the output voltages in the efficiency measurement. Vo (V) 1 1.2 1.5 1.8 3.3 5 L (uH) 0.51 0.51 0.68 0.68 1.2 1.2 P/N 59PR9876N 59PR9876N ETQP4LR68XFC ETQP4LR68XFC MPL105-1R2 MPL105-1R2 DCR (mOhm) 0.29 0.29 1.58 1.58 2.9 2.9 97 95 Efficiency (%) 93 91 89 87 85 83 81 79 0.9 1.8 2.7 3.6 4.5 5.4 6.3 7.2 8.1 9.0 Load Current (A) Power Loss (W) 1.0V 1.2V 1.5V 1.8V 3.3V 5V 3.0 2.8 2.6 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.9 1.8 2.7 3.6 4.5 5.4 6.3 7.2 8.1 9.0 Load Current (A) 1.0V Rev 5.0 1.2V 1.5V 1.8V 3.3V 5.0V 8 PD-97514 IR3859MPbF Typical Efficiency and Power Loss Curves Vin=5V, Vcc=5V, Io=0.9A- 9A, Fs=600kHz, Room Temperature, No Air Flow The table below shows the inductors used for each of the output voltages in the efficiency measurement. Vo (V) 1 1.2 1.5 1.8 3.3 L (uH) 0.4 0.51 0.51 0.51 0.51 P/N 59PR9875N 59PR9876N 59PR9876N 59PR9876N 59PR9876N DCR (mOhm) 0.29 0.29 0.29 0.29 0.29 97 96 95 94 Efficiency (%) 93 92 91 90 89 88 87 86 85 84 83 0.9 1.8 2.7 1.0V 3.6 4.5 5.4 Load Current (A) 1.2V 6.3 1.5V 7.2 8.1 1.8V 9.0 3.3V 2.7 2.5 2.3 Power Loss (W) 2.1 1.9 1.7 1.5 1.3 1.1 0.9 0.7 0.5 0.3 0.1 0.9 1.8 2.7 3.6 4.5 5.4 6.3 7.2 8.1 9.0 Load Current (A) 1.0Vout Rev 5.0 1.2Vout 1.5Vout 1.8Vout 3.3Vout 9 PD-97514 IR3859MPbF Resistance [m Ω ] Rdson of MOSFETs Over Temperature at Vcc=5V 30 28 26 24 22 20 18 16 14 12 10 8 -40 -20 0 20 40 60 Temperature [ °C] Sync-FET 80 100 120 Ctrl-FET Thermal De-rating Curves Test Conditions: Vin=12V, Vout=1.8V, Vcc=5V, Fs=600kHz, 0- 200LFM L=0.68uH (ETQP4LR68XFC) Maximum Load Current (A) 9.0 8.5 8.0 7.5 7.0 6.5 6.0 25 30 35 40 45 50 55 60 65 70 75 80 85 Ambient Temperature (°C) 0 LFM Rev 5.0 100LFM 200LFM 10 PD-97514 IR3859MPbF TYPICAL OPERATING CHARACTERISTICS (-40oC - 125oC) Fs=500 kHz Icc(Dyn) 13.5 270 12.5 250 11.5 230 [mA] [uA] Icc(Standby) 290 210 10.5 9.5 8.5 190 7.5 170 6.5 150 -40 -20 0 20 40 60 80 100 5.5 120 -40 o Temp[ C] 20 60 80 100 120 80 100 120 80 100 120 60 80 100 120 60 80 100 120 IOCSET(500kHz) 54.0 53.0 52.0 520 51.0 510 50.0 [uA] 530 500 490 49.0 48.0 47.0 480 46.0 470 45.0 460 44.0 43.0 450 -40 -20 0 20 40 60 Temp[ oC] 80 100 -40 120 -20 0 20 40 60 Temp[ oC] Vcc(UVLO) Start 4.46 Vcc(UVLO) Stop 4.16 4.11 4.36 4.06 4.31 4.01 [V] 4.41 4.26 3.96 4.21 3.91 4.16 3.86 4.11 3.81 3.76 4.06 -40 -20 0 20 40 60 o 80 100 -40 120 -20 0 20 Enable(UVLO) Start 1.36 40 60 Temp[ oC] Temp[ C] Enable(UVLO) Stop 1.06 1.34 1.04 1.32 1.30 1.02 1.28 1.00 1.26 [V] [V] 40 Temp[ oC] 540 [kHz] 0 FREQUENCY 550 [V] -20 1.24 0.98 1.22 0.96 1.20 0.94 1.18 0.92 1.16 1.14 0.90 -40 -20 0 20 40 o 60 80 100 120 -40 -20 0 Temp[ C] 20 40 Temp[ οC] ISS 26.0 Vfb 711 24.0 706 [uA] [mV] 22.0 20.0 701 18.0 696 16.0 691 14.0 686 -40 -20 0 20 40 o 60 Temp[ C] Rev 5.0 80 100 120 -40 -20 0 20 40 o Temp[ C] 11 PD-97514 IR3859MPbF Circuit Description THEORY OF OPERATION Introduction The IR3859 uses a PWM voltage mode control scheme with external compensation to provide good noise immunity and maximum flexibility in selecting inductor values and capacitor types. The switching frequency is programmable from 250kHz to 1.5MHz and provides the capability of optimizing the design in terms of size and performance. IR3859 provides precisely regulated output voltage programmed via two external resistors from 0.7V to 0.9*Vin. If the input to the Enable pin is derived from the bus voltage by a suitably programmed resistive divider, it can be ensured that the IR3859 does not turn on until the bus voltage reaches the desired level. Only after the bus voltage reaches or exceeds this level will the voltage at Enable pin exceed its threshold, thus enabling the IR3859. Therefore, in addition to being a logic input pin to enable the IR3859, the Enable feature, with its precise threshold, also allows the user to implement an Under-Voltage Lockout for the bus voltage Vin. This is desirable particularly for high output voltage applications, where we might want the IR3859 to be disabled at least until Vin exceeds the desired output voltage level. The IR3859 operates with an external bias supply from 4.5V to 5.5V, allowing an extended operating input voltage range from 1.5V to 21V. The device utilizes the on-resistance of the low side MOSFET as current sense element, this method enhances the converter’s efficiency and reduces cost by eliminating the need for external current sense resistor. IR3859 includes two low Rds(on) MOSFETs using IR’s HEXFET technology. These are specifically designed for high efficiency applications. Under-Voltage Lockout and POR The under-voltage lockout circuit monitors the input supply Vcc and the Enable input. It assures that the MOSFET driver outputs remain in the off state whenever either of these two signals drop below the set thresholds. Normal operation resumes once Vcc and Enable rise above their thresholds. The POR (Power On Ready) signal is generated when all these signals reach the valid logic level (see system block diagram). When the POR is asserted the soft start sequence starts (see soft start section). Enable The Enable features another level of flexibility for start up. The Enable has precise threshold which is internally monitored by Under-Voltage Lockout (UVLO) circuit. Therefore, the IR3859 will turn on only when the voltage at the Enable pin exceeds this threshold, typically, 1.2V. Rev 5.0 Fig. 3a. Normal Start up, Device turns on when the Bus voltage reaches 10.2V Figure 3b. shows the recommended start-up sequence for the non-sequenced operation of IR3859, when Enable is used as a logic input. Fig. 3b. Recommended startup sequence, Non-Sequenced operation 12 PD-97514 IR3859MPbF Figure 3c. shows the recommended startup sequence for sequenced operation of IR3859 with Enable used as logic input. Fig. 5. Pre-Bias startup pulses Soft-Start Fig. 3c. Recommended startup sequence, Sequenced operation Pre-Bias Startup The IR3859 has a programmable soft-start to control the output voltage rise and to limit the current surge at the start-up. To ensure correct start-up, the soft-start sequence initiates when the Enable and Vcc rise above their UVLO thresholds and generate the Power On Ready (POR) signal. The internal current source (typically 20uA) charges the external capacitor Css linearly from 0V to 3V. Figure 6 shows the waveforms during the soft start. The start up time can be estimated by: (1.4 - 0.7) * CSS IR3859 is able to start up into pre-charged output, which prevents oscillation and disturbances of the output voltage. Tstart = The output starts in asynchronous fashion and keeps the synchronous MOSFET off until the first gate signal for control MOSFET is generated. Figure 4 shows a typical Pre-Bias condition at start up. During the soft start the OCP is enabled to protect the device for any short circuit and over current condition. 20μA - - - - - - - - - - - - - - - - - - - - (1) The synchronous MOSFET always starts with a narrow pulse width and gradually increases its duty cycle with a step of 25%, 50%, 75% and 100% until it reaches the steady state value. The number of these startup pulses for the synchronous MOSFET is internally programmed. Figure 5 shows a series of 32, 16, 8 startup pulses. Fig. 6. Theoretical operation waveforms during soft-start Fig. 4. Pre-Bias startup Rev 5.0 13 PD-97514 IR3859MPbF Operating Frequency The switching frequency can be programmed between 250kHz – 1500kHz by connecting an external resistor from Rt pin to Gnd. Table 1 tabulates the oscillator frequency versus Rt. Table 1. Switching Frequency and IOCSet vs. External Resistor (Rt) Rt (kΩ) 47.5 35.7 28.7 23.7 20.5 17.8 15.8 14.3 12.7 11.5 10.7 9.76 9.31 Fs (kHz) 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500 Iocset (μA) 29.4 39.2 48.7 59.07 68.2 78.6 88.6 97.9 110.2 121.7 130.8 143.4 150.3 Shutdown The IR3859 can be shutdown by pulling the Enable pin below its 1 V threshold. This will tristate both, the high side driver as well as the low side driver. Alternatively, the output can be shutdown by pulling the soft-start pin below 0.3V. Normal operation is resumed by cycling the voltage at the Soft Start pin. Over-Current Protection The over current protection is performed by sensing current through the RDS(on) of low side MOSFET. This method enhances the converter’s efficiency and reduces cost by eliminating a current sense resistor. As shown in figure 7, an external resistor (ROCSet) is connected between OCSet pin and the switch node (SW) which sets the current limit set point. An internal current source sources current (IOCSet ) out of the OCSet pin. This current is a function of Rt and hence, of the free-running switching frequency. Rev 5.0 I OCSet (μA ) = 1400 .......... .......... ...............( 2) R t (kΩ) Table 1. shows IOCSet at different switching frequencies. The internal current source develops a voltage across ROCSet. When the low side MOSFET is turned on, the inductor current flows through the Q2 and results in a voltage at OCSet which is given by: VOCSet = ( IOCSet ∗ ROCSet ) − ( RDS(on) ∗ I L ) ...........(3) Fig. 7. Connection of over current sensing resistor An over current is detected if the OCSet pin goes below ground. Hence, at the current limit threshold, VOCset=0. Then, for a current limit setting ILimit, ROCSet is calculated as follows: ROCSet = RDS ( on) * ILimit IOCSet ........................(4) An overcurrent detection trips the OCP comparator, latches OCP signal and cycles the soft start function in hiccup mode. The hiccup is performed by shorting the soft-start capacitor to ground and counting the number of switching cycles. The Soft Start pin is held low until 4096 cycles have been completed. The OCP signal resets and the converter recovers. After every soft start cycle, the converter stays in this mode until the overload or short circuit is removed. The OCP circuit starts sampling current typically 160 ns after the low gate drive rises to about 3V. This delay functions to filter out switching noise. 14 PD-97514 IR3859MPbF Thermal Shutdown Temperature sensing is provided inside IR3859. The trip threshold is typically set to 140oC. When trip threshold is exceeded, thermal shutdown turns off both MOSFETs and discharges the soft start capacitor. 1.5V <Vin<16V 4.5V <Vcc<5.5V Enable Vin Boot Vo(master) Vcc SW PGood PGood OCSet Seq Automatic restart is initiated when the sensed temperature drops within the operating range. There is a 20oC hysteresis in the thermal shutdown threshold. RA Fb Rt SS/ SD RB Gnd PGnd Comp 1.5V <Vin<16V Output Voltage Sequencing The IR3859 can accommodate user programmable sequencing options using Seq, Enable and Power Good pins. 4.5V <Vcc<5.5V Enable Vo(master) Vin Boot Vo(slave) Vcc SW PGood RE PGood OCSet Seq RF Rt RD Vo1 SS/ SD Vo2 RC Fb Gnd PGnd Comp Fig. 8b. Application Circuit for Simultaneous Sequencing Power-Good and Over-voltage Protection Simultaneous Powerup Fig. 8a. Simultaneous Power-up of the slave with respect to the master. Through these pins, voltage sequencing such as simultaneous and sequential can be implemented. Figure 8. shows simultaneous sequencing configurations. In simultaneous power-up, the voltage at the Seq pin of the slave reaches 0.7V before the Fb pin of the master. For RE/RF =RC/RD, therefore, the output voltage of the slave follows that of the master until the voltage at the Seq pin of the slave reaches 0.7 V. After the voltage at the Seq pin of the slave exceeds 0.85V, the internal 0.7V reference of the slave dictates its output voltage. The Vsns pin forms an input to a window comparator whose upper and lower thresholds are 0.805V and 0.595V, respectively. Hence, the Power Good signal is flagged when the Vsns pin voltage is within the PGood window, i.e. between 0.595V to 0.805V, as shown in figure 9. The PGood pin is open drain and it needs to be externally pulled high. High state indicates that output is in regulation. Figure 9a shows the PGood timing diagram for non-tracking operation. In this case, during startup, PGood goes high after the SS voltage reaches 2.1V if the Vsns voltage is within the PGood comparator window. Figure 9.a and Figure 9.b also show a 256 cycle delay between the Vsns voltage entering within the thresholds defined by the PGood window and PGood going high. If the output voltage exceeds the over voltage threshold, an over voltage trip signal asserts, this will result to turn off the high side driver and turn on the low side driver until the Vsns voltage drops below 1.15*Vref threshold. Both drivers are latched off until a reset performed by cycling either Vcc or Enable. The OVP threshold can be externally programmed to user defined value. Figure 10 shows the response in over-voltage condition. Rev 5.0 15 PD-97514 IR3859MPbF TIMING DIAGRAM OF PGOOD FUNCTION 2.1V 1.4V 0.7V SS 0 1.15*Vref(typical), +/-5% for Min/Max PGood window Vsns 0.85*Vref(typical), +/-5% for Min/Max 0 At point “A” the power Good signal goes low, high drive turns off, low drive turns on till Vsns is above Over Voltage threshold and the device latches off. POR (Vcc/Enable) needs to be recycled for new start up. PGood 0 100ns(typical) Delay 100ns(typical) Delay A Fig.9a IR3859 Non-Tracking Operation (Seq=Vcc) 256/Fs Fig.9b IR3859 Tracking Operation Rev 5.0 16 PD-97514 IR3859MPbF TIMING DIAGRAM OF Over Voltage Protection Fig.10 IR3859 Over Voltage Timing Diagram External Synchronization The IR3859 incorporates an internal circuit which enables synchronization of the internal oscillator (using rising edge) to an external clock. An external resistor from Rt pin to Gnd is still required to set the free-running frequency close to the Sync input frequency. This function is important to avoid sub-harmonic oscillations due to beat frequency for embedded systems when multiple POL (point of load) regulators are used. The synchronization clock can be applied during IR3859 normal operation or before IR3859 startup. In any case, IR3859 will perform with the external after the end of the PreBias cycle. Applying the external signal to the Sync input changes the effective value of the ramp signal (Vramp/Vosc). Vosc ( eff ) = 1.8 × fFree _ Run fSync ........................ (5) the frequency of the Sync (fSync) and the freerunning frequency (fFree_Run) results in more change in the effective amplitude of the ramp signal. Therefore, since the ramp amplitude takes part in calculating the loop-gain and bandwidth of the regulator, it is recommended not to use a Sync frequency which is much higher than the freerunning frequency. In addition, the effective value of the ramp signal, given by equation (5), should be used when the compensator is designed for the regulator. The pulse width of the external clock, which is applied to the sync, should be greater than 100ns and its high level should be greater than 2V, while its lower level is less than 0.6V. If this pin is left floating, the IC will run with the free running frequency set by the resistor Rt. Equation (5) shows that the effective amplitude of the ramp (Vosc(eff)) is reduced after the external Sync signal is applied. More difference between Rev 5.0 17 PD-97514 IR3859MPbF Minimum on time Considerations Maximum Duty Ratio Considerations The minimum ON time is the shortest amount of time for which the Control FET may be reliably turned on, and this depends on the internal timing delays. For the IR3859, the typical minimum on-time is specified as 50 ns. Any design or application using the IR3859 must ensure operation with a pulse width that is higher than this minimum on-time and preferably higher than 100 ns. This is necessary for the circuit to operate without jitter and pulse-skipping, which can cause high inductor current ripple and high output voltage ripple. A fixed off-time of 200 ns maximum is specified for the IR3859. This provides an upper limit on the operating duty ratio at any given switching frequency. It is clear, that higher the switching frequency, the lower is the maximum duty ratio at which the IR3859 can operate. To allow a margin of 50ns, the maximum operating duty ratio in any application using the IR3859 should still accommodate about 250 ns off-time. Fig 10. shows a plot of the maximum duty ratio v/s the switching frequency, with 250 ns off-time. = M a x Duty Cycle D Fs Vout Vin × Fs In any application that uses the IR3859, the following condition must be satisfied: t on (min) ≤ t on ∴ t on (min) ≤ Vout Vin × Fs Vout t on(min) The minimum output voltage is limited by the reference voltage and hence Vout(min) = 0.7 V. Therefore, for Vout(min) = 0.7 V, ∴ Vin × Fs ≤ ∴ Vin × Fs ≤ Max D uty C ycle (%) t on = 95 90 85 80 75 70 65 60 55 250 450 650 850 1050 1250 1450 1650 S w itchin g Freq uency (kH z ) Fig. 11. Maximum duty cycle v/s switching frequency. Vout (min) t on(min) 0.7 V ∴ Vin × Fs ≤ = 7 × 10 6 V/s 100 ns Therefore, at the maximum recommended input voltage 21V and minimum output voltage, the converter should be designed at a switching frequency that does not exceed 333 kHz. Conversely, for operation at the maximum recommended operating frequency 1.65 MHz and minimum output voltage, any voltage above 4.2 V may not be stepped down without pulseskipping. Rev 5.0 18 PD-97514 IR3859MPbF When an external resistor divider is connected to the output as shown in figure 12. Equation (6) can be rewritten as: Application Information Design Example: The following example is a typical application for IR3859. The application circuit is shown on page 25. Vin = 12 V ( 13.2V max) Vo = 1.8 V Io = 9 A ΔVo ≤ ± 5% of Vo Fs = 600 kHz ⎛ V ⎞ R9 = R8 ∗ ⎜⎜ ref ⎟⎟ ..................................(9) ⎝ V o−Vref ⎠ For the calculated values of R8 feedback compensation section. and R9 see VOUT IR3859 IR3624 R8 Fb R9 Enabling the IR3859 As explained earlier, the precise threshold of the Enable lends itself well to implementation of a UVLO for the Bus Voltage. V in IR3859 Enable R1 R2 For a maximum Enable threshold of VEN = 1.36 V Vin(min) * R2 = VEN = 1.36V........... (6) R1 + R2 VEN R2 = R1 .......... (7) Vin( min ) − VEN For a Vin (min)=10.2V, R1=49.9K and R2=7.5K is a good choice. Programming the frequency For Fs = 600 kHz, select Rt = 23.7 kΩ, using Table. 1. Output Voltage Programming Output voltage is programmed by reference voltage and external voltage divider. The Fb pin is the inverting input of the error amplifier, which is internally referenced to 0.7V. The divider is ratioed to provide 0.7V at the Fb pin when the output is at its desired value. The output voltage is defined by using the following equation: ⎛ R ⎞ Vo = Vref ∗ ⎜⎜ 1 + 8 ⎟⎟ .......... .......... .(8) R9 ⎠ ⎝ Rev 5.0 Fig. 12. Typical application of the IR3859 for programming the output voltage Soft-Start Programming The soft-start timing can be programmed by selecting the soft-start capacitance value. From (1), for a desired start-up time of the converter, the soft start capacitor can be calculated by using: CSS ( μF ) = Tstart ( ms ) × 0.02857 .......... (10) Where Tstart is the desired start-up time (ms). For a start-up time of 3.5ms, the soft-start capacitor will be 0.099μF. Choose a 0.1μF ceramic capacitor. Bootstrap Capacitor Selection To drive the Control FET, it is necessary to supply a gate voltage at least 4V greater than the voltage at the SW pin, which is connected the source of the Control FET . This is achieved by using a bootstrap configuration, which comprises the internal bootstrap diode and an external bootstrap capacitor (C6), as shown in Fig. 13. The operation of the circuit is as follows: When the lower MOSFET is turned on, the capacitor node connected to SW is pulled down to ground. The capacitor charges towards Vcc through the internal bootstrap diode, which has a forward voltage drop VD. The voltage Vc across the bootstrap capacitor C6 is approximately given as Vc ≅ Vcc − VD .......................... (11) When the upper MOSFET turns on in the next cycle, the capacitor node connected to SW rises to the bus voltage Vin. However, if the value of C6 is appropriately chosen, the voltage Vc 19 PD-97514 IR3859MPbF across C6 remains approximately unchanged and the voltage at the Boot pin becomes: VBoot ≅ Vin + Vcc − VD ........................................ (12) Fig. 13. Bootstrap circuit to generate Vc voltage A bootstrap capacitor of value 0.1uF is suitable for most applications. Inductor Selection The inductor is selected based on output power, operating frequency and efficiency requirements. A low inductor value causes large ripple current, resulting in the smaller size, faster response to a load transient but poor efficiency and high output noise. Generally, the selection of the inductor value can be reduced to the desired maximum ripple current in the inductor (Δi ) . The optimum point is usually found between 20% and 50% ripple of the output current. For the buck converter, the inductor value for the desired operating ripple current can be determined using the following relation: 1 Δi ; Δt = D ∗ Fs Δt ....................... (15) Vo L = (Vin − Vo ) ∗ Vin ∗ Δi * Fs Vin − Vo = L ∗ Where: Vin = Maximum input voltage Input Capacitor Selection The ripple current generated during the on time of the upper MOSFET should be provided by the input capacitor. The RMS value of this ripple is expressed by: Vo = Output Voltage Δi = Inductor ripple current F s = Switching frequency Δt = Turn on time D = Duty cycle IRMS = Io ∗ D ∗ ( 1 − D ) ........................(13) V D = o ................................ (14) Vin If Δi ≈ 42%(Io), then the output inductor is calculated to be 0.69μH. Select L=0.68 μH. The ETQP4LR68XFC from Panasonic provides a compact inductor suitable for this application. Where: D is the Duty Cycle IRMS is the RMS value of the input capacitor current. Io is the output current. For Io=9A and D = 0.15, the IRMS = 3.21A. Ceramic capacitors are recommended due to their peak current capabilities. They also feature low ESR and ESL at higher frequency which enables better efficiency. For this application, it is advisable to have 4x10uF 25V ceramic capacitors C3216X5R1E106M from TDK. In addition to these, although not mandatory, a 1X330uF, 25V SMD capacitor EEV-FK1E331P may also be used as a bulk capacitor and is recommended if the input power supply is not located close to the converter. Rev 5.0 20 PD-97514 IR3859MPbF Output Capacitor Selection The voltage ripple and transient requirements determine the output capacitors type and values. The criteria is normally based on the value of the Effective Series Resistance (ESR). However the actual capacitance value and the Equivalent Series Inductance (ESL) are other contributing components. These components can be described as ΔVo = ΔVo( ESR ) + ΔVo( ESL ) + ΔVo( C ) The output LC filter introduces a double pole, –40dB/decade gain slope above its corner resonant frequency, and a total phase lag of 180o (see figure 13). The resonant frequency of the LC filter is expressed as follows: FLC = 1 2 ∗ π Lo ∗ Co ................................ (17) Figure 14 shows gain and phase of the LC filter. Since we already have 180o phase shift from the output filter alone, the system runs the risk of being unstable. ΔVo( ESR ) = ΔIL * ESR ⎛ V − Vo ⎞ ΔVo( ESL ) = ⎜ in ⎟ * ESL ⎝ L ⎠ ΔVo( C ) = ΔI L 8 * Co * Fs ΔVo = Output voltage ripple ΔIL = Inductor ripple ............... (16) current Since the output capacitor has a major role in the overall performance of the converter and determines the result of transient response, selection of the capacitor is critical. The IR3859 can perform well with all types of capacitors. As a rule, the capacitor must have low enough ESR to meet output ripple and load transient requirements. The goal for this design is to meet the voltage ripple requirement in the smallest possible capacitor size. Therefore it is advisable to select ceramic capacitors due to their low ESR and ESL and small size. Six of the TDK C2102X5R0J226M (22uF, 6.3V, 3mOhm) capacitors is a good choice. Feedback Compensation The IR3859 is a voltage mode controller. The control loop is a single voltage feedback path including error amplifier and error comparator. To achieve fast transient response and accurate output regulation, a compensation circuit is necessary. The goal of the compensation network is to provide a closed-loop transfer function with the highest 0 dB crossing frequency and adequate phase margin (greater than 45o). Rev 5.0 Fig. 14. Gain and Phase of LC filter The IR3859 uses a voltage-type error amplifier with high-gain (110dB) and wide-bandwidth. The output of the amplifier is available for DC gain control and AC phase compensation. The error amplifier can be compensated either in Type-II or Type-III compensation. Local feedback with Type-II compensation is shown in figure 14. This method requires that the output capacitor should have enough ESR to satisfy stability requirements. In general, for Type-II compensation the output capacitor’s ESR generates a zero typically at 5kHz to 50kHz which is essential for an acceptable phase margin. The ESR zero of the output capacitor is expressed as follows: FESR = 1 ........................... (18) 2 ∗ π*ESR*Co 21 PD-97514 IR3859MPbF Where: Vin = Maximum Input Voltage Vosc = Oscillator Ramp Voltage Fo = Crossover Frequency FESR = Zero Frequency of the Output Capacitor FLC = Resonant Frequency of the Output Filter R8 = Feedback Resistor To cancel one of the LC filter poles, place the zero before the LC filter resonant frequency pole: Fz = 75% FLC Fz = 0.75 * Fig. 15. Type II compensation network and its asymptotic gain plot The transfer function (Ve/Vo) is given by: 1+ sR3C4 Z Ve .....(19) = H( s ) = − f = − ZIN sR8C4 Vo The (s) indicates that the transfer function varies as a function of frequency. This configuration introduces a gain and zero, expressed by: H (s ) = Fz = R3 ......... ............................. (20) R8 1 ............................ (21) 2π * R3 * C4 First select the desired zero-crossover frequency (Fo ): Fo > FESR and Fo ≤ (1/5 ~ 1/10 ) * Fs Vosc * Fo * FESR * R8 Vin * 2 FLC ........................... (22) 2π Lo * Co ..................................... (23) Use equations (21), (22) and (23) to calculate C4. One more capacitor is sometimes added in parallel with C4 and R3. This introduces one more pole which is mainly used to suppress the switching noise. The additional pole is given by: FP = 1 ...............................(24) C * CPOLE 2π * R3 * 4 C 4 + CPOLE The pole sets to one half of the switching frequency which results in the capacitor CPOLE: CPOLE = 1 1 π*R3*Fs − C4 ≅ 1 ......................(25) π*R3*Fs For a general solution for unconditional stability for any type of output capacitors, and a wide range of ESR values, we should implement local feedback with a Type-III compensation network. The typically used compensation network for voltage-mode controller is shown in figure 16. Again, the transfer function is given by: Ve Z = H(s) = − f Vo ZIN Use the following equation to calculate R3: R3 = 1 By replacing Zin and Zf according to figure 16, the transfer function can be expressed as: − (1 + sR3C4 )[1 + sC7 (R8 + R10 )] ⎡ ⎛ C * C3 ⎞ ⎤ ⎟⎟⎥ (1 + sR10C7 ) sR8 (C 4 + C3 )⎢1 + sR3 ⎜⎜ 4 ⎝ C 4 + C3 ⎠⎦⎥ ⎣⎢ ....... (26) H( s ) = Rev 5.0 22 PD-97514 IR3859MPbF VOUT ZIN C3 C7 R3 R10 C4 R8 Zf Fb R9 Gain(dB) E/A Comp Ve VREF FZ2 FP2 FP3 Frequency Fig.16. Type III Compensation network and its asymptotic gain plot The compensation network has three poles and two zeros and they are expressed as follows: FP 1 = 0 ..............................................................(27) 1 ...........................................(28 ) FP 2 = 2π * R10 * C7 1 1 ............ (29) ≅ FP 3 = ⎛ C 4 * C3 ⎞ 2π * R3 * C3 ⎟⎟ 2π * R3 ⎜⎜ ⎝ C 4 + C3 ⎠ 1 ..................................... ........(30) FZ 1 = 2π * R3 * C 4 1 1 ≅ ..........(31) FZ 2 = 2π * C7 * ( R8 + R10 ) 2π * C7 * R8 Cross over frequency is expressed as: Fo = R3 * C7 * FESR vs Fo Output Capacitor Type II FLC<FESR<Fo<Fs/2 Electrolytic Tantalum Type III FLC<Fo<FESR Tantalum Ceramic The higher the crossover frequency, the potentially faster the load transient response. However, the crossover frequency should be low enough to allow attenuation of switching noise. Typically, the control loop bandwidth or crossover frequency is selected such that H(s) dB FZ1 Compensator Type Vin 1 * ....................... (32) Vosc 2π * Lo * Co Based on the frequency of the zero generated by the output capacitor and its ESR, relative to crossover frequency, the compensation type can be different. The table below shows the compensation types for relative locations of the crossover frequency. Fo ≤ (1/5 ~ 1/10 ) * Fs The DC gain should be large enough to provide high DC-regulation accuracy. The phase margin should be greater than 45o for overall stability. For this design we have: Vin=12V Vo=1.8V Vosc=1.8V Vref=0.7V Lo=0.68uH Co=6x22uF, ESR=3mOhm each It must be noted here that the value of the capacitance used in the compensator design must be the small signal value. For instance, the small signal capacitance of the 22uF capacitor used in this design (i.e. C3216X5R1E106M from TDK) is 9.5uF at 1.8 V DC bias and 600 kHz frequency. It is this value that must be used for all computations related to the compensation. The small signal value may be obtained from the manufacturer’s datasheets, design tools or SPICE models. Alternatively, they may also be inferred from measuring the power stage transfer function of the converter and measuring the double pole frequency FLC and using equation (16) to compute the small signal Co. These result to: FLC=25.5 kHz FESR=5.5 MHz Fs/2=300 kHz Select crossover frequency Fo=100 kHz Since FLC<Fo<Fs/2<FESR, Type-III is selected to place the pole and zeros. Rev 5.0 23 PD-97514 IR3859MPbF Detailed calculation of compensation Type-III Desired Phase Margin Θ = 70o FZ2 = Fo 1− sin Θ = 17.63 kHz 1+ sin Θ FP2 = Fo 1+ sin Θ = 567.1kHz 1− sin Θ RDS( on ) = 11 mΩ * 1.25 = 13.75 mΩ ISET ≅ Io( LIM ) = 9 A * 1.5 = 13.5 A (50% over nominal output current ) IOCSet = 59.07 μA (at Fs = 600 kHz) R OCSet = 3.14 kΩ Select R7 = 3.16 kΩ Select: FZ1 = 0.5* FZ2 = 8.82 kHz and FP3 = 0.5* Fs = 300 kHz Setting the Power Good Threshold Select: C7 = 2.2nF Power Good threshold can be programmed by using two external resistors (R5, R7 on Page 24). Calculate R3, C3 and C4 : R3 = 2π * Fo * Lo * Co * Vosc ; R3 = 1.66 kΩ C7 * Vin Select: R3 = 1.65 kΩ 1 ; C4 = 10.94 nF, Select: C4 = 10 nF C4 = 2π * FZ1 * R 3 1 C3 = ; C3 = 321 pF, Select: C3 = 270 pF 2π * FP3 * R3 Calculate R10, R8 and R9 : R10 = 1 ; R10 = 128 Ω, Select: R10 = 130 Ω 2π * C7 * FP2 1 - R10; R8 = 3.97 kΩ, R8 = 2π * C7 * FZ2 V R9 = ref * R8 ; R9 = 2.56 kΩ Select: R9 = 2.55 kΩ Vo -Vref Programming the Current-Limit The Current-Limit threshold can be set by connecting a resistor (ROCSET) from the SW pin to the OCSet pin. The resistor can be calculated by using equation (4). This resistor ROCSET must be placed close to the IC. The RDS(on) has a positive temperature coefficient and it should be considered for the worst case operation. Rev 5.0 ROCSet ∗ IOCSet R DS ( on ) R6 = ( Vo ( PGood _TH ) 0.85 * Vref − 1) * R7 - - (33) Where: 0.85*Vref is reference of the internal comparator, for IR3859. Vo(PGood_TH) is the selectable output voltage threshold for power good, for this design it is 1.53V (i.e. 0.85*1.8V). Select R7=2.55KOhm Using (24): R5=3.97KOhm Select R6=4.02KOhm Select: R8 = 4.02 kΩ ISET = I L ( critical ) = The following formula can be used to set the threshold: The PGood is an open drain output. Hence, it is necessary to use a pull up resistor RPG from PGood pin to Vcc. The value of the pull-up resistor must be chosen such as to limit the current flowing into the PGood pin, when the output voltage is not in regulation, to less than 5 mA. A typical value used is 10kΩ. .......... . (32) 24 PD-97514 IR3859MPbF Application Diagram: Vin=12V Cin= 4 X 10 uF + 330 uF+1x0.1uF R1 49.9 K 4.5V <Vcc<5.5V R2 7.5K Enable Seq Vin Boot Vcc RPG 10 K R7 4.02 K OCSet Vsns Sync CSS 0.1 uF Vo ROCSet 3.16 K PGood Rt 23.7 K Lo 0.68uH SW CVcc 1uF PGood C6 0.1 uF Rt Fb SS/ SD Gnd PGnd Comp R5 2.55 K C4 10 nF R3 1.65 K R8 4.02 K C7 2.2nF Co=6X22uF R10 130 R9 2.55 K C3 270 pF Fig. 17. Application circuit diagram for a 12V to 1.8 V, 9A Point Of Load Converter Suggested Bill of Materials for the application circuit: Part Reference Cin Lo Co R1 R2 Rt RPG Css C6 R3 C3 C4 R8 R6 R9 R5 Rocset R10 C7 CVcc U1 Rev 5.0 Quantity 1 4 1 1 6 1 1 1 1 2 1 1 1 2 2 1 1 1 1 1 Value 330uF 10uF 0.1uF 0.68uH 22uF 49.9k 7.5k 23.7k 10k 0.1uF 1.65k 270pF 10nF 4.02k 2.55k 3.16k 130 2200pF 1.0uF IR3859 Description SMD Elecrolytic, Fsize, 25V, 20% 1206, 25V, X5R, 20% 0603, 25V, X7R, 10% 11.7x10x4mm, 20%, 1.58mOhm 0805, 6.3V, X5R, 20% Thick Film, 0603,1/10 W,1% Thick Film, 0603,1/10W,1% Thick Film, 0603,1/10W,1% Thick Film, 0603,1/10W,1% 0603, 25V, X7R, 10% Thick Film, 0603,1/10W,1% 50V, 0603, NPO, 5% 0603, 50V, X7R, 10% Thick Film, 0603,1/10W,1% Thick Film, 0603,1/10W,1% Thick Film, 0603,1/10W,1% Thick Film, 0603,1/10W,1% 0603, 50V, X7R, 10% 0603, 16V, X5R, 20% SupIRBuck, 9A, PQFN 4x5mm Manufacturer Panasonic TDK Panasonic Panasonic TDK Rohm Rohm Rohm Rohm Panasonic Rohm Panasonic Panasonic Rohm Rohm Rohm Panasonic Panasonic Panasonic International Rectifier Part Number EEV-FK1E331P C3216X5R1E106M ECJ-1VB1E104K ETQP4LR68XFC C2102X5R0J226M MCR03EZPFX4992 MCR03EZPFX7501 MCR03EZPFX2372 MCR03EZPFX1002 ECJ-1VB1E104K MCR03EZPFX1651 ECJ-1VC1H271J ECJ-1VB1H103K MCR03EZPFX4021 MCR03EZPFX2551 MCR03EZPFX3161 ERJ-3EKF1300V ECJ-1VB1H222K ECJ-BVB1C105M IR3859MPbF 25 PD-97514 IR3859MPbF TYPICAL OPERATING WAVEFORMS Vin=12.0V, Vcc=5V, Vo=1.8V, Io=0-9A, Room Temperature, No Air Flow Fig. 18: Start up at 9A Load Ch1:Vin, Ch2:Vout, Ch3:Vss, Ch4:Enable Fig. 19: Start up at 9A Load, Ch1:Vin, Ch2:Vout, Ch3:Vss, Ch4:VPGood Fig. 20: Start up with 1.62V PreBias, 0A Load, Ch2:Vout, Ch3:VSS Fig. 21: Output Voltage Ripple, 9A load Ch2: Vout Fig. 22: Inductor node at 9A load Ch2: Switch Node Fig. 23: Short (Hiccup) Recovery Ch2:Vout , Ch3:Vss Rev 5.0 26 PD-97514 IR3859MPbF TYPICAL OPERATING WAVEFORMS Vin=12V, Vcc=5V, Vo=1.8V, Io=4.5A- 9A, Room Temperature, No Air Flow Fig. 24: Transient Response, 4.5A to 9A step 2.5A/μs Ch2:Vout, Ch4:Iout Rev 5.0 27 PD-97514 IR3859MPbF TYPICAL OPERATING WAVEFORMS Vin=12V, Vcc=5V, Vo=1.8V, Io=9A, Room Temperature, No Air Flow Fig. 25: Bode Plot at 9A load shows a bandwidth of 92kHz and phase margin of 54 degrees Fig. 26: Synchronization to 700kHz external clock signal at 9A load Ch1: SW (Switch Node) Ch2:Sync Rev 5.0 28 PD-97514 IR3859MPbF TYPICAL OPERATING WAVEFORMS Simultaneous Tracking at Power Up and Power Down Vin=12V, Vo=1.8V, Io=9A, Room Temperature, No Air Flow VOUT 3.3V 4.02K R s1 2.55K Rs2 IR3859 IR3624 Seq R8 4.02K Fb R9 2.55K Fig. 27: Simultaneous Tracking a 3.3V input at power-up and shut-down Ch1: SEQ(3.3V) Ch2:SS(1.8V) Ch4: Vout(1.8V) Rev 5.0 29 PD-97514 IR3859MPbF Layout Considerations The layout is very important when designing high frequency switching converters. Layout will affect noise pickup and can cause a good design to perform with less than expected results. Make all the connections for the power components in the top layer with wide, copper filled areas or polygons. In general, it is desirable to make proper use of power planes and polygons for power distribution and heat dissipation. The inductor, output capacitors and the IR3859 should be as close to each other as possible. This helps to reduce the EMI radiated by the power traces due to the high switching currents through them. Place the input capacitor directly at the Vin pin of IR3859. The feedback part of the system should be kept away from the inductor and other noise sources. The critical bypass components such as capacitors for Vcc should be close to their respective pins. It is important to place the feedback components including feedback resistors and compensation components close to Fb and Comp pins. The connection between the OCSet resistor and the SW pin should not share any trace with the connection between the bootstrap capacitor and the SW pin. Instead, it is recommended to use a Kelvin connection of the trace from the OCSet resistor and the trace from the bootstrap Vin PGnd capacitor at the SW pin. In a multilayer PCB use one layer as a power ground plane and have a control circuit ground (analog ground), to which all signals are referenced. The goal is to localize the high current path to a separate loop that does not Vout analog control interfere AGnd with the more sensitive function. These two grounds must be connected together on the PC board layout at a single point. The Power QFN is a thermally enhanced package. Based on thermal performance it is recommended to use at least a 4-layers PCB. To effectively remove heat from the device the exposed pad should be connected to the ground plane using vias. Figure 28 illustrates the implementation of the layout guidelines outlined above, on the IRDC3859 4 layer demoboard. Vin AGnd PGnd Vout Enough copper & minimum length ground path between Input and Output Compensation parts should be placed as close as possible to the Comp pin. Vin PGnd All bypass caps should be placed as close as possible to their connecting pins. Resistors Rt, SS cap, and Rocset should be placed as close as possible to their pins. Vout AGnd Fig. 28a. IRDC3859 demoboard layout considerations – Top Layer Rev 5.0 30 PD-97514 IR3859MPbF PGnd Vin Single point connection between AGND & PGND; It should be close to the SupIRBuck, kept away from noise sources. SW PGnd Vout Fig. 28b. IRDC3859 demoboard layout considerations – Bottom Layer PGnd AGnd Fig. 28c. IRDC3859 demoboard layout considerations – Mid Layer 1 Use separate trace for connecting Boost cap and Rocset to the switch node and with the minimum length traces. Avoid big loops. Feedback trace should be kept away form noise sources Fig. 28d. IRDC3859 demoboard layout considerations – Mid Layer 2 Rev 5.0 31 PD-97514 IR3859MPbF PCB Metal and Components Placement Evaluations have shown that the best overall performance is achieved using the substrate/PCB layout as shown in following figures. PQFN devices should be placed to an accuracy of 0.050mm on both X and Y axes. Self-centering behavior is highly dependent on solders and processes, and experiments should be run to confirm the limits of self-centering on specific processes. For further information, please refer to “SupIRBuck™ Multi-Chip Module (MCM) Power Quad Flat No-Lead (PQFN) Board Mounting Application Note.” (AN-1132) PCB metal pad sizing (all dimensions in mm) PCB metal pad spacing (all dimensions in mm) Rev 5.0 32 PD-97514 IR3859MPbF Solder Resist IR recommends that the larger Power or Land Area pads are Solder Mask Defined (SMD.) This allows the underlying Copper traces to be as large as possible, which helps in terms of current carrying capability and device cooling capability. When using SMD pads, the underlying copper traces should be at least 0.05mm larger (on each edge) than the Solder Mask window, in order to accommodate any layer to layer misalignment. (i.e. 0.1mm in X & Y.) However, for the smaller Signal type leads around the edge of the device, IR recommends that these are Non Solder Mask Defined or Copper Defined. When using NSMD pads, the Solder Resist Window should be larger than the Copper Pad by at least 0.025mm on each edge, (i.e. 0.05mm in X&Y,) in order to accommodate any layer to layer misalignment. Ensure that the solder resist in-between the smaller signal lead areas are at least 0.15mm wide, due to the high x/y aspect ratio of the solder mask strip. Rev 5.0 33 PD-97514 IR3859MPbF Stencil Design Stencils for PQFN can be used with thicknesses of 0.100-0.250mm (0.004-0.010"). Stencils thinner than 0.100mm are unsuitable because they deposit insufficient solder paste to make good solder joints with the ground pad; high reductions sometimes create similar problems. Stencils in the range of 0.125mm-0.200mm (0.005-0.008"), with suitable reductions, give the best results. Evaluations have shown that the best overall performance is achieved using the stencil design shown in following figure. This design is for a stencil thickness of 0.127mm (0.005"). The reduction should be adjusted for stencils of other thicknesses. Stencil pad sizing (all dimensions in mm) Stencil pad spacing (all dimensions in mm) Rev 5.0 34 PD-97514 IR3859MPbF IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 This product has been designed and qualified for the Industrial market (Note5) Visit us at www.irf.com for sales contact information Data and specifications subject to change without notice. 08/12 Rev 5.0 35