APPLICATION NOTE Comparing Micron N25Q128A with Macronix MX25U12835F 1. Introduction This application note serves as a guide to compare Micron N25Q128A with Macronix MX25U12835F 1.8V 128Mb SPI flash. The document does not provide detailed information on each individual device, but highlights the similarities and differences between them. The comparison covers the general features, performance, command codes, and other differences. If common features are used in standard traditional modes, they may need only minimal software modification. The information provided in this document is based on datasheets listed in Section 9. Newer versions of the datasheets may override the contents of this document. 2. Features Both flash device families have similar features and functions as shown in Table 2-1 and 2-2. Significant differences are highlighted in blue and may require special consideration. Table 2-1: Feature Comparison Type / Function Macronix MX25U12835F Micron N25Q128A VCC Voltage Range 1.65V-2.0V 1.7V-2.0V Normal Read Clock Frequency 55MHz 54MHz (1) Maximum Clock Frequency 104MHz 108MHz Configurable Dummy Cycle YES YES Sector Size 4KB/32KB/64KB 4KB/64KB Program Buffer Size 256Byte 256Byte Security OTP 512Byte 64Byte (3) XIP / Performance Enhanced Mode YES YES (3) XIP / Performance Enhanced Mode Set at Power-on YES Program/Erase Suspend & Resume YES YES Wrap Around Read Mode YES YES Adjustable Output Drivers YES YES Deep Power Down YES YES S/W Reset Command YES YES HOLD#/RESET# Pin Reset# Hold#/Reset# Block Protection Mode (BP bits) Top/Bottom Top/Bottom (2) Individual Sector Protection (Volatile) YES YES Program/Erase Cycles 100K 100K Notes: 1. 133Mhz is the maximum clock frequency with 8 dummy cycles for the MX25U12835FZNI-08G only. 2. Please see App Note section 4-4 for detailed comparison of Individual Sector Protection. 3. Macronix supports 1-4-4 and 4-4-4 mode XIP; Micron supports XIP in all fast read modes. P/N: AN0244 1 Ver.1, July 05, 2013 APPLICATION NOTE Comparing Micron N25Q128A with Macronix MX25U12835F Table 2-2: Read Performance Macronix MX25U12835F I/O Mode Default Dummy Cycles Max Speed @ Default Dummy Cycles Micron N25Q128A Default Dummy Cycles Max Speed @ Default Dummy Cycles Fast Read 8 104MHz 8 108MHz (1-1-1) Dual Output (DREAD) 8 108MHz (1-1-2) Dual I/O (2READ) 4 84MHz 8 108MHz (1-2-2) Dual Peripheral Interface 9 108MHz (2-2-2) Quad Output (QREAD) 8 108MHz (1-1-4) Quad I/O (4READ) 6 104MHz(1) 10 108MHz (1-4-4) Quad Peripheral Interface (QPI) 6 104MHz(1) 11 108MHz (4-4-4) Notes: 1. 133Mhz is the maximum clock frequency with 8 dummy cycles for the MX25U12835FZNI-08G only. 3. Package and Pinout Both devices are available in 16-pin SOP and 8-WSON packages with similar footprints. Pinout definitions are identical with the two exceptions shown in Table 3-2. Where Macronix has a RESET#/SIO3 pin, Micron has either a HOLD#/DQ3 or a RESET#/DQ3 pin. If the Micron device has a RESET# pin, then the devices are pin compatible. If the Micron device has a HOLD# pin, but the HOLD# function is not used, then the devices are also pin compatible. Macronix does not support the VPP (10V Fast Programming Voltage) function available on Micron’s W#/VPP/DQ2 pin. This function is normally only used on external programmers to accelerate Program/Erase operations and is generally not used for “in-circuit” programming. Please consult the latest Macronix datasheet new package additions. Table 3-1: Packages Packages 8-WSON (6x5mm) 8-WSON (8x6mm) 16-SOP (300mil) 8-SOP 24TPBGA P/N: AN0244 Macronix MX25U12835F YES YES YES - 2 Micron N25Q128A YES YES YES YES YES Ver.1, July 05, 2013 APPLICATION NOTE Comparing Micron N25Q128A with Macronix MX25U12835F Figure 3-1: 16- PIN SOP (300mil) 16-PIN SOP (300mil) Macronix MX25U12835F Micron N25Q128A Macronix MX25U12835F Micron N25Q128A RESET#/SIO3 VCC NC NC NC NC CS# SO/SIO1 HOLD#/DQ3 VCC DNU DNU DNU DNU S# DQ1 SCLK SI/SIO0 NC NC NC NC GND WP#/SIO2 C DQ0 DNU DNU DNU DNU VSS W#/ VPP /DQ2 Macronix MX25U12835F VCC RESET#/SIO3 SCLK SI/SIO0 Micron N25Q128A Figure 3-2: 8-WSON 8-WSON Macronix MX25U12835F CS# SO/SIO1 WP#/SIO2 GND Micron N25Q128A S# DQ1 W#/ VPP /DQ2 VSS VCC HOLD#/DQ3 C DQ0 Table 3-2: Pin Definition Comparison Packag e / Pin# 8-WSON Macronix MX25U12835F Pin #3 WP#/SIO2 Pin #7 RESET#/SIO3 Micron N25Q128A Comments W#/ VPP /DQ2 HOLD#/DQ 3 HOLD# not supported by Macronix. Dedicated Micron part numbers offer RESET# instead of HOLD#. DNU#/SIO3 HOLD#/DQ 3 HOLD# not supported by Macronix. Dedicated Micron part numbers offer RESET# instead of HOLD#. NC DNU WP#/SIO2 W#/ VPP /DQ2 Macronix does not support VPP 16-SOP Pin #1 Pin #3, 4, 5, 6, 11, Pin 12, #9 P/N: AN0244 NC means “No Connect” DNU means “Do Not Use” Macronix does not support VPP 3 Ver.1, July 05, 2013 APPLICATION NOTE Comparing Micron N25Q128A with Macronix MX25U12835F 4. Key Feature and Operational Differences 4-1 Status Register and Configuration Register Differences Both devices use status and configuration registers to control device behavior and report status. The registers and bits used are similar but not identical. Micron also has Non-Volatile registers not shown. Both the Micron and Macronix devices use BP[3:0] bits to select the same memory areas for protection. The N25Q128A Block Protection bits BP[3:0] are located in Status Register (bits 6 and [4:2]). The Top/Bottom bit is located in Status Register bit 5 and selects whether block protection starts at the top or bottom of memory. The BP[3:0] and Top/Bottom bits are nonvolatile and reprogrammable. The MX25U12835F Block Protection bits BP[3:0] are located in Status Register bits [5:2]. The top/bottom starting point is controlled by the TB bit, which is located in Configuration Register bit 3. The default setting of the TB bit starts block protection at the top of memory. If the ‘bottom’ starting point is selected, it can never be returned to the ‘top’ starting point. The BP[3:0] bits are all nonvolatile and reprogrammable. The TB bit is nonvolatile and one-time-programmable. Table 4-1: Status Register Bits Register Bit Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Macronix MX25U12835F WIP; 1=write operation WEL; 1=write enable BP0; BP protection BP1; BP protection BP2; BP protection BP3; BP protection QE; 1=Quad mode enable SRWD; 1=SR write disable Micron N25Q128A WIP; 1=write operation WEL; 1=write enable BP0; BP protection BP1; BP protection BP2; BP protection T/B; Top/Bottom Protect BP3; BP protection SRWD; 1=SR write disable Table 4-2: Volatile Configuration Register Bits Register Bit Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 P/N: AN0244 Macronix MX25U12835F ODS0 (Output Driver Strength) ODS1 (Output Driver Strength) ODS2 (Output Driver Strength) TB; 1=Bottom area protect Reserved Reserved Reserved Dummy cycle 4 Micron N25Q128A Wrap Wrap Reserved XiP Dummy cycle Dummy cycle Dummy cycle Dummy cycle Ver.1, July 05, 2013 APPLICATION NOTE Comparing Micron N25Q128A with Macronix MX25U12835F Table 4-3: Macronix Security Register vs. Micron Flag Status Register Register Bit Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Macronix MX25U12835F 4Kb Secured OTP; 1=factory lock LDSO; 1=OTP lock down PSB (Program/Suspend bit) ESB (Erase/Suspend bit) Reserved P_FAIL; 1=Program fail E_FAIL; 1=Erase fail WPSEL; 1=Individual WP Micron N25Q128A Reserved Protection PSB (Program/Suspend bit) Vpp P_FAIL; 1=Program fail E_FAIL; 1=Erase fail ESB (Erase/Suspend bit) Program/Erase Status bit 4-2 QPI Differences Micron’s Quad I/O mode is entered by setting a bit in the Nonvolatile Configuration Register, which remembers this mode after power cycles, or by setting a bit in the Enhanced Volatile Configuration Register and is reset after a power cycle. The MX25U12835F requires an EQIO (35h) command to enter the equivalent QPI mode. This mode can be terminated by a RSTQIO (F5h) command or by a power cycle or software reset. 4-3 XIP Differences The XIP (eXecute In Place) feature (Macronix refers to this as Performance Enhance Mode) is only used during Fast Read operations and eliminates the need to input read commands prior to entering an address and reading data. This is an overhead reduction feature that increases data throughput. Both devices offer this feature, but entry and exit methods are different. The MX25U12835F enters XIP mode whenever all four bits of the first and second dummy cycles of a 4READ (EBh) instruction are not equal and will exit XIP mode if any of the bits of the first and second dummy cycles are equal. Macronix only supports XIP in Quad I/O (1-4-4) and QPI (4-4-4) modes. Micron supports XIP in all Fast Read I/O modes. P/N: AN0244 5 Ver.1, July 05, 2013 APPLICATION NOTE Comparing Micron N25Q128A with Macronix MX25U12835F 4-4 Individual Sector Protection Differences Both devices have the ability to write protect individual 64KB sectors/blocks of memory. Individual Sector Protection does not use the nonvolatile BP bits in the Status Register. With the Micron flash, it is possible to use both methods of write protection (BP bits and Individual Sector Protection) simultaneously, and the protected area is the combination of the two. When using the Macronix flash, either BP bit Protection or Individual Block Protection can be selected exclusively, with the default being the use of the BP bits. The N25Q128A has one volatile Lock Register for each 64KB sector to control the sector’s program/erase protection status. The protection can be turned on or off at any time unless the sector’s Lock Register has been locked by the application. Once locked, its associated sector will remain in the protected or unprotected state until the next power cycle or reset. All sectors not protected by the Status Register BP configuration will be unprotected after power up and all Lock Registers will be unlocked. The MX25U12835F has one volatile protection register for each of the top sixteen 4KB sectors, bottom sixteen 4KB sectors, and 254 middle 64KB blocks of memory. These protection registers can only be used after permanently disabling the Status Register BP protection bits. This is done by executing the WPSEL instruction once. Please note that this irreversible and the individual sector/block protection method will be permanently selected. After permanently selecting the individual sector/block protection method for the MX25U12835F, all sectors and blocks will be locked by default on power up. Sectors/blocks must be unlocked before they can be programmed or erased. Unlocking sectors/blocks can be done on an individual basis with the SBULK (Single Block Unlock) command or on all sectors/blocks with the GBULK (Global Block Unlock) command. Sectors and blocks can be relocked as necessary with the SBLK (Single Block Lock) command or GBLK (Global Block Lock) command. Since the smallest individual sector protection size in the N25Q128A is 64KB, if an application is currently locking/unlocking the top and/or bottom 64KB sector(s), it will need to lock/unlock each of the 16 top and/or bottom 4KB sectors in the MX25U12835F for equivalent results. P/N: AN0244 6 Ver.1, July 05, 2013 APPLICATION NOTE Comparing Micron N25Q128A with Macronix MX25U12835F 5. Performance Tables 5-1 and 5-2 show that the two devices have similar AC and DC performance. Table 5-1: AC Parameter Comparison Clock High Time Clock Low Time Symbol Macronix Micron tCH tCH tCL tCL Clock Low to Output Valid tCLQV tCLQV Data In Setup Time Data In Hold Time tDVCH tCHDX tDVCH tCHDX VCC(min) to CS# low tVSL tVTW Page Program Time (256 Bytes) tPP tPP Erase 4KB Subsector/Sector tSSE tSE Erase 32KB Sector tBE32 - Erase 64KB Sector/Block tBE tSE Bulk Erase / Chip Erase tCE tBE Parameter Condition min min max @10pF max @15pF max @30pF min min min max typ max typ max typ max typ max typ max Macronix MX25U12835F 4.5ns 4.5ns 6ns 7ns 2ns 3ns 500us 1.2ms 3ms 60ms 200ms 250ms 1s 500ms 2s 72s 160s Micron N25Q128A 4ns 4ns 5ns 7ns 2ns 3ns 150us 0.5ms 5ms 250ms 800ms 700ms 3s 120s 240s Table 5-2: DC Parameter Comparison Leakage Current Symbol Macronix Micron ILI/ILO ILI/ILO Standby Current ISB1 Parameter VCC Read Current (Fast Read) VCC Program Current VCC Write Status Register Current VCC Erase Current P/N: AN0244 ICC1 ICC1 ICC3 Condition max typ max max @ 108MHz (Quad I/O) max @ 104MHz (Quad I/O) max @ 84MHz Macronix MX25U12835F +/- 2uA 30uA 80uA Micron N25Q128A +/- 2uA 100uA - 20mA 20mA - 15mA - ICC2 ICC4 max @ 54MHz max 25mA 6mA 20mA ICC3 ICC5 max 20mA 20mA ICC4,5 ICC6 max 25mA 20mA 7 Ver.1, July 05, 2013 APPLICATION NOTE Comparing Micron N25Q128A with Macronix MX25U12835F 6. Command Code Both devices use the same basic command set, but there are a few minor differences highlighted in Table 6-1. Table 6-1: Command Code Comparison Instruction Type Read ID Read Write Read Identification Read Electronic Manufacturer ID & Signature Read Data Bytes Read Data Bytes at Higher Speed Dual Output Fast Read Dual Input/Output Fast Read Quad Output Fast Read Quad Input/Output Fast Read Quad Input/Output Fast Read (4 dummy) Macronix MX25U12835F 9Fh 90h 03h 0Bh BBh EBh E7h Micron N25Q128A 9Eh/9Fh 03h 0Bh 3Bh BBh 6Bh EBh - RDSFDP Read Serial Flash Discoverable Parameters 5Ah 5Ah WREN WRDI PP 4PP SE BE 32K SE 64K CE RDSR RDCR WRSR RDSCUR WRSCUR Write Enable Write Disable Page Program Dual Input Fast Program (1-1-2) Dual I/O Fast Program (1-2-2) Quad Input Fast Program (1-1-4) Quad Page Program (1-4-4) Sector Erase 4KB Block Erase 32KB Block Erase 64KB Chip Erase Read Status Register Read Configuration Register Write Status Register Read Security Register Write Security Register Read Lock Register Write to Lock Register Read Flag Status Register Clear Flag Status Register Read Non-volatile Configuration Register Write Non-volatile Configuration Register Read Volatile Configuration Register Write Volatile Configuration Register Read Enhance Volatile Configuration Register Write Enhance Volatile Configuration Register Enter Secured OTP Exit Secured OTP Read OTP Area Program OTP Area 06h 04h 02h 38h 20h 52h D8h 60 or C7h 05h 15h 01h 2Bh 2Fh 06h 04h 02h A2h D2h 32h 12h 20h D8h C7h 05h 01h E8h E5h 70h 50h B5h B1h 85h 81h 65h 61h 4Bh 42h Instruction Description RDID REMS READ FAST_READ DOFR DIOFR QOFR QIOFR W4READ RDLR WRLR Register OTP P/N: AN0244 RFSR CLFSR ENSO EXSO ROTP POTP 8 - B1h C1h - Ver.1, July 05, 2013 APPLICATION NOTE Comparing Micron N25Q128A with Macronix MX25U12835F Table 6-1: Command Code Comparison - Continued Instruction Type QPI Others Instruction Description Macronix MX25U12835F 35h F5h AFh B0h Micron N25Q128A AFh 75h EQIO RSTQIO QPIID PGM/ERS Suspend Enable QPI Reset (Exit) QPI QPI ID Read Program or Erase Suspend PGM/ERS Resume RSTEN RST DP RDP Program or Erase Resume Reset Enable Reset Memory Deep Power Down Release from Deep Power Down 30h 66h 99h B9h ABh 7Ah 66h 99h B9h ABh WPSEL Write Protect Selection (OTP) 68h - SBLK Single Block Lock 36h - SBULK Single Block Unlock 39h - RDBLOCK Block Protect Status Read 3Ch - GBLK Gang Block Lock 7Eh - GBULK Gang Block Unlock 98h - C0h Note 1 SBL Set Burst Length Note 1: Micron uses their Volatile Configuration Register to control this function. 7. Manufacturer and Device ID Table 7-1: Manufacturer and Device ID Comparison ID Type Macronix MX25U12835F C2h Micron N25Q128A 20h Memory Type 25h BBh Memory Capacity 38h N/A 18h 17 Bytes Manufacturer ID Device ID Unique ID 8. Summary The Macronix MX25U12835F and Micron N25Q128A have similar commands, functions, and features. The devices are command compatible for basic read, program, and erase (4KB and 64KB) operations. The devices are essentially pin compatible if the HOLD# function is not used. A more detailed analysis should be done if “special” functions such as XIP or Individual Sector Write Protection are used. If common features are used in standard traditional modes, they may need only minimal software modification. P/N: AN0244 9 Ver.1, July 05, 2013 APPLICATION NOTE Comparing Micron N25Q128A with Macronix MX25U12835F 9. References Table 9-1 shows the datasheet versions used for comparison in this application note. For the most current, detailed Macronix specification, please refer to the Macronix Website at http://www.macronix.com. Table 9-1: Datasheet Version Datasheet Location Date Issued Version MX25U12835F Macronix Website Dec. 17, 2012 1.2 n25q_128mb_1_8v_65nm Micron Website Jan. 2013 L 10. Appendix Table 10-1 shows the basic part number and package information cross reference between Macronix MX25U12835F and Micron N25Q128 parts. Table 10-1: Part Number Cross Reference Macronix Part No. MX25U12835FMI-10G MX25U12835FMI-10G MX25U12835FMI-10G MX25U12835FMI-10G MX25U12835FZNI-10G MX25U12835FZNI-10G MX25U12835FZNI-10G MX25U12835FZNI-10G MX25U12835FZ2I-10G MX25U12835FZ2I-10G MX25U12835FZ2I-10G MX25U12835FZ2I-10G Micron Part No. N25Q128A11ESF40 N25Q128A21ESF40 N25Q128A31ESF40 N25Q128A41ESF40 N25Q128A11EF740 N25Q128A21EF740 N25Q128A31EF740 N25Q128A41EF740 N25Q128A11EF840 N25Q128A21EF840 N25Q128A31EF840 N25Q128A41EF840 Package 16-SOP 16-SOP 16-SOP 16-SOP 8-WSON 8-WSON 8-WSON 8-WSON 8-WSON 8-WSON 8-WSON 8-WSON Dimension 300 mil 300 mil 300 mil 300 mil 6 x 5 mm 6 x 5 mm 6 x 5 mm 6 x 5 mm 8 x 6 mm 8 x 6 mm 8 x 6 mm 8 x 6 mm Note Hold# pin, Micron XIP Hold# pin, basic XIP Reset# pin, Micron XIP Reset# pin, basic XIP Hold# pin, Micron XIP Hold# pin, basic XIP Reset# pin, Micron XIP Reset# pin, basic XIP Hold# pin, Micron XIP Hold# pin, basic XIP Reset# pin, Micron XIP Reset# pin, basic XIP 11. Revision History Revision 1.0 P/N: AN0244 Description Initial Release 10 Date June 18, 2013 Ver.1, July 05, 2013 APPLICATION NOTE Comparing Micron N25Q128A with Macronix MX25U12835F Except for customized products which have been expressly identified in the applicable agreement, Macronix's products are designed, developed, and/or manufactured for ordinary business, industrial, personal, and/or household applications only, and not for use in any applications which may, directly or indirectly, cause death, personal injury, or severe property damages. In the event Macronix products are used in contradicted to their target usage above, the buyer shall take any and all actions to ensure said Macronix's product qualified for its actual use in accordance with the applicable laws and regulations; and Macronix as well as it’s suppliers and/or distributors shall be released from any and all liability arisen therefrom. Copyright© Macronix International Co., Ltd. 2013. All rights reserved, including the trademarks and tradename thereof, such as Macronix, MXIC, MXIC Logo, MX Logo, Integrated Solutions Provider, NBit, Nbit, NBiit, Macronix NBit, eLiteFlash, HybridNVM, HybridFlash, XtraROM, Phines, KH Logo, BE-SONOS, KSMC, Kingtech, MXSMIO, Macronix vEE, Macronix MAP, Rich Au-dio, Rich Book, Rich TV, and FitCAM. The names and brands of third party referred thereto (if any) are for identification purposes only For the contact and order information, please visit Macronix’s Web site at: http://www.macronix.com P/N: AN0244 11 Ver.1, July 05, 2013