AN1503/D ECLinPS and ECLinPS Lite SPICE Modeling Kit Prepared by Senad Lomigora, Paul Shockman ON Semiconductor Logic Applications Engineering http://onsemi.com APPLICATION NOTE Objective The objective of this kit is to provide customers with enough circuit schematic and SPICE parameter information to allow them to perform system level interconnect modeling for the current devices of the standard ECLinPS and ECLinPS Lite logic line, ON Semiconductor’s high performance ECL family. The kit is not intended to provide information necessary to perform circuit level modeling on ECLinPS devices. With packaged gate delays of 300 ps and output edge rates as low as 175 ps, this family defines the state−of−the−art in ECL logic. The ECLinPS line is one of ON Semiconductor’s high performance ECL/PECL family of products. Device Input and Output Buffers Schematic Information The kit contains representative input and output schematics, netlists, and waveform used for the standard ECLinPS and ECLinPS Lite devices. This application note will be modified as new devices are added. There are four terminals on all transistor models: Emitter, Base, Collector, and Substrate (biased to VEE). Table 1 describes the nomenclature used in the schematics and netlists. VEE. A model can be used at the VEE pin: but is not necessary since the current in the VEE pin is a constant. The Appendix A includes explanation on the package models nodes. For package model CDIP−16 only a center and end pin values are provided. Remaining pins may be ratio values between those two given pins. Table 2. Available Packages 5 V FOR PECL AND (0 V) FOR ECL VEE −5 V FOR ECL AND (0 V) FOR PECL GND 0V VTT* VCC − 2 V TERMINATION PLANE* IN TRUE INPUT TO CKT INB or IN INVERTED INPUT TO CKT Q TRUE OUTPUT OF CKT QB or Q INVERTED OUTPUT OF CKT *Except for EL89, VTT = VCC − 3 V Package A case model for various package types is included to improve the accuracy of the system model (see Table 2). The package model represents the parasitics as they are measured on a pin. The package pin model should be placed on each device input pin connecting to an input model, all device output pins connecting to an output model, VCC, and Semiconductor Components Industries, LLC, 2002 July, 2002 − Rev. 6 Page Number SO−8 15 TSSOP−8 17 SO−20 19 PLCC−28 25 PLCC−20 32 CDIP−16 33 Input Buffer The typical input buffer schematic is shown in Figure 2 (INBUFTYPICAL), and by netlist to represent the general structure currently in use on the existing devices in this family. The schematics require the addition of ESD models (Figure 9) and package models (see Table 2) to more accurately model behavior of the certain device. The internal input pulldown resistor, RPD, is shown in Figure 2. Single ended operation is shown although differential operation may be represented by changing VBB to INB (INVERTED INPUT TO CKT). The INB node will require ESD, package, and RPD models. Revise the netlist accordingly. It is unnecessary to include an ESD or Package model for the VBB pins of the models because VBB is intended as an internal node for most applications. If VBB is modeled as an external node it is usually bypassed because it is a constant voltage, and adding ESD and Package parameters provide no additional benefit. Output Buffer The output buffer schematics (see Table 3) and netlists may contain the temperature compensation structure, so only the ESD and package models need to be added. Use the proper ESD structure from Figure 9: for EL series devices use “ECLinPS Lite ESD Circuitry”, and for E series devices use “ECLinPS ESD Circuitry”. For the EL series Output Table 1. Schematics and Netlist Nomenclature VCC Package Model 1 Publication Order Number: AN1503/D AN1503/D modeling, delete the 185 series resistor in the ESD schematic, ECLinPS Lite ESD Circuitry. Any input or output that is driving or being driven by an off chip signal should include the ESD and package models. The output buffers show differential inputs and outputs. When simulating a single ended output, the termination or load resistor, package model, ESD structure and output emitter follower, of the unused output, should not be eliminated to simplify the system model. SPICE Netlists The netlists are organized as a group of subcircuits. In each subcircuit model netlist, the model name is followed by a list of node interconnects. Temperature Compensation Network for 100 Series The output netlists include temperature compensation network circuitry for 100 style output buffers. The temperature compensation circuitry should be placed as pictured in the output buffer schematics with L and R representing left and right of the schematic. The circuit components of the temperature compensation networks are shown in Figure 8. For simulating 10 style outputs these components should either be deleted or commented out of the subcircuit netlists. SPICE Parameter Information In addition to the schematics and netlists is a listing of the SPICE parameters for the transistors referenced in the schematics and netlists. These parameters represent a typical device of a given transistor. Varying the typical parameters will affect the DC and AC performance of the structures; but for the type of modeling intended by this note, the actual delay times are not necessary and are not modeled, as a result variation of the device parameters are meaningless. The performance levels are more easily varied by other methods and will be discussed in the next section. The resistors referenced in the schematics are polysilicon and have little parasitic capacitance in the real circuit so none is required in the model. The schematics display the only devices needed in the SPICE netlists. Modeling Information The bias drivers for the devices are not detailed since their circuitry would result in a substantial increase of model complexity and simulation time. Instead, these internal reference voltages (VBB, LVCS, Etc.) should be driven with ideal constant voltage sources. The typical interconnect schematic has been modeled to provide an output waveform of the ECLinPS Line. The 50 6″ Line typical input buffer may be driven with output buffer as shown in Figure 10. The schematics and SPICE parameters will provide a typical output waveshape, which can be seen in Figure 11. Simple adjustments can be made to the models allowing output characteristics to simulate conditions at or near the corners of some of the data book specifications. Consistent cross−point voltages need to be maintained. • To adjust rise and fall times: Produce the desired rise and fall times output slew rates by adjusting collector load resistors to change the gates tail current. The VCS voltage will affect the tail current in the output differential, which will interact with the load resistor and collector resistor to determine tr and tf at the output. • To adjust the VOH: Adjust the VOH and VOL level by the same amount by varying VCC. The output levels will follow changes in VCC at a 1:1 ratio. • To adjust the VOL only: Adjust the VOL level independently of the VOH level by increasing or decreasing the collector load resistance. Note that the VOH level will also change slightly due to a IBASER drop across the collector load resistor. VOL can be changed by varying the VCS supply, and therefore the gate current through the current source resistor. Summary The information included in this kit provides adequate information to run a SPICE level system interconnect simulation. The block diagram in Figure 1 illustrates a typical situation which can be modeled using the information in this kit. Device input or output models are presented in Table 4 and Table 5. Table 3. Buffer Model Figures Buffer Model Figure Number Page Number OBUF_A 3 6 OBUF_B 4 7 OBUF_C 5 8 OBUF_D 6 9 OBUF_E 7 10 INBUFTYPICAL 2 5 50 3″ Line 50 10″ Line Typical Input 50 Typical Output Typical Input Typical Input Figure 1. Typical Application for I/O SPICE Modeling Kit http://onsemi.com 2 VTT AN1503/D Table 4. E Input/Output Selection Device Function All Inputs Output E016 8 bit Sync. Binary Up Counter INBUFTYPICAL OBUF_A E101 Quad 4 input OR/NOR Gate INBUFTYPICAL OBUF_A E104 Quint 2 input AND/NAND Gate INBUFTYPICAL OBUF_A E107 Quint 2 input XOR/XNOR Gate INBUFTYPICAL OBUF_A E111 1:9 Diff. Clock Driver INBUFTYPICAL OBUF_A E112 Quad Driver INBUFTYPICAL OBUF_A E116 Quint Diff. Line Receiver INBUFTYPICAL OBUF_A E122 9 Bit Buffer INBUFTYPICAL OBUF_A E131 4 Bit D Flip−Flop INBUFTYPICAL OBUF_A E136 6 Bit Universal Up/Down Counter INBUFTYPICAL OBUF_A E137 8 Bit Ripple Counter INBUFTYPICAL OBUF_A E141 8 Bit Shift Register INBUFTYPICAL OBUF_A E142 9 Bit Shift Register INBUFTYPICAL OBUF_A E143 9 Bit Hold Register INBUFTYPICAL OBUF_A E150 6 Bit D Latch INBUFTYPICAL OBUF_A E151 6 Bit D Register INBUFTYPICAL OBUF_A E154 5 Bit 2:1 Mux−Latch INBUFTYPICAL OBUF_A E155 6 Bit 2:1 Mux−Latch INBUFTYPICAL OBUF_A E156 3 Bit 4:1 Mux−Latch INBUFTYPICAL OBUF_A E157 Quad 2:1 Multiplexer INBUFTYPICAL OBUF_A E158 5 Bit 2:1 Multiplexer INBUFTYPICAL OBUF_A E160 12 Bit Parity Generator/Checker INBUFTYPICAL OBUF_A E163 2 Bit 8:1 Multiplexer INBUFTYPICAL OBUF_A E164 16:1 Multiplexer INBUFTYPICAL OBUF_A E166 9 Bit Magnitude Comparator INBUFTYPICAL OBUF_A E167 6 Bit 2:1 Mux−Register INBUFTYPICAL OBUF_A E171 3 Bit 4:1 Multiplexer INBUFTYPICAL OBUF_A E175 9 Bit Latch with Parity INBUFTYPICAL OBUF_A E193 Error Detection/Correction Circuit INBUFTYPICAL OBUF_A E195 Programmable Delay Chip INBUFTYPICAL OBUF_B E196 Programmable Delay Chip INBUFTYPICAL OBUF_B E197 Data Separator INBUFTYPICAL OBUF_A E210 Dual 1:4, 1:5 Diff. Fanout Buffer INBUFTYPICAL OBUF_A E211 1:6 Diff. Clock Distribution Chip INBUFTYPICAL OBUF_B E212 3 Bit Scannable Registered Address Driver INBUFTYPICAL OBUF_B E241 8 Bit Scannable Register INBUFTYPICAL OBUF_A E256 3 Bit 4:1 Mux−Latch INBUFTYPICAL OBUF_A E310 Low Voltage 2:8 Diff. Fanout Buffer INBUFTYPICAL OBUF_A E336 3 Bit Registered Bus Transceiver INBUFTYPICAL OBUF_C E337 3 Bit Scannable Registered Bus Transceiver INBUFTYPICAL OBUF_C E404 Quad Diff. AND/NAND INBUFTYPICAL OBUF_B E411 1:9 Diff. PECL/NECL RAMBus Clock Buffer INBUFTYPICAL OBUF_A http://onsemi.com 3 AN1503/D Table 4. E Input/Output Selection E416 Quint Diff. Line Receiver INBUFTYPICAL OBUF_D E431 3 Bit Diff. Flip−Flop INBUFTYPICAL OBUF_A E445 4 Bit Serial/Parallel Converter (pins 17, 18 OBUF_B) INBUFTYPICAL OBUF_A E446 4 Bit Parallel/Serial Converter (pins 14, 15 OBUF_B) INBUFTYPICAL OBUF_A E451 6 Bit D Register Diff. Data and Clock INBUFTYPICAL OBUF_A E452 5 Bit Diff. Register INBUFTYPICAL OBUF_A E457 Triple Diff. 2:1 Multiplexer INBUFTYPICAL OBUF_B E1651 Dual ECL Output Comparator with Latch INBUFTYPICAL OBUF_A E1652 Dual ECL Output Comparator with Latch INBUFTYPICAL OBUF_A Table 5. EL Input/Output Selection Device All Inputs Output EL01 4 input OR/NOR INBUFTYPICAL OBUF_B EL04 2 input Diff. AND/NAND INBUFTYPICAL OBUF_B EL05 3 input AND/NAND INBUFTYPICAL OBUF_B EL07 3 input XOR/XNOR INBUFTYPICAL OBUF_B EL11 1:2 Diff. Fanout Buffer INBUFTYPICAL OBUF_B EL12 Low Impedance Driver INBUFTYPICAL OBUF_B EL13 Dual 1:3 Fanout Buffer INBUFTYPICAL OBUF_A EL14 1:5 Clock Distribution Chip INBUFTYPICAL OBUF_A EL15 1:4 Clock Distribution Chip INBUFTYPICAL OBUF_A EL16 Diff. Receiver INBUFTYPICAL OBUF_B EL17 Quad Diff. Receiver INBUFTYPICAL OBUF_A EL29 Dual Diff. Data and Clock D Flip−Flop with Set&Reset INBUFTYPICAL OBUF_A EL30 D Flip−Flop with Set&Reset INBUFTYPICAL OBUF_A EL31 Triple D Flip−Flop with Set&Reset INBUFTYPICAL OBUF_B EL32 2 Divider INBUFTYPICAL OBUF_B EL33 4 Divider INBUFTYPICAL OBUF_B EL34 2, 4, 8 Clock Generation Chip INBUFTYPICAL OBUF_A EL35 JK Flip−Flop INBUFTYPICAL OBUF_B EL38 2, 4/6 Clock Generation Chip INBUFTYPICAL OBUF_A EL39 2/4, 4/6 Clock Generation Chip INBUFTYPICAL OBUF_A EL51 Diff. Clock D Flip−Flop INBUFTYPICAL OBUF_B EL52 Diff. Data and Clock D Flip−Flop INBUFTYPICAL OBUF_B EL56 Dual Diff. 2:1 Multiplexer INBUFTYPICAL OBUF_A EL57 4:1 Diff. Multiplexer INBUFTYPICAL OBUF_B EL58 2:1 Multiplexer INBUFTYPICAL OBUF_A EL59 Triple 2:1 Multiplexer INBUFTYPICAL OBUF_A Coaxial Cable Driver * INBUFTYPICAL OBUF_E EL90 Triple ECL Input to PECL Output Translator INBUFTYPICAL OBUF_A EL91 Triple LVPECL/PECL Input to −5V ECL Output Translator INBUFTYPICAL OBUF_A EL89 * Function *EL89 has an output swing of 1.6 V and it is terminated 50 to VCC − 3 V (see Figure 7) http://onsemi.com 4 AN1503/D Netlists and Schematics VCC VCC PKG R1 250 1 R2 270 R3 270 Q4 TN6 3 2 Q5 TN6 Q QB IN Q1 TN6 PKG Rpd 50 k ESD PROTECTION CIRCUITRY 4 VBB Q6 TN6 6 VCS = VEE + 1.33 PULL DOWN RESISTOR Q2 TN6 Q3 TN6 R4 325 7 Q8 TN6 5 Ig = 1.5 mA Q7 TN6 9 Ief = 0.75 mA Q9 TN6 8 R5 650 VEE RESISTOR TC = 0.405M, 2.2U VEE Figure 2. Typical Input Buffer (INBUFTYPICAL) .SUBCKT INBUFTYPICAL Q1 2 IN 4 TN6 Q2 3 VBB 4 TN6 Q3 4 VCS 5 TN6 Q4 VCC 3 Q TN6 Q5 VCC 2 QB TN6 Q6 QB QB 6 TN6 Q7 Q Q 7 TN6 Q8 6 VCS 9 TN6 Q9 7 VCS 8 TN6 R1 VCC 1 250 R2 1 2 270 R3 1 3 270 R4 5 VEE 325 R5 9 VEE 650 R6 8 VEE 650 RPD IN VEE 50K .ENDS INBUFTYPICAL http://onsemi.com 5 R6 650 AN1503/D VCC VCC + 0 Vdc − R1 300 0 STYLE A TEMPERATURE COMPENSATION NETWORK IN R2 300 1 Q4 TNECLIPS TCN A Q1 TN13P5 + IN −1.33 Vdc − INB Q2 TN13P5 3 OUT V1 = −0.95 V2 = −1.75 TD = 1n TR = 0.35n TF = 0.35n PW = 1.5n PER = 3.7n 0 VCS Q3 TN13P5 + −3.7 Vdc − Q5 TNECLIPS 2 VCS 0 4 R3 125 + INB − R4 50 0 R5 50 VTT + −2 Vdc − VEE + VEE −5 Vdc − OUTB VTT 0 0 TERMINATION Figure 3. Output Buffer (OBUF_A) .SUBCKT OBUF_A Q_Q1 1 IN 3 TN13P5 Q_Q2 2 INB 3 TN13P5 Q_Q3 3 VCS 4 TN13P5 Q_Q4 VCC 1 OUTB TNECLIPS Q_Q5 VCC 2 OUT TNECLIPS R_R1 1 VCC 300 R_R2 2 VCC 300 R_R3 VEE 4 125 R_R4 VTT OUT 50 R_R5 VTT OUTB 50 V_IN IN 0 −1.33Vdc V_INB INB 0 V_VCC VCC 0 0Vdc V_VEE VEE 0 −5Vdc V_VTT VTT 0 −2Vdc V_VCS VCS 0 −3.7Vdc +PULSE −0.95 −1.75 1n 0.35n 0.35n 1.5n 3.7n .END OBUF_A http://onsemi.com 6 AN1503/D VCC VCC + 0 Vdc − R1 150 0 STYLE B TEMPERATURE COMPENSATION NETWORK IN Q1a + IN −1.33 Vdc − R2 150 1 Q1 TN13P5 6 Q2a TN13P5 V1 = −0.95 V2 = −1.75 TD = 1n TR = 0.35n TF = 0.35n PW = 2.5n PER = 5.7n 0 Q3a −3.7 Vdc − VCS 0 TN13P5 R4 4 INB Q2 TN13P5 3 VCS Q5 TNECLIPS 5 TCN B TN13P5 + Q4 TNECLIPS 2 Q3 TN13P5 4 R3 65 OUT + OUTB INB − R6 50 0 R7 50 VTT + −2 Vdc − VEE + VEE −5 Vdc − R5 4 VTT 0 0 TERMINATION Figure 4. Output Buffer (OBUF_B) .SUBCKT OBUF_B Q_Q1 1 IN 3 TN13P5 Q_Q1a 1 IN 3 TN13P5 Q_Q2 2 INB 3 TN13P5 Q_Q2a 2 INB 3 TN13P5 Q_Q3 3 VCS 4 TN13P5 Q_Q3a 3 VCS 4 TN13P5 Q_Q4 VCC 2 5 TNECLIPS Q_Q5 VCC 1 6 TNECLIPS R_R1 1 VCC 150 R_R2 2 VCC 150 R_R3 VEE 4 65 R_R4 OUT 5 4 R_R5 OUTB 6 4 R_R6 VTT OUT 50 R_R7 VTT OUTB 50 V_IN IN 0 −1.33Vdc V_INB INB 0 V_VCC VCC 0 0Vdc V_VEE VEE 0 −5Vdc V_VCS VCS 0 −3.7Vdc V_VTT VTT 0 −2Vdc +PULSE −0.95 −1.75 1n 0.35n 0.35n 2.5n 5.7n .END OBUF_B http://onsemi.com 7 AN1503/D VCC VCC + 0 Vdc − 0 STYLE C TEMPERATURE COMPENSATION NETWORK R1 100 R2 100 TCN C 1 2 R4 60 R3 60 Q4a 3 4 Q4 TNECLIPS TNECLIPS 7 IN IN −1.33 Vdc Q1b + Q1a Q1 TN13P5 TN13P5 TN13P5 INB Q2 TN13P5 Q2a R6 4 Q2b BUS TN13P5 TN13P5 5 − V1 = −0.95 V2 = −1.75 TD = 1n TR = 2n TF = 2n PW = 2n PER = 8n 0 VCS Q3b + −3.91 Vdc − Q3a VCS TN13P5 TN13P5 Q3 TN13P5 6 R5 40 0 OUT + INB − R7 50 0 VTT + −2 Vdc − VEE + VEE −5 Vdc − VTT 0 0 TERMINATION Figure 5. Output Buffer (OBUF_C) .SUBCKT OBUF_C Q_Q1 3 IN 5 TN13P5 Q_Q1a 3 IN 5 TN13P5 Q_Q1b 3 IN 5 TN13P5 Q_Q2 4 INB 5 TN13P5 Q_Q2a 4 INB 5 TN13P5 Q_Q2b 4 INB 5 TN13P5 Q_Q3 5 VCS 6 TN13P5 Q_Q3a 5 VCS 6 TN13P5 Q_Q3b 5 VCS 6 TN13P5 Q_Q4 VCC 3 7 TNECLIPS Q_Q4a VCC 3 7 TNECLIPS R_R1 1 VCC 100 R_R2 2 VCC 100 R_R3 3 1 60 R_R4 4 2 60 R_R5 VEE 6 40 R_R6 BUS 7 4 R_R7 VTT BUS 50 V_IN IN 0 −1.33Vdc V_INB INB 0 V_VCC VCC 0 0Vdc V_VEE VEE 0 −5Vdc V_VCS VCS 0 −3.91Vdc V_VTT VTT 0 −2Vdc +PULSE −0.95 −1.75 1n 2n 2n 2n 8n .END OBUF_C http://onsemi.com 8 AN1503/D VCC VCC + 0 Vdc − R1 100 0 STYLE D TEMPERATURE COMPENSATION NETWORK IN Q1b + IN −1.33 Vdc − Q1a R2 100 1 Q1 TN13P5 6 Q2a −3.7 Vdc − VCS TN13P5 TN13P5 0 Q2b TN13P5 TN13P5 3 Q3a R4 4 INB Q2 TN13P5 V1 = −0.95 V2 = −1.75 TD = 1n TR = 0.35n TF = 0.35n PW = 2.5n PER = 5.7n 0 Q3b Q5 TNECLIPS 5 TCN D TN13P5 TN13P5 + Q4 TNECLIPS 2 Q3 TN13P5 4 R3 43 OUT + OUTB INB − R6 50 0 R7 50 VTT + −2 Vdc − VEE + VEE −5 Vdc − R5 4 VTT 0 0 TERMINATION Figure 6. Output Buffer (OBUF_D) .SUBCKT OBUF_D Q_Q1 1 IN 3 TN13P5 Q_Q1a 1 IN 3 TN13P5 Q_Q1b 1 IN 3 TN13P5 Q_Q2 2 INB 3 TN13P5 Q_Q2a 2 INB 3 TN13P5 Q_Q2b 2 INB 3 TN13P5 Q_Q3 3 N19458 4 TN13P5 Q_Q3a 3 N19458 4 TN13P5 Q_Q3b 3 N19458 4 TN13P5 Q_Q4 VCC 2 5 TNECLIPS Q_Q5 VCC 1 6 TNECLIPS R_R1 1 VCC 100 R_R2 2 VCC 100 R_R3 VEE 4 43 R_R4 OUT 5 4 R_R5 OUTB 6 4 R_R6 VTT OUT 50 R_R7 VTT OUTB 50 V_INB INB 0 V_IN IN 0 −1.33Vdc V_VCC VCC 0 0Vdc V_VEE VEE 0 −5Vdc V_VCS N19458 0 −3.7Vdc V_VTT VTT 0 −2Vdc +PULSE −0.95 −1.75 1n 0.35n 0.35n 2.5n 5.7n .END OBUF_D http://onsemi.com 9 AN1503/D VCC VCC + 0 Vdc − R1 280 R2 280 Q4 TNECLIPS 2 0 1 Q6 IN INB TNJ Q1a + IN −1.33 Vdc − Q1 Q2 TN13P5 TN13P5 TN13P5 −3.67 Vdc − TN13P5 3 8 Q7 Q9 VCS + VCS 0 TNJ Q2a 4 0 Q5 TNECLIPS Q8 TNJ Q3a 5 TN13P5 R3 323 Q3 TN13P5 TNJ 6 7 R4 68 V1 = −0.95 V2 = −1.75 TD = 1n TR = 0.2n TF = 0.2n PW = 2.2n PER = 4.8n + INB − OUT 0 R6 50 R7 50 VTT R5 323 + −3 Vdc − VEE + VEE −5 Vdc − OUTB VTT 0 0 TERMINATION Figure 7. Output Buffer (OBUF_E) .SUBCKT OBUF_E Q_Q1 1 4 3 TN13P5 Q_Q1a 1 4 3 TN13P5 Q_Q2 2 8 3 TN13P5 Q_Q2a 2 8 3 TN13P5 Q_Q3 3 VCS 6 TN13P5 Q_Q3a 3 VCS 6 TN13P5 Q_Q4 VCC 2 OUT TNECLIPS Q_Q5 VCC 1 OUTB TNECLIPS Q_Q6 VCC IN 4 TN8 Q_Q7 4 VCS 5 TN8 Q_Q8 VCC INB 8 TN8 Q_Q9 8 VCS 7 TN8 R_R1 1 VCC 280 R_R2 2 VCC 280 R_R3 VEE 5 323 R_R4 VEE 6 68 R_R5 VEE 7 323 R_R6 VTT OUT 50 R_R7 VTT OUTB 50 V_IN IN 0 −1.33Vdc V_INB INB 0 V_VCC VCC 0 0Vdc V_VEE VEE 0 −5Vdc V_VTT VTT 0 −3Vdc V_VCS VCS 0 −3.67Vdc +PULSE −0.95 −1.75 1n 0.2n 0.2n 2.2n 4.8n .END OBUF_E http://onsemi.com 10 AN1503/D L RTC 180 QT1 TN4 R L RTC 80 QT1 TN4 QT2 TN4 QT2 TN4 RESISTOR TC = 0.405M, 2.2U Style A L RTC 90 R QT1 TN4 R L Style B RTC 60 QT1 TN4 R QT2 TN4 Style C Style D Figure 8. Temperature Compensation Networks ECLinPS Lite ESD Circuitry ECLinPS ESD Circuitry VCC INPUT DESD1 CBVCC RB 185 INPUT To Input Transistor QESD 1 TN6 QESD 2 TN6 DESD2 CBSUB RESISTOR TC = 0.405M, 2.2U VEE VEE Figure 9. ESD Protection Circuitry http://onsemi.com 11 AN1503/D VCC VCC + 0 Vdc − R1 300 R2 300 Q5 TNECLIPS 0 Q4 TNECLIPS OBUF_A IN + IN −1.33 Vdc − Q1 TN13P5 Q2 TN13P5 OUT 0 VCS Q3 TN13P5 + −3.7 Vdc − INB VCS R3 125 0 V1 = −0.95 V2 = −1.75 TD = 1n TR = 0.35n TF = 0.35n PW = 1.5n PER = 3.7n + OUTB INB R4 50 − R5 50 VTT 0 + −2 Vdc − VEE VTT 0 VEE + −5 Vdc − TERMINATION 0 R1′ 250 R2′ 270 R3′ 270 Q4′ TN6 Q5′ TN6 IN′ Q1′ TN6 Q2′ TN6 Q6′ TN6 IN′ Q7′ TN6 INBUFTYPICAL Q3′ TN6 Q8′ TN6 R4′ 325 TYPICAL INPUT BUFFER Figure 10. Typical Interconnect Schematic http://onsemi.com 12 R5′ 650 VEE Q9′ TN6 R6′ 650 AN1503/D VOUT, OUTPUT VOLTAGE (V) −0.8 VOH = −920 mV 80% −1.2 tr = 531 ps tf = 528 ps CROSS POINT −1.6 20% VOL = −1800 mV −2.0 6.0 6.4 6.8 7.2 TIME (ns) 7.6 Figure 11. Typical Output Waveform http://onsemi.com 13 8.0 AN1503/D ****************** Transistor and Diodes Nominal SPICE Models ******************* ***************************************************************************** .MODEL TN4 NPN (IS=5.27E−18 BF=120 NF=1 VAF=30 IKF=6.48mA + ISE=2.75E−16 BR=10 NE=2 VAR=5 IKR=567uA + IRB=8.1uA RB=461.6 RBM=142.5 RE=21.6 RC=83.1 + CJE=19.9fF VJE=0.9 MJE=0.4 XTB=0.73 + CJC=25.1fF VJC=0.67 MJC=0.32 XCJC=0.3 + CJS=49.6fF VJS=0.6 MJS=0.4 FC=0.9 + TF=8pS TR=1nS XTF=10 VTF=1.4V ITF=17.0mA + ISC=0 EG=1.11 XTI=4.0 PTF=0 KF=0 AF=1 NR=1 NC=2) ***************************************************************************** .MODEL TN6 NPN (IS=8.56E−18 BF=120 NF=1 VAF=30 IKF=10.5mA + ISE=4.48E−16 BR=10 NE=2 VAR=5 IKR=922uA + IRB=13.2uA RB=291.4 RBM=95.0 RE=13.3 RC=62.7 + CJE=29.9fF VJE=0.9 MJE=0.4 XTB=0.73 + CJC=31.2fF VJC=0.67 MJC=0.32 XCJC=0.3 + CJS=60.9fF VJS=0.6 MJS=0.4 FC=0.9 + TF=8pS TR=1nS XTF=10 VTF=1.4V ITF=27.6mA + ISC=0 EG=1.11 XTI=4.0 PTF=0 KF=0 AF=1 NR=1 NC=2) ***************************************************************************** .MODEL TN13P5 NPN (IS=2.09E−17 BF=120 NF=1 VAF=30 IKF=25.7mA + ISE=1.09E−15 BR=10 NE=2 VAR=5 IKR=2.25mA + IRB=32.2uA RB=122.6 RBM=42.2 RE=5.44 RC=32.8 + CJE=67.4fF VJE=0.9 MJE=0.4 XTB=0.73 + CJC=53.8fF VJC=0.67 MJC=0.32 XCJC=0.3 + CJS=103fF VJS=0.6 MJS=0.4 FC=0.9 + TF=8pS TR=1nS XTF=10 VTF=1.4V ITF=67.5mA + ISC=0 EG=1.11 XTI=4.0 PTF=0 KF=0 AF=1 NR=1 NC=2) ***************************************************************************** .MODEL TN8 NPN (IS=1.18E−17 BF=120 NF=1 VAF=30 IKF=14.6mA + ISE=6.20E−16 BR=10 NE=2 VAR=5 IKR=1.28mA + IRB=18.2uA RB=213.1 RBM=71.2 RE=9.60 RC=50.4 + CJE=39.9fF VJE=0.9 MJE=0.4 XTB=0.73 + CJC=37.2fF VJC=0.67 MJC=0.32 XCJC=0.3 + CJS=72.2fF VJS=0.6 MJS=0.4 FC=0.9 + TF=8pS TR=1nS XTF=10 VTF=1.4V ITF=38.3mA + ISC=0 EG=1.11 XTI=5.2 PTF=0 KF=0 AF=1 NR=1 NC=2) ***************************************************************************** .MODEL TNECLIPS NPN (IS=2.27E−16 BF=120 NF=1 VAF=30 IKF=279mA + ISE=1.19E−14 BR=10 NE=2 VAR=5 IKR=24.4mA + IRB=349uA RB=15.98 RBM=4.17 RE=0.501 RC=11.1 + CJE=611fF VJE=0.9 MJE=0.4 XTB=0.73 + CJC=440fF VJC=0.67 MJC=0.32 XCJC=0.3 + CJS=668fF VJS=0.6 MJS=0.4 FC=0.9 + TF=8pS TR=1nS XTF=10 VTF=1.4V ITF=733mA + ISC=0 EG=1.11 XTI=4.0 PTF=0 KF=0 AF=1 NR=1 NC=2) ***************************************************************************** .MODEL CBVCC (IS=1.00E−15 CJO=527fF Vj=0.545 M=0.32 BV=14.5 IBV=0.1E−6 XTI=5 TT=1nS) ***************************************************************************** .MODEL CBSUB (IS=1.00E−15 CJO=453fF TT=1nS) ***************************************************************************** http://onsemi.com 14 AN1503/D −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− Package: SO−8 * SPICE subcircuit file of coupled transmission lines * * Transmission line model * * Conductor number−pin designation cross reference: * Conductor Pin * 1 1 * 2 2 * 3 3 * 4 4 * 5 5 * 6 6 * 7 7 * 8 8 * * number of lumps: 1 * FASTEST APPLICABLE EDGE RATE: 0.076 ns * COMPRESSION OF SUBCIRCUITS PERFORMED: discard ratio is 0.050 * Connect chip side to N**I and board side to N**O * .SUBCKT LINES N01I N01O N02I N02O N03I N03O N04I N04O + N05I N05O N06I N06O N07I N07O N08I N08O L01WB N01I N01M 1.367e−09 L01 N01M N01O 7.794e−10 C01 N01M 0 2.445e−13 L02WB N02I N02M 1.287e−09 L02 N02M N02O 5.473e−10 C02 N02M 0 1.888e−13 L03WB N03I N03M 1.287e−09 L03 N03M N03O 5.473e−10 C03 N03M 0 1.901e−13 L04WB N04I N04M 1.367e−09 L04 N04M N04O 7.723e−10 C04 N04M 0 2.443e−13 L05WB N05I N05M 1.367e−09 L05 N05M N05O 7.710e−10 C05 N05M 0 2.478e−13 L06WB N06I N06M 1.287e−09 L06 N06M N06O 5.489e−10 C06 N06M 0 1.916e−13 L07WB N07I N07M 1.287e−09 L07 N07M N07O 5.495e−10 C07 N07M 0 1.930e−13 L08WB N08I N08M 1.367e−09 L08 N08M N08O 7.786e−10 C08 N08M 0 2.451e−13 K0102 L01 L02 0.1687 K0102WB L01WB L02WB 0.3400 C0102 N01O N02O 3.674e−14 K0103 L01 L03 0.0702 K0103WB L01WB L03WB 0.1847 K0203 L02 L03 0.1822 K0203WB L02WB L03WB 0.3505 C0203 N02O N03O 3.521e−14 K0204 L02 L04 0.0682 K0204WB L02WB L04WB 0.1847 K0304 L03 L04 0.1694 K0304WB L03WB L04WB 0.3400 http://onsemi.com 15 AN1503/D C0304 N03O N04O 3.675e−14 K0305WB L03WB L05WB 0.1847 K0405WB L04WB L05WB 0.3455 K0406WB L04WB L06WB 0.1847 K0506 L05 L06 0.1697 K0506WB L05WB L06WB 0.3400 C0506 N05O N06O 3.720e−14 K0507 L05 L07 0.0682 K0507WB L05WB L07WB 0.1847 K0607 L06 L07 0.1824 K0607WB L06WB L07WB 0.3505 C0607 N06O N07O 3.570e−14 K0608 L06 L08 0.0702 K0608WB L06WB L08WB 0.1847 K0708 L07 L08 0.1691 K0708WB L07WB L08WB 0.3400 C0708 N07O N08O 3.632e−14 .ENDS LINES −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− http://onsemi.com 16 AN1503/D −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− Package: TSSOP−8 * SPICE subcircuit file of coupled transmission lines * * Transmission line model * * Conductor number−pin designation cross reference: * counter−clockwise * Conductor Pin * 1 1 * 2 2 * 3 3 * 4 4 * 5 5 * 6 6 * 7 7 * 8 8 * * number of lumps: 1 * FASTEST APPLICABLE EDGE RATE: 0.048 ns * COMPRESSION OF SUBCIRCUITS PERFORMED: discard ratio is 0.050 * R_SHORT 0 GND 0.0001 * X_777 N01I N01O N02I N02O N03I N03O N04I N04O + N05I N05O N06I N06O N07I N07O N08I N08O GND PACKAGE * .SUBCKT PACKAGE N01I N01O N02I N02O N03I N03O N04I N04O + N05I N05O N06I N06O N07I N07O N08I N08O GND R01WB N01I N01W 4.727e−02 L01WB N01W N01R 1.158e−09 R01 N01R N01C 9.680e−04 C01 N01C GND 8.978e−14 L01 N01C N01O 7.466e−10 R02WB N02I N02W 3.815e−02 L02WB N02W N02R 9.835e−10 R02 N02R N02C 9.680e−04 C02 N02C GND 7.711e−14 L02 N02C N02O 7.466e−10 R03WB N03I N03W 3.815e−02 L03WB N03W N03R 9.835e−10 R03 N03R N03C 9.680e−04 C03 N03C GND 7.704e−14 L03 N03C N03O 7.465e−10 R04WB N04I N04W 4.727e−02 L04WB N04W N04R 1.158e−09 R04 N04R N04C 9.680e−04 C04 N04C GND 8.983e−14 L04 N04C N04O 7.460e−10 R05WB N05I N05W 4.727e−02 L05WB N05W N05R 1.158e−09 R05 N05R N05C 9.680e−04 C05 N05C GND 8.983e−14 L05 N05C N05O 7.460e−10 R06WB N06I N06W 3.815e−02 L06WB N06W N06R 9.835e−10 R06 N06R N06C 9.680e−04 C06 N06C GND 7.704e−14 L06 N06C N06O 7.465e−10 R07WB N07I N07W 3.815e−02 http://onsemi.com 17 AN1503/D L07WB N07W N07R 9.835e−10 R07 N07R N07C 9.680e−04 C07 N07C GND 7.711e−14 L07 N07C N07O 7.466e−10 R08WB N08I N08W 4.727e−02 L08WB N08W N08R 1.158e−09 R08 N08R N08C 9.680e−04 C08 N08C GND 8.978e−14 L08 N08C N08O 7.466e−10 K0102 L01 L02 0.2481 K0102WB L01WB L02WB 0.1729 C0102 N01C N02C 2.283e−14 K0103 L01 L03 0.1067 K0103WB L01WB L03WB 0.0598 K0104 L01 L04 0.0593 K0203 L02 L03 0.2479 K0203WB L02WB L03WB 0.1463 C0203 N02C N03C 2.136e−14 K0204 L02 L04 0.1068 K0204WB L02WB L04WB 0.0598 K0304 L03 L04 0.2481 K0304WB L03WB L04WB 0.1729 C0304 N03C N04C 2.279e−14 K0506 L05 L06 0.2481 K0506WB L05WB L06WB 0.1513 C0506 N05C N06C 2.279e−14 K0507 L05 L07 0.1068 K0507WB L05WB L07WB 0.0615 K0508 L05 L08 0.0593 K0607 L06 L07 0.2479 K0607WB L06WB L07WB 0.1729 C0607 N06C N07C 2.136e−14 K0608 L06 L08 0.1067 K0608WB L06WB L08WB 0.0615 K0708 L07 L08 0.2481 K0708WB L07WB L08WB 0.1513 C0708 N07C N08C 2.283e−14 .ENDS PACKAGE −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− http://onsemi.com 18 AN1503/D −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− Package: SO−20 * SPICE subcircuit file of coupled transmission lines * * Transmission line model * * Conductor number−pin designation cross reference: * Conductor Pin * 1 1 * 2 2 * 3 3 * 4 4 * 5 5 * 6 6 * 7 7 * 8 8 * 9 9 * 10 10 * 11 11 * 12 12 * 13 13 * 14 14 * 15 15 * 16 16 * 17 17 * 18 18 * 19 19 * 20 20 * * number of lumps: 1 * FASTEST APPLICABLE EDGE RATE: 0.275 ns * COMPRESSION OF SUBCIRCUITS PERFORMED: discard ratio is 0.050 * .SUBCKT PACKAGE N01I N01O N02I N02O N03I N03O N04I N04O + N05I N05O N06I N06O N07I N07O N08I N08O N09I N09O + N10I N10O N11I N11O N12I N12O N13I N13O N14I N14O + N15I N15O N16I N16O N17I N17O N18I N18O N19I N19O + N20I N20O BD_GND R01WB N01I N01W 3.732e−02 L01WB N01W N01R 9.678e−10 R01 N01R N01C 1.700e−02 C01 N01C BD_GND 4.680e−13 L01 N01C N01O 3.814e−09 R02WB N02I N02W 8.086e−02 L02WB N02W N02R 1.822e−09 R02 N02R N02C 1.300e−02 C02 N02C BD_GND 1.924e−13 L02 N02C N02O 2.724e−09 R03WB N03I N03W 9.122e−02 L03WB N03W N03R 2.033e−09 R03 N03R N03C 9.000e−02 C03 N03C BD_GND 1.377e−13 L03 N03C N03O 1.814e−09 R04WB N04I N04W 7.878e−02 L04WB N04W N04R 1.780e−09 R04 N04R N04C 8.000e−02 C04 N04C BD_GND 1.484e−13 L04 N04C N04O 1.551e−09 R05WB N05I N05W 6.634e−02 L05WB N05W N05R 1.531e−09 R05 N05R N05C 7.000e−02 http://onsemi.com 19 AN1503/D C05 L05 R06WB L06WB R06 C06 L06 R07WB L07WB R07 C07 L07 R08WB L08WB R08 C08 L08 R09WB L09WB R09 C09 L09 R10WB L10WB R10 C10 L10 R11WB L11WB R11 C11 L11 R12WB L12WB R12 C12 L12 R13WB L13WB R13 C13 L13 R14WB L14WB R14 C14 L14 R15WB L15WB R15 C15 L15 R16WB L16WB R16 C16 L16 R17WB L17WB R17 C17 L17 N05C N05C N06I N06W N06R N06C N06C N07I N07W N07R N07C N07C N08I N08W N08R N08C N08C N09I N09W N09R N09C N09C N10I N10W N10R N10C N10C N11I N11W N11R N11C N11C N12I N12W N12R N12C N12C N13I N13W N13R N13C N13C N14I N14W N14R N14C N14C N15I N15W N15R N15C N15C N16I N16W N16R N16C N16C N17I N17W N17R N17C N17C BD_GND N05O N06W N06R N06C BD_GND N06O N07W N07R N07C BD_GND N07O N08W N08R N08C BD_GND N08O N09W N09R N09C BD_GND N09O N10W N10R N10C BD_GND N10O N11W N11R N11C BD_GND N11O N12W N12R N12C BD_GND N12O N13W N13R N13C BD_GND N13O N14W N14R N14C BD_GND N14O N15W N15R N15C BD_GND N15O N16W N16R N16C BD_GND N16O N17W N17R N17C BD_GND N17O 1.635e−13 1.508e−09 6.634e−02 1.531e−09 7.000e−02 1.584e−13 1.508e−09 7.878e−02 1.780e−09 8.000e−02 1.476e−13 1.553e−09 4.976e−02 1.206e−09 9.000e−02 1.322e−13 1.820e−09 8.086e−02 1.822e−09 1.300e−02 1.864e−13 2.725e−09 7.256e−02 1.655e−09 1.700e−02 4.681e−13 3.814e−09 3.732e−02 9.678e−10 1.700e−02 4.761e−13 3.795e−09 8.086e−02 1.822e−09 1.300e−02 1.888e−13 2.745e−09 9.122e−02 2.033e−09 9.000e−02 1.346e−13 1.879e−09 7.878e−02 1.780e−09 8.000e−02 1.496e−13 1.436e−09 6.634e−02 1.531e−09 7.000e−02 1.550e−13 1.464e−09 6.634e−02 1.531e−09 7.000e−02 1.568e−13 1.465e−09 7.878e−02 1.780e−09 8.000e−02 1.492e−13 1.437e−09 http://onsemi.com 20 AN1503/D R18WB L18WB R18 C18 L18 R19WB L19WB R19 C19 L19 R20WB L20WB R20 C20 L20 K0102 K0102WB C0102 K0103 K0104 K0105 K0106 K0107 K0108 K0111 K0112 K0113 K0114 K0115 K0116 K0117 K0118 K0203 K0203WB C0203 K0204 K0205 K0206 K0207 K0208 K0209 K0211 K0212 K0213 K0214 K0215 K0216 K0217 K0218 K0304 K0304WB C0304 K0305 K0306 K0307 K0308 K0309 K0310 K0311 K0312 K0313 K0314 N18I N18W N18R N18C N18C N19I N19W N19R N19C N19C N20I N20W N20R N20C N20C L01 L01WB N01C L01 L01 L01 L01 L01 L01 L01 L01 L01 L01 L01 L01 L01 L01 L02 L02WB N02C L02 L02 L02 L02 L02 L02 L02 L02 L02 L02 L02 L02 L02 L02 L03 L03WB N03C L03 L03 L03 L03 L03 L03 L03 L03 L03 L03 N18W N18R N18C BD_GND N18O N19W N19R N19C BD_GND N19O N20W N20R N20C BD_GND N20O L02 L02WB N02C L03 L04 L05 L06 L07 L08 L11 L12 L13 L14 L15 L16 L17 L18 L03 L03WB N03C L04 L05 L06 L07 L08 L09 L11 L12 L13 L14 L15 L16 L17 L18 L04 L04WB N04C L05 L06 L07 L08 L09 L10 L11 L12 L13 L14 9.122e−02 2.033e−09 9.000e−02 1.346e−13 1.892e−09 8.086e−02 1.822e−09 1.300e−02 1.880e−13 2.767e−09 7.256e−02 1.655e−09 1.700e−02 4.712e−13 3.825e−09 0.4539 0.1239 2.674e−13 0.2557 0.1742 0.1290 0.1011 0.0834 0.0636 −0.0789 −0.0755 −0.0716 −0.0594 −0.0669 −0.0657 −0.0672 −0.0625 0.3964 0.1239 1.529e−13 0.2341 0.1587 0.1206 0.0974 0.0760 0.0554 −0.0743 −0.0723 −0.0707 −0.0604 −0.0678 −0.0677 −0.0685 −0.0682 0.3767 0.1239 1.006e−13 0.2211 0.1564 0.1219 0.0956 0.0762 0.0639 −0.0654 −0.0662 −0.0688 −0.0614 http://onsemi.com 21 AN1503/D K0315 K0316 K0317 K0318 K0319 K0320 K0405 K0405WB C0405 K0406 K0407 K0408 K0409 K0410 K0411 K0412 K0413 K0414 K0415 K0416 K0417 K0418 K0419 K0420 K0506 K0506WB C0506 K0507 K0508 K0509 K0510 K0511 K0512 K0513 K0514 K0515 K0516 K0517 K0518 K0519 K0520 K0607 K0607WB C0607 K0608 K0609 K0610 K0611 K0612 K0613 K0614 K0615 K0616 K0617 K0618 K0619 K0620 K0708 K0708WB C0708 K0709 K0710 L03 L03 L03 L03 L03 L03 L04 L04WB N04C L04 L04 L04 L04 L04 L04 L04 L04 L04 L04 L04 L04 L04 L04 L04 L05 L05WB N05C L05 L05 L05 L05 L05 L05 L05 L05 L05 L05 L05 L05 L05 L05 L06 L06WB N06C L06 L06 L06 L06 L06 L06 L06 L06 L06 L06 L06 L06 L06 L07 L07WB N07C L07 L07 L15 L16 L17 L18 L19 L20 L05 L05WB N05C L06 L07 L08 L09 L10 L11 L12 L13 L14 L15 L16 L17 L18 L19 L20 L06 L06WB N06C L07 L08 L09 L10 L11 L12 L13 L14 L15 L16 L17 L18 L19 L20 L07 L07WB N07C L08 L09 L10 L11 L12 L13 L14 L15 L16 L17 L18 L19 L20 L08 L08WB N08C L09 L10 −0.0683 −0.0692 −0.0684 −0.0730 −0.0609 −0.0501 0.3731 0.1239 8.137e−14 0.2290 0.1637 0.1218 0.0976 0.0836 −0.0645 −0.0673 −0.0722 −0.0658 −0.0724 −0.0733 −0.0708 −0.0763 −0.0673 −0.0597 0.3775 0.1239 8.844e−14 0.2293 0.1565 0.1208 0.1013 −0.0636 −0.0679 −0.0742 −0.0683 −0.0737 −0.0741 −0.0704 −0.0760 −0.0684 −0.0622 0.3743 0.1239 7.898e−14 0.2214 0.1591 0.1293 −0.0607 −0.0668 −0.0752 −0.0700 −0.0741 −0.0742 −0.0690 −0.0754 −0.0697 −0.0652 0.3762 0.1239 1.016e−13 0.2343 0.1746 http://onsemi.com 22 AN1503/D K0711 K0712 K0713 K0714 K0715 K0716 K0717 K0718 K0719 K0720 K0809 K0809WB C0809 K0810 K0812 K0813 K0814 K0815 K0816 K0817 K0818 K0819 K0820 K0910 K0910WB C0910 K0913 K0914 K0915 K0916 K0917 K0918 K0919 K0920 K1011WB K1013 K1014 K1015 K1016 K1017 K1018 K1019 K1020 K1112 K1112WB C1112 K1113 K1114 K1115 K1116 K1117 K1118 K1213 K1213WB C1213 K1214 K1215 K1216 K1217 K1218 K1314 K1314WB L07 L07 L07 L07 L07 L07 L07 L07 L07 L07 L08 L08WB N08C L08 L08 L08 L08 L08 L08 L08 L08 L08 L08 L09 L09WB N09C L09 L09 L09 L09 L09 L09 L09 L09 L10WB L10 L10 L10 L10 L10 L10 L10 L10 L11 L11WB N11C L11 L11 L11 L11 L11 L11 L12 L12WB N12C L12 L12 L12 L12 L12 L13 L13WB L11 L12 L13 L14 L15 L16 L17 L18 L19 L20 L09 L09WB N09C L10 L12 L13 L14 L15 L16 L17 L18 L19 L20 L10 L10WB N10C L13 L14 L15 L16 L17 L18 L19 L20 L11WB L13 L14 L15 L16 L17 L18 L19 L20 L12 L12WB N12C L13 L14 L15 L16 L17 L18 L13 L13WB N13C L14 L15 L16 L17 L18 L14 L14WB −0.0581 −0.0657 −0.0756 −0.0707 −0.0736 −0.0730 −0.0667 −0.0735 −0.0692 −0.0661 0.3970 0.1239 1.545e−13 0.2564 −0.0591 −0.0723 −0.0685 −0.0698 −0.0693 −0.0624 −0.0702 −0.0681 −0.0670 0.4542 0.1239 2.677e−13 −0.0675 −0.0688 −0.0687 −0.0693 −0.0618 −0.0723 −0.0742 −0.0759 0.1239 −0.0616 −0.0675 −0.0668 −0.0685 −0.0609 −0.0731 −0.0773 −0.0803 0.4562 0.1239 2.679e−13 0.2725 0.1533 0.1161 0.0901 0.0702 0.0567 0.4103 0.1239 1.538e−13 0.2091 0.1398 0.1055 0.0812 0.0684 0.3577 0.1239 http://onsemi.com 23 AN1503/D C1314 N13C N14C 1.026e−13 K1315 L13 L15 0.2088 K1316 L13 L16 0.1474 K1317 L13 L17 0.1074 K1318 L13 L18 0.0930 K1319 L13 L19 0.0693 K1320 L13 L20 0.0578 K1415 L14 L15 0.3383 K1415WB L14WB L15WB 0.1239 C1415 N14C N15C 7.843e−14 K1416 L14 L16 0.1987 K1417 L14 L17 0.1302 K1418 L14 L18 0.1078 K1419 L14 L19 0.0825 K1420 L14 L20 0.0715 K1516 L15 L16 0.3631 K1516WB L15WB L16WB 0.1239 C1516 N15C N16C 9.179e−14 K1517 L15 L17 0.1988 K1518 L15 L18 0.1480 K1519 L15 L19 0.1072 K1520 L15 L20 0.0918 K1617 L16 L17 0.3380 K1617WB L16WB L17WB 0.1239 C1617 N16C N17C 7.810e−14 K1618 L16 L18 0.2096 K1619 L16 L19 0.1419 K1620 L16 L20 0.1183 K1718 L17 L18 0.3595 K1718WB L17WB L18WB 0.1239 C1718 N17C N18C 1.034e−13 K1719 L17 L19 0.2122 K1720 L17 L20 0.1565 K1819 L18 L19 0.4140 K1819WB L18WB L19WB 0.1239 C1819 N18C N19C 1.536e−13 K1820 L18 L20 0.2766 K1920 L19 L20 0.4603 K1920WB L19WB L20WB 0.1239 C1920 N19C N20C 2.679e−13 .ENDS PACKAGE −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− http://onsemi.com 24 AN1503/D −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− Package: PLCC−28 * SPICE subcircuit file of coupled transmission lines * * Transmission line model * * Note: * 1. The model assume ground plane is 15 mil below package * 2. The model assume flag is floating * 3. The flag is 170 x 170 mil square, pin 1 starts from up left corner * 4. The lead sequence is counter clockwise * * Conductor number−pin designation cross reference: * Conductor Pin * 1 1 * 2 2 * 3 3 * 4 4 * 5 5 * 6 6 * 7 7 * 8 8 * 9 9 * 10 10 * 11 11 * 12 12 * 13 13 * 14 14 * 15 15 * 16 16 * 17 17 * 18 18 * 19 19 * 20 20 * 21 21 * 22 22 * 23 23 * 24 24 * 25 25 * 26 26 * 27 27 * 28 28 * * number of lumps: 1 * FASTEST APPLICABLE EDGE RATE: 0.209 ns * COMPRESSION OF SUBCIRCUITS PERFORMED: discard ratio is 0.050 * * ECLinPS usage requires the input nodes used in the subcircuit call * statement (X_777) that are tied to global ports(VCC, VCCO, and VEE internal * to the die) to have the same global names in the subcircuit call statement(X_777). * For example, if VCC is wirebonded to pin 20 for a certain design, then N20I * should be relabeled to VCC. Again, the change needs only to be incorporated * in the X_777 subcircuit callout statement. Since this requires a change to * the netlist below, it is necessary for each design to have a copy of this file with * the appropriate changes made that are required for that design. * * R_SHORT 0 ground 0.0001 * X_777 N01I N01O N02I N02O N03I N03O N04I N04O + N05I N05O N06I N06O N07I N07O N08I N08O N09I N09O http://onsemi.com 25 AN1503/D + N10I N10O N11I N11O N12I N12O N13I N13O N14I N14O + N15I N15O N16I N16O N17I N17O N18I N18O N19I N19O + N20I N20O N21I N21O N22I N22O N23I N23O N24I N24O + N25I N25O N26I N26O N27I N27O N28I N28O ground PACKAGE * .SUBCKT PACKAGE N01I N01O N02I N02O N03I N03O N04I N04O + N05I N05O N06I N06O N07I N07O N08I N08O N09I N09O + N10I N10O N11I N11O N12I N12O N13I N13O N14I N14O + N15I N15O N16I N16O N17I N17O N18I N18O N19I N19O + N20I N20O N21I N21O N22I N22O N23I N23O N24I N24O + N25I N25O N26I N26O N27I N27O N28I N28O ground R01WB N01I N01W 1.124e−01 L01WB N01W N01R 2.474e−09 R01 N01R N01C 1.120e−02 C01 N01C ground 3.919e−13 L01 N01C N01O 2.346e−09 R02WB N02I N02W 9.952e−02 L02WB N02W N02R 2.204e−09 R02 N02R N02C 1.120e−02 C02 N02C ground 1.950e−13 L02 N02C N02O 2.180e−09 R03WB N03I N03W 9.164e−02 L03WB N03W N03R 2.042e−09 R03 N03R N03C 1.100e−02 C03 N03C ground 1.789e−13 L03 N03C N03O 2.050e−09 R04WB N04I N04W 9.039e−02 L04WB N04W N04R 2.016e−09 R04 N04R N04C 1.100e−02 C04 N04C ground 1.748e−13 L04 N04C N04O 2.030e−09 R05WB N05I N05W 9.164e−02 L05WB N05W N05R 2.042e−09 R05 N05R N05C 1.100e−02 C05 N05C ground 1.800e−13 L05 N05C N05O 2.049e−09 R06WB N06I N06W 9.952e−02 L06WB N06W N06R 2.204e−09 R06 N06R N06C 1.120e−02 C06 N06C ground 1.936e−13 L06 N06C N06O 2.184e−09 R07WB N07I N07W 1.124e−01 L07WB N07W N07R 2.474e−09 R07 N07R N07C 1.120e−02 C07 N07C ground 3.916e−13 L07 N07C N07O 2.341e−09 R08WB N08I N08W 1.124e−01 L08WB N08W N08R 2.474e−09 R08 N08R N08C 1.120e−02 C08 N08C ground 3.916e−13 L08 N08C N08O 2.341e−09 R09WB N09I N09W 9.952e−02 L09WB N09W N09R 2.204e−09 R09 N09R N09C 1.120e−02 C09 N09C ground 1.936e−13 L09 N09C N09O 2.184e−09 R10WB N10I N10W 9.164e−02 L10WB N10W N10R 2.042e−09 R10 N10R N10C 1.100e−02 C10 N10C ground 1.800e−13 L10 N10C N10O 2.049e−09 R11WB N11I N11W 9.039e−02 http://onsemi.com 26 AN1503/D L11WB R11 C11 L11 R12WB L12WB R12 C12 L12 R13WB L13WB R13 C13 L13 R14WB L14WB R14 C14 L14 R15WB L15WB R15 C15 L15 R16WB L16WB R16 C16 L16 R17WB L17WB R17 C17 L17 R18WB L18WB R18 C18 L18 R19WB L19WB R19 C19 L19 R20WB L20WB R20 C20 L20 R21WB L21WB R21 C21 L21 R22WB L22WB R22 C22 L22 R23WB L23WB R23 N11W N11R N11C N11C N12I N12W N12R N12C N12C N13I N13W N13R N13C N13C N14I N14W N14R N14C N14C N15I N15W N15R N15C N15C N16I N16W N16R N16C N16C N17I N17W N17R N17C N17C N18I N18W N18R N18C N18C N19I N19W N19R N19C N19C N20I N20W N20R N20C N20C N21I N21W N21R N21C N21C N22I N22W N22R N22C N22C N23I N23W N23R N11R N11C ground N11O N12W N12R N12C ground N12O N13W N13R N13C ground N13O N14W N14R N14C ground N14O N15W N15R N15C ground N15O N16W N16R N16C ground N16O N17W N17R N17C ground N17O N18W N18R N18C ground N18O N19W N19R N19C ground N19O N20W N20R N20C ground N20O N21W N21R N21C ground N21O N22W N22R N22C ground N22O N23W N23R N23C 2.016e−09 1.100e−02 1.748e−13 2.030e−09 9.164e−02 2.042e−09 1.100e−02 1.789e−13 2.050e−09 9.952e−02 2.204e−09 1.120e−02 1.950e−13 2.180e−09 1.124e−01 2.474e−09 1.120e−02 3.919e−13 2.346e−09 1.124e−01 2.474e−09 1.120e−02 3.919e−13 2.346e−09 9.952e−02 2.204e−09 1.120e−02 1.950e−13 2.180e−09 9.164e−02 2.042e−09 1.100e−02 1.789e−13 2.050e−09 9.039e−02 2.016e−09 1.100e−02 1.748e−13 2.030e−09 9.164e−02 2.042e−09 1.100e−02 1.800e−13 2.049e−09 9.952e−02 2.204e−09 1.120e−02 1.936e−13 2.184e−09 1.124e−01 2.474e−09 1.120e−02 3.916e−13 2.341e−09 1.124e−01 2.474e−09 1.120e−02 3.916e−13 2.341e−09 9.952e−02 2.204e−09 1.120e−02 http://onsemi.com 27 AN1503/D C23 L23 R24WB L24WB R24 C24 L24 R25WB L25WB R25 C25 L25 R26WB L26WB R26 C26 L26 R27WB L27WB R27 C27 L27 R28WB L28WB R28 C28 L28 K0102 K0102WB C0102 K0103 K0103WB K0104 K0105 K0106 K0107 K0124 K0125 K0126 K0127 K0128 C0128 K0203 K0203WB C0203 K0204 K0204WB K0205 K0206 K0207 K0225 K0226 K0227 K0228 K0304 K0304WB C0304 K0305 K0305WB K0306 K0307 K0308 N23C N23C N24I N24W N24R N24C N24C N25I N25W N25R N25C N25C N26I N26W N26R N26C N26C N27I N27W N27R N27C N27C N28I N28W N28R N28C N28C L01 L01WB N01C L01 L01WB L01 L01 L01 L01 L01 L01 L01 L01 L01 N01C L02 L02WB N02C L02 L02WB L02 L02 L02 L02 L02 L02 L02 L03 L03WB N03C L03 L03WB L03 L03 L03 ground N23O N24W N24R N24C ground N24O N25W N25R N25C ground N25O N26W N26R N26C ground N26O N27W N27R N27C ground N27O N28W N28R N28C ground N28O L02 L02WB N02C L03 L03WB L04 L05 L06 L07 L24 L25 L26 L27 L28 N28C L03 L03WB N03C L04 L04WB L05 L06 L07 L25 L26 L27 L28 L04 L04WB N04C L05 L05WB L06 L07 L08 1.936e−13 2.184e−09 9.164e−02 2.042e−09 1.100e−02 1.800e−13 2.049e−09 9.039e−02 2.016e−09 1.100e−02 1.748e−13 2.030e−09 9.164e−02 2.042e−09 1.100e−02 1.789e−13 2.050e−09 9.952e−02 2.204e−09 1.120e−02 1.950e−13 2.180e−09 1.124e−01 2.474e−09 1.120e−02 3.919e−13 2.346e−09 0.4380 0.1463 2.394e−13 0.2472 0.0501 0.1557 0.1083 0.0742 0.0543 0.0506 0.0745 0.1092 0.1565 0.2194 5.401e−14 0.4331 0.1463 2.332e−13 0.2413 0.0708 0.1554 0.1051 0.0741 0.0619 0.0898 0.1237 0.1565 0.4342 0.2238 2.254e−13 0.2434 0.0853 0.1552 0.1083 0.0506 http://onsemi.com 28 AN1503/D K0327 K0328 K0405 K0405WB C0405 K0406 K0406WB K0407 K0408 K0409 K0427 K0428 K0506 K0506WB C0506 K0507 K0507WB K0508 K0509 K0528 K0607 K0607WB C0607 K0608 K0609 K0610 K0611 K0708 K0708WB C0708 K0709 K0710 K0711 K0712 K0809 K0809WB C0809 K0810 K0810WB K0811 K0812 K0813 K0814 K0910 K0910WB K0910 K0911 K0911WB K0912 K0913 K0914 K1011 K1011WB C1011 K1012 K1012WB K1013 K1014 K1015 K1112 K1112WB C1112 L03 L03 L04 L04WB N04C L04 L04WB L04 L04 L04 L04 L04 L05 L05WB N05C L05 L05WB L05 L05 L05 L06 L06WB N06C L06 L06 L06 L06 L07 L07WB N07C L07 L07 L07 L07 L08 L08WB N08C L08 L08WB L08 L08 L08 L08 L09 L09WB N09C L09 L09WB L09 L09 L09 L10 L10WB N10C L10 L10WB L10 L10 L10 L11 L11WB N11C L27 L28 L05 L05WB N05C L06 L06WB L07 L08 L09 L27 L28 L06 L06WB N06C L07 L07WB L08 L09 L28 L07 L07WB N07C L08 L09 L10 L11 L08 L08WB N08C L09 L10 L11 L12 L09 L09WB N09C L10 L10WB L11 L12 L13 L14 L10 L10WB N10C L11 L11WB L12 L13 L14 L11 L11WB N11C L12 L12WB L13 L14 L15 L12 L12WB N12C 0.0898 0.1092 0.4355 0.2238 2.282e−13 0.2418 0.0708 0.1558 0.0742 0.0613 0.0619 0.0745 0.4330 0.1463 2.324e−13 0.2474 0.0501 0.1087 0.0889 0.0506 0.4383 0.1463 2.402e−13 0.1558 0.1228 0.0889 0.0613 0.2174 0.0811 5.266e−14 0.1558 0.1087 0.0742 0.0506 0.4383 0.1463 2.402e−13 0.2474 0.0501 0.1558 0.1083 0.0741 0.0543 0.4330 0.1463 2.324e−13 0.2418 0.0708 0.1552 0.1051 0.0742 0.4355 0.2238 2.282e−13 0.2434 0.0853 0.1554 0.1083 0.0506 0.4342 0.2238 2.254e−13 http://onsemi.com 29 AN1503/D K1113 K1113WB K1114 K1115 K1116 K1213 K1213WB C1213 K1214 K1214WB K1215 K1216 K1314 K1314WB C1314 K1315 K1316 K1317 K1318 K1415 K1415WB C1415 K1416 K1417 K1418 K1419 K1516 K1516WB C1516 K1517 K1517WB K1518 K1519 K1520 K1521 K1617 K1617WB C1617 K1618 K1618WB K1619 K1620 K1621 K1718 K1718WB C1718 K1719 K1719WB K1720 K1721 K1722 K1819 K1819WB C1819 K1820 K1820WB K1821 K1822 K1823 K1920 K1920WB C1920 L11 L11WB L11 L11 L11 L12 L12WB N12C L12 L12WB L12 L12 L13 L13WB N13C L13 L13 L13 L13 L14 L14WB N14C L14 L14 L14 L14 L15 L15WB N15C L15 L15WB L15 L15 L15 L15 L16 L16WB N16C L16 L16WB L16 L16 L16 L17 L17WB N17C L17 L17WB L17 L17 L17 L18 L18WB N18C L18 L18WB L18 L18 L18 L19 L19WB N19C L13 L13WB L14 L15 L16 L13 L13WB N13C L14 L14WB L15 L16 L14 L14WB N14C L15 L16 L17 L18 L15 L15WB N15C L16 L17 L18 L19 L16 L16WB N16C L17 L17WB L18 L19 L20 L21 L17 L17WB N17C L18 L18WB L19 L20 L21 L18 L18WB N18C L19 L19WB L20 L21 L22 L19 L19WB N19C L20 L20WB L21 L22 L23 L20 L20WB N20C 0.2413 0.0708 0.1557 0.0745 0.0619 0.4331 0.1463 2.332e−13 0.2472 0.0501 0.1092 0.0898 0.4380 0.1463 2.394e−13 0.1565 0.1237 0.0898 0.0619 0.2194 0.0811 5.401e−14 0.1565 0.1092 0.0745 0.0506 0.4380 0.1463 2.394e−13 0.2472 0.0501 0.1557 0.1083 0.0742 0.0543 0.4331 0.1463 2.332e−13 0.2413 0.0708 0.1554 0.1051 0.0741 0.4342 0.2238 2.254e−13 0.2434 0.0853 0.1552 0.1083 0.0506 0.4355 0.2238 2.282e−13 0.2418 0.0708 0.1558 0.0742 0.0613 0.4330 0.1463 2.324e−13 http://onsemi.com 30 AN1503/D K1921 L19 L21 0.2474 K1921WB L19WB L21WB 0.0501 K1922 L19 L22 0.1087 K1923 L19 L23 0.0889 K2021 L20 L21 0.4383 K2021WB L20WB L21WB 0.1463 C2021 N20C N21C 2.402e−13 K2022 L20 L22 0.1558 K2023 L20 L23 0.1228 K2024 L20 L24 0.0889 K2025 L20 L25 0.0613 K2122 L21 L22 0.2174 K2122WB L21WB L22WB 0.0811 C2122 N21C N22C 5.266e−14 K2123 L21 L23 0.1558 K2124 L21 L24 0.1087 K2125 L21 L25 0.0742 K2126 L21 L26 0.0506 K2223 L22 L23 0.4383 K2223WB L22WB L23WB 0.1463 C2223 N22C N23C 2.402e−13 K2224 L22 L24 0.2474 K2224WB L22WB L24WB 0.0501 K2225 L22 L25 0.1558 K2226 L22 L26 0.1083 K2227 L22 L27 0.0741 K2228 L22 L28 0.0543 K2324 L23 L24 0.4330 K2324WB L23WB L24WB 0.1463 C2324 N23C N24C 2.324e−13 K2325 L23 L25 0.2418 K2325WB L23WB L25WB 0.0708 K2326 L23 L26 0.1552 K2327 L23 L27 0.1051 K2328 L23 L28 0.0742 K2425 L24 L25 0.4355 K2425WB L24WB L25WB 0.2238 C2425 N24C N25C 2.282e−13 K2426 L24 L26 0.2434 K2426WB L24WB L26WB 0.0853 K2427 L24 L27 0.1554 K2428 L24 L28 0.1083 K2526 L25 L26 0.4342 K2526WB L25WB L26WB 0.2238 C2526 N25C N26C 2.254e−13 K2527 L25 L27 0.2413 K2527WB L25WB L27WB 0.0708 K2528 L25 L28 0.1557 K2627 L26 L27 0.4331 K2627WB L26WB L27WB 0.1463 C2627 N26C N27C 2.332e−13 K2628 L26 L28 0.2472 K2628WB L26WB L28WB 0.0501 K2728 L27 L28 0.4380 K2728WB L27WB L28WB 0.1463 C2728 N27C N28C 2.394e−13 .ENDS PACKAGE * * −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− http://onsemi.com 31 AN1503/D −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− Package: PLCC−20 * ECLinPS Package Model (20−lead PLCC) * GND = 0V * * EXT = (External Input to Pin) * INT = (Internal Output of the Pin) * .SUBCKT PKG20 EXT INT GND CPKG 82 GND 0.65PF RPKG1 EXT 82 750 RPKG2 82 83 750 RPKG3 83 INT 0.2 LPKG1 EXT 82 0.9NH LPKG2 82 83 0.9NH .ENDS PKG20 −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− RPKG1 750 RPKG2 750 EXT LPKG1 0.9 nH LPKG2 0.9 nH CPKG 0.65 pF http://onsemi.com 32 RPKG3 0.2 INT AN1503/D −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− Package: CDIP−16 −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− * ECLinPS Package Model (16−lead CERDIP END PIN) * EXT = (External Input to Pin) INT = (Internal Output of the Pin) GND = (0V) * −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− .SUBCKT PKG16EP EXT INT GND CPKG 82 GND 1.3PF RPKG1 EXT 82 750 RPKG2 82 83 750 RPKG3 83 INT 0.1 LPKG1 EXT 82 5.5NH LPKG2 82 83 5.5NH .ENDS PKG16EP −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− * ECLinPS Package Model (16−lead CERDIP CENTER PIN) * EXT = (External Input to Pin) INT = (Internal Output of the Pin) GND = (0V) * −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− .SUBCKT PKG16CP EXT INT GND CPKG 82 GND 0.7PF RPKG1 EXT 82 750 RPKG2 82 83 750 RPKG3 83 INT 0.1 LPKG1 EXT 82 2.5NH LPKG2 82 83 2.5NH .ENDS PKG16CP −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− http://onsemi.com 33 AN1503/D APPENDIX A Package Models Help In the SPICE netlist, X_777 is a circuit element (black box) with connections to a subcircuit: circuit element X_777 connections N01I N01O N021 N02O N03I N03O N04I N04O +N05I N05O N061 N06O N07I N07O N08I N08O GND subcircuit PACKAGE The defined connection nodes of the circuit element are declared as: N01I N01O N021 N02O N03I N03O N04I N04O N05I N05O N061 N06O N07I N07O N08I N08O GND The subcircuit PACKAGE is connected to these same nodes: .SUBCKT PACKAGE N01I N01O N021 N02O N03I N03O N04I N04O +N05I N05O N061 N06O N07I N07O N08I N08O GND where: N01I is the PACKAGE pin #1 internal node connection to the chip pad N01O is the PACKAGE pin #1 external node connecting to the lead Internal to the subcircuit PACKAGE are several nodes for each pin (See Figure 7). For pin 2, of the 8 pin TSSOP, the netlist: R02WB L02WB R02 C02 L02 N02I N02W N02R N02C N02C N02I N02W N02R N02C GND N02O 3.815e−02 9.835e−10 9.680e−04 7.711e−14 7.466e−10 N02W R02WB N02R L02WB N02O L02 R02 N02C C02 GND Figure 12. Parasitic Mutual inductance, K, and capacitance, C, is also represented. Such as “K0102”, where inductance from Lead #1 (L01) to Lead #2 (L02) is indicated. K0102 K0102WB C0102 K0103 K0103WB K0104 K0203 K0203WB C0203 K0204 K0204WB L01 L01WB N01C L01 L01WB L01 L02 L02WB N02C L02 L02WB L02 L02WB N02C L03 L03WB L04 L03 L03WB N03C L04 L04WB 0.2481 0.1729 2.283e−14 0.1067 0.0598 0.0593 0.2479 0.1463 2.136e−14 0.1068 0.0598 http://onsemi.com 34 AN1503/D N01I N01W R01WB N01R N01O L01WB L01 R01 K0103WB N01C C0102 C01 K0102WB K0102 GND K0104 N02I N02W R02WB N02R L02WB N02O L02 R02 K0103 K0102 K0203WB N02C C02 GND N03I N03W R03WB N03R L03WB N03O L03 R03 N03C C03 GND N04I N04W R04WB N04R L04WB N04O L04 R04 N04C C04 GND Figure 13. http://onsemi.com 35 AN1503/D ECLinPS Plus and ECLinPS Lite are trademarks of Semiconductor Components Industries, LLC. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. PUBLICATION ORDERING INFORMATION Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: [email protected] JAPAN: ON Semiconductor, Japan Customer Focus Center 4−32−1 Nishi−Gotanda, Shinagawa−ku, Tokyo, Japan 141−0031 Phone: 81−3−5740−2700 Email: [email protected] ON Semiconductor Website: http://onsemi.com For additional information, please contact your local Sales Representative. N. American Technical Support: 800−282−9855 Toll Free USA/Canada http://onsemi.com 36 AN1503/D